Melexis TH7122 Technical data

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

Features

 Single chip solution with only a few external

components

 Stand-alone fixed-frequency user mode
 Programmable multi-channel user mode
 Low current consumption in active mode and

very low standby current

 PLL-stabilized RF VCO (LO) with internal

varactor diode

 Lock detect output in programmable

user mode

 On-chip AFC for extended input frequency

acceptance range

Ordering Information

Part Number Temperature Code Package Code Delivery Form

 3wire bus serial control interface
 FSK/ASK mode selection
 FSK for digital data or FM for analog signal

reception

 RSSI output for signal strength indication and

ASK reception

 Peak detector for ASK detection
 Switchable LNA gain for improved dynamic

range

 Automatic PA turn-on after PLL lock
 ASK modulation achieved by PA on/off keying
 32-pin Low profile Quad Flat Package (LQFP)

TH7122.1
(only for existing designs,

E (-40 °C to 85 °C) NE (LQFP32)
not for new design-ins)
TH7122.2
(for new design-ins)

E (-40 °C to 85 °C) NE (LQFP32)

Application Examples

 General bi-directional half duplex digital data

RF signaling or analog signal communication

 Tire Pressure Monitoring Systems (TPMS)
 Remote Keyless Entry (RKE)
 Low-power telemetry systems
 Alarm and security systems
 Wireless access control
 Garage door openers
 Networking solutions
 Active RFID tags
 Remote controls
 Home and building automation

250 pc/tray
2000 pc/T&R

250 pc/tray
2000 pc/T&R

Pin Description

OUT_PA

IN_LNA

VEE_LNA

OUT_LNA

GAIN_LNA

IN_MIX
VEE_IF

OUT_MIX

24

25

TH7122

32

1

IN_IFA

LF

TNK_LO

INT2/PDO

FS0/S DEN

VCC_PLL

FS1/LD

VEE_DIG

17

16

9

8

INT1

RSSI

OUT_DTA

OUT_DEM

VEE_PLL

VCC_IF

IN_DEM

RE/SCLK
VCC_DIG
ASK/FSK
IN_DTA
FSK_SW
RO
VEE_RO

General Description

The TH7122 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multi­channel programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used
for applications in automotive, industrial-scientific-medical (ISM), short range devices (SRD) or similar appli­cations operating in the frequency range of 300 MHz to 930 MHz. In programmable user mode, the trans­ceiver can operate down to 27 MHz by employing an external VCO varactor diode.

39010 07122 Page 1 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

Document Content

1 Theory of Operation...................................................................................................4

1.1 General............................................................................................................................. 4

1.2 Technical Data Overview.................................................................................................. 4

1.3 Note on ASK Modulation .................................................................................................. 4

1.4 Block Diagram.................................................................................................................. 5

1.5 User Mode Features......................................................................................................... 5

2 Pin Definitions and Descriptions..............................................................................6

3 Functional Description ............................................................................................10

3.1 PLL Frequency Synthesizer ........................................................................................... 10

3.1.1 Reference Oscillator (XOSC)..................................................................................................... 11

3.1.2 Reference Divider...................................................................................................................... 11

3.1.3 Feedback Divider....................................................................................................................... 11

3.1.4 Frequency Resolution and Operating Frequency...................................................................... 11

3.1.5 Phase-Frequency Detector........................................................................................................12

3.1.6 Lock Detector............................................................................................................................. 12

3.1.7 Voltage Controlled Oscillator with external Loop Filter.............................................................. 13

3.1.8 Loop Filter.................................................................................................................................. 13

3.2 Receiver Part.................................................................................................................. 13

3.2.1 LNA............................................................................................................................................ 14

3.2.2 Mixer .......................................................................................................................................... 14

3.2.3 IF Amplifier.................................................................................................................................14

3.2.4 ASK Demodulator...................................................................................................................... 14

3.2.5 FSK Demodulator ...................................................................................................................... 15

3.3 Transmitter Part.............................................................................................................. 15

3.3.1 Power Amplifier.......................................................................................................................... 15

3.3.2 Output Power Adjustment.......................................................................................................... 16

3.3.3 Modulation Schemes................................................................................................................. 16

3.3.4 ASK Modulation......................................................................................................................... 16

3.3.5 FSK Modulation ......................................................................................................................... 17

3.3.6 Crystal Tuning............................................................................................................................17

4 Description of User Modes......................................................................................18

4.1 Stand-alone User Mode Operation................................................................................. 18

4.1.1 Frequency Selection.................................................................................................................. 18

4.1.2 Operation Mode......................................................................................................................... 18

4.1.3 Modulation Type ........................................................................................................................ 19

4.1.4 LNA Gain Mode ......................................................................................................................... 19

4.2 Programmable User Mode Operation.............................................................................19

4.2.1 Serial Control Interface Description........................................................................................... 19

5 Register Description................................................................................................20

39010 07122 Page 2 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

5.1 Register Overview .......................................................................................................... 21

5.1.1

Default Register Settings for FS0, FS1...................................................................................... 21

5.1.2 A – word.....................................................................................................................................22

5.1.3 B – word.....................................................................................................................................23

5.1.4 C – word..................................................................................................................................... 24

5.1.5 D – word..................................................................................................................................... 25

6 Technical Data..........................................................................................................26

6.1 Absolute Maximum Ratings............................................................................................ 26

6.2 Normal Operating Conditions......................................................................................... 26

6.3 DC Characteristics.......................................................................................................... 27

6.4 PLL Synthesizer Timings................................................................................................ 29

6.5 AC Characteristics of the Receiver Part......................................................................... 29

6.6 AC Characteristics of the Transmitter Part..................................................................... 30

6.7 Serial Control Interface................................................................................................... 30

6.8 Crystal Parameters......................................................................................................... 30

7 Application Circuit Examples..................................................................................31

7.1 FSK Application Circuit Programmable User Mode (internal AFC option)...................... 31

7.2 FSK Application Circuit Stand-alone User Mode............................................................ 32

7.3 FSK Test Circuit Component List (Fig. 14 and Fig. 15).................................................. 33

7.4 ASK Application Circuit Programmable User Mode (normal data slicer option)............. 34

7.5 ASK Test Circuit Component List (Fig. 16)..................................................................... 35

7.6 ASK Application Circuit Programmable User Mode (peak detector option).................... 36

7.7 ASK Test Circuit Component List (Fig. 17)..................................................................... 37

8 Extended Frequency Range....................................................................................38

8.1 Board Component List (Fig. 18) ..................................................................................... 38

9 TX/RX Combining Network......................................................................................39

9.1 Board Component List (Fig. 19) ..................................................................................... 39

9.2 Typical LNA S-Parameters in Receive Mode ................................................................. 39

9.3 LNA Input Impedances in Transmit Mode ...................................................................... 40

10 Package Description................................................................................................41

10.1 Soldering Information ..................................................................................................... 41

11 Reliability Information..............................................................................................42

12 ESD Precautions......................................................................................................42

13 Disclaimer................................................................................................................. 44

39010 07122 Page 3 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

1 Theory of Operation

1.1 General

The main building block of the transceiver is a programmable PLL frequency synthesizer that is based on an
integer-N topology. The PLL is used for generating the carrier frequency during transmission and for
generating the LO signal during reception. The carrier frequency can be FSK-modulated either by pulling the
crystal or by modulating the VCO directly. ASK modulation is done by on/off keying of the power amplifier.
The receiver is based on the principle of a single conversion superhet. Therefore the VCO frequency has to
be changed between transmit and receive mode. In receive mode, the default LO injection type is low-side
injection.

The TH7122 transceiver IC consists of the following building blocks:

 Low-noise amplifier (LNA) for high-sensitivity

RF signal reception with switchable gain

 Mixer (MIX) for RF-to-IF down-conversion
 IF amplifier (IFA) to amplify and limit the IF

signal and for RSSI generation

 Phase-coincidence FSK demodulator with

external ceramic discriminator or LC tank

 Operational amplifier (OA1), connected to

demodulator output

 Operational amplifier (OA2), for general use
 Peak detector (PKDET) for ASK detection

 Control logic with 3wire bus serial control

interface (SCI)

 Reference oscillator (RO) with external crystal
 Reference divider (R counter)
 Programmable divider (N/A counter)
 Phase-frequency detector (PFD)
 Charge pump (CP)
 Voltage controlled oscillator (VCO) with internal

varactor

 Power amplifier (PA) with adjustable output

power

1.2 Technical Data Overview

 Frequency range: 300 MHz to 930 MHz in

programmable user mode

 Extended frequency range with external VCO

varactor diode: 27 MHz to 930 MHz

 315 MHz, 433 MHz, 868 MHz or 915 MHz fixed-

frequency settings in stand-alone mode

 Power supply range: 2.2 V to 5.5 V
 Temperature range: -40 °C to +85 °C
 Standby current: 50 nA
 Operating current in receive: 6.5 mA (low gain)
 Operating current in transmit: 12 mA (at -2 dBm)
 Adjustable RF power range: -20 dBm to +10dBm
 Sensitivity: -105 dBm at FSK with 180 kHz

IF filter BW

 Sensitivity: -107 dBm at ASK with 180 kHz

IF filter BW

 Max. data rate with crystal pulling: 20 kbps NRZ
 Max. data rate with direct VCO modulation:

115 kbps NRZ

 Max. input level: -10 dBm at FSK

and -20 dBm at ASK

 Input frequency acceptance: ± 10 to ± 150 kHz

(depending on FSK deviation)

 FM/FSK deviation range: ±2.5 to ±80 kHz
 Analog modulation frequency: max. 10 kHz
 Crystal reference frequency: 3 MHz to 12 MHz
 External reference frequency: 1 MHz to 16 MHz

1.3 Note on ASK Operation

Optimum ASK performance can be achieved by using an 8-MHz crystal for operation at 315 MHz, 434 MHz
and 915 MHz. For details please refer to the software settings shown in sections 7.4 and 7.6. FSK operation
is the preferred choice for applications in the European 868MHz band.

39010 07122 Page 4 of 44 Data Sheet
Rev. 010 Feb/09

V

1.4 Block Diagram

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

27

IN_LNA

26

OUT_PA

25

VEE_LNA

29

LNA

24

ASK

PA

PS_PA

GAIN_LNA

MIX

VCO

TNK_LO

32 31 1

IF

LO

N

counter

20

OUT_MIX

VCC_PLL

28 30

IN_MIX

OUT_LNA

21 18

IN_IFA

VEE_IF

LF

23 22

2

IFA

7

VCC_IF

R

counter
RO

EE_PLL

3

RSSI

1.5pF

RO

RO

10

IN_DEM

DemodulatorFSK

MIX

FSK

FSK_SW

FS1/LD

11 1 9 9

PKDET

SW1

VEE_RO

6

OUT_DEM

SW2

Control Logic

IN_DTA

ASK/FSK

RE/SCLK

16151312

200k

TE/SDT A

17

bias

OA2

OA1

4

INT2/PDO

5

INT1

8

OUT_DTA

SCI

SCLK

SDTASDEN

FS0/SDEN

VEE_DIG14VCC_DIG

Fig. 1: TH7122 block diagram

1.5 User Mode Features

The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled
programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Stand­alone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to V
order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz,

433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up
in order to remain in fixed-frequency mode.

After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode
(PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins
FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the
3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer.

A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two
idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL
settings for the PLL idle mode are taken over from the last operating mode which can be either receive or
transmit mode.

The different operating modes can be set in SUM and PUM as well. In SUM the user can program the trans­ceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select the
modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI.

or VCC in

EE

39010 07122 Page 5 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

2 Pin Definitions and Descriptions

Pin No. Name I/O Type Functional Schematic Description

1 IN_IFA input

2 VCC_IF supply

3 IN_DEM analog I/O

4 INT2/PDO output

IN_IFA

1

VCC

IN_DEM

3

VEE

INT2/PDO

VCC VCC

2.2k

50

140µA

VEEVEE

VCC

90k

60k

1.5p
10µA

VCC

100µA

VEE

IF amplifier input, approx.
2 kΩ single-ended

positive supply of LNA, MIX,
IFA, FSK Demodulator, PA,
OA1 and OA2

IF amplifier output and de­modulator input, connection
to external ceramic discrimi­nator or LC tank

OA2 output or peak detector
output, high impedance in
transmit and idle mode

5 INT1 input

INT1

5

6 OUT_DEM analog I/O

bias

7 RSSI output

OA2

VCC

120

VEE

RSSI

7

4

VEE

200k

VCC

inverting inputs of OA1 and
OA2

+

OA1

VCC

VCC

550k

550k

120

10p

1k

VEE

120

120

10p

31k

OUT_DEM

6

demodulator output and
non-inverting OA1 input,

high impedance in transmit
and idle mode

RSSI output, approx. 31 kΩ

VEE

39010 07122 Page 6 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

Pin No. Name I/O Type Functional Schematic Description

8 OUT_DTA output

VCC

OUT_DTA

8

OA1 output, high impedance
in transmit and idle mode

9 VEE_RO ground

10 RO analog I/O

11 FSK_SW analog I/O

12 IN_DTA input

13 ASK/FSK input

RO

10

FSK_SW

IN_DTA

12

VEE

ground of RO

2.6µA

36p

39k

VCC

VEE

VCC

36p

RO input, base of bipolar
transistor

FSK pulling pin, switch to
ground or OPEN

The switch is open in re-

11

VEE

VCC

ceive and idle mode

ASK/FSK modulation data
input, pull down resistor

120

120k

VEE

VCC

120kΩ

ASK/FSK mode select input

14 VCC_DIG supply

ASK/FSK

13

VEE

120

positive supply of serial port
and control logic

15 RE/SCLK input

VCC

receiver enable input / clock
input for the shift register,

RE/SCLK

15

16 TE/SDTA input

VCC

120k

VEE

120

pull down resistor 120kΩ

transmitter enable input /
serial data input, pull down

TE/SDTA

16

120k

VEE

120

resistor 120kΩ

39010 07122 Page 7 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

Pin No. Name I/O Type Functional Schematic Description

17 FS0/SDEN input

FS0/SDEN

17

VCC

120

frequency select input / se­rial data enable input

18 VEE_DIG ground

19 FS1/LD

input /
output

20 VCC_PLL analog I/O

21 TNK_LO analog I/O

TNK_LO

21

VCC

LF

23

23 LF analog I/O

22 VEE_PLL ground

24 PS_PA analog I/O

VEE

VCC

FS1/LD

19

VEE

6.3pF

VEE

6.5k

VCC

120

VEE

VCC VCC

10µA

120

VD

VCOCUR

VEE

VCC_PLL

20

VEE

ground of serial port and
control logic

frequency select input / lock
detector output

VCO open-collector output,
connection to VCC or exter­nal LC tank

VCO open-collector output,
connection to external LC
tank

charge pump output, con­nection to external loop filter

ground of PLL frequency
synthesizer

power-setting input

PS_PA

24

25 OUT_PA output

OUT_PA

120

VEE VEE

25

20p

VEE VEE

VCC

1k

power amplifier open­collector output

39010 07122 Page 8 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

C

27 to 930MHz

FSK/FM/ASK Transceiver

Pin No. Name I/O Type Functional Schematic Description

27 VEE_LNA ground

28 OUT_LNA output

26 IN_LNA input

OUT_LNA

bias

37

3.8k

IN_LNA

28

VEE

ground of LNA and PA

LNA open-collector output,
connection to external LC
tank at RF

LNA input, single-ended

29 GAIN_LNA input

30 IN_MIX input

31 VEE_IF ground

32 OUT_MIX output

26

GAIN_LNA

IN_MIX

30

29

VEE

VCC

210

LO

VEE VEE

OUT_MIX

120

VC

100

VCC

0.8p

VEEVEE

LNA gain control input

mixer input, approx. 200Ω
single-ended

bias

ground of IFA, Demodulator,
OA1 and OA2

mixer output, approx. 330Ω
single-ended

32

VEE

39010 07122 Page 9 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

3 Functional Description

3.1 PLL Frequency Synthesizer

The TH7122 contains an integer-N PLL frequency synthesizer. A PLL circuit performs the frequency synthe­sis via a feedback mechanism. The output frequency f
detector comparison frequency f

of a crystal oscillator. The phase detector utilizes this signal as a reference to tune the VCO and in the

f

RO

.This reference frequency fR is generated by dividing the output frequency

R

locked state it must be equal to the desired output frequency, divided by the feedback divider ratio N.

Reference

Oscillator

f

RO

Reference

Divider

Phase-frequency

Detector

f

R

Charge

Pump

f

N

Fig. 2: Integer-N PLL Frequency Synthesizer Topology

The output frequency of the synthesizer f

can be selected by programming the feedback divider and the

VCO

reference divider. The only constraint for the frequency output of the system is that the minimum frequency
resolution, or the channel spacing, must be equal to the PFD frequency f
frequency f

and the reference divider factor R:

RO

f

RO

f

R

. (1)

=

R

When the PLL is unlocked (e.g. during power up or during reprogramming of a new feedback divider ratio N),
the phase-frequency detector PFD and the charge pump create an error signal proportional to the phase
difference of the two input signals. This error signal is low-pass filtered through the external loop filter and
input to the VCO to control its frequency. A very low frequency resolution increases the settling time of the
PLL and reduces the ability to cancel out VCO perturbations, because the loop filter is updated every 1/f
After the PLL has locked, the VCO frequency is given by the following equation:

f

VCO

RO

N f ⋅=⋅=

R

fN

There are four registers available to set the VCO frequencies in receive (registers RR and NR) and in trans­mit mode (registers RT and NT). These registers can be programmed using the Serial Control Interface in
Programmable User Mode (PUM). In case of Stand-alone User Mode (SUM), the registers are set fixed val­ues (refer to para. 4.1.1).

The VCO frequency is equal to the carrier frequency in transmit mode. While in receive mode the VCO
frequency is offset by the intermediate frequency IF. This is because of the super-heterodyne nature of the
receive part.

is generated as an integer multiple of the phase

VCO

VCC

External

Loop Filter

LF

Feedback

Divider

. (2)

R

Voltage Controlled

Oscillator

, which is given by the reference

R

f

VCO

.

R

39010 07122 Page 10 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

⋅

≤

≤

27 to 930MHz

FSK/FM/ASK Transceiver

3.1.1 Reference Oscillator (XOSC)

The reference oscillator is based on a Colpitts topology with two integrated functional capacitors as shown in
figure 3. The circuitry is optimized for a load capacitance range of 10 pF to 15 pF. The equivalent input
capacitance CRO offered by the oscillator input pin RO is about 18pF.

XTAL

CX2

CX1

RO

FSKSW

36pF

VCC

VEE

I

RO

36pF

To ensure a fast and reliable start-up and a very stable frequency
over the specified supply voltage and temperature range, the
oscillator bias circuitry provides an amplitude regulation. The am­plitude on pin RO is monitored in order to regulate the current of
the oscillator core I

. There are two limits ROMAX and ROMIN

RO

between the regulation is maintained. These values can be
changed via serial control interface in Programmable User Mode
(PUM). In Stand-alone User Mode (SUM), ROMAX and ROMIN
are set to default values (refer to para. 5.1.3). ROMAX defines the
start-up current of the oscillator. The ROMIN value sets the de­sired steady-state current. If ROMIN is sufficient to achieve an
amplitude of about 400 mV on pin RO, the current I

will be set

RO

to ROMIN. Otherwise the current will be permanently regulated
between ROMIN and ROMAX. If ROMIN and ROMAX are equal,
no regulation takes place. For most of the applications ROMIN
and ROMAX should not be changed from default.

Fig. 3: Reference oscillator circuit

3.1.2 Reference Divider

The reference divider provides the input signal of the phase detector by dividing the signal of the reference
oscillator. The range of the reference divider is

1023R4 ≤≤ . (3)

3.1.3 Feedback Divider

The feedback divider of the PLL is based on a pulse-swallow topology. It contains a 4-bit swallow A-counter,
a 13-bit program B-counter and a prescaler. The divider ratio of the prescaler is controlled by the program
counter and the swallow counter. During one cycle, the prescaler divides by 17 until the swallow A-counter
reaches its terminal count. Afterwards the prescaler divides by 16 until the program counter reaches its
terminal count. Therefore the overall feedback divider ratio can be expressed as:

+⋅= . (4)

The A-counter configuration represents the lower bits in the feedback divider register (N
upper bits the B-counter configuration (N

4-16

= B

ranges are implemented:

15A0 ≤≤ ; 8191B4

and therefore the range of the overall feedback divider ratio results in:

A)-(B16A17N

= A

) respectively. According to that, the following counter

0-12

0-3

whereas > A (5) B

) and the

0-3

131071N64 ≤≤ . (6)

The user does not need to care about the A- and B-counter settings. It is only necessary to know the overall
feedback divider ratio N to program the register settings.

3.1.4 Frequency Resolution and Operating Frequency

It is obvious from (2) that, at a given frequency resolution fR, the maximum operating frequency of the VCO is
limited by the maximum N-counter setting. The table below provides some illustrative numbers. Please also
refer to section 4.4.1 for the pre-configured settings in Stand-alone User Mode (SUM).

39010 07122 Page 11 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

Crystal

frequency fRO

3.0000MHz 2.93kHz 1023 13107 38.437MHz

3.0000MHz 2.93kHz 1023 131071 384.372MHz

8.0000MHz 12.5kHz 640 35812 447.65MHz

8.0000MHz 25kHz 320 34746 868.65MHz

8.0000MHz 250kHz 32 3660 915.0MHz

3.1.5 Phase-Frequency Detector

The phase-frequency detector creates an error voltage proportional to the phase difference between the
reference signal f
is very useful because it decreases the acquisition time significantly. The gain of the phase detector can be
expressed as:

where ICP is the charge pump current which is set via register CPCUR. In the TH7122 design the VCO
frequency control characteristic is with negative polarity. This means the VCO frequency increases if the loop
filter output voltage decreases and vice versa. When an external varactor diode is added to the VCO tank,
the tuning characteristic can be changed between positive and negative depending on the particular varactor
diode circuitry. Therefore the PDFPOL register can be used to define the phase detector polarity.

and fN. The implementation of the phase detector is a phase-frequency type. That circuitry

R

Frequency

resolution fR

I

= , (7)

K

PD

CP

R

counter

N

counter

Operating

frequency f

VCO

π2

3.1.6 Lock Detector

In Programmable User Mode a lock-detect signal LD is available at pin FS1/LD (pin 19). The lock detection
circuitry uses Up and Down signals from the phase detector to check them for phase coherency. Figure 4
shows an overview of the lock signal generation. The locked state and the unlock condition will be decided
on the register settings of LDTM and ERTM respectively. In the start-up phase of the PLL, Up and Down
signals are quite unbalanced and counter CNT_LD receives no clock signal. When the loop approaches
steady state, the signals Up and Down begin to overlap and CNT_LD counts down. Herein register LDTM
sets the number of counts which are necessary to set the lock detection signal LD. If an unlock condition
occurs, the counter CNT_LD will be reloaded and therefore its CARRY falls back.

LDTM [1 : 0]

Up

Down

PFD

ERTM [1 : 0]

2

&

&

D

CR

LOAD

CNT_LD

CARRY

=

2

D

CARRY

F

RO

&

RO

CR

LOAD

CNT_ER

Control

Logic

RESET LD

S

LOCKMODE

QR

MUX

Fig. 4: Lock Detection Circuit

LD

39010 07122 Page 12 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

V

27 to 930MHz

FSK/FM/ASK Transceiver

The CNT_ER supervises the unlock condition. If Up and Down are consecutive, the counter CNT_ER will be
reloaded permanently and its CARRY will not be set, otherwise the counter level of CNT_ER will be reduced
by the reference oscillator clock (1/f
during Up and Down signals can be non-consecutive without loosing the locked state.
The transceiver offers two ways of analyzing the locked state. If the register LOCKMODE is set to ‘0’, only
one occurrence of the locked state condition is needed to remain LD = 1 during the whole active mode, oth­erwise the state of the PLL will be observed permanently.

3.1.7 Voltage Controlled Oscillator with external Loop Filter

The transceiver provides a LC-based voltage-controlled oscillator with an
external inductance element connected between VCC and pin TNK_LO.
An internal varactor diode in series with a fixed capacitor forms the vari­able part of the oscillator tank. The oscillation frequency is adjusted by
the DC-voltage at pin LF. The tuning sensitivity of the VCO is approxi­mately 20MHz/V for 433MHz operations and 40MHz/V at 868MHz. Since
the internal varactor is connected to VCC, a lower voltage on pin LF
causes the capacitance to decrease and the VCO frequency to increase.
For this reason the phase detector polarity should be negative (PFDPOL
= 0). If the operation frequency is below 300MHz, an external varactor
diode between pin TNK_LO and VCC_PLL is necessary. The corre­sponding application schematic is shown in section 8. The VCO current
VCOCUR can be adjusted via serial control interface in order to ensure
stable oscillations over the whole frequency range. For lowest LO emis­sion in receive mode, VCOCUR should be set to the lowest value.

). The register ERTM decides on the maximum number of clocks

RO

VCC

External

Loop Filter

TNK_LO LF

6.3pF

VCC_PLL

VD

+

Charge Pump

VCOCUR

VEE

Fig. 5: VCO schematic

3.1.8 Loop Filter

Since the loop filter has a strong impact on the function of the PLL, it
must be chosen carefully. For FSK operation the bandwidth of the loop
filter must be selected wide enough for a fast relock of the PLL during
crystal pulling. The bandwidth must of course also be larger than the data
rate. In case of ASK or OOK the bandwidth should be extended even
further to allow the PLL to cancel out VCO perturbations that might be
caused by the PA on/off keying. The suggested filter topology is shown in
Fig. 6. The dimensions of the loop filter elements can be derived using
well known formulas in application notes and other reference literature.

Fig. 6: 2

nd

order Loop filter

RF

CF1

CO

VCC

CF2

LF

+

3.2 Receiver Part

The RF front-end of the receiver part is a super-heterodyne configuration that converts the input radio­frequency (RF) signal into an intermediate frequency (IF) signal. The most commonly used IF is 10.7 MHz,
but IFs in the range of 0.4 to 22 MHz can also be used. According to the block diagram, the front-end con­sists of a LNA, a Mixer and an IF limiting amplifier with received signal strength indicator (RSSI). The local
oscillator (LO) signal for the mixer is generated by the PLL frequency synthesizer.
As the receiver constitutes a superhet architecture, there is no inherent suppression of the image frequency.
It depends on the particular application and the system’s environmental conditions whether an RF front-end
filter should be added or not. If image rejection and/or good blocking immunity are relevant system parame­ters, a band-pass filter must be placed either in front or after the LNA. This filter can be a SAW (surface
acoustic wave) or LC-based filter (e.g. helix type).

39010 07122 Page 13 of 44 Data Sheet
Rev. 010 Feb/09

TH7122

27 to 930MHz

FSK/FM/ASK Transceiver

3.2.1 LNA

The LNA is based on a cascode topology for low-noise, high gain and good reverse isolation. The open col­lector output has to be connected to an external resonance circuit which is tuned to the receive frequency.
The gain of the LNA can be changed in order to achieve a high dynamic range. There are two possibilities for
the gain setting which can be selected by the register bit LNACTRL. External control can be done via the pin
GAIN_LNA, internal control is given by the register bit LNAGAIN. In case of external gain control, a hystere­sis of about 340 mV can be chosen via the register bit LNAHYST. This configuration is useful if an automatic
gain control loop via the RSSI signal is established. In transmit mode the LNA-input is shorted to protect the
amplifier from saturation and damaging.

3.2.2 Mixer

The mixer is a double-balanced mixer which down converts the receive frequency to the IF. The default LO
injection type is low side (f
the data signal´s polarity is inverted due to the mixing process. To avoid this, the transmitted data stream can
be inverted too by setting DTAPOL to ‘1’.
The output impedance of the mixer is about 330Ω in order to match to an external IF filter.

= fRX – fIF). But also high side injection is possible (f

VCO

3.2.3 IF Amplifier

After passing the channel select filter which sets the IF bandwidth the signal is limited by means of an high
gain limiting amplifier. The small signal gain is about 80 dB. The RSSI signal is generated within the IF ampli­fier. The output of the RSSI signal is available at pin RSSI. The voltage at this pin is proportional to the input
power of the receiver in dBm. Using this RSSI output signal the signal strength of different transmitters can
be distinguished.

= fRX + fIF). In this case,

VCO

3.2.4 ASK Demodulator

The receive part of the TH7122 allows for two ASK demodulation configurations:

• standard ASK demodulation or

• ASK demodulation with peak detector.

The default setting is standard ASK demodulation. In this mode SW1 and SW2 are closed and the RSSI
output signal directly feeds the data slicer setup by means of OA1. The data slicer time constant equals to

C3200kT ⋅Ω= , (8)

with C3 external to pin INT1. This time constant should be larger than the longest possible bit duration of the
data stream. This is required to properly extract the ASK data’s DC level. The purpose of the DC (or mean)
level at the negative input of OA1 is to set an adaptive comparator threshold to perform the ASK detection.

Alternatively a peak detector can be used to define the ASK detection threshold. In this configuration the
peak detector PKDET is enabled, SW1 is closed and SW2 is open, and the peak detector output is multi­plexed to pin INT2/PDO. This way the peak detector can feed the data slicer, again constituted by OA1 and a
few external R and C components. The peak detection mode is selectable in programmable user mode.

39010 07122 Page 14 of 44 Data Sheet
Rev. 010 Feb/09