Table 5-1. DAC Selection and Update Mode
No write function if S3 setUpdate All DACsXXX1
Latch new D/A Value for DAC7Update DAC6 & 71110
Latch new D/A Value for DAC6Update DAC6 & 70110
Latch new D/A Value for DAC5Update DAC4 & 51010
Latch new D/A Value for DAC4Update DAC4 & 50010
Latch new D/A Value for DAC3Update DAC2 & 31100
Latch new D/A Value for DAC2Update DAC2 & 30100
Latch new D/A Value for DAC1Update DAC0 & 11000
Latch new D/A Value for DAC0Update DAC0 & 10000
Function on Base + 0,
Base + 1 Write
Function on
Base + 0 Read
S0S1S2S3
S3: Setting the S3 bit to 1 enables simultaneous update mode. Setting S3 to 0
updates the DACs in pairs.
Note that DACs are always updated in pairs if S3 is set to 0. For example, if you latch
new data to DAC1, then update the DAC0 and DAC1 pair, DAC1 updates with the
new value and DAC0 updates with the same value as before since the latch (data for
output) has not changed.
If S3 is set to 1, a read from the base +0 register will simultaneously update all eight
DACs with the data previously latched to the DAC registers.
CLR: Setting the CLR bit to 1 resets all eight DAC outputs to 0V. Default and
normal operation is CLR = 0, which has no effect on the DAC outputs.
BASE + 3 - Digital I/O (8 bits)
DIO0DIO1DIO2DIO3DIO4DIO5DIO6DIO7
01234567
WRITE: Updates output of DIO bits set for output.
READ: Reads current status of DIO bits for input. Reads back output state of DIO
bits set for output.
BASE + 4 - Interrupt Control & Digital I/O Direction Control
LDIRUDIRINT_ENINTREQ
XXXX
01234567
WRITE: Set control bits.
READ: Read status of control bits.
INTREQ Default is no interrupt has occurred = 0. When set to 1 an interrupt has
occurred.
External interrupts, when enabled, occur at TTL falling edge.
A read of base + 1 clears this bit.
7