CIO-DAS16/M1/16
High Speed Analog Inputs
& Digital I/O
User’s Guide
Revision 4
November, 2000
LIFETIME WARRANTY
Every hardware product manufactured by Measurement Computing Corp. is warranted against defects in
materials or workmanship for the life of the product, to the original purchaser. Any products found to be
defective will be repaired or replaced promptly.
LIFETIME HARSH ENVIRONMENT WARRANTY
TM
Any Measurement Computing Corp. product which is damaged due to misuse may be replaced for only
50% of the current price. I/O boards face some harsh environments, some harsher than the boards are
designed to withstand. When that happens, just return the board with an order for its replacement at only
50% of the list price. Measurement Computing Corp. does not need to profit from your misfortune. By the
way, we will honor this warranty for any other manufacture’s board that we have a replacement for!
30 DAY MONEY-BACK GUARANTEE
Any Measurement Computing Corp. product may be returned within 30 days of purchase for a full refund of
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even if Measurement Computing Corp. has been notified in advance of the possibility of such damages.
MEGA-FIFO, the CIO prefix to data acquisition board model numbers, the PCM prefix to data acquisition
board model numbers, PCM-DAS08, PCM-D24C3, PCM-DAC02, PCM-COM422, PCM-COM485,
PCM-DMM, PCM-DAS16D/12, PCM-DAS16S/12, PCM-DAS16D/16, PCM-DAS16S/16,
PCI-DAS6402/16, Universal Library, InstaCal, Harsh Environment Warranty and Measurement Computing
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President of Measurement Computing Corp. Life support devices/systems are devices or
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Measurement Computing Corp. products are not designed with the components required,
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© Copyright 2000, Measurement Computing Corp
HM CIO-DAS16_M1_16.lwp
Table of Contents
1 INTRODUCTION
2 INSTALLATION
................................................................
................................................................
3 SIGNAL CONNECTIONS
4 SOFTWARE
5 REGISTER MAP
..................................................................
................................................................
6 CALIBRATION AND TEST
7 SPECIFICATIONS
.............................................................
......................................................
.....................................................
1
1
12.1 SOFTWARE ...................................................................
12.2 HARDWARE ..................................................................
2
23.1 ANALOG CONNECTOR DIAGRAM ...............................................
33.2 ANALOG INPUTS ..............................................................
33.3 CONNECTING SIGNALS TO THE ANALOG INPUTS .................................
33.3.1 KEEP HIGH AND LOW WIRES TOGETHER .....................................
33.3.2 SHIELDING ...............................................................
33.3.3 GROUNDED SIGNAL SOURCE ...............................................
43.3.4 FLOATING SIGNALS .......................................................
43.3.5 AVOID GROUND LOOPS ....................................................
53.4 DIGITAL OUTPUTS & INPUTS ...................................................
63.5 DIGITAL I/O CONNECTOR ......................................................
63.6 DT-CONNECT .................................................................
8
84.1 CUSTOM SOFTWARE UTILIZING THE UNIVERSAL LIBRARY ......................
84.2 FULLY INTEGRATED SOFTWARE PACKAGES (e.g. SoftWIRE) .......................
84.3 DIRECT REGISTER LEVEL PROGRAMMING ......................................
9
95.1 DAS16/M1/16 REGISTER MAP ...................................................
95.2 A/D DATA WORD REGISTER ....................................................
105.3 CHANNEL MUX HI/LO LIMITS WORD REGISTER .................................
105.4 8-BIT DIGITAL I/O REGISTERS .................................................
115.5 STATUS REGISTER ...........................................................
115.6 INTERRUPT AND PACER CONTROL REGISTER ..................................
135.7 BURST LENGTH, EXTERNAL TRIGGER, CTR0/TRG0 ..............................
135.8 COUNTER, GAIN/RANGE CONTROL ............................................
145.9 8254 DATA AND CONTROL REGISTERS .........................................
155.10 82C55 DIGITAL I/O DATA AND CONTROL REGISTERS ...........................
16
17
This page is blank.
1 INTRODUCTION
CIO-DAS16/M1/16 sets the standard for high speed, 16-bit data acquisition boards for ISA bus compatible computers.
The board provides 8 fully differential input channels with a variety of software programmable input ranges. The
board will transfer a full 1 million samples per second to Measurement Computing’s MEGA-FIFO memory board, and
directly over the ISA bus when used in high speed (200 MHz+) Pentium™ computers.
The board supports a variety of trigger modes. Triggers may be edge based on falling/rising or high/low states. The
board also provides 32-bits of digital I/O (24-bits CMOS, 8-bits TTL).
The CIO-DAS16/M1/16 is fully supported by the Universal Library® package which supplies a language interface for
all Windows and DOS based programming languages. The board includes the helpful InstaCal® installation, test and
calibration software package. The CIO-DAS16/M1/16 is also supported by a wide variety of third party data
acquisition and analysis software packages such as SoftWIRE.
2 INSTALLATION
2.1 SOFTWARE
The board has only one set of switches to set before installing the board in your computer. By far the simplest way to
configure your board is to use the InstaCal
TM
program provided as part of your software package. InstaCalTM will
show you any available options and how to configure the switches to match your application requirements. It will
create a configuration file that your application software (and the Universal Library) will refer to so the software you
use will automatically know the exact configuration of the board.
Please refer to the Software Installation Manual regarding the installation and operation of InstaCal
TM
. The following
hard copy information is provided as a matter of completeness, and will allow you to set the hardware configuration of
the board if you do not have immediate access to InstaCal
2.2 HARDWARE
BASE ADDRESS
Unless there is already a board in your system using address
300h, leave the switches as they are set at the factory.
In Figure 2-1 at right, the board is set at base address 300h.
TM
and/or your computer.
9876
5
4
SW
A9
A8
A7
A6
A5
A4
HEX
200
100
80
40
20
10
BASE ADDRESS SWITCH
Figure 2-1. Base Address Switches
1
- Address 300H shown here.
3 SIGNAL CONNECTIONS
There are two connectors on the CIO-DAS16/M1/16. The 37-pin connector which extends through the mounting plate
and extends out the rear of the PC is primarily for analog signals, and is referred to as the analog connector. The
40-pin header connector at the rear of the board carries the 24 digital I/O and is referred to as the digital connector.
3.1 ANALOG CONNECTOR DIAGRAM
The analog connector is a 37-pin, D-type connector, accessible from the rear of the PC through the expansion
backplate (Figure 3-1). With the exception of the missing D/A signals, the signals available are identical to the
CIO-DAS16.
The connector accepts female 37-pin, D-type connectors, such as those on the C73FF-2, a 2-foot cable with
connectors. If frequent changes to signal connections or signal conditioning is required, please refer to the information
on the CIO-TERMINAL or CIO-MINI37 screw terminal boards.
EXT TRIG/GATE/DIG.IN 1
Figure 3-1. Analog Connector
2
3.2 ANALOG INPUTS
Connect analog inputs to the board as shown in the following sections. Pay close attention to cabling and grounding
of the shield. Failure to cable as shown
will likely result in signal noise
.
CAUTION - PLEASE READ
TIP: Measure the voltage between the ground signal at the signal source and the PC. Use a volt meter and place the
red probe on the PC ground and the black probe on the signal ground. If there is more than 10 Volts, do not connect
to this signal source because you will not be able to make a valid reading. If the voltage is over 20 Volts, DO NOT
connect to this signal because it will damage the board and possibly the computer.
3.3 CONNECTING SIGNALS TO THE ANALOG INPUTS
Signal wiring should be done with consideration for the high speed sampling involved. Even if your A/D pacing rate
is not high, the converter is always converting in under 1uS and the internal MUX switching is done at similarly high
speeds. Close attention must be paid to how analog signals are connected to the board.
The CIO-DAS16/M1/16 has eight differential analog input channels. Each channel has a signal high input and a
signal low input. The measurement made by the A/D is the voltage difference between the LOW and HIGH inputs.
Differential inputs have a common mode range (see application note). The CIO-DAS16/M1/16 may have as much as
+11V or -6V of common mode between LLGND and signal LOW.
3.3.1 KEEP HIGH AND LOW WIRES TOGETHER
Keep the signal wires for a channel together. As a minimum, use twisted pair. This will reduce EMI or RFI noise on
your input signal.
3.3.2 SHIELDING
To further protect the input signals from noise, a use shielded wire. Shielded twisted pair is readily available. The
shield should be connected as shown in the diagrams below otherwise ground loops and signals noise may result.
3
3.3.3 GROUNDED SIGNAL SOURCE
S
C
C
C
L
G
S
C
L
A grounded signal source is defined as having the signal low referenced to chassis ground. If an instrument has only
two poles, HI and LOW, it is probably referenced to chassis ground internally. It is easy to check with an Ohmmeter
between LOW and the power cord ground prong. If an instrument has three poles, a HI, LOW and GND then you can
strap LO to GND as shown in Figure 3-2, or use the connection for Floating Signal Source.
IO-DAS16/M1/16
Instrument
Shielded Cable
Signal High
ignal Low
Tie Low to GND
hannel # High
hannel # Low
ND
GROUNDED SIGNAL SOURCE - Suggested way to connect
signal and cable shield. Ground is completed through
power ground. Voltage between outlet grounds not to
exceed the common mode range.
LGND
Figure 3-2. Recommended Cabling Method
3.3.4 FLOATING SIGNALS
A floating signal source is defined as having the signal low with no reference to earth ground (PC Chassis ground or
LLGND). Examples are a battery, an isolated precision power supply or a sensor which is not earth grounded.
A reference between signal LOW and LLGND must be provided because the CIO-DAS16/M1/16 inputs are
differential. Failure to supply the reference resistor (10K) will result in unrepeatable readings (Figure 3-3).
hielded
CIO-DAS16/M1/16
able
Signal High
Signal Low
Channel # High
Channel # Low
FLOATING SIGNAL SOURCE - Suggested way to connect signals
and cable shield. Connection is made to Earth ground through
power ground.
Figure 3-3. Recommended Method for Connecting Floating Signals
10K
LGND
4
3.3.5 AVOID GROUND LOOPS
C
C
C
L
Figure 3-4 shows the wrong way to connect a shielded cable. It creates a ground loop. Any current flowing between
grounds can interfere with your readings.
Instrument
Shielded Cable
Signal High
Signal Low
Ground Loop Created Here
WRONG WAY! - This is the wrong way to connect cable shield.
IO-DAS16/M1/16
hannel # High
hannel # Low
LGND
Figure 3-4. The Wrong Way to Connect a Shielded Cable
3.4 DIGITAL OUTPUTS & INPUTS
All the digital outputs and inputs on main I/O connector are TTL level. The binary logic inside the PC is all TTL or
LSTTL (Low power Schotky TTL).
If you desire to control or sense any device other than TTL IC chips, please use appropriate signal conditioning, such
as solid state relays or electromechanical relays. See the Measurement Computing catalog for SSR-RACK24 and
CIO-ERB24 interface accessories.
5
3.5 DIGITAL I/O CONNECTOR
39NC37GND35+5V33GND31N
29G
27NC25GND23NC21GND19P
17P
15P
13P
11P
9
P
7
P
5
P
3
N
1
A second connector at the rear of the board contains signals from
an 82C55
. These 24 bits of digital I/O are available
for on/off control, switch monitoring or other digital interface tasks. The connector and register alignment is identical
to that of the CIO-DIO24.
The 40-pin header (Figure 3-5) at the rear of the board is pinned out such that when connected to a 37-pin connector
via a BP40-37, the 37 pin connector's pinouts are identical to that of the CIO-DIO24. We recommend using a
BP40-37 to provide access to the 24 bits of digital I/O on the back panel
Figure 3-6 is the pin out of a BP40-37 when connected to the 40-pin digital connector.
NC 40
NC 38
PORT A0 36
PORT A1 34
PORT A2 32
PORT A3 30
PORT A4 28
PORT A5 26
PORT A6 24
PORT A7 22
PORT C0 20
PORT C1 18
PORT C2 16
PORT C3 14
PORT C4 12
PORT C5 10
PORT C6 8
PORT C7 6
GND
4
+5V 2
C
ND
ORT B0
ORT B1
ORT B2
ORT B3
ORT B4
ORT B5
ORT B6
ORT B7
C
NC
Figure 3-5 Digital Connector Pinout Figure 3-6. BP40-37 Pinout
3.6 DT-CONNECT
There is no hardware configuration or installation required for DT-Connect. Software enables/disables DT-Connect,
and of course, you must have a DT-Connect equipped accessory board before using the DT-Connect.
3.6.1 DT-CONNECT IN MASTER MODE ONLY
The CIO-DAS16/M1/16 implements DT-Connect MASTER MODE only. DT-Connect is always enabled and is never
busy. The ENABLED and BUSY signal levels are fixed in hardware. Since DT-Connect is always enabled, any A/D
conversions are always transferred out the DT-Connect regardless of the bus transfer method specified. The
CIO-DAS16/M1/16 can only operate in DT-Connect schemes where it is the sole master.
To assure that DT-Connect is properly initialized prior to any A/D transfer, the DT-Connect DT-Request handshake
line is reset each time the programmable gain (Base + 11) register is written to. Therefore, it is not possible to use the
DT-Connect for A/D sets which involve setting the gain between samples. This is not really a problem because any
6
such scheme would be low speed and therefore store data to disk, obviating the need to use DT-Connect to store data
on a memory board.
Please see the data sheet on the MEGA-FIFO, Measurement Computing’s 128 million sample buffer board as an
example of a DT-Connect
accessory.
7
4 SOFTWARE
There are three common methods for generating software for the CIO-DAS16/M1/16. These are: Writing custom
software using our Universal Library package, using a fully integrated software package (e.g. SoftWIRE), or doing
direct, register-level programming.
4.1 CUSTOM SOFTWARE UTILIZING THE UNIVERSAL LIBRARY
Many users write custom software using Universal Library. The Universal Library takes care of all the board I/O
commands and lets you concentrate on the application part of the software. For additional information regarding using
the Universal Library, please refer to the documentation supplied with the Universal Library.
TM
Insta
calibrate your data acquisition board.
the Universal Library
4.2 FULLY INTEGRATED SOFTWARE PACKAGES (e.g. SoftWIRE)
is a complete installation, calibration and test package. Use it to guide the installation procedure and to
Cal
InstaCal also creates a configuration file required for programmers who use
.
Many customers now take advantage of the power and simplicity offered by one of the most powerful upper level data
acquisition packages available. Please refer to SoftWIRE’s documentation for setup and usage details.
4.3 DIRECT REGISTER LEVEL PROGRAMMING
For advanced programmers, we provide a detailed register mapping information in Chapter 5.
8
5.1 DAS16/M1/16 REGISTER MAP
Table 5-1. DAS16/M1/16 Register Descriptions
5 REGISTER MAP
WRITE FUNCTIONREAD FUNCTIONADDRESS
Software Start A/D ConversionA/D Data - 16 bits BASE
Not UsedNot UsedBASE + 1
Channel Mux read/Reset FIFOChannel Mux SetBASE + 2
Digital Output Bits 0 to 3ID, Digital In 0 to 3, External ControlBASE + 3
Not UsedNot UsedBASE + 4
Not UsedNot UsedBASE + 5
Not UsedNot UsedBASE + 6
Not UsedNot UsedBASE + 7
Clear the interruptStatus, Mux settingBASE + 8
Interrupt selection, Pacer/triggerInterrupt Enable/select, Pacer/triggerBASE + 9
Burst Length, Trigger, CTR1/TRG0 Burst Length, Trigger, CTR1/TRG0BASE + 10
Gain/Range Control, Res CTRGain/Range status, FFNE, Res CTRBASE + 11
Counter 0 Data - Residual CounterCounter 0 Data - Residual CounterBASE +12
Counter 1 Data - A/D PacerCounter 1 Data - A/D Pacer ClockBASE +13
Counter 2 Data - A/D PacerCounter 2 Data - A/D Pacer ClockBASE + 14
Pacer Clock (8254) ControlNone. No read back on 8254BASE +15
8255 Port A Data8255 Port A DataBASE+400h
8255 Port B Data8255 Port B DataBASE+401h
8255 Port C Data8255 Port C DataBASE+402h
8255 Control RegisterNone. No 8255 Read-backBASE+403h
The register map shown above is 8-bit transfers, except for BASE + 1 which is the A/D data register. It is for 16-bit
transfers only. This permits high-speed REP-INSW operation.
5.2 A/D DATA WORD REGISTER
BASE + 0 Example, 300h, 768 Decimal
0132456789101112131415
AD15
MSB
AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14
AD0
LSB
A read/write register. The A/D Data Register is configured as a word because REP INSW can be used to quickly read
data from the board, allowing for higher A/D conversion rates than would be possible if using DMA, which accesses
the A/D data as two bytes.
9
READ
On read, the 16-bit ADC value is presented in 'left-justified' format, with the most-significant ADC bit at position
#15; the least significant ADC bit at position #0 of the data word.
WRITE
A write to the base address causes an A/D conversion, (Bits “0” and “1” of BASE+9 must be “0”.)
Also, the write to base address acts as an Internal Trigger to start conversions if the method of converting is External
or Internal Pacer.
5.3 CHANNEL MUX HI/LO LIMITS WORD REGISTER
BASE ADDRESS +2 Example, 302h, 770 Decimal
01324567
CH1LCH2LCH4LCH8LCH1HCH2HCH4HCH8H
This register functions the same as DAS1600 products in 8-channel differential mode. The channel mux setting is
written and read from in this register. To configure the channels to convert, the upper nibble sets the high channel and
the lower nibble sets the low channel.
For example:
- To sample channel 1 only, write 11h to BASE+2
- To sample channels 0 to 2, write 20h to BASE+2
- To sample channels 5 and 6, write to 65h to BASE+2
WRITE
Sets the channel mux and resets the FIFO.
READ
Reads the current channel mux which the A/D will convert on the next trigger pulse.
5.4 8-BIT DIGITAL I/O REGISTERS
BASE ADDRESS +3 Example, 303h, 771 Decimal
READ
01324567
DI30011
DI2
GATE0
DI1
ExtTrig
The four digital inputs and the upper nibble of the board ID are read as one byte. Three of the pins have special
functions in addition to being digital input pins. They are:
y
ExtPacer/DI0 External Pacer: Single A/D conversion on each active edge.
y
ExtTrig/DI1 External Trigger/Gate: Starts Pacer (Internal/External) which generates A/D Conversions on
each active edge of pacer.
y
GATE0/DI2 Gate for CTR0. Used to Gate Counter 0.
DI0
ExtPacer
10
WRITE
All of the four bits are latched TTL outputs.
The WRITE to this register also clears external trigger latched bit.
5.5 STATUS REGISTER
BASE ADDRESS + 8 Example, 308h, 776 Decimal
READ
Description of Status Register read bits:
- End of Conversion. 1 = Busy, 0 = Conversion complete.
EOC
- Unipolar/Bipolar. 0 = Bipolar A/D input, 1 = Unipolar A/D input.
U/B
OVRN
INTB
MA3:0
- FIFO Overrun status. 0 = has not overrun (not full), 1 = overrun (FIFO is full).
(The OVRN bit is latched. The latch is cleared by a FIFO clear write to Base + 2).
- State of interrupt flop. Latched. 0 = no interrupt occurred, 1 = interrupt occurred.
- Current channel mux setting for next conversion.
01324567
DO0DO1DO2DO3Not UsedNot UsedNot UsedNot Used
01234567
MA0MA1MA2MA3INTB OVRNU/B EOC
WRITE
The write function clears the interrupt.
5.6 INTERRUPT AND PACER CONTROL REGISTER
BASE ADDRESS +9 Example, 309h, 777 Decimal
READ/WRITE
01234567
TS0TS1-BMDEINT1INT2INT4INT8
Burst Mode is a method of performing pseudo-simultaneous sample-and-hold on a specified number of channels
without using an external sample-and-hold board or providing individual sample-and-hold amplifiers or A/D
converters on each channel. When Burst Mode is selected, each channel in the burst is sampled at the maximum
speed of the A/D converter (1 MHz) and the time between bursts is set by TS1:0. The channels contained in the burst
are set by register BASE +2 and the number of channels in the burst are set by register BASE +Ah.
The interrupts are enabled/disabled and selected using the following four bits. The routing of the interrupts is set by
the TS0/TS1 bits. When TS1 is set to 1 (not Software conversions), the interrupt is generated by FIFO Half-Full.
That is, when the A/D is sampling and reaches 512 samples, this interrupt is generated to allow the user to perform a
REP INSW block transfer. When TS0 and TS1 are set to 0, Software triggers are enabled in Low Speed Mode and the
interrupts are generated at the end of each FIFO write. That is, when a sample of data is written into the FIFO an
interrupt is generated to allow the user to read it. Finally, when performing REP INSW, if the number of samples is
not a 512 block multiple, there will be a residual number of samples to be taken. By setting the Enhanced bit (register
Base + 11), when RCG is set, the residual samples are to be taken and the interrupts are generated from the residual
counter - Counter 0 (see Base +Bh for further description).
11
INT4:1
- Interrupt selection
Table 5-2. Interrupt Coding
INTERRUPTINT1INT2INT4INT8
DISABLED0000
Not Available1000
20100
31100
40010
51010
60110
71110
Not Available0001
Not Available1001
100101
111101
120011
Not Available1011
140111
151111
BMDE
- Burst Mode Enable. 0 = disable, 1 = enabled. The number of channels in the burst are set in BASE +Ah
register.
- A/D trigger source
TS1:0
Table 5-3. Trigger Source Coding
TRIGGER SOURCETS0TS1
Software TriggerX0
Rising External Pacer 01
Internal Paced 11
To perform conversions in Software Mode, the A/D converter samples at 1 MHz. The maximum delay from the
trigger to the first 1 MHz convert pulse is < 1 uSec, since the trigger enables the 1 MHz pulse train to pass through to
the counter circuit to count 3 pulses which in turn will generate the FIFO write pulse. Therefore, the maximum delay
from the Software Trigger (Base + 0 Write) is 3 uSec.
To perform conversions in Pacer modes, the following sequence must be followed by the program:
The counter (Internal Paced) or DIN0 (External Paced) must be set.
Set the Pacer generator, TS1/0, appropriately.
To initiate the conversions, perform a WRITE to Base + 0 (as in Software Mode) or set an external trigger/gate.
To stop conversions, perform a Base + 9 Write cycle. If using an external trigger, the clearing of the trigger pulse will
end conversions.
12
5.7 BURST LENGTH, EXTERNAL TRIGGER, CTR0/TRG0
BASE ADDRESS +Ah Example, 30Ah, 778 Decimal
READ/WRITE
01234567
TRG0CTR0TRGSELTRGPOLBL0BL1BL2BL3
BL3:0 - Burst Length
. The number of channels in the burst are set by BL3:0, where the channels that are contained
in the burst are set by register BASE+2. For example:
To do a channel burst conversion on channels 0 to 2, set BASE +2 to 20 hex and the upper
nibble of BASE +Ah to 3.
TRGPOL
TRGSEL
- Trigger polarity. 0 = rising trigger/high gate, 1 = falling trigger/low gate.
- Trigger select. 0 = Gate - generate conversions while signal is active, 1 = Trigger - single edge to
initiate conversions.
CTR0
TRG0
- Counter 0 control. 0 = external clock input to counter 0, 1 = internal 1 MHz input.
- Trigger enable. 0 = Gates for counters 1 and 2 enabled preventing external triggers, 1 = external
trigger enabled allowing rising edge to trigger counter (A/D converter).
5.8 COUNTER, GAIN/RANGE CONTROL
BASE ADDRESS +11 Example, 30Bh, 779 Decimal
READ/WRITE
01234567
G0G1U/BFFNE*RCGEnhancedNot UsedNot Used
* Read Only
Enhanced Mode and RCG bits are used in REP INSW conversion mode to allow the correct number of samples to be
taken. In REP INSW, an interrupt is generated every 512 samples at which point the REP INSW function is used to
perform a block transfer of the 512 samples. When the number of samples to be taken is not a multiple of 512, the
final interrupt would never be generated. Therefore, a mechanism has been implemented allowing the software to
know how many samples are left in the FIFO. The Residual Counter functions as follows:
The software knows how many samples the user wants to convert, and divides this number by 512 (the number of
samples in a REP INSW block) - this will be the total number of interrupts generated by the FIFO. The remaining
number of samples is written to Counter 0.
The user then starts conversions, taking interrupts every 512 sample blocks. When the number of interrupts is 1 less
than the total, software will set the RCG bit. When the last interrupt is generated, each subsequent conversion counts
down Counter 0 until it reaches terminal count, at which time the final interrupt is generated to read off remaining
samples.
ENHANCED
- Enhanced Mode. Enhanced Mode is used to enable Counter 0 to function as the residual counter,
disconnecting it from being a general purpose counter to the user. 0 = default, 1 = Enhanced mode.
13
- Residual Counter Gate. 0 = disabled, 1 = enabled. The Residual Counter Gate gates Counter 0 'on' to allow the
RCG
software to count the residual number of samples taken off the FIFO in REP INSW mode.
- FIFO Not Empty. 0 = FIFO is not empty - contains A/D data, 1 = FIFO is empty.
FFNE
UNI/BIP
G1:0
- A/D input Unipolar/Bipolar mode select. 0 = Bipolar mode, 1 = Unipolar mode.
- A/D input Gain setting.
Table 5-4. Analog Input Range/Gain Coding
ANALOG INPUT GAING0G1
5.9 8254 DATA AND CONTROL REGISTERS
5.9.1 8254 COUNTER 0 DATA -
BASE + 12 Example, 30Ch, 780 decimal
READ/WRITE
GENERAL PURPOSE OR RESIDUAL COUNTER
ANALOG INPUT VOLTAGE
RANGE
0 to 10V or ±5V100
0 to 5V or ±2.5V210
0 to 2.5V or ±1.25V401
0 to 1.25V or ±.625V811
01324567
D1D2D3D4D5D6D7D8
In default mode, Counter 0 is a general purpose counter supplied to the user. When REP INSW conversions are
performed and the user sets Enhanced Mode, Counter 0 becomes a residual counter (See register Base + 11 for further
description).
*NOTE: Total count must be greater than 512 for the residual counter to work correctly.
6.9.2 8254 COUNTER 1 DATA
- PACER DIVIDER LOWER
BASE + 13 Example, 30Dh, 781 decimal
READ/WRITE
01324567
D1D2D3D4D5D6D7D8
6.9.3 8254 COUNTER 2 DATA
- PACER DIVIDER UPPER
BASE + 14 Example, 30Eh, 782 decimal
READ/WRITE
01324567
D1D2D3D4D5D6D7D8
Counter 2 is the lower 16 bits of the 32-bit pacer clock divider. It's output is fed to the clock input of Counter 2 which
is the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a 10 MHz precision oscillator source.
Counter 2's output is called the 'Internal Pacer' and can be selected by software to be the A/D Pacer source. Counters
1 and 2 should be configured to operate in 8254 Mode 2.
14
6.9.4 8254 CONTROL REGISTER
BASE + Fh Example, 30Fh, 783 decimal
WRITE ONLY
01324567
D1D2D3D4D5D6D7D8
The control register is used to set the operating Modes of 8254 Counters 0, 1, and 2. A counter is configured by
writing the correct Mode information to the Control Register, then the proper count data must be written to the
specific Counter Register.
The Counters on the 82C54 are 16-bit devices. Since the interface to the 82C54 is only eight bits wide, Count data is
written to the Counter Register as two successive bytes. First the low byte is written, then the high byte. The Control
Register is eight bits wide. Further information can be obtained on the 82C54 data sheet, available from Intel or
Harris.
5.10 82C55 DIGITAL I/O DATA AND CONTROL REGISTERS
The 82C55 Digital I/O port is at Register BASE +400h to follow the register configuration of the CIO-DAS1600
family.
5.10.1 8255 PORT A DATA
BASE + 400h Example, 700h, 1792 decimal
READ/WRITE
5.10.2 8255 PORT B DATA
BASE + 401h Example, 701 hex, 1793 decimal
READ/WRITE
5.10.3 8255 PORT C DATA
BASE + 402h Example, 702h, 1794 decimal
READ/WRITE
5.10.4 8255 CONTROL REGISTER
BASE + 403h Example, 703h, 1795 decimal
WRITE ONLY
01324567
D1D2D3D4D5D6D7D8
01324567
D1D2D3D4D5D6D7D8
01324567
D1D2D3D4D5D6D7D8
01324567
The control register is used to set the operating Modes of 8255 Ports A, B, and C. A port is configured by writing the
correct Mode information to the Control Register, then the proper data must be written to the specific digital output
register or read from the specific input register. Further information can be obtained on the 8255 data sheet, available
from Intel or Harris.
D1D2D3D4D5D6D7D8
15
Table 5-5. 82C55 Registers
WRITE FUNCTIONREAD FUNCTIONADDRESS
Port A OutputPort A Input of 82C55 BASE + 400
Port B OutputPort B InputBASE + 401
Port C OutputPort C InputBASE + 402
Configure 82C55 None. No read back on 82C55BASE + 403
The two groups of ports, group A and group B, may be independently programmed in one of several modes. The most
commonly used mode is mode 0, input / output mode. The codes for programming the 82C55 in this mode are shown
in Table 5-6 below.
Table 5-6. 82C55 Configuration Coding
CLBCUADECHEXD0D1D3D4
OUTOUTOUTOUT128800000
INOUTOUTOUT129811000
OUTINOUTOUT130820100
ININOUTOUT131831100
OUTOUTINOUT136880010
INOUTINOUT137891010
OUTININOUT1388A0110
INININOUT1398B1110
OUTOUTOUTIN144900001
INOUTOUTIN145911001
OUTINOUTIN146920101
ININOUTIN147931101
OUTOUTININ152980011
INOUTININ153991011
OUTINININ1549A0111
ININININ1559B1111
NOTE: D7 is always “1”. D6, D5, and D2 are always “0”.
6 CALIBRATION AND TEST
Every board is fully tested and calibrated before leaving the factory. For normal environments a calibration interval of
six months to one year is recommended. If frequent variations in temperature or humidity are common then
recalibrate at least once every three months. It takes less than 30 minutes to calibrate the board.
You will not need an extender card to calibrate theboard but you will need to have the cover off your computer with
the power on, so trim pots can be adjusted during calibration.
The A/D is calibrated by applying a known voltage to an analog input channel and adjusting trim pots for offset and
gain. There are two trim pots requiring adjustment to calibrate the analog input section. The entire procedure is
described in detail in the
Insta
The CIO-DAS16/M1/16 should be calibrated for the range you intend to use it in. When the range is changed, slight
variations in zero and full scale may result. These variations can be measured and removed in software if necessary.
TM
, calibration routine.
Cal
16
7 SPECIFICATIONS
Analog input section
A/D converter type Datel ADS-30356 Subranging
Resolution 16 bits
Programmable ranges ±5V, ±2.5V, ±1.25V, ±.625V, 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V
A/D pacing Programmable: internal counter or external source (Din0, rising edge) or
software polled
Burst mode intersample time 1 µs
Data transfer Word wide from 1k sample FIFO via REP INSW, interrupt, DT Connect
or software polled
Polarity Unipolar/Bipolar software selectable, 10 ms delay switching
Number of channels 8 differential
A/D Trigger sources External trigger/gate (DIN1)
A/D Triggering Modes
Digital: Software configurable for edge (triggered) or level-activated (gated).
Programmable polarity (rising/falling edge trigger, high/low gate).
A/D conversion time 1 µs
Throughput 1 MHz max
Differential Linearity error ±1 LSB max
Integral Linearity error ±6 LSB max
Offset Error ±10 LSB max
Common Mode Range +11V, −6V
CMRR (60Hz, Vin = CMR) 90dB
No missing codes guaranteed 16 bits
Gain drift (A/D specs) ±30 ppm/°C, all ranges
Input leakage current (@25 Deg C) < 200 nA
Input impedance Min 10 MegOhms
Absolute maximum input voltage ±15V
Digital Input / Output
Digital Type (Main Connector)
Input: 74LS244
Output: 74LS197
Configuration Two dedicated ports, 4 input and 4 output
Output High 2.7 volts @−0.4mA min
Output Low 0.4 volts @ 8 mA min
Input High 2.0 volts min, 7 volts absolute max
Input Low 0.8 volts max, −0.5 volts absolute min
1
Digital Type (Auxiliary Connector) 82C55
Configuration 2 banks of 8, 2 banks of 4, programmable by bank as input or output
Output High 3.0 volts min @ −2.5mA
Output Low 0.4 volts max @ 2.5mA
1
Offset error can be trimmed to zero by adjusting the offset potentiometer for zero offset at the sampling
frequency to be used.
17
Input High 2.0 volts min, 5.5 volts absolute max
Input Low 0.8 volts max, −0.5 volts absolute min
Interrupts Programmable levels 2 to 7, 10 to12, 14, 15; Positive-edge triggered
Interrupt enable Programmable
Interrupt sources A/D End-of-conversion, A/D FIFO half full, A/D Residual Counter
Counter
section
Counter type 82C54
Configuration 3 down-counters, 16 bits each
Counter 0 - General purpose counter or ADC residual sample counter when using
REPINSW.
Source: Programmable: external (CTR0IN), internal (1 MHz osc) or ADC
pacer (when using REPINSW).
Gate: Programmable source: external (DIN2) or internal (when using
REPINSW)
Output: Programmable: user connector, end-of-acquisition interrupt (when
using REPINSW).
Counter 1 - ADC Pacer Lower Divider
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source: external (DIN1) or
internal.
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source: external (DIN1) or
internal.
Output: ADC Pacer clock, output available at user connector (CTR2 Out).
Clock input frequency 10 Mhz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
18
Environmental
Operating temperature range 0 to 60°C
Storage temperature range
40 to 100°C
−
Humidity 0 to 90% non-condensing
Power consumption
+5V: Operating 2.25 A typical / 2.9 A maximum
All Specifications typical for 25 DegC unless otherwise specified.
19
For your notes.
20
EC Declaration of Conformity
We, Measurement Computing Corp., declare under sole responsibility that the product:
High speed analog input board and Digital I/OCIO-DAS16/M1/16
DescriptionPart Number
to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied
according to the relevant EC Directives listed below using the relevant section of the following EC standards and other normative
documents:
EU EMC Directive 89/336/EEC: Essential requirements relating to electromagnetic compatibility.
EU 55022 Class B: Limits and methods of measurements of radio interference characteristics of information technology
equipment.
EN 50082-1: EC generic immunity requirements.
IEC 801-2: Electrostatic discharge requirements for industrial process measurement and control equipment.
IEC 801-3: Radiated electromagnetic field requirements for industrial process measurements and control equipment.
IEC 801-4: Electrically fast transients for industrial process measurement and control equipment.
Carl Haapaoja, Director of Quality Assurance
Measurement Computing Corporation
16 Commerce Boulevard,
Middleboro, MA 02346
(508) 946-5100
Fax: (508) 946-9500
E-mail: info@measurementcomputing.com
www. measurementcomputing.com
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