Measurement PC104-DIO48 User Manual

PC104-DAS08

User’s Manual

Revision 4

September, 2001

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11 INSTALLATION
1 1.1 SOFTWARE INSTALLATION
1 1.2 HARDWARE INSTALLATION
2 1.2 .1 Setting the Base Address Switches
3 1.2 .2 INTERRUPT LEVEL SELECT
5 1.2 .3 RANGE SWITCH SETTING
62 SIGNAL CONNECTIONS
6 2.1 CONNECTOR DIAGRAMS
7 2.2 ANALOG INPUTS
7 2.3 SINGLE-ENDED INPUTS
83 REGISTER ARCHITECTURE
8 3.1 CONTROL & DATA REGISTERS

9 3.2 A/D DATA REGISTER
10 3.3 STATUS AND CONTROL REGISTER
11 3.4 UNUSED ADDRESS
11 3.5 COUNTER LOAD & READ REGISTERS
12 3.6 COUNTER CONTROL REGISTER
13 3.7 COUNTER TIMER
14 3.8 DIGITAL INPUT
14 3.9 DIGITAL OUTPUT
14 3.10 TRIGGER & INTERRUPT LOGIC
154 SPECIFICATIONS

This page intentionally left blank.

1.1 SOFTWARE INSTALLATION

1 INSTALLATION

Before you open your computer and install the board, install and run
installation, calibration and test utility included with your board.

Insta

Insta

Cal will guide

Cal, the

you through switch and jumper settings for your board. Detailed information
regarding these settings can be found below. Refer to the

Manual

for

Insta

Cal installation instructions.

Software Installation

1.2 HARDWARE INSTALLATION

The PC104-DAS08 has three sets of switches / jumpers that should be set before
installing the board in the PC. There is a bank of DIP switches for setting the base
address, a jumper for setting the interrupt level and a bank of switches for setting the

RANGE SELECT
SWITCHES (S2)

ADDRESS SELECT
SWITCHES
Default 300h sh ow n

INTERRUPT LEVEL
SELECT JUMPERS
X (NO IRQ) SHOWN

analog input range. See Figure 1-1 below.

Figure 1-1. Switch and Jumper Locations

PIN 1
(UNDER)

1

1.2 .1 Setting the Base Address Switches

Select a base address from those available in your system. The PC104-DAS08 uses
eight addresses.

Set the switches on your base address switch as shown on the diagram. Unless there
is already a board in your system using address 300 hex (768 decimal), leave the
switches as they are set at the factory.

In the example shown in Figure 1-2, the switches are set for base address 300h.

1 234 56 7

SW

98

A9
A8
A7

7

A6

6

A5
A4

5

A3

HEX
200
100
80
40
20
10
08

4

3

BASE ADDRESS SWITCH -

Address 300H shown here.

Figure 1-2. Base Address Switch

Certain addresses are used by the PC, others are free and may be used by the
PC104-DAS08 and other expansion boards. Refer to Table 1-1 for PC addresses.

2

Table 1-1. PC I/O Addresses

FUNCTIONHEX

RANGE

070-071

The BASE switches can be set for address in the range of 000-3F8 so it should not be
hard to find a free address area. If you are not using IBM prototyping cards,
300-31F HEX are free to use.

CMOS RAM & NMI MASK
(AT)

RANGE

FUNCTIONHEX

EGA2C0-2CF8237 DMA #1000-00F
EGA2D0-2DF8259 PIC #1020-021
GPIB (AT)2E0-2E78253 TIMER040-043
SERIAL PORT2E8-2EF8255 PPI (XT)060-063
SERIAL PORT2F8-2FF8742 CONTROLLER (AT)060-064
PROTOTYPE CARD300-30F

PROTOTYPE CARD310-31FDMA PAGE REGISTERS080-08F
HARD DISK (XT)320-32F8259 PIC #2 (AT)0A0-0A1
PARALLEL PRINTER378-37FNMI MASK (XT)0A0-0AF
SDLC380-38F8237 #2 (AT)0C0-0DF
SDLC3A0-3AF80287 NUMERIC CO-P (AT)0F0-0FF
MDA3B0-3BBHARD DISK (AT)1F0-1FF
PARALLEL PRINTER3BC-3BFGAME CONTROL200-20F
EGA3C0-3CFEXPANSION UNIT (XT)210-21F
CGA3D0-3DFBUS MOUSE238-23B
SERIAL PORT3E8-3EFALT BUS MOUSE23C-23F
FLOPPY DISK3F0-3F7PARALLEL PRINTER270-27F
SERIAL PORT3F8-3FFEGA2B0-2BF

Address not specifically listed, such as 390-39F, are free.

1.2 .2 INTERRUPT LEVEL SELECT

The interrupt jumper need only be set if the software you are using requires it. If you
do set the interrupt jumper, please check your PC's current configuration for
interrupt conflicts.

Do not use IR2 in PC/AT class machines (or higher).
There is a jumper block on the PC104-DAS08 located just above the PC bus

interface (see Figure 1-1). The factory default setting is that no interrupt level is set
(the jumper is in the 'X' position). See Figure 1-3.

If you need to pace conversions through hardware (either the on-board pacer or an
external clock), move this jumper to one of the other positions (see Table 1-2).

3

IRQ2

IRQ5

Figure 1-3. Interrupt Jumper Block

Table 1-2. IRQ Assignments

DESCRIPTIONNAMEDESCRIPTIONNAME

REAL TIME CLOCK (AT)IRQ8PARITYNMI
RE-DIRECTED TO IRQ2 (AT)IRQ9TIMERIRQ0
UNASSIGNEDIRQ10KEYBOARDIRQ1
UNASSIGNEDIRQ11RESERVED (XT)

INT 8-15 (AT)

UNASSIGNEDIRQ12COM OR SDLCIRQ3
80287 NUMERIC CO-PIRQ13COM OR SDLCIRQ4
HARD DISKIRQ14HARD DISK (AT)

LPT (AT)

UNASSIGNEDIRQ15FLOPPY DISKIRQ6

Note: IRQ8-15 are AT onlyLPTIRQ7

4

1.2 .3 RANGE SWITCH SETTING

The DIP switch labeled S2 controls the range (gain) settings for both bipolar ranges
(±5V and ±10V), and for the unipolar range (0 to 10V). For location, see Figure 1-1.
Switch S2 has four ganged switches to select an input range for the analog inputs
(Figure 1-4).

Refer to Table 1-3 to determine the correct positions of switches S2-1 through S2-4
for the range you desire.

These switches control the analog input range for all eight channels.

Table 1-3. Range Select Switch (S2) Settings

S4S3S2S1

RESOLUTIONRANGEGAIN

2.44mV / bit±5V1DownUpDownUp

4.88mV / bit±10V0.5DownUpUpDown

2.44mV / bit0 to 10V1UpDownDownUp
NOTE: Up = open; Down = closed.
Positions other than those listed are not valid.
The PC104-DAS08 is ready to test. You can try running the software supplied with

your board now, or you can continue reading the next section on Software
Installation
and
Calibration
.

S2 SWITCH SETTINGS FOR +/-5V

(Up)

(Down)

13

2

(Up)

(Down)

4

Figure 1-4. Range Select Switch S2

5

2 SIGNAL CONNECTIONS

g

g

g

g

g

g

g

g

g

g

2.1 CONNECTOR DIAGRAMS

The PC104-DAS08 analog connector is a 40-pin header connector.

The connector accepts female 40-pin
header connectors, such as those on the
C40FF-2, 2 foot cable with connectors.
If connector compatibility with a
CIO-DAS08 is required, the C40-37F-#
or BP40-37 adapter cables can be used.
The C40-37F-# cable converts the
signals on the 40-pin header into the
standard DAS08 37-pin, D connector
pin assignments. If a connector on a
standard PC bracket is required, the
BP40-37 adapter cable can be used to
convert the 40-pin female header to a
37-pin male mounted on a bracket. See
Figure 2-2 for the BP40-37 pinout.

Figure 2-3 shows the cabling of the
BP-40-37..

If frequent changes to signal
connections or signal conditioning is
required, please refer to the
information on the CIO-TERMINAL
and CIO-MINI37 screw terminal
boards, CIO-EXP32, 32 channels
analog MUX/AMP or the
ISO-RACK08, 8-position 5B module
interface rack.

NC 40

NC 38
Ch0 36
Ch1

34

Ch2

32

Ch3

30

Ch4

28

Ch5

26

Ch6

24

Ch7

PC Bu s +5 20
Digital

Digital
Digital

Digital

In 1 / T rig 12

IR Inp ut / XCLK 10

PC BUS -12V 2

22

Gnd 18

In 3 16
In 2 14

G A T E 2 8
G A T E 1 6
G A T E 0 4

Figure 2-1. Analog Connector

+10V REF 19

LLGND 18
LLGND
LLGND
LLGND
LLGND
LLGND
LLGND

ital Gnd 11

Di

ital Out 4 10

Di

9

Di

ital Out 3
ital Out 2

Di

ital Out 1

Di
Cou nte r 2 Out 6
Cou nte r 1 Out

Cou nte r 1 In
Cou nte r 0 Out

Cou nte r 0 In
PC BUS +12V 1

17
16
15
14
13
12

8
7

5
4
3
2

39 NC
37 +10V REF
35 LLGND

LLGND

33

LLGND

31

LLGND

29

LLGND

27

LLGND

25

LLGND

23

D i g ital Gn d

21
1 9 Di g ital Ou t 4

Digital

1 7 O u t 3

Ou t 2

Digital

15

Ou t 1

Digital

13
11 Coun ter 2 O ut
9 Counter 1 Out
7 C o un ter 1 In
5 Counter 0 Out
3 C o un ter 0 In
1 PC B U S +1 2V

37 C h 0 Lo w

Ch 1 Low

36

Ch 2 Low

35

Ch 3 Low

34

Ch 4 Low

33

Ch 5 Low

32

Ch 6 Low

31

Ch 7 Low

30
29 PC Bus +5

ita l Gnd

28 Di

ital In 3

27

Di

ital In 2

Di

26

Di

25

ital In 1 / Tri
24 IR Input / XCLK
23

Gate 2

22

Gate 1

21

Gate 0

20 PC BUS -12V

Figure 2-2. BP40-37 Adapter Cable Pinout

6

PC104-DAS08

BP40-37

Figure 2-3. BP40-37 Adapter Cabling

2.2 ANALOG INPUTS

Analog inputs to the PC104-DAS08 are single-ended.

CAUTION - PLEASE READ

Measure the voltage between signal ground at the signal source
and the PC’s ground. If the voltage exceeds 0.5V (AC or DC), DO
NOT CONNECT the PC104-DAS08 to this signal source because
you will not be able to make an accurate measurement.

Voltage between the two grounds means that you will create a
ground loop if you connect the signal ground to the PC104-DAS08
board ground. Current flow in the ground loop can damage the
board and possibly the computer.

37-pin cable, as
C37FF-x, etc.

Back Plate

2.3 SINGLE-ENDED INPUTS

A single-ended input is two wires connected to th e boar d, a channel high (CH# HI)
and a Low Level Groun d (LLGND). The LLGND sign al mu st be the sam e ground
the PC is on. The CH# HI is the voltage signal source. There is no common mode
rejection on a single-ended input so shielding and proper grounding is important
both for voltage differentials and for noise immunity. If greater amplification or
expanded differential inputs are required, we suggest using a CIO-EXP32, 32
channel or CIO-EXP16, 16-channel analog input multiplexer and amplifier.

7

3 REGISTER ARCHITECTURE

3.1 CONTROL & DATA REGISTERS

The PC104-DAS08 is controlled and monitored by writing to and reading from eight
consecutive 8-bit I/O addresses. The first address, or BASE ADDRESS, is
determined by setting a bank of switches on the board.

Most often, register manipulation is best left to experienced programmers as most of
the PC104-DAS08 possible functions are implemented in easy to use Universal
Library functions.

The register descriptions follow the format:

01234567

A/D11A/D10A/D9

LSB

Numbers along the top row are the bit positions within the 8-bit byte and the
numbers and symbols in the bottom row are the functions associated with that bit.

To write to or read from a register in decimal or HEX, the weights in Table 3-1
apply:

Table 3-1. Bit Weights

CH1CH2CH4CH8A/D12

HEX VALUEDECIMAL VALUEBIT POSITION

110
221
442

883
10164
20325
40646
801287

To write control words or data to a register, the individual bits must be set to 0 or 1
then combined to form a byte.

The method of programming required to set/read bits from bytes is beyond the scope
of this manual.

In summary form, the registers and their function are listed on Table 4-2. Within
each register are eight bits which either constitute a byte of data or eight individual
bit set/read functions.

8

Table 3-2. Board Registers

BASE + 2

EOC, IP1-IP3, IRQ, MUX
Address

3.2 A/D DATA REGISTER

BASE ADDRESS

A/D11A/D10A/D9

LSB
A read/write register.
READ

WRITE FUNCTIONREAD FUNCTIONADDRESS

Start 8 bit A/D conversionA/D Bits 9-12(LSB)BASE
Start 12 bit A/D conversionA/D Bits 1(MSB)-8BASE + 1
OP1-OP4, INTE & MUX
Address
Not usedNot usedBASE + 3
Load Counter 0Read Counter 0BASE + 4
Load Counter 1Read Counter 1BASE + 5
Load Counter 2Read Counter 2BASE + 6
Counter ControlNot usedBASE + 7

01234567
0000A/D12

On read, it contains the least significant four digits of the analog input data.
These four bits of analog input data must be combined with the eight bits of analog

input data in BASE + 1, forming a complete 12-bit number. The data is in the
format 0 = minus full scale. 4095 = +FS.

WRITE
Writing any data to the register causes an immediate 8-bit A/D conversion.
BASE ADDRESS + 1

01234567

A/D8A/D7A/D6A/D5A/D4A/D3A/D2A/D1

MSB

9

READ
On read the most significant A/D byte is read.
The A/D Bits code corresponds to the voltage on the input according to Table 4-3.

Table 3-3. A/D Bit Codes

UNIPOLARBIPOLARHEXDECIMAL

+Full Scale+ Full ScaleFFF4095

½ Full Scale0 Volts8002048

00

WRITE
Writing to this register starts a 12-bit A/D conversion.
Note: Place several NO-OP instructions between consecutive 12-bit A/D conversions

to avoid over-running the A/D converter.

−Full Scale

0 Volts

3.3 STATUS AND CONTROL REGISTER

BASE ADDRESS + 2
This register address is two registers, one is read active and one is write active.
READ = STATUS

01234567

MUX0MUX1MUX2IRQIP1IP2IP3EOC
EOC = 1 the A/D is busy converting and data should not be read.
EOC = 0 the A/D is not busy and data may be read.
IP3 to IP1 are the digital input lines.
IRQ is the status of an edge triggered latch connected to the “Interrupt Req” pin on

the analog connector. It is high (1) when a positive edge has been detected. It may
be reset to 0 by writing to the INTE mask at BASE + 2 write.

MUX 2 to MUX 0 is the current multiplexer channel. The current channel is a
binary coded number between 0 and 7 .

WRITE = CONTROL

01234567

MUX0MUX1MUX2INTEOP1OP2OP3OP4
OP4 to OP1 are the digital output lines.

10

INTE = 1 enables interrupts (positive edge triggered) onto the PC bus IRQ selected
via the IRQ jumper on the PC104-DAS08.

INTE = 0 disables the passing of the interrupt detected at pin 10 to the PC bus.
IRQ is set to 1 every time an interrupt occurs. If you want to process successive

interrupts then set INTE = 1 as the last step in your interrupt service
routine.

MUX2 to MUX0. Set the current channel address by writing a binary coded number
between 0 and 7 to these three bits.

NOTE

Every write to this register sets the current A/D channel MUX
setting to the number in bits 2-0.

3.4 UNUSED ADDRESS

BASE ADDRESS + 3
This address is not used

3.5 COUNTER LOAD & READ REGISTERS

COUNTER 0
BASE ADDRESS + 4

COUNTER 1
BASE ADDRESS + 5

COUNTER 2
BASE ADDRESS + 6

01234567

D0D1D2D3D4D5D6D7

01234567

D0D1D2D3D4D5D6D7

01234567

D0D1D2D3D4D5D6D7

11

The data in the counter read register, and the action taken on the data in a counter
load register, is dependent upon the control code written to the control register.

The counters are 16-bit types, each with an 8-bit window (the read / load
register). Data is shifted into and out of the 16-bit counters through these 8-bit
windows according to the control byte. You will need an 8254 data sheet if you want
to program the 8254 directly at the register level. You can download a copy from our
WEB site at http://www.computerboards.com/PDFmanuals/82C54.pdf

3.6 COUNTER CONTROL REGISTER

BASE ADDRESS + 7

01234567

BCDM0M1M2RL0RL1SC0SC1

WRITE ONLY
SC1 to SC0 are the counter-select bits. They are binary coded between 0 and 2.
RL1 to RL0 are the read and load control bits:

RL1 RL0 OPERATION

0 0 Latch counter.
0 1 Read/load high byte.
1 0 Read/load low byte.
1 1 Read/load low the high byte (word transfer).

M2 to M0 are the counter control operation type bits:

M2 M1 M0 OPERATION TYPE

0 0 0 Change on terminal count.
0 0 1 Programmable one-shot.
0 1 0 Rate generator
0 1 1 Square wave generator
1 0 0 Software triggered strobe.

1 0 1 Hardware triggered strobe.
If BCD = 0, then counter data is 16-bit binary. (65,535 max)
If BCD = 1, then counter data is 4-decade Binary Coded Decimal. (9,999 max)

12

3.7 COUNTER TIMER

The 82C54 counter timer chip can be used for event counting, frequency and pulse
measurement and as a pacer clock for the A/D converter. Several of the Universal
Library A/D routines assume that counter 2, which is hard-wired to the PC bus
signal PCLK, is pacing the A/D samples. All inputs, outputs and gates of the counter
are accessible at the 40 pin analog con nector with the exception of the coun ter 2
input.

+5VDC

82C54

COUNTER

COUNTER 0

COUNTER 1

CTR0 OUT

CTR1 OUT

10K

GATE0 IN

Typ.

CTR0 IN

GATE1 IN

CTR1 IN

GATE2 IN

CTR2 IN

COUNTER 2

ANALOG CONNECTOR

CTR2 OUT

Figure 3-1. 82C54 Counter Block Diagram

The primary purpose of the counter timer chip is to pace the A/D samples. The
input to Counter 2 is hard-wired to the PC bus PCLK signal so that a precise timing
signal will always be available on the board. The counter gates, inputs an d outputs
are TTL.

The counter GATE2 IN line allows or inhibits TTL level pulses present at the CLK
input into the counter 2 register. The OUT line then transitions (pulses or shifts)
depending on the codes in the control register.

The PCLK signal is divided by two prior to the input at counter 2. Therefor e, if th e
PCLK signal on your PC/AT is 8 MHz, the signal at the input of counter 2 is 4 MHz.

Assuming a 4 MHz signal at count er 2, the rates out of counter 2 (pin 11) can vary
between 2 MHz (4 MHz / 2) to 61 Hz (4 MHz / 65,535). For rates slower than 61 Hz
the output of counter 2 should be wired to the input of counter 1. The output of

13

counter 1 would then be wired to the interrupt input (pin 10). The slowest rate
would then be once every 17 minutes.

3.8 DIGITAL INPUT

The digital inputs are TTL-level lines. They feed an 8-bit register which has other
on-board signals applied to it. The resultant 8-bit status byte can be read at BASE
address + 2.

The digital inputs IP1, IP2 & IP3 can be used as status lines to trigger or hold off
A/D conversions, and in fact, the Universal Library uses IP1 for that purpose.

3.9 DIGITAL OUTPUT

The digital output lines, OP1, OP2, OP3 & OP4 are TTL level lines which are
controlled with part of an 8-bit register located at BASE address + 2. These lines
may be used to control the multiplexer address on an external CIO-EXP32
differential amplifier/ multiplexer if one is installed.

3.10 TRIGGER & INTERRUPT LOGIC

The trigger logic works as follows: The INTERRUPT REQ signal on Pin 10 of the
40-pin connector is an input to a flip-flop. It can be read at BASE address + 2 on the
IRQ bit. The PC104-DAS08 can be triggered by polling this bit until a trigger pulse
(rising edge) has occurred. It must be reset by a write to BASE + 2 before it can
respond to additional rising edges.

By writing a 1 to the INTE control bit at BASE + 2, the rising edge detected by the
flip-flop will be translated into an interrupt pulse which can be used to interrupt the
CPU's 8259 interrupt controller on the PC motherboard.

The interrupt level jumper on the PC104-DAS08 must also be installed. Move it
from the 'X' position to the IRQ number you want the interrupt pulse on.

The 82C54 counter/timer chip is primarily a pacer for A/D samples. It is an integral
part of the trigger logic. To employ the 82C54 as an A/D pacer, wire the output of
the counter you program to provide pacing pulses directly into the INTERRUPT
REQ input (pin 10).

14

4 SPECIFICATIONS

Power Consumption

+5V: 130 mA typical, 185 mA max
+12V: 18 mA typical, 25 mA max

−12V: 12 mA typical, 18 mA max

Analog Input Section

A/D converter type AD674
Resolution 12 bits
Number of channels 8, single-ended
Input Ranges ±10V, ±5V, 0 to +10V, switch selectable
Polarity Unipolar/Bipolar, switch selectable
A/D pacing Internal counter or external source

(Interrupt Input, jumper selectable, rising
edge) or software polled

A/D Trigger sources External polled gate trigger (Digital In 1)

Data transfer Interrupt or software polled
DMA None

A/D conversion time 15 µs
Throughput 20 kHz, PC dependent

Accuracy ±0.01% of reading ±1 LSB
Differential Linearity error ±1 LSB
Integral Linearity error ±0.5 LSB
No missing codes guaranteed 12 bits
Gain drift (A/D specs) ±25 ppm/°C
Zero drift (A/D specs) ±10µV/°C
Common Mode Range ±10V
CMRR 72 dB

Input leakage current (@25 Deg C) 100 nA
Input impedance 10 MegOhms min
Absolute maximum input voltage ±35V

15

Digital Input / Output

Digital Type (Main connector)

Output: 74LS273

Input: 74LS244

Configuration 4 fixed output bits, 3 fixed input bits

Number of channels 4 out, 3 in

Output High 2.7 volts min @ −0.4 mA

Output Low 0.4 volts max @ 8 mA

Input High 2.0 volts min, 7 volts absolute max

Input Low 0.8 volts max, −0.5 volts absolute min

Output power-up / reset state

Interrupts 2 thru 7, jumper-selectable
Interrupt enable Programmable
Interrupt sources External (Interrupt In), rising edge

Counter Section

Counter type 82C54
Configuration 3 down-counters, 16 bits each

Counter 0 - independent, user configurable

Source: user connector (Counter 0 In)
Gate: user connector (Gate 0)
Output: user connector (Counter 0 Out)

Counter 1 - independent, user configurable

Source: user connector (Counter 1 In)
Gate: user connector (Gate 1)
Output: user connector (Counter 1 Out)

Counter 2 - independent, user configurable

Source: PC SysClk via divide by 2 circuit
Gate: user connector (Gate 2)

Output: user connector (Counter 2 Out)
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min

Environmental

Operating temperature range 0 to 50°C
Storage temperature range −20 to 70°C
Humidity 0 to 90% non-condensing

16

For Your Notes

17

For Your Notes

18

EC Declaration of Conformity

We,

Measurement Computing Corporation, declare under sole responsibility that the

product:

Analog Input, DI/O and Counter card PC104-DAS08

DescriptionPart Number

to which this declaration relates, meets the essential requirements, is in conformity
with, and CE marking has been applied according to the relevant EC Directives
listed below using the relevant section of the following EC standards and other
normative documents:

EU EMC Directive 89/336/EEC: Essential requirements relating to
electromagnetic compatibility.

EU 55022 Class B: Limits and methods of measurements of radio interference
characteristics of information technology equipment.

EN 50082-1: EC generic immunity requirements.

IEC 801-2: Electrostatic discharge requirements for industrial process measurement

and control equipment.

IEC 801-3: Radiated electromagnetic field requirements for industrial process
measurements and control equipment.

IEC 801-4: Electrically fast transients for industrial process measurement and
control equipment.

Carl Haapaoja, Director of Quality Assurance

Measurement Computing Corporation

10 Commerce Way

Suite 1008

Norton, Massachusetts 02766

[phone]

Fax: [phone]

E-mail: [e-mail]

www.mccdaq.com