Measurement CIO-QUAD0x User Manual

CIO-QUAD02
CIO-QUAD04

2 & 4 Channel Quadrature

Encoder Input Boards

User’s Manual

Revision 2

December, 2000

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MEGA-FIFO, the CIO prefix to data acquisition board model numbers, the PCM prefix to data acquisition boa rd model
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TM

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HM CIO-QUAD0#.lwp

Copyright 2000, Measurement Computing Corp.

©

Table of Contents

1 INTRODUCTION

2 INSTALLATION

3 CIO-QUAD CONNECTOR DIAGRAM
4 REGISTER MAP AND DESCRIPTIONS

5 ELECTRICAL SPECIFICATIONS

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1

11.1 QUADRATURE ENCODERS AND THE CIO-QUAD .........................................

3

32.1 SOFTWARE ...........................................................................

32.2 HARDWARE ..........................................................................

32.2.1 Base Address Switch .................................................................

32.2.2 Interrupt Level Select ................................................................

32.2.3 Single-Ended/Differential Switch and Jumper Settings ......................................

42.2.4 Termination Resistors ................................................................

42.3 PLUG IN THE CIO-QUAD BOARD ........................................................

52.4 TESTING THE INSTALLATION ..........................................................

52.4.1 InstaCAL ..........................................................................

52.4.2 QUAD Encoder Demo Software .......................................................

5
6

64.1 OVERVIEW ...........................................................................

74.2 CHANNEL CONTROL REGISTERS (Base + 0 through Base + 7) ................................

74.2.1 Base +0, 2, 4 and 6 : Output Latch and Preset Registers .....................................

74.2.2 Base +1, 3, 5 and 7: FLAG, RLD, CMR, IOR and IDR Registers .............................

114.3 GLOBAL CONTROL REGISTERS (Base +8 through Base +12) ................................

114.3.1 Base +8: Index & Interrupt Routing Control Register ......................................

124.3.2 Base +9: Input Signal Control Register .................................................

124.3.3 Base +10 and 11: Programmable Interrupt Controller Registers ..............................

124.3.4 Base +12: Interrupt Select Register ....................................................

13

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1 INTRODUCTION

The CIO-QUAD02 is an ISA plug-in board that provides inputs and decoding for one or two incremental quadrature
encoders. A four channel version, the CIO-QUAD04, provides inputs and decoding for up to four encoders. Either the
CIO-QUAD02 or 04 can also be used as a high speed pulse counter for general counting applications.

PLEASE NOTE: If you have a CIO-QUAD04, all instructions in this manual apply. If you have a CIO-QUAD02, you
should ignore all references to channels 3 and 4. In all other respects, the two models are identical. In this manual, we will
refer to both boards generically as CIO-QUAD.

1.1 QUADRATURE ENCODERS AND THE CIO-QUAD

Incremental quadrature encoders are used to provide feedback signals from motors, that is, to count rotations and convert
the physical movement into a series of electrical signals. These signals are sent to the computer which then decides whether
or not to trigger signals that control the motor’s movement and what those control signals should be. The Measurement
Computing Corp. CIO-QUAD is the link between incremental quadrature encoders and the computer.

The CIO-QUAD is a plug-in board for PC/XT/AT computers; it uses one ISA slot and one rear panel opening for up to 2
channels (CIO-QUAD02) or one ISA slot and two rear panel openings for up to four channels (CIO-QUAD04). Each
incremental quadrature encoder connects to an input channel o n the CIO-QUAD through a DB9 female connector on the
board’s rear panel. Channels 1 and 2 connect to the DB9 connectors attached directly to the board. Channels 3 and 4
(CIO-QUAD04) connect to the DB9 connectors on an auxiliary rear panel bracket.

For each channel, the signals at the DB9 connectors are:

y

Phase A+, A-

y

Phase B+, B-

y

Index +/-

y

+5 and GND (optional power for +5V encoders)

For pinout diagrams refer to Section 2.3.

The CIO-QUAD board provides inputs for three basic signals, Phase A, Phase B, and Index. Phase A and Phase B are
generated at a 90° phase shift with respect to each other. Using these signals, a computer with a CIO-QUAD can determine
system position (counts), velocity, (counts per second), and direction of rotation.

The Index signal is used to establish an absolute reference position within one count of the encoder rotation (360°).
Therefore, the Index signal is often used to reset o r preset the position counter, particularly upon system startup when the
incremental encoder cannot determine the starting position of the motor. The Index signal can also be used to generate an
interrupt signal to the computer.

The Phase A, Phase B, and Index inputs are jumper-selectable for differential or single-ended input. These signals, after
being routed through differential receiver s, offer various paths to the LS7266 inputs through the FPGA. The inputs a re
register-selectable for:

y

individual incremental encoder inputs to allow up to four channels

y

cascadable counters to allow non-quadrature counting up to 96-bits

y

routing the Index input to either the Load Counter/Load Latch input or the Reset Counter/Gate input with quarter cycle
and half cycle signals supported

y

routing the Compare or Carry/Borrow output signals to the 8259 Interrupt controller

The heart of the CIO-QUAD is the LSI Computer Systems, Inc., LS7266R1 24-bit Dual Axis Quadrature Counter chip.

1

This component contains:

y

two, 24-bit counters

y

associated 24-bit preset and 24-bit output latch registers

y

integrated digital filtering with 8-bit counter prescalers

It provides:

y

programmable index functionality

y

programmable count modes including non-quadrature modes.

y

CIO-QUAD can also operate as a high-speed pulse and general purpose counter, cascadable to 96 bits. The 24-bit
counter can count either in binary or BCD through register selection.

The CIO-QUAD also includes an 8259 Programmable Interrupt Controller which accepts the four Index inputs directly and
the Carry/Borrow outputs from the LS7266 (counter overflow/underflow or count value match) to generate interrupts to the
PC bus. The interrupt controller operates in Polled Mode and allows for masking and priority setting of the interrupt inputs.
For an overall view of CIO-QUAD functionality, see the block diagrams in Figure 1-1 below.

CIO-QUAD04

QUADRATURE

ENCODER

INPUT

QUADRATURE

ENCODER

INPUT

Channel 1

Channel 2

Channel 1

Channel 2

Channel 3

Channel 4

S.E./Diff.

Setting

Termination

S.E./Diff.

Setting

Termination

S.E./Diff.

Setting

Termination

S.E./Diff.

Setting

Termination

S.E./Diff.

Setting

Termination

S.E./Diff.

Setting

Termination

75ALS175

75ALS175

75ALS175

75ALS175

8259 PIC

75ALS175

75ALS175

INTERRUPT

IRQ’S

Signal Routing

8

DATA

TRANSCEIVER

8
DATA

ISA-BUS

CIO-QUAD02

Control

Signal Routing

Control

Decode

FPGA

Decode

FPGA

ADDRESS
DECODER

LS7266: 24-Bit Dual-Axis

Quadrature Counter

Channels

Signalling

Signalling

CONTROL

ADDRESS

LS7266: 24-Bit Dual-Axis

Quadrature Counter

Signalling

1&2

Channels

3&4

BUFFER

CONTROL

Channels

1&2

DATA BUS

DATA BUS

INTERRUPT

8259 PIC

IRQ’S

8

DATA

TRANSCEIVER

8
DATA

ISA-BUS

ADDRESS
DECODER

Figure 1-1. Functional Block Diagrams

2

ADDRESS

CONTROL

BUFFER

CONTROL