Measurement CIO-PDMAxx User Manual
CIO-PDMA16
&
CIO-PDMA32
High Speed
Digital Input/Output
User’s Manual
Revision 5
September, 2000
MEGA-FIFO, the CIO prefix to data acquisition board model numbers, the PCM prefix to data
acquisition board model numbers, PCM-DAS08, PCM-D24C3, PCM-DAC02, PCM-COM422,
PCM-COM485, PCM-DMM, PCM-DAS16D/12, PCM-DAS16S/12, PCM-DAS16D/16,
PCM-DAS16S/16, PCI-DAS6402/16, Universal Library, InstaCal, Harsh Environment
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HM CIO-PDMA##.lwp
Table of Contents
1.0 INTRODUCTION
2.0 SOFTWARE INSTALLATION
3.0 HARDWARE INSTALLATION
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4.0 CABLING TO THE CIO-PDMA##
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5.0 REGISTER MAPS
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6.0 SPECIFICATIONS
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1
2
2
23.1 SETTING THE BASE ADDRESS SWITCHES
33.2 INTERRUPT & DMA LEVEL SELECT
43.3 WAIT STATE JUMPER
43.4 INSTALLING THE CIO-PDMA BOARD
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54.1 SIGNAL CONNECTIONS
64.2 SIGNAL FUNCTIONAL DESCRIPTIONS
64.3 DIGITAL OUTPUTS & INPUTS
64.4 TERMINATING DIGITAL LINES
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85.1 CIO-PDMA16 REGISTER MAP
85.1.1 DIGITAL I/O REGISTERS - PORTS A & B
95.1.2 DMA CONTROL REGISTER
105.1.3 INTERRUPT CONTROL REGISTER
115.1.4 8254 COUNTER LOAD & READ REGISTERS
115.1.5 COUNTER CONTROL REGISTER
135.2 CIO-PDMA32 REGISTER MAP
135.2.1 PORTS A & B Base Address + 0 and Base Address + 1
145.2.2 DMA Control Register
155.2.3 Interrupt Control Register
155.2.4 Counter Load & Read Registers Base Address + 4, 5, 6, & 7
165.2.5 Counter Control Register
175.2.6 DMA Level Select Register
175.2.7 Interrupt Level Register
175.2.8 Interrupt Status Register
185.2.9 FIFO Clear Start Address Register
185.2.10 REP String Control Register
205.2.11 REP mode ARM register
205.2.12 FIFO Register
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1.0 INTRODUCTION
The CIO-PDMA16 and CIO-PDMA32 are high speed, 16-bit digital interfaces for
ISA bus personal computers. The CIO-PDMA16 utilizes 8-bit DMA transfers over
the ISA bus and will transfer internally or externally-clocked synchronous data at rates
of 250,000 bytes per second or 125,000 words per second. The CIO-PDMA16 is
100% compatible with MetraByte's PDMA-16. The software interface and connector
pin-out are identical. Software and cabling designed for the MetraByte board may be
used with the CIO-PDMA16.
The CIO-PDMA32 performs 16-bit transfers over the ISA bus, and offers a maximum
data transfer rate of 200,000 words per second in DMA mode, or 750,000 words per
second in REP INSW or REP OUTSW modes. In DMA mode, the CIO-PDMA32 is
fully compatible with the MetraByte PDMA-32. However, if faster transfers are
required, the user has the option of operating the board in the faster REP
INSW/OUTS modes.
Both boards provide a counter timer on the board that can be used as a digital pacer
circuit. In addition, the data transfers can be synchronized to an external clock or
timer.
Both boards include the convenient InstaCal installation and test software and are
fully compatible with the powerful Universal Library (UL) software driver package.
1
2.0 SOFTWARE INSTALLATION
Before you open your computer and install the board, install and run InstaCal, the
installation, calibration and test utility included with your board. If you are using the
CIO-PDMA32, install the 32 bit version of InstaCal (for Windows 95, 98 and NT).
InstaCal will guide you through switch and jumper settings for your board. Detailed
information regarding these settings can be found below. Refer to the Software
Installation Manual for InstaCal installation instructions.
Installation varies only slightly between the CIO-PDMA16 and the CIO-PDMA32
board. Both boards can be configured by running the InstaCal
calibration and test program, then verifying. If necessary, you can change the default
base address using on-board dip switches before installing the board.
If you will be using the Universal Library with the CIO-PDMA32, please note that the
CIO-PDMA32 board is not currently supported by the 16-bit library. You should
install the 32 bit version. Please contact the factory if you require 16-bit library
support.
TM
installation,
3.0 HARDWARE INSTALLATION
The CIO-PDMA16 has a bank of DIP switches for setting the base address and a Wait
State jumper. The jumper won’t need to be changed before installing the board but the
base address switches may. The CIO-PDMA32 has only the base address switches.
The procedure for setting the base address switch bank is very similar on both boards.
3.1 SETTING THE BASE ADDRESS SWITCHES
Before installing the CIO-PDMA board, you may need to set the base address by
using the dip switches located on the board. However, unless there is another board in
your system using address 300 hex (768 decimal), leave the switches as set at the
factory. If you are unfamiliar with this operation, you can use InstaCal to show you
how to enter the correct switch settings.
If are already familiar with setting ISA base addresses, use the base address switch
graphic in Figure 3-1 and 3-2 below to help you set the switches.
2
Figure 3-1. CIO-PDMA16 Base Address Switches (300h shown)
A complete address is constructed by calculating the hexadecimal number which
corresponds to all the address bits the CIO-PDMAx can respond to. The range of
base addresses are:
CIO-PDMA16 200h to 3F8h
CIO-PDMA32 200h to 3F0h
In the default configuration, shown in Figures 3-1 and 3-2, addresses 9 and 8 are
DOWN, and all others are UP. Address 9 = 200 hex (512 decimal) and address 8 =
100 hex (256 decimal). When added together they equal 300 hex (768 decimal).
9876
5
4
SW
A9
A8
A7
A6
A5
A4
HEX
200
100
80
40
20
10
Figure 3-2. CIO-PDMA32 Base Address Switches (300h shown)
NOTE: The CIO-PDMA32 has one fewer switch than the CIO-PDMA16.
NOTE
DISREGARD NUMBERS PRINTED ON THE SWITCH. REFER
ONLY TO WHITE NUMBERS PRINTED ON THE BOARD.
3.2 INTERRUPT & DMA LEVEL SELECT
The interrupt and DMA levels used by the CIO-PDMA boards are selected in
software. Refer to the documentation for the software package you are using to set
these parameters.
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3.3 WAIT STATE JUMPER
The CIO-PDMA16 board has a wait state jumper (Figure 3-3) which can enable an
on-board wait-state generator. A wait state is an extra delay injected into the
processor's clock via the bus. This delay slows the processor slightly so that signals
from slow devices (chips) will be valid. The default position is Disabled. Only rarely,
and then only if processing fast signals, might the Enabled position be required.
NOTE: The wait state generator on the CIO-PDMA16 is only active when the board
is being accessed. In general, your PC will not be slowed down by using the wait
state.
Figure 3-3. Wait State Jumper Positions
3.4 INSTALLING THE CIO-PDMA BOARD
1. Shut the computer down, remove power, and open the case.
2. Locate an empty ISA expansion slot in your computer. The CIO-PDMA32 board
requires a 16-bit slot (with two connectors), while the CIO-PDMA16 can be
installed in either an 8-bit or a 16-bit slot.
3. Push the board firmly down into the expansion bus connector. If it is not seated
fully it may fail to work and could short circuit the PC bus power onto a PC bus
signal. This could damage the motherboard in your PC as well as the
CIO-PDMA board. Use the screw provided on your computer's backplate to
secure the board in it's location.
4. Replace the cover on the computer and turn it ON.
5. To verify proper installation, you should now run
function.
4
Insta
Cal and select the
Test
4.0 CABLING TO THE CIO-PDMA##
4.1 SIGNAL CONNECTIONS
The CIO-PDMA16 and CIO-PDMA32 connector is a 37-pin D-type connector
accessible from the rear of the PC through the expansion backplate.
The connector accepts female 37-pin D-type connectors, such as those on the
C37FF-2, 2-foot cable with connectors. If frequent changes to signal connections or
signal conditioning is required, please refer to the information on the
CIO-TERMINAL, CIO-SPADE50 and CIO-MINI37 screw terminal boards.
TRANSFER REQ IN
X
Figure 4-1. 37-Pin Signal Connector
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4.2 SIGNAL FUNCTIONAL DESCRIPTIONS
Port A input/output lines. A0 = LSBPORT A0 - A7
Port B input/output lines. B0 = LSBPORT B0 - B7
Output-only digital lines.AUX DIG 1- 3
Output only. 0 = input, 1 = outputPORT A DIR. OUT
Output only. 0 = input, 1 = outputPORT B DIR. OUT
TRANSFER REQ IN
TRANSFER ACK. OUT
TIMER GATE
INTERRUPT
Positive edge initiates a DMA transfer if DMA is
enabled and bit 3 of the DMA control register = 0.
This line goes low upon receipt of a TRANSFER
ACK. OUT then returns high after the DMA transfer
has completed. At that point, the transfer has taken
place and if it was an output, is valid to be read from
port(s) A (and B).
Output from 8254 counter 1. TIMER OUT
A low on this signal will hold the gates of 8254
counter 0 and counter 1 low, thereby inhibiting inputs
to the counters. This signal is pulled up by a 10K
resitor to +5V.
Positive or negative edge triggered input. Software
programmable.
4.3 DIGITAL OUTPUTS & INPUTS
All the digital inputs/outputs on the CIO-PDMA board are at TT L level. TTL is an
electronics industry term, short for Transistor-Transistor-Logic, which describes a
standard for digital signals which are either at 0V or 5V (nominal).
Under normal operating conditions, the voltages on Port A or P ort B pins range from
0 to 0.45 volts for the low (0) state to between 2.4 to 5.0 volts for the high (1) state.
At 0.45 volts, a port can safely sink 24 mA. At 2.4 volts, a port can source 2.6 mA.
These values are typical of TTL devices.
4.4 TERMINATING DIGITAL LINES
When transferring digital data at high rates over cables, the impedance of the cable
and both ends should be matched as closely as possible to avoid “ringing” or
reflections in the line. To accomplish this, it may be necessary to add resistors in
series with the data lines at the source of the signals.
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