Measurement CIO-INT-32 User Manual

CIO-INT32

User’s Manual

Revision 4

September, 2000

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HM CIO-INT32.lwp

Table of Contents

1.0 INTRODUCTION

2.0 SOFTWARE INSTALLATION

3.0 HARDWARE INSTALLATION

4.0 SPECIFICATIONS

5.0 ELECTRONICS AND INTERFACING

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2
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23.1 BASE ADDRESS ...............................................

33.2 INTERRUPT LEVEL SELECT ...................................

53.3 INSTALLING THE CIO-INT32 IN THE COMPUTER .................

63.4 CABLING TO THE CONNECTOR ................................

63.5 SIGNAL CONNECTION ........................................

73.6 CONNECTOR DIAGRAM .......................................

73.7 Z8536 CONTROL & DATA REGISTERS ...........................

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115.1 PULL UP & PULL DOWN RESISTORS ...........................

135.2 VOLTAGE DIVIDERS .........................................

155.3 LOW PASS FILTERS DE-BOUNCE INPUTS ......................

This page is blank.

1.0 INTRODUCTION

This manual provides technical information for the CIO-INT32. It is intended to be
used with the ZILOG 8536 integrated circuit data sheet and programming manual.

The CIO-INT32 can accept up to 32 vector interrupts and output an interrupt to the
PC. The board contains two Z8536 chips each of which accepts up to 16 independent
inputs that can be used to generate interrupts from bit patterns or individual bit states
or transitions.

The interrupt outputs from two X8536 chips can be ANDed by an on-board jumper.

Many other functions can be performed by the CIO-INT32 including digital pattern
recognition, counting with six, 16-bit counters, and up to 40 bits of digital I/O.

The 16-bit counters can be set up independently or chained together in groups of
three.

The CIO-INT32 is shipped with InstaCal

TM

, a package of software for installation and

testing of the board

TM

In addition, the board can be supported by the Universal Library

which provides

programming support for all Windows languages.

The CIO-INT32 has a pair of Z8536 I/O chips interfaced to the ISA bus. All of its I/O
lines are accessible through a 50-pin header connector. The I/O pins of an Z8536 are
TTL levels. Connections to the board typically use the C50FF-# cable and the
CIO-MINI50 terminal board.

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2.0 SOFTWARE INSTALLATION

In order to easily test your installation, it is recommended that you install InstaCal, the
installation, calibration and test utility that was supplied with your board. Refer to the
Software Installation Manual for information on the initial setup, loading, and
installation of InstaCal and optional Universal Library software.

3.0 HARDWARE INSTALLATION

3.1 BASE ADDRESS

The CIO-INT32 employs the PC bus for power, communications and data transfer.
As such it draws power from the PC, monitors the address lines and control signals
and responds to it's I/O address, and it receives and places data on the 8 data lines. If
enabled, it has interrupt capability.

The BASE address is the most important user selectable bus related feature of the
CIO-INT32. The base address is the location that software writes to and reads from
when communicating with the CIO-INT32.

The base address switch is the means for setting the base address. Each switch
position corresponds to one of the PC bus address lines. By placing the switch down,
the CIO-INT32 address decode logic is instructed to respond to that address bit.

A complete address is constructed by calculating the HEX or decimal number which
corresponds to all the address bits
the CIO-INT32 has been instructed
to respond to.

For example, shown to the right are
address 9 and 8 ON, all others
OFF.

Address 9 = 200H (512D) and
address 8 = 100H (256D), when
added together they equal 300H
(768D).

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Certain address are used by the PC, others are free and may be used by the
CIO-INT32 and other expansion boards. We recommend BASE = 300H (768D) be
tried first.

Table 1. PC I/O Addresses

FUNCTIONHEX

EGA2C0-2CF8237 DMA #1000-00F
EGA2D0-2DF8259 PIC #1020-021
GPIB (AT)2E0-2E78253 TIMER040-043
SERIAL PORT2E8-2EF8255 PPI (XT)060-063
SERIAL PORT2F8-2FF8742 CONTROLLER (AT)060-064
PROTOTYPE CARD300-30F
PROTOTTYPE CARD310-31FDMA PAGE REGISTERS080-08F
HARD DISK (XT)320-32F8259 PIC #2 (AT)0A0-0A1
PARALLEL PRINTER378-37FNMI MASK (XT)0A0-0AF
SDLC380-38F8237 #2 (AT)0C0-0DF
SDLC3A0-3AF80287 NUMERIC CO-P (AT)0F0-0FF
MDA3B0-3BBHARD DISK (AT)1F0-1FF
PARALLEL PRINTER3BC-3BFGAME CONTROL200-20F
EGA3C0-3CFEXPANSION UNIT (XT)210-21F
CGA3D0-3DFBUS MOUSE238-23B
SERIAL PORT3E8-3EFALT BUS MOUSE23C-23F
FLOPPY DISK3F0-3F7PARALLEL PRINTER270-27F
SERIAL PORT3F8-3FFEGA2B0-2BF

RANGE

070-071

FUNCTIONHEX

RANGE

CMOS RAM & NMI MASK (AT)

The CIO-INT32 BASE switch may be set for address in the range of 000-3F8 so it
should not be hard to find a free address area for you CIO-INT32. Once again, if you
are not using IBM prototyping cards or some other board which occupies these
addresses, then 300-31F HEX are free to use.

Addresses not specifically listed, such as 390-39F, are free.

3.2 INTERRUPT LEVEL SELECT

If the software you are writing employs interrupt service routines, you will need to
select and enable interrupts from the CIO-INT32 to the PC bus.

The table below lists typical IRQ assignments. The IRQs described as
UNASSIGNED are typically available to you.

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Table 2. Available IRQs

DESCRIPTIONNAMEDESCRIPTIONNAME

REAL TIME CLOCK (AT)IRQ8PARITYNMI
RE-DIRECTED TO IRQ2 (AT)IRQ9TIMERIRQ0
UNASSIGNEDIRQ10KEYBOARDIRQ1

IRQ2

INT 8-15 (AT)

IRQ5

LPT (AT)

The CIO-INT32 may assert interrupts either:

1. From an external source brought to the connector.

2. Individually from each Z8536 for 16 external interrupt lines per chip

3. Chained as a set of 32 interrupt lines.

Choose a chained or unchained scheme by selecting chained (W) or not chained
(W/O) at the INT PRIORITY jumper.

UNASSIGNEDIRQ11RESERVED (XT)

UNASSIGNEDIRQ12COM OR SDLCIRQ3
80287 NUMERIC CO-PIRQ13COM OR SDLCIRQ4
HARD DISKIRQ14HARD DISK (AT)

UNASSIGNEDIRQ15FLOPPY DISKIRQ6

Note: IRQ8-15 are AT onlyLPTIRQ7

Choose the source of the interrupt to be routed to the PC bus using the INT SRC
jumper. If the Z8536s are chained, you must choose 1 (Chip 1 or Chip 2).

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