Measurement CIO-DAS640212 User Manual

CIO-DAS6402/12

&

CIO-DAS6402/16

ANALOGAND$IGITAL)/"OARDS

Revision 2

© Copyright, October, 2000

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HM CIO-DAS6402_1#.doc

TABLE OF CONTENTS

1 INTRODUCTION
2 SOFTWARE INSTALLATION
3 HARDWARE INSTALLATION

4 ANALOG CONNECTIONS

4.1.1 Single-Ended and Differential Inputs

4.1.2 Single-Ended Inputs

4.1.3 System Grounds and Isolation

4.2.1 Common Ground / Single-Ended Inputs

4.2.2 Common Ground / Differential Inputs

4.2.3 Common Mode Voltage < +/-10V / Single-Ended Inputs

4.2.4 Common Mode Voltage < +/-10V / Differential Inputs

4.2.5 Common Mode Voltage > +/-10V

4.2.6 Isolated Grounds / Single-Ended Inputs

4.2.7 Isolated Grounds / Differential Inputs

5 REGISTER ARCHITECTURE

6 CALIBRATION AND TEST

7 SIGNAL CONDITIONING CIRCUITS

8 SPECIFICATIONS

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1
1
2

23.1 BASE ADDRESS

23.2 D/A OUTPUT RANGE SWITCH (CIO-DAS6402/16 ONLY)

33.3 D/A UPDATE MODE (CIO-DAS6402/16 ONLY)

53.4 CONNECTOR PIN-OUT
6

64.1 ANALOG INPUTS
6
6
8

104.2 WIRING CONFIGURATIONS
11
11
11
11
12
12
13

134.3 ANALOG OUTPUTS
14

145.1 INTRODUCTION

155.2 A/D DATA WORD REGISTERS

165.3 CHANNEL MUX HI/LO LIMITS WORD REGISTER

175.4 8-BIT DIGITAL I/O REGISTERS

175.5 DIGITAL TO ANALOG CONVERTER (ANALOG OUT) REGISTERS

185.6 STATUS REGISTER

205.7 INTERRUPT AND PACER CONTROL REGISTER

215.8 TRIGGER CONTROL/ DAC RANGE SELECT REGISTER

225.9 COMPATIBLE MODE CONTROL REGISTER

245.10 PACER CLOCK DATA AND CONTROL REGISTERS
25

256.1 REQUIRED EQUIPMENT

256.2 CALIBRATING THE A/D & D/A CONVERTERS
25

257.1 VOLTAGE DIVIDERS

267.2 LOW PASS FILTERS
27

278.1 CIO-DAS6402/16

308.2 CIO-DAS6402/12

This page is blank.

1 INTRODUCTION

The CIO-DAS6402/16 and CIO-DAS6402/12 provide 32 differential or 64 single-ended inputs. They have sample rates as high as
330 kHz (100 kHz for the 16-bit version). Using a 100-pin connector, the CIO-DAS6402 board provides large channel counts
without the need for external expansion boards.

The installation and operation of all CIO-DAS6402 series boards is very similar. Throughout this manual we use CIO-DAS6402 as
a generic designation for the CIO-DAS6402/12 and CIO-DAS6402/16. When required, due to the differences in the boards, the
specific board name is used.

The board’s analog input ranges are entirely software-selectable in bipolar ranges from ±10 to ±1.25 Volts and unipolar ranges
from 0 to 10V to 0 to 1.25V. The A/D converter can be triggered externally, or internally based on edge or level trigger sources.
The board supports standard (post) and pre-trigger operation and so is capable of continuous, scheduled or event-triggered data
acquisition.

High speed data acquisition without the chance of a lost sample is assured by the boards’ use of the REP INSW data transfers and
the on-board 1-Kilosample FIFO memory. In addition to the analog input section, each board also provides two channels of analog
output, eight bits of digital input, eight bits of digital output, and a number of counter/timer functions.

TM

All CIO-DAS6402 functions are fully supported by the Universal Library
programming support for all DOS and Windows based operating systems. The CIO-DAS6402 is also shipped with InstaCal
powerful and easy-to-use installation, test, and calibration software package.

software package. This software provides upper level

TM

, a

We recommend that you install InstaCal

TM

before installing the board in your computer. The InstaCalTM operations will show you

how to set the switches and jumpers on the board.

2 SOFTWARE INSTALLATION

The CIO-DAS6402 has a variety of switches and jumpers to set before installing the board in your computer. By far the simplest
way to configure your board is to use the Insta

TM

Insta

will show you all available options, how to configure the various switches and jumpers to match your application

Cal

requirements, and will create a configuration file that your application software (and the Universal Library) will refer to so the
software you use will automatically know the exact configuration of the board.

Please refer to the Software Installation Manual regarding the installation and operation of Insta
information is provided as a matter of completeness, and will allow you to set the hardware configuration of the CIO-DAS6402
board if you do not have immediate access to Insta
are shown in the figures below.

TM

program provided as part of your CIO-DAS6402 software package.

Cal

TM

. The follo wing hard co py

Cal

TM

and/or your computer. The locations of each of the switches and jumpers

Cal

1

3 HARDWARE INSTALLATION

3.1 BASE ADDRESS

Unless there is already a board in your system using address 300h (768 Decimal), leave the switches as they are set at the factory.
In Figure 3-1, the CIO-DAS6402 is set at base address 300h. See Figures 3-6 and 3-7 for the locations of the switches

9876

BASE A DDRESS S W ITCH

Figure 3-1. Base Address Switches

5

4

SW
A9
A8
A7
A6
A5
A4

HEX
200
100
80
40
20
10

- Address 300H shown here.

3.2 D/A OUTPUT RANGE SWITCH (CIO-DAS6402/16 ONLY)

The analog output ranges of the CIO-DAS6402/12 are set via software. The analog output ranges of the CIO-DAS6402/16 are set
by dip switches on the board (Figure 3-7). Figure 3-2 shows the the allowable switch settings and Table 3-1 gives the range/switch
settings.

1 2 3 4 5

O
N

CIO-DAS6402/16 Analog Output

C o n f ig u r a tion S w it c h

(sh o wn a s +/- 1 0 Vo lt fu ll-s c ale )

Figure 3-4. D/A Output Range Switches

2

Table 3-1. D/A Analog Range Switch Settings

(

Range SW 1 SW 2 SW 3 SW 4 SW 5

DNUPDNUPDN±10.0 V

UPDNDNUPDN±5.0 V

DNDNDNUPDN±2.5 V

DNUPUPDNUP0 to 10 V

UPDNUPDNUP0 to 5.0 V

DNDNUPDNUP0 to 2.5 V

3.3 D/A UPDATE MODE (CIO-DAS6402/16 ONLY)

The analog outputs can be configured to update independently or
simultaneously. The update mode is set by a jumper on the
CIO-DAS6402/16. This jumper is shown in Figure 3-5.

Place the jumper on the XFER side for simultaneous update. Place the
jumper on the UPDATE side for independent operation.

CIO-DAS6402/16 D/A

XFERUPDATE

UPDATE MODE SELECT

SHOWN IN SIM ULTANEOUS UPDATE MODE)

Figure 3-5. D/A Update Mode Select Jumper

Base Address Switch

Figure 3-6. CIO-DAS6402/12 Base Address Switches Location

3

D/A Range and
Mode Selection
Switches

Figure 3-7. CIO-DAS6402/16 Base Address, D/A Range & Mode Switches Location

Update Mode
Select Jumper

Base Address Switch

3.4 CONNECTOR PIN-OUT

The CIO-DAS6402 analog connector (Figure 3-8) is a 100 pin high-density connector accessible from the rear of the PC through
the expansion back plate.

The connector interfaces with the C100FF-2, a two-foot cable. This cable connects directly to the CIO-TERM100 screw terminal
board.

LLGND 1

IN 0 + 2

IN0-/IN32+ 3

IN 1 + 4

IN1-/IN33+ 5

IN 2 +

IN2-/IN34+

IN 3 +

IN3-/IN35+
IN4-/IN36+
IN5-/IN37+
IN6-/IN38+
IN7-/IN39+

IN8-/IN40+

IN9-/IN41+
IN10-/IN42+
IN 11 -/IN 4 3 +
IN12-/IN44+
IN13-/IN45+
IN14-/IN46+
IN15-/IN47+

GROUND FO R DAC0 35

DAC0 OUTPUT 36

GROUND FO R DAC1 37

DAC1 OUTPUT 38

CTR0 CLK IN 39

DIN2/CTR0 GATE 40

COUNTER 0 OUTPUT 41

DIN0/AD PACER IN 42

DIN1/AD GATE/AD TRIG 43

-5V RE F OUT 4 7

+5V SU PP LY OUT 48

SSH OUT 49

CHASSIS GND 50

10

IN 4 +

11
12

IN 5 +

13
14

IN 6 +

15
16

IN 7 +

17

LLGND 18

19

IN 8 +

20
21

IN 9 +

22
23

IN10+

24
25

IN 11 +

26
27

IN12+

28
29

IN13+

30
31

IN14+

32
33

IN15+

34

DIN 3 44
DIN 4 45
DIN 5 46

51 LLGN D
52 IN16+
53 IN16 - /IN48 +
54

IN1 7 +

55
6
7
8
9

IN1 7 - /IN49 +

56

IN1 8 +

57

IN1 8 - /IN50 +

58

IN1 9 +

59

IN1 9 - /IN51 +

60

IN2 0 +

61

IN2 0 - /IN52 +

62

IN2 1 +

63

IN2 1 - /IN53 +

64

IN2 2 +

65

IN2 2 - /IN54 +

66

IN2 3 +

67

IN2 3 - /IN55 +
68 LLGN D
69

IN2 4 +
70

IN2 4 - /IN56 +
71

IN2 5 +
72

IN2 5 - /IN57 +
73

IN2 6 +
74

IN2 6 - /IN58 +
75

IN2 7 +
76

IN2 7 - /IN59 +
77

IN2 8 +
78

IN2 8 - /IN60 +
79

IN2 9 +
80

IN2 9 - /IN61 +
81

IN3 0 +
82

IN3 0 - /IN62 +
83

IN3 1 +
84

IN3 1 - /IN63 +
85 DOUT0
86

DOUT1
87

DOUT2
88

DOUT3
89 CHA SSIS GND
90 +12V SUP PLY OUT
91 CHA SSIS GND
92 -12V SUPPLY OU T
93 DIN6
94 DIN7
95 DOUT4
96 DOUT5
97 DOUT6
98 DOUT7
99 EXTERNAL INTERRUPT IN
10 0 C H A S S IS G N D

CIO-DAS6402 ANALOG SIGNAL CONNECTOR - View from rear of the com puter.

Figure 3-8. 100-Pin I/O Connector

5

4 ANALOG CONNECTIONS

4.1 ANALOG INPUTS

The following section provides explanations and helpful hints regarding analog input connections. This section is designed to help
you achieve the optimum performance from your CIO-DAS6402 series board.

Prior to jumping into actual connection schemes, you should have at least a basic understanding of Single-Ended/Differential inputs
and system grounding/isolation. If you are already comfortable with these concepts you may wish to skip to the next section (on
wiring configurations).

4.1.1 SINGLE-ENDED AND DIFFERENTIAL INPUTS

The CIO-DAS6402 provides either 32 differential or 64 single-ended input channels.

4.1.2 SINGLE-ENDED INPUTS

A single-ended input measures the voltage between the input signal and ground. In this case, in single-ended mode the
CIO-DAS6402 measures the voltage between the input channel and LLGND. The single-ended input configuration requires only
one physical connection (wire) per channel and allows the CIO-DAS6402 to monitor more channels than the (2-wire) differential
configuration using the same connector and onboard multiplexor. However, since the CIO-DAS6402 is measuring the input voltage
relative to its own low level ground, single-ended inputs are more susceptible to both EMI (Electro Magnetic Interference) and any
ground noise at the signal source. Figure 4-1 shows the theory of single-ended input configuration

CH IN

LL GND

I/O

Connector

+

-

Inp u t

Amp

To A/D

Single-Ended Input

~

CH IN

Vs

1

g

Any voltage differential between grounds
g1 and g2 shows up a s an error signal
at the input amplifier

Vs + Vg2 - Vg1

LL GN D

+

Inp u t
Amp

To A/ D

-

2

g

Single-ended input w ith C om mon M ode Voltage

Figure 4-1. Single-Ended Voltage Input Theory

6

Differential Inputs

Differential inputs measure the voltage between two distinct input signals. Within a certain range (referred to as the common mode
range), the measurement is almost independent of signal source to CIO-DAS6402 ground variations. A differential input is also
much more immune to EMI than a single-ended one. Most EMI noise induced in one lead is also induced in the other, the input
only measures the difference between the two leads, and the EMI common to both is ignored. This effect is a major reason there is
twisted pair wire as the twisting assures that both wires are subject to virtually identical external influence. Figure 4-2 below shows
a typical differential input configuration.

CH High

CH Low

LL GN D

I/O

Connector

Vs

~

Vcm = Vg2 - Vg1

Common M ode Voltage (Vcm) is ignored
by differential input configura tion. H ow ever,
no te th a t Vc m + V s must re main within
the amplifier’s com mon mode range of ±10V

+

Inp ut

Amp

-

Differential Input

Vcm

Vs

CH High

CH Low

LL GND

gg1 2

To A/ D

+

Inp u t

Amp

-

Differential
Inp u t

To A/ D

Figure 4-2. Differential input Theory

Before moving on to the discussion of grounding and isolation, it is important to explain the concepts of common mode, and
common mode range (CM Range). Common mode voltage is depicted in the d iagram above as Vcm. T hough differential input s
measure the voltage between two signals, without (almost) respect to the either signal’s voltages relative to ground, there is a limit
to how far away from ground either signal can go. Though the CIO-DAS6402 has differential inputs, it will not measure the
difference between 100V and 101V as 1 Volt (in fact the 100V would destroy the board!). This limitation or common mode range
is depicted graphically in Figure 4-3. The CIO-DAS6402 common mode range is +/- 10 Volts. Even in differential mode, no input
signal can be measured if it is more than 10V from the board’s low level ground (LLGND).

7

+13V
+12V
+11V
+10V
+9V
+8V
+7V
+6V
+5V
+4V
+3V
+2V
+1V

-1V

-2V

-3V

-4V

-5V

-6V

-7V

-8V

-9V

-10V

-11V

-12V

-13V

Gray area represents comm on m ode range
Both V+ and V- must always remain within
the co mmo n m o d e ra n ge r ela tive to L L Gn d

W ith V c m= + 5V DC,
+Vs mus t be les s t h an +5 V, or the co mmon mod e ran ge will b e ex c eeded (>+ 10 V)

Vcm

Vcm (Comm on M o de Voltage) = +5 Volts

Figure 4-3. Common Mode Range

4.1.3 SYSTEM GROUNDS AND ISOLATION

There are three scenarios possible when connecting your signal source to your CIO-DAS6402 board.

1. The CIO-DAS6402 and the signal source may have the same (or

common

ground. This signal source may be connected directly to the CIO-DAS6402.

2. The CIO-DAS6402 and the signal source may have an offset voltage
between their grounds (AC and/or DC). This offset it commonly
referred to a

common mode voltage

. Depending on the magnitude of
this voltage, it may or may not be possible to connect the CIO-DAS6402
directly to your signal source. We will discuss this topic further in a later
section.

3. The CIO-DAS6402 and the signal source may already have

grounds

. This signal source may be connected directly to the

isolated

CIO-DAS6402.

Which system do you have?

Try the following test: Using a battery powered voltmeter*, measure the voltage between the ground signal at your signal source
and at your PC. Place one voltmeter probe on the PC ground and the other on the signal source ground. Measure both the AC and
DC Voltages.

*If you do not have access to a voltmeter, skip the experiment and read the following three sections. You may be able to identify your system type
from the descriptions provided.

)

If both AC and DC readings are 0.00 volts, you may have a system with common grounds. However, since voltmeters will average
out high frequency signals, there is no guarantee. Please refer to the section below titled Common Grounds.

If you measure reasonably stable AC and DC voltages, your system has an offset voltage between the grounds category. This offset
is referred to as a Common Mode Voltage. Please be careful to read the following warning and then proceed to the section
describing Common Mode systems.

8

WARNING

If either the AC or DC voltage is greater than 10 volts, do not connect the CIO-DAS6402 to this signal source.
You are beyond the boards usable common mode range and will need to either adjust your grounding system
or add special Isolation signal conditioning to take useful measurements. A ground offset voltage of more
than 30 volts will likely damage the CIO-DAS6402 board and possibly your computer. Note that an offset
voltage much greater than 30 vo lts will not only damage yo ur electronics, but it may also be hazardous to
your health.

This is such an important point, that we will state it again. If the voltage between the ground of your signal
source and your PC is greater than 10 volts, your board will not take useful measurements. If this voltage is
greater than 30 volts, it will likely cause dam age, a nd may represent a serious sho ck hazard! In this case you
will need to either reconfigure your system to red uce the ground dif ferentials, or p urchase and insta ll special
electrical isolation signal conditioning.

If you cannot obtain a stable DC voltage measurement between the grounds, or the voltage drifts around considerably, the two
grounds are most likely isolated. The easiest way to check for isolation is to change your voltmeter to it’s ohm scale and measure
the resistance between the two grounds. It is recommended that you turn both systems off prior to taking this resistance
measurement. If the measured resistance is more than 100 Kohm, it’s a fairly safe bet that your system has electrically isolated

grounds.

Systems with Common Grounds

In the simplest (but perhaps least likely) case, your signal source will have the same ground as the CIO-DAS6402. This would
typically occur when providing power or excitation to your signal source directly from the CIO-DAS6402. There may be other
common ground configurations, but it is important to note that any voltage between the CIO-DAS6402 ground and your signal
ground is a potential error voltage if you set up your system based on a common ground assumption.

As a safe rule of thumb, if your signal source or sensor is not connected directly to an LLGND pin on your CIO-DAS6402, it’s
best to assume that you do not have a common ground even if your voltmeter measured 0.0 Volts. Configure your system as if the re
is ground offset voltage between the source and the CIO-DAS6402. This is especially true if you are using either the
CIO-DAS6402/16 or the CIO-DAS6402/12 at high gains, since ground potentials in the sub millivolt range will be large enough to
cause A/D errors, yet will not likely be measured by your handheld voltmeter.

Systems with Common Mode (ground offset) Voltages

The most frequently encountered grounding scenario involves grounds that are somehow connected, but have AC and/or DC offset
voltages between the CIO-DAS6402 and signal source grounds. This offset voltage may be AC, DC or both and may be caused by
EMI pickup , resistive voltage drops in ground wiring and connectio ns, etc. Ground o ffset voltage is a mor e appropri ate term to
describe this type of system, but since our goal is to keep things simple, and help you make appropriate connections, we’ll stick
with our somewhat loose usage of the phrase Common Mode.

Small Common Mode Voltages

If the voltage between the signal source ground and CIO-DAS6402 ground is small, the combination of the ground voltage and
input signal will not exceed the CIO-DAS6402’s +/-10V common mode range, (i.e. the voltage between grounds, added to the
maximum input voltage, stays within +/-10V), This input is compatible with the CIO-DAS6402 and the system may be connected
without additional signal conditioning. Fortunately, most systems will fall in this category and have a small voltage differential
between grounds.

Large Common Mode Voltages

If the ground diffe rential is large enough, the CIO -DAS6402’s +/- 10V common mode range will be exceeded (i.e. the voltage
between CIO-DAS6402 and signal source grounds, added to the maximum input voltage you’re trying to measure exceeds +/-10V).
In this case the CIO-DAS6402 cannot be directly connected to the signal source. You will need to change your system grounding
configuration or add isolation signal conditioning. (Please look at our ISO-RACK and ISO-5B-series products to add electrical
isolation, or give our technical support group a call to discuss other options.)

9

NOTE
Do not rely on the earth prong of a 120VAC receptacle for signal ground connections. Different ground plugs
may have large and potentially even dangerous voltage differentials. Remember that the ground pins on 120VAC
outlets on different sides of the room may only be connected in the basement. This leaves the possibility that the
“ground” pins may have a significant voltage differential (especially if the two 120VAC outlets happen to be on
different phases.)

CIO-DAS6402 and signal source already have isolated grounds

Some signal sources will already be electrically isolated from the CIO-DAS6402. The diagram below shows a typical isolated
ground system. These signal sources are often battery powered, or are fairly expensive pieces of equipment (since isolation is not
an inexpensive proposition), isolated ground systems provide excellent performance, but require some extra effort during
connections to assure optimum performance is obtained. Please refer to the following sections for further details.

4.2 WIRING CONFIGURATIONS

Combining all the grounding and input typ e possibilities provides us with the following potential connection configurations. The
combinations along with our recommendations on usage are shown in Table 4-1 below.

Table 4-1. Input vs. Grounding Recommendations

Ground Category Input Configuration Our view

RecommendedSingle-Ended InputsCommon Ground

AcceptableDifferential InputsCommon Ground

Common Mode

Voltage < +/-10V

Common Mode

Voltage < +/-10V

Common Mode

Voltage > +/- 10V

Common Mode

Voltage > +/-10V

Already Isolated

Grounds

The following sections depicts recommended input wiring schemes for each of the eight possible input configuration/grounding
combinations.

Single-Ended Inputs

Differential Inputs

Not RecommendedSingle-Ended Inputs

RecommendedDifferential Inputs

Unacceptable without

adding Isolation

Unacceptable without

adding Isolation

AcceptableSingle-ended InputsAlready Isolated Grounds

RecommendedDifferential Inputs

10

4.2.1 COMMON GROUND / SINGLE-ENDED INPUTS

Single-ended is the r ecommended configuration for common ground connections. Ho wever, if some of your inputs are common
ground and some are not, we recommend you use the differential mode. There is no performance penalty (other than loss of
channels) for using a d ifferential input to measure a common ground signal source. However the reverse is not true. Figur e 4-4
below shows a recommended connection diagram for a common ground / single-ended input system

Signal

So u r ce with

Co mm o n Gn d

Optional wire
since signal source
and A/D board share
comm on g round

Signal source and A/D board
sharing comm on ground connected
to single-ended input.

Figure 4-4. Common Ground / Single-Ended Inputs





CH IN

LL GND

I/O

Connector

+

-

Input
Amp

To A /D

A/D Board

4.2.2 COMMON GROUND / DIFFERENTIAL INPUTS

The use of differential inputs to monitor a signal so urce with a common ground is a acceptable configuration though it requires
more wiring and offers fewer channels than selecting a single-ended configuration. Figure 4-5 below shows the recommended
connections in this configuration.

Signal

S ou rc e w ith

C ommon Gnd

Optional wire
since signa l source
and A/D board share
commo n g round





Required connection
of LL GND to CH Low

CH High

CH Low

LL GND

I/O

Connector

+

Input

Amp

-

A/D Board

To A /D

Signal source and A/D board
sharing comm on ground connected
to differe n tia l in p ut.

Figure 4-5. Common Ground / Differential Inputs

4.2.3 COMMON MODE VOLTAGE < +/-10V / SINGLE-ENDED INPUTS

This is not a recommended configuration. In fact, the phrase common mode has no meaning in a single-ended system and this case
would be better described as a system with offset grounds. Anyway, you are welcome to try this configuration, no system damage
should occur and depending on the overall accuracy you require, you may receive acceptable results.

4.2.4 COMMON MODE VOLTAGE < +/-10V / DIFFERENTIAL INPUTS

11

Signal Source

with Co mm o n

Mod e V o lta g e

The voltage differential
between these grounds,
added to the maximum
input signal must stay
within +/-1 0V

GND





CH High

CH Low

LL GND

I/O

Connector

+

Input
Amp

-

A/D Board

To A /D

Signal source and A/D board
w ith c ommon m o d e vo ltag e
connected to a differential input.

Systems with varying ground potentials should always be monitored in the differential mode. Care is required to assure that the sum
of the input signal and the ground differential (referred to as the common mode voltage) does not exceed the common mode range
of the A/D board (+/-10V on the CIO-DAS6402). Figure 4-6 below show recommended connections in this configuration.

Figure 4-6. Common Mode Voltage < +/-10V / Differential Inputs

4.2.5 COMMON MODE VOLTAGE > +/-10V

The CIO-DAS6402 will not directly monitor signals with common mode voltages greater than +/-10V. You will either need to alter
the system ground configuration to reduce the overall common mode voltage, or add isolated signal conditioning between the
source and your board. See Figure 4-7 and 4-8 below.

arge common

L

mode voltag e

between signal

source & A/D board

GND





Iso la t io n

Barrier

CH IN

LL GND

+

Inp u t
Amp

To A /D

-

I/O

When the voltage difference
between signal source and
A/D board ground is large
enough so the A/D board’s
common mode range is
exceeded, isolate d signal
conditioning must be added.

System with a Large Comm on M ode Voltage,

Connected to a Single-Ended Input

Connector

A/D Board

Figure 4-7. Common Mode Voltage > +/-10V. Single-Ended Input

Isola tio n

Barrier

arge common

L

mo d e v o ltag e

between signal

sou rc e & A /D b o a rd

When the voltage difference
between signal source a nd
A/D board ground is large
enough so the A/D board’s
common mode range is
exceeded, isolated signal
conditioning must be added.





GND

10 K

10K is a recommended value. You m ay short LL GND to CH Low
instead, but this w ill reduce your system’s noise immunity.

System with a Large Com m on M ode Voltage,

Connected to a Differential Input

I/O

Connector

CH High

CH Low

LL GND

+

Input
Amp

-

A/D Board

To A / D

Figure 4-8. Common Mode Voltage > +/-10V. Differential Input

4.2.6 ISOLATED GROUNDS / SINGLE-ENDED INPUTS

Single-ended inputs can be used to monitor isola ted inputs, though the use of the d iffer entia l mode will increase you system’s noise
immunity. Figure 4-9 below shows the recommended connections is this configuration.

12

Iso la t e d

s ign al

s o urc e





CH IN

LL GND

I/O

Connector

+

-

Inpu t
Amp

To A /D

A/D Board

Isolated Signal Source

Connected to a Single-E nded Input

Figure 4-9. Isolated Grounds / Single-Ended Input

4.2.7 ISOLATED GROUNDS / DIFFERENTIAL INPUTS

Optimum performance with isolated signal sources is assured with the use of the differential input setting. Figure 4-10 below shows
the recommend connections is this configuration.

Signal Source

and A/D Board

A lr ead y Is ola te d.

GND





10 K

CH High

CH Low

LL GND

+

-

Input

Amp

To A /D

These grounds are
electrically isolated.

I/O

Connector

10K is a recommended value. You m ay short LL GND to CH Low
inste ad, but this w ill reduce your system’s noise imm unity.

A/D Board

Already isolated signal source
and A/D board connected to
a differential input.

Figure 4-10. Isolated Grounds / Differential Inputs

4.3 ANALOG OUTPUTS

Analog outputs are simple voltage outputs which can be connected to any device which will recor d, display or be controlled by a
voltage. The CIO-DAS6402 analog outputs are 4 quadrant multiplying DACs. This means that they accept an input voltage
reference and provide an output voltage which is inverse to the reference voltage and proportional to the digital value in the output
register.

For example, the supplied reference of −5V provides a +5V output when the value in the output register is 4095 (full scale at
12-bits of resolution). It provides a value of 2.5V when the value in the output register is 2048.

The output ranges of the CIO-DAS6402/12 are set by software. The output ranges of the CIO-DAS6402/16 are set by dip switch.
Please refer to Section 3 for information regarding setting these switches.

13

5 REGISTER ARCHITECTURE

5.1 INTRODUCTION

The CIO-DAS6402 is controlled and monitored by reading and writing to 16 I/O addresses. The first address is referred to as the
BASE ADDRESS and is set by a bank of switches on the board. All other addresses are located at the BASE ADDRESS plus a
specified offset.

Registers are easy to r ead fro m and write to, though to cr eate a co mplete d ata ac quisitio n software p ro gram at the re gister le vel is a
significant undertaking. Unless there is a specific reason that you need to write your program at the register lever, we recommend
using our Universal Library.

In summary form, the registers and their function are listed on the following table. Within each register are eight bits which may
constitute a byte of data or be eight individual bit set/read functions.

Table 5-1. DAS6402 I/O Map - COMPATIBLE Mode

(BOLD indicates register definition for DAS6402/16)

WRITE FUNCTIONREAD FUNCTIONADDRESS
Software Start A/D ConversionA/D bits 0(LSB) - 3 & Channel # BASE
NoneA/D Bits 4 -11 (MSB)BASE + 1

Software Start A/D ConversionA/D bits 0 (LSB) - 7 BASE
NoneA/D Bits 8 - 15 (MSB)BASE + 1

8/16 Channel Mux / Reset FIFO8/16 Channel Mux BASE + 2
Digital Output Bits 0-3 Digital Input bits 0-3 / External controlBASE + 3
D/A 0 Bits 0-3NoneBASE + 4
D/A 0 Bits 4-11NoneBASE + 5
D/A 1 Bits 0-3NoneBASE + 6
D/A 1 Bits 4-11NoneBASE + 7
Reset interrupt flip-flopEOC, UNI/BIP, SEDIFF, MuxBASE + 8
DMA Enable, Interrupt, Pacer SourceDMA Enable, Interrupt, Pacer Source BASE + 9
DAC range, TRIG0/CTR0DAC range, TRIG0/CTR0BASE +10
MODE, A/D Gain ControlDMA, U/B, SEDIFF, MODE, A/D GainBASE +11
Counter 0 DataCounter 0 DataBASE +12
CTR 1 Data - A/D Pacer ClockCTR 1 Data - A/D Pacer ClockBASE +13
CTR 2 Data - A/D Pacer ClockCTR 2 Data - A/D Pacer ClockBASE +14
8254 Counter Control RegisterNone. No read back on 8254BASE +15

14

Table 5-2. DAS6402 I/O Map - ENHANCED Mode

(BOLD indicates register definition for DAS6402/16)

WRITE FUNCTIONREAD FUNCTIONADDRESS
Software Start A/D Conversion A/D bits 0(LSB) -11 (MSB) (Word)BASE

Software Start A/D Conversion A/D bits 0(LSB) -15 (MSB) (Word)BASE

None Do not use, use BASE onlyBASE + 1
32/64 Channel Mux (Word) /Reset FIFOPost-Trigger Index CounterBASE + 2
Digital Output Bits 0-7 Digital Input bits 0-7 / External controlBASE + 3
D/A 0 Bits 0-3NoneBASE + 4
D/A 0 Bits 4-11NoneBASE + 5
D/A 1 Bits 0-3NoneBASE + 6
D/A 1 Bits 4-11NoneBASE + 7
Extend modes and clear interruptsFIFO, Interrupt Status, Clock rateBASE + 8
Burst Enable, Interrupt, Pacer SourceBurst Enable, Interrupt, Pacer SourceBASE + 9
DAC range, Pacer clock controlDAC range, Pacer clock controlBASE +10
UB,SEDIFF,MODE,Int source, ADGainUB,SEDIFF,MODE,Int source, ADGainBASE +11
CTR 0 Data: Preload for residual countCTR 0 Data: (Residual/ End of acq) BASE +12
CTR 1 Data - A/D Pacer ClockCTR 1 Data - A/D Pacer ClockBASE +13
CTR 2 Data - A/D Pacer ClockCTR 2 Data - A/D Pacer ClockBASE +14
8254 Counter Control RegisterNone. No read back on 8254BASE +15

5.2 A/D DATA WORD REGISTERS

In Enhanced Mode, two of the data registers are configured for 'Word' reads or writes, as opposed to performing the I/O operation
as separate byte reads or writes. These two registers are the A/D Data Register at the BASE+0, and the Channel Mux Hi/Lo
Register at BASE+2. Any IO accesses (reads or writes) to either of these registers is interpreted by the board as Word IO.

A/D DATA WORD REGISTER - 12 BIT

BASE + 0 Example, 300h, 768 Decimal
READ/WRITE

0132456789101112131415Mode

ENHANCED

MSB

COMPATIBLE

MSB

A read/write register. The A/D Data Register is configured as a wo rd because REP INSW can be used to quickly read data from
the board, allowing for higher A/D conversion rates than would be possible if using DMA, which accesses the A/D data as two
bytes.

READ
On read, the 12-bit ADC value is presented in 'left-justified' format, with the most-significant ADC bit occupying the data word
bit position #15; the least-significant ADC bit occupies bit position #4 of the data word.

WRITE
A write to the base address will cause an A/D conversion, (Bits 0&1 of BASE+9 must be 0.)

AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11

LSB

AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11

LSB

0000AD0

MA0MA1MA2MA3AD0

ENHANCED MODE: The channel tag is not available in enhanced mode, thus the lowest four bits of the data word will be read
back as zero.

COMPATIBLE MODE: The channel tag is available in compatible mode, occupying the lowest four bits of the data word.

15

A/D DATA WORD REGISTER - 16 BIT

BASE + 0 Example, 300h, 768 Decimal
READ/WRITE

0132456789101112131415Mode

ENHANCED

MSB

COMPATIBLE

MSB

READ
On read, the 16-bit ADC value is presented in 'left-justified' format, with the most-significant ADC bit occupying the data word
bit position #15; the least-significant ADC bit occupies bit position #0 of the data word.

WRITE
A write to the base address will cause an A/D conversion, (Bits 0&1 of BASE+9 must be 0.)

Whether in ENHANCED or COMPATIBLE MODE, there is no channel tag.

AD0

AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15

LSB
AD0

AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15

LSB

5.3 CHANNEL MUX HI/LO LIMITS WORD REGISTER

BASE ADDRESS +2 Example, 302h, 770 Decimal
WRITE

0132456789101112131415Mode

LO0LO1LO2LO3LO4LO5--HI 0HI 1HI 2 HI 3HI 4HI 5 --ENHANCED

1L2L4L8L1H2H4H8H--- --- --COMPATIBLE

WRITE
Writing to this register clears the FIFO.

ENHANCED MODE:
This register is configured as a Word to allow for additional bits, two for the low channel limit and two for the high channel limit,
which are used to generate the 6-bit counter sequence. This register cannot be accessed as two separate byte writes, access must
be done as an entire word. If a byte write to address 302 is attempted, then the HI0-HI5 data will be undefined. If a byte write to
address 303 is attempted, the board will assume that the data is to be written to the DOUT register.
When this register is written, the analog input multiplexers are set to the channel specified in LO0-LO5. After each conversion, the
input multiplexers increment to the next channel, reloading to the "LO" channel after the "HI" channel is reached.

READ
Used to return the pre-trigger index value as was done by an 8254 counter.

COMPATIBLE MODE:
READ/WRITE
The mux register operates as the DAS1600 series. The lower eight bits are separated in two nibbles; the upper four bits represent
the upper c hannel and the lo wer four b its re prese nt the lo wer channel . For example: to sca n channels 2 thro ugh 5, write the va lue
52 to Base + 2. The upper eight bits in this register are written to but cannot be read, and do not affect the mux sequencing circuit.

16

5.4 8-BIT DIGITAL I/O REGISTERS

BASE ADDRESS +3 Example, 303h, 771 Decimal
READ

01324567

DI3DI4DI5DI6DI7

The signals present at the 8 digital inputs are read as one byte. Three of the pins have special functions in addition to digital input.:

XPACER/DI0 External Pacer: Starts an A/D Conversion on each active edge.
XTRIG/DI1 External Trigger: Causes an entire acquisition to start or stop.
GATE0/DI2 Gate for CTR0 Used in Compatible mode only.

These special functions are optionally enabled in software, and are explained below. External Interrupt is enabled at BASE +9,
External Pacer and External Trigger are enabled at BASE +10. Please see those register descriptions for details.

WRITE

All of the eight bits are latched TTL outputs.

DI2

GATE0

DI1

XTRIG

DI0

XPACER

01324567

DO0DO1DO2DO3DO4DO5DO6DO7

5.5 DIGITAL TO ANALOG CONVERTER (ANALOG OUT) REGISTERS

D/A 0 REGISTERS

BASE ADDRESS +4 Example, 304h, 772 Decimal

6402/

BASE ADDRESS +5 Example, 305h, 773 Decimal

6402/

D/A 1 REGISTERS

BASE ADDRESS +6 Example, 306h, 774 Decimal

6402/

01234567

0000D/A0D/A1D/A2D/A312-BIT

D/A0D/A1D/A2D/A3D/A4D/A5D/A6D/A716-BIT

01234567

D/A4D/A5D/A6D/A7D/A8D/A9D/A10D/A1112-BIT
D/A8D/A9D/A10D/A11D/A12D/A13D/A14D/A1516-BIT

01234567

0000D/A0D/A1D/A2D/A312-BIT

D/A0D/A1D/A2D/A3D/A4D/A5D/A6D/A716-BIT

BASE ADDRESS +7 Example, 307h, 775 Decimal

6402/

WRITE ONLY

01234567

D/A4D/A5D/A6D/A7D/A8D/A9D/A10D/A1112-BIT
D/A8D/A9D/A10D/A11D/A12D/A13D/A14D/A1516-BIT

17

6402/12

Each 12 bit D/A output line has two 8-bit registers. The first contains the four least-significant bits of the data and four 'don't-care'
bits. The second register contains the eight most significant bits of the data.

Data can be written as two successive bytes or as one word. When two bytes are written, the lower address byte must be written
first, and then the higher byte, as the DAC output is updated when the higher byte is written.

When the data is written as a single word, the most significant bit of the DAC data is the most significant bit of the word. The
CPU will automatically write the data to the board as two successive bytes, writing the low and then the high byte.

6402/16

Each 16-bit D/A output line has two 8-bit registers. The first contains the eight least significant bits of the data and the second
register contains the eight most significant bits of the data. The data is written as two successive bytes - the lower first (or LSB's)
followed by the higher byte (or MSB's).
The 6402/16 also has a jumper (HD1) to select either individual update (UPDATE) or simultaneous updating (XFER) of both
DAC's. In UPDATE mode, when the higher address is written, that DAC is updated. In XFER mode, after both DAC's are loaded,
a Read cycle to any of the DAC registers with update both DAC's simultaneously.

5.6 STATUS REGISTER

BASE ADDRESS + 8 Example, 308h, 776 Decimal

READ

01234567Mode

FFNEFHALFFFULLXINTINT XTRIGINDGT 1/10MHzENHANCED

MA0MA1MA2MA3INTSEDIFFUNIBIPEOCCOMPATIBLE

Description of Status Register read bits:

ENHANCED MODE:

1/10MHz - Internal Pacer clock source. = 1, Pacer clock is 10MHz, = 0, Pacer clock is 1MHz.

INDGT - Index Gate. Signals when the ind ex counter has been shut off due to FIFO going Half Full. Whe n = 0, index counter

active or flip-flop has been reset (by CLRXTR). When = 1, index counter has been shut off.

XTRIG - State of external trigger flop, used when edge-triggering. When =1, the trigger has been activated. When = 0 idle or not
active. Cleared by CLRXTR.

INT - State of interrupt flop, from 1 of 4 sources on the bo ard. W hen = 1, the flip-flop indicates an interrupt conditio n. W hen = 0
no interrupt. Cleared by CLRINT. See BASE + 9 for interrupt enable and interrupt level and BASE + 11 for interrupt sources.

XINT - State of external interrupt flop, acts independently of on-board interrupt sources. When = 1, external interrupt occurred,
When = 0 no external interrupt. Cleared by CLRXIN.

FFULL - latched status of FIFO Full condition.

When = 1, FIFO exceeded

FHALF - indicates if FIFO is above or below half-full. Can be used as an interrupt source for REP INSW ADC.

When = 1, FIFO is above half-full. When = 0, FIFO is at or below half-full. (not latched)

FFNE - Not empty state of FIFO. Can be used as interrupt for single conversion ADC mode.

When = 1, FIFO is not empty (contains ADC data). When = 0, FIFO is empty (has no ADC data).

full state, data may have been lost. When = 0, FIFO has not exceeded full state.

COMPATIBLE MODE:

EOC - End-of-conversion, When 1 = busy. When = 0, conversion complete.

UNIBIP - Analog input Unipolar/Bipolar status, When 1 = unipolar. When 0, = bipolar.

18

SEDIFF - Analog input channel configuration, 0 = differential, 1 = single ended.

MA3:0 - Analog input channel mux setting (for next conversion).

WRITE

01234567

EXTENDARMEDPOSTMODE1/10MHz

ENHANCED MODE:

The write functions of the status register are to clear certain flip-flop states, and set the Pacer clock to 1 or 10 MHz.

CLRINT - Clear Interrupt flip-flop when = 1. No action when = 0.

CLRXTR - Clear External Trigger flip-flop when = 1. No action when = 0

CLRXIN - Clear External Interrupt flip-flop when = 1. No action when = 0.

(These 'Clear' functions get automatically reset to 0 in 1 to 2 µsec).

EXTEND - Qualifier for bits 5 to 7 data. Must be set to 1 prior to setting the desired bits at 5 to 7.
=0, any data at bits 5 to 7 will be ignored and the state of the bit will not change.
The MODE bit must be = 1 (Enhanced) to change the EXTEND bit.

Example: to set the 1/10MHz bit to set the Pacer time base to 10MHz:

-

CLRINTCLRXTRCLRXIN

Do each step as separate write operations:

1. Set MODE bit to 1 (base + B, bit 4)

2. Set EXTEND to 1 (base + 8, bit 4)

3. Set 1/10 bit to 1 (base + 8, bit 7), be sure to leave bit 4 set as well, including bits 5/6 if desired to leave them set.

4. Set EXTEND bit to 0, leave the bits in 5 to 7 set as required.
After EXTEND bit is zeroed, any writes to bits 5 to 7 are masked off (doesn't change).

Please note that the clear flip-flop bits in 0 to 2 will be active if their corresponding data bits are high during any write to base+8 in
Enhanced Mode.

ARMED - Used with various pre and post-trigger scenarios to gate a 'residual' counter on (CTR0 of the 8254).

Counter 0 operates in Mode 0 and counts conversions, stopping the acquisition process when it reaches terminal count.
When = 0, counting of post-trigger samples is disabled. When =1, counting of post-trigger samples is enabled.
See also POSTMODE.

POSTMODE - Used to select whether FifoHalf Full or ADC convert starts Counter 0. Used in conjunction with
PRETRIG to select a strobe to latch the Counter 0 gate. (See BASE + 10 for PRETRIG.) Refer to Table 6-3.

Total # of counts (N) less- than-or-equal-to FIFO 1/2-full is a special case:

Table 5-3. Post-Mode Operations

fifo>N>1/2fifo

N>fifo

Pretrig?Gate CTR0:

no
no

POST-MODE
0
0

0
0

ARMED bit is set by:Ctr 0 gate strobe:
Before acquisition is startedon last fifo half full
Next to last full 'packet'on last fifo half full

0

N <= 1/2 fifo

N> 1/2 fifo

N < =1/2 fifo

1/10MHz - Sets Pacer clock frequency. .

When bit 7 = 1, Forces Pacer clock to 10 MHz. When = 0, forces Pacer clock to 1 MHz.

no

yes
yes

1
1

1
0

1

19

Before acquisition is started1st conversion
ISR on last full 'packet'on fifo half (last interrupt)

Before acquisition is startedon the external trigger

COMPATIBLE MODE:

Write to Base + 8 only clears the interrupt flip-flop (sets CLRINT only (= 1)).

5.7 INTERRUPT AND PACER CONTROL REGISTER

BASE ADDRESS +9 Example, 309h, 777 Decimal

READ/WRITE

01234567

ENH

INTE =1, Analog Interrupts are enabled, =0, interrupts are disabled.
The system interrupt level is determined by the three HC_IS0-2 bits. The interrupt source (Single AD, FIFO Half-Full, End of
Burst) is selected by the two Analog Interrupt Source bits HC_AI0 & HC_AI1 (Base + 11). Use of external interrupt (XINTE) also
requires that INTE = 1.

HC_IS2, HC_IS1, HC_IS0 will map an enabled interrupt onto a specific ISA bus interrupt level. See Table 6-4 below:

Table 5-4. Interrupt Levels - Enhanced & Compatible

HC_PS0HC_PS1BURSTEXINTEHC_IS0HC_IS1HC_IS2INTE

HC_PS0HC_PS1DMAENXINTEHC_IS0HC_IS1HC_IS2INTECOM

Compatible (ref)Interrupt Level- EnhancedHC_IS0HC_IS1HC_IS2

nonenone000
none11100

22010
33110

none - see Note10001

55101
615011
77111

Note: Some Interrupt levels in Enhanced Mode are different from Interrupt levels in Compatible Mode. IRQ4 was dropped from
the Compatible-mode IRQ's to allow a single GAL to decode all IRQ's, and since COM1 uses IRQ4, the DAS1600 will probably
never use it.

XINTE: =1, External Interrupt enabled. =0, External Interrupt disabled. The external interrupt is a direct digital path from the
100-pin connector to the system interrupt. External Interrupt shares the Interrupt Level with the Analog Interrupt path. (Only
enabled in Enhanced mode).
BURSTE When = 1, Burst Mode is enabled. When = 0, Burst Mode is disabled. The number of channels in the burst is
determined by the Mux Hi/Lo register.
(BURST Mode also enabled by write to BASE + 406hex bit 6 as on DAS1600 series).

HC_PS1, HC_PS0: Controls the source of the A/D conversion Pacer according Table 6-5 below:

Table 5-5. Control Source of A/D Conversion Pacer

HC_PS0HC_PS1

External Pacer Falling Edge10

20

Pacer Source

Software Convert00

External Pacer Rising Edge01

Internal Pacer (8254)11

5.8 TRIGGER CONTROL/ DAC RANGE SELECT REGISTER

Triggering and Gating are digital means to control pacing. Triggering means that an active edge on the DI1 pin will start the A/D
Pacer. When the active edge occurs, the state of the pin is Don't Care. Gating means that a digital level on the DI1 pin will start or
stop the A/D Pacer; when the gate is active, A/D conversions are enabled. When the gate is inactive, A/D conversions are
suspended but they will resume when the gate returns to its active state. Gating and triggering both share DI1 pin and thus are
mutually exclusive. External Pacing, where each A/D conversion is started by an external signal, is tied to the DI0 pin. This means
that External Pacing can be combined with a Trigger/Gate function.

BASE ADDRESS +10 Example, 30Ah, 778 Decimal

WRITE

01234567Mode
ENHANCED
COMPATIBLE

NOTE: DACxRx ARE USED WIT H THE 6402/12 ONLY, (FOR THE 6402/16 THESE BITS HAVE NO FUNCTION - THE
DAC'S RANGES ARE SELECTED BY SWITCHES)

DAC0R0DAC0R1DAC1R0DAC1R1

G

T/G ENT/G SELT/G POLPRETRI

TRG0CTR0--DAC0R0DAC0R1DAC1R0DAC1R1

DAC#R0:
DAC#R1:

ENHANCED MODE:
T/G EN

T/G SEL

T/G POL

: Trigger/Gate Enable bit

: Trigger/Gate Select bit (Requires T/G EN =1)

: Trigger/Gate Polarity bit (Requires T/G EN =1 or PRETRIG = 1)

Output Range select bit for DAC #. When = 1, range is ±5V or 0 to 5V. When = 0; range is ±10V or 0 to 10V.
Output Polarity select bit for DAC #. When = 1, polarity is Unipolar. When = 0, polarity is Bipolar

When = 1, DI1 pin is enabled for Trigger/Gate function.
When = 0, Trigger/Gate function is not used. DI1 pin is strictly used for digital input.
If pretriggering, then set T/G EN to 0 since this will gate in the CTR0OUT clock with ARMED.

When = 0, DI1 pin functions as a Gate, the active level is determined by the T/G POL bit.
When = 1, DI1 pins functions as a Trigger, the active edge is determined by T/G POL bit.

When = 0, if trigger, active edge is rising; if gate, active level is high.
When = 1, if trigger, active edge is falling; if gate, active level is low.

Table 5-6. Output Range Select Codes

Set DAC Output Range

DAC#R0DAC#R1

00±5V
10±10V
010 to 5V
110 to 10V

PRETRIG

Counter 0 clock input is generated from the Conversion Complete pulse to count the number of conversions performed.
A 'Pre-trigger ind ex' counter value can be read (as a Word) from Base + 2 to give the number o f conversions that ha ve occurred
from the Trigger to the half-full or End-of-Acq uisition interrupt. Sinc e current FIFO half-full is 512 conversions this number will
be in the range of 0 to 511.

: Used to stop pacing a certain number of conversions after the trigger occurs.

When = 1 , Pre-trigger Mode enabled. =0, Pre-trigger Mode disabled.
8254 Counter 0 is used as the 'Post-Trigger' counter
(Pre-trigger mode requires that T/G EN = 0, and that T/G SEL = 1 for edge triggering)

21

COMPATIBLE MODE:
TRIG0: Trigger/Gate Enable bit

When = 1, Enables DIN0 input to gate the pacer (external trigger/gate).
When = 0, Enables pacer gate preventing external trigger/gate control.

CTR0: Counter 0 input control

When = 1, 100 khz input to counter 0 if external counter 0 input is pulled high (or unconnected since the pin is
internally pulled high).
When = 0, external clock input generates pulses to counter 0 clock input.

READ

01234567Mode
ENHANCED
COMPATIBLE

PACERGATEARMEDPOSTMODE­PACERGATEARMEDPOSTMODE-

T/G ENT/G SELT/G POLPRETRIG

TRG0CTR0--

ARMED - When = 0, counting of post-trigger samples is disabled. When = 1, counting of post-trigger samples is enabled.

POSTMODE - SEE REGISTER BASE+8 FOR FULL DESCRIPTION.

PACERGATE - When = 0: the Gate for the 8254 PACER is off. When = 1, the Pacer is on.

5.9 COMPATIBLE MODE CONTROL REGISTER

BASE ADDRESS +11 Example, 30Bh, 779 Decimal

READ/WRITE

01234567

GAIN0GAIN1HC_AI0HC_AI1MODESE/DIFFUNI/BIPDMA1/3

Since the DAS6402 has no switches or jumpers, certain options must be selectible for Compatible Mode. This is done by placing
these selections in the Compatible Mode register. The Mode bit must be set to 1 first to allow the following bits to be changed:

DMA1/3, UNI/BIP, SE/DIFF. The default state for all three bits is 0, which is how the DAS1600 is shipped.

DMA1/3 - When = 1, DMA channel 3 is selected.

When = 0, DMA channel 1 is selected.

DMA is allowed only in Compatible Mode, but the DMA channel selection bit can only b e changed when the board is in
Enhanced mode. The programmed state will be retained when the board is switched back to Compatible mode.

UNI/BIP - When = 1, Analog Front-End in Unipolar Range

When = 0, Analog Front-End in Bipolar Range

UNI/BIP is used for both Compatible and Enhanced modes, but the bit can only be changed when the board is in
Enhanced mode. The programmed state will be retained when the board is switched back to Compatible mode.

SE/DIFF: When = 1, Analog Front-End in Single-ended Mode

When = 0, Analog Front-End in Differential Mode

SE/DIFF is used for both Compatible and Enhanced modes, but the bit can only be changed when the board is in
Enhanced mode. In Compatible mode, the number of channels is limited according to the table below. The programmed
state will be retained when the board is switched back to Compatible mode.

MODE: When = 1, Board is configured in Enhanced Mode, which in general allows for 64 analog input channels,

enhanced triggering, FIFO/REP INSW support, etc..

When = 0, Board is configured in "Compatible" mode, it is software compatible to the DAS1600.

22

Table 5-7. Comparison of Features: Compatible vs. Enhanced Mode

# Analog Input Channels

# Digital I/O

External Triggering

connector

Interrupts

16 S-E

8 Diff

4 in

4 out

Combined w/ Pacing on DIN1, gate
only

Single ADC

DMA

MODEFeature

EnhancedCompatible

64 S-E

32 Diff

8 in

8 out

Separate from Pacing, uses DIN1.
Can be gate (level) or trigger
(edge)

Separate from Trigger, uses DIN0Combined w/ Trigger on DIN1External Pacing

noyesDMA

yesnoREP INSW

no, CTR0 used for pre-triggeringyes, CTR0Independent Counter at user

YesYes Burst Mode

Single ADC

REP INSW

End of Burst

External

YesNoPre-trigger

In Enhanced mode, HC_AI1, HC_AI0 select the interrupt source, which also will determine the acquisition mode the board is to
be operated under. These bits are 0 in Compatible mode. Refer to Table 6-8.

Table 5-8. Interrupt Source Coding - Enhanced Mode

HC_AI0HC_AI1

Interrupt SourceADC Acquisition Mode

noneSingle ADC polled 00

FIFO Not EmptySingle ADC interrupt10

FIFO ½ FullFifo REP INSW (512 samples)01
End of BurstBurst REP INSW ( 2-64 samples)11

If pre-trigger is enabled, (allowed during a REP INSW mode, HC_AI1=1) then an End-of-Acquisition interrupt will be enabled.
This interrupt occurs a pre-determined number of conversions after the trigger. Counter 0 is programmed to count conversions after
the trigger and will cause the interrupt when it counts down and reaches Terminal Count.

GAIN1, GAIN0 select the front end gain (Table 5-9). They are valid for Enhanced or Compatible Mode.

Table 5-9. Front-End Gain Coding

GAIN0GAIN1

Analog Input Voltage RangeAnalog Input Gain

0 to 10V or ±10V100

0 to 5V or ±5V210

0 to 2.5V or ±2.5V401

0 to 1.25V or ±1.25V811

23

5.10 PACER CLOCK DATA AND CONTROL REGISTERS

8254 COUNTER 0 DATA - POST TRIGGER CONVERSION COUNTER

BASE + 12 Example, 30Ch, 780 decimal

READ/WRITE

01324567

D1D2D3D4D5D6D7D8

Counter 0 is used to count conversions to stop the acquisition when a known number of samples have occurred. It essentially is
gated on when only a 'residual' number of conversions remain. The main counting of samples is d one by the Interrupt Service
Routine, which will increment each time by 'packets' equal to Fifo 1/2-full (Fifo 1/2-full is 512 for DAS6400). Generally the value
loaded into Counter 0 is N mod 512, where N is the total count, or the post trigger count, since Total count is not known when
pre-trigger is active. Counter 0 will be enabled by use of the
processed.
Counter 0 is to operated in Mode 0.

ARMED

bit (Base+8) when the next-to-last 1/2-full interrupt is

8254 COUNTER 1 DATA

BASE + 13 Example, 30Dh, 781 decimal

READ/WRITE

8254 COUNTER 2 DATA

BASE + 14 Example, 30Eh, 782 decimal

READ/WRITE

Counter 1 is the lower 16 bits of the 32-bit pacer clock divider. It's output is fed to the clock input of Counter 2 which is the upper
16-bits of the pacer clock divider. The clock input to Counter 1 is a precision oscillator source, selected by software to be 1MHz or
10MHz
Counter 2's output is called the 'Internal Pacer' and can be selected by software to the be the A/D Pacer source. Counters 1 & 2
should be configured to operate in 8254 Mode 2.

8254 CONTROL REGISTER

- PACER DIVIDER LOWER

01324567

D1D2D3D4D5D6D7D8

- PACER DIVIDER UPPER

01324567

D1D2D3D4D5D6D7D8

BASE + 15 Example, 30Fh, 783 decimal
WRITE ONLY

01324567

D1D2D3D4D5D6D7D8

The control register is used to set the operating Modes of 8254 Counters 0,1 & 2. A counter is configured by writing the correct
Mode information to the Control Register, then the proper count data must be written to the specific Counter Register. The
Counters on the 8254 are 16-bit devices. Since the interface to the 8254 is only eight bits wide, Count data is written to the
Counter Register as two successive bytes. First the low byte is written, then the high byte. The Control Register is eight bits wide.
Further information can be obtained on the 8254 data sheet, available from Intel or Harris.

24

6 CALIBRATION AND TEST

Every board was fully tested and calibrated before being placed in finished goods inventory at the factory. For normal
environments a calibration interval of 6 months to one year is recommended. If frequent variations in temperature or humidity are
common then recalibrate at least once every three months. It takes less than 20 minutes to calibrate a CIO-DAS6402.

6.1 REQUIRED EQUIPMENT

Ideally, you will need a precision voltage source, a 4 1/2 digit digital voltmeter (5 ½ digit for the CIO-DAS-6402/16), a calculator
and some wire. If you do not have a precision voltage source, you will need a non-precision source and have to make a few
calculations.

You will not need an extender card to calibrate the board but you will need to have the cover off you computer with the power on,
so trim pots can be adjusted during calibration. For that reason a plastic screwdriver has been supplied with your CIO-DAS6402.
In the event that the screwdriver is dropped into the PC, no damage will result from short circuits.

6.2 CALIBRATING THE A/D & D/A CONVERTERS

The A/D is calibrated by applying a known voltage to an analog input channel and adjusting trim pots for offset and gain. There
are four trim pots requiring adjustment to calibrate the analog input section of the CIO-DAS6402. The entire procedure is
described in detail in the Insta

TM

, calibration routine.

Cal

The CIO-DAS6402 should be calibrated for the range you intend to use it in. When the range is changed, slight variation in Zero
and Full Scale may result. These variations can be measured and removed in software if necessary.

7 SIGNAL CONDITIONING CIRCUITS

7.1 VOLTAGE DIVIDERS

An alternative method of measuring a signal which varies over a range greater than the input range of a digital input, is to use a
voltage divider. When correctly designed, it can drop the voltage of the input signal to a safe level the digital input can accept.

Ohm's law states:

Voltage = Current x Resistance

Kirkoff's law states:

The sum of the voltage drops around a circuit will be equal to the voltage drop for the entire circuit.

In a voltage divider, the voltage across one resistor in a series circuit is proportional to the total resistance divided by the one
resistor (see formula below).

The object in a voltage divider is to choose two resistors having the proportions of the maximum voltage of the input signal to the
maximum allowed input voltage.

The formula for attenuation is:

Attenuation = R1 + R2

R2

2 = 10K + 10K

10K

For example, if the signal varies between 0 and 20
volts and you wish to measure that with an analog
input with a full scale range of 0 to 10 volts, the
attenuation (A) is 2:1 or just 2.

25

R1 = (A-1) x R2

S

For a given atte nuation, pick a resistor and call it
R2, the use this formula to calculate R1.

Digital inputs often require the use of voltage dividers. For example, if you wish to measure a digital signal that is at 0 volts when
off and 24 volts when on, you cannot connect that directly to a digital input. The voltage must be dropped to 5 volts max when on.
The attenuation is 24:5 or 4.8.

Using the equation above, if R2 is 1K, R1 = (4.8−1) x 1000 = 3.8K.

Remember that a TTL input is 'on' when the input voltage is greater than 2.5 volts.

NOTE

2

The resistors, R1 and R2, are going to dissipate power in the divider circuit according to the equation W = I

x R;
(Current (I) = Voltage/Resistance). The higher the value of the resistance (R1 + R2), the less power dissipated
by the divider circuit. Here is a simple rule:

For attenuation of <5:1, no resistor should be less than 10K.

For attenuation of > 5:1, no resistor should be less than 1K.

7.2 LOW PASS FILTERS

A low pass filter is placed on the signal wires between a signal and an A/D board. It stops frequencies greater than the cutoff
frequency from entering the A/D board's analog or digital inputs.

The cutoff frequency is that frequency above which no variation of voltage with respect to time may enter the circuit. For example,
if a low pass filter had a cutoff frequency of 30 Hz, the kind of interference associated with line voltage (60 Hz) would be filtered
out but a signal of 25 Hz would be allowed to pass.

In a digital circuit, a low-pass filter is often used to filter an input
from a momentary contact button or relay.

IGNAL HIGH

A simple low-pass filter may be constructed from one resistor (R)
and one capacitor (C). The cutoff frequency is determined according
to the formulas below: (Use π= 3.14, R = ohms, C = Farads.)

LOW PASS FILTER

R

SIGNAL

VOLTS

C

A/D BOARD
HIGH INPUT

F

=

C

1

2*P i*R*C

1
Fc = --------------

SIGNAL LOW

A/D BOARD

LOW INPUT

2 * π * R * C

1
R = ---------------- Figure 7-2. Low-Pass Filter Theory
2* π * C * Fc

26

8 SPECIFICATIONS

8.1 CIO-DAS6402/16

Typical for 25 DegC unless otherwise specified.
Power consumption

Icc: Operating 1.17 A typical, 1.67 A max

Analog input section

A/D converter type AD976A, successive-approximation
Resolution 16 bits
Programmable ranges ±10V, ±5V, ±2.5V, ±1.25V, 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V
A/D pacing Programmable: internal counter or external source (DIN0, rising edge)

Data transfer Compatible: Byte wide, interrupt, software polled, DMA

Enhanced: Word wide, interrupt, software polled, REP INSW
Above via 1 kilo sample FIFO
Burst Mode (programmable option) @ 100 kHz

Polarity Unipolar/Bipolar, software selectable
Number of channels Compatible: 8 differential or 16 single-ended, software-selectable

Enhanced: 32 differential or 64 single-ended, software-selectable

Interrupts Programmable levels 2, 3, 5, 7, 10, 11, 15

Positive-edge triggered

Interrupt enable Programmable interrupt enable for internal and external interrupt
Interrupt sources End-of-conversion, FIFO not empty, FIFO half full, end-of-burst, external
Trigger sources Compatible: External hardware/software (DIN0)

Enhanced: External trigger/gate (DIN1), edge/level,polarity/edge programmable.

A/D Triggering Modes Digital:

Software configurable for Edge (triggered) or level-activated (gated).

Programmable polarity (rising/falling edge trigger, high/low gate).
Pre-trigger:
Unlimited pre- and post-trigger samples. Total # of samples must be > 512.

A/D conversion time 5 µs

Throughput 100 kHz min
Integral Linearity error ±2 LSB max

No missing codes guaranteed 16 bits
Gain drift (A/D specs) ±7 ppm/°C, all ranges
Zero drift (A/D specs) ±2 ppm/°C, all ranges
Input leakage current (@25 Deg C) 200 nA
Input impedance Min 10 Meg Ohms
Absolute maximum input voltage ±15V

27

Analog Output

Resolution 16 bits
Number of channels 2 Voltage Outputs
D/A type AD660BN
Voltage Ranges ±2.5, ±5, ±10, 0 to 2.5, 0 to 5, 0 to 10, switch-selectable

Offset error Adjustable to zero by potentiometer
Gain error Adjustable to zero by potentiometer
Differential nonlinearity ±1LSB max
Integral nonlinearity ±1LSB max
Monotonicity Guaranteed monotonic to 15 bits over temperature
Gain drift ±15 ppm/°C max
Bipolar offset drift ±5 ppm/°C max
Unipolar offset drift ±3 ppm/°C max

D/A pacing Software
D/A trigger modes N/A
Data transfer Byte or word update
Throughput System-dependent (software-paced)

Settling time (20V step to ±½LSB) 12 µs typ, 19 us max
Settling time (10V step to ±½LSB) 6 µs typ, 9 us max
Slew Rate 2.8 V/uS Typical

Current Drive ±5 mA min
Output short-circuit duration 40 mA min Continuous
Output Coupling DC
Amp Output Impedance (OP-27) 0.1 Ohms max

Miscellaneous Double buffered output latches

Update DACs individually or simultaneously (jumper selectable)
Power up and reset, all DAC's cleared to 0 volts (switch selects bipolar or
unipolar zero)

Digital Input / Output

Digital Type Output: 74LS244

Input: 74LS273

Configuration Compatible: Two dedicated ports, 4 inputs and 4 outputs

Enhanced: Two dedicated ports, 8 inputs and 8 outputs
Output High 2.7 volts @ -0.4 mA min
Output Low 0.4 volts @ 8 mA min
Input High 2.0 volts min, 7 volts absolute max
Input Low 0.8 volts max, - 0.5 volts absolute min

28

Counter section

Counter type 82C54
Configuration 3 down-counters, 16 bits each

Counter 0

Compatible mode - Independent

Source: Programmable external (CTR0 CLK) or 100 kHz internal source).
Gate: Available at connector (DIN2).
Output: Available at connector (CTR0 OUT).

Enhanced mode - ADC residual sample counter

Source: ADC Clock.
Gate: Internal use.
Output: End-of-Acquisition interrupt.

Counter 1 - ADC Pacer Lower Divider

Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.

Counter 2 - ADC Pacer Upper Divider

Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: ADC Pacer clock, available at user connector.

Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min

Environmental

Operating temperature range 0 to 70°C
Storage temperature range - 40 to 100°C
Humidity 0 to 90% non-condensing

29

8.2 CIO-DAS6402/12

Typical for 25°C unless otherwise specified.

Power consumption

Icc: Operating 1.05 A typical, 1.6 A max

Analog input section

A/D converter type ADS7800, Successive Approximation
Resolution 12 bits
Programmable ranges ±10V, ±5V, ±2.5V, ±1.25V, 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V
A/D pacing Programmable: internal counter or external source (DIN0, rising edge)
Data transfer Compatible: Byte wide, interrupt, software polled, DMA

Enhanced: Word wide, interrupt, software polled, REP INSW

Above via 1k sample FIFO

Burst Mode (programmable option) @ 250 kHz

Polarity Unipolar/Bipolar, software-selectable
Number of channels Compatible: 8 differential or 16 single-ended, software-selectable

Enhanced: 32 differential or 64 single-ended, software-selectable

Interrupts Programmable levels 2, 3, 5, 7, 10, 11, 15

Positive-edge triggered
Interrupt enable Programmable interrupt enable for internal and external interrupt
Interrupt sources End-of-conversion, FIFO not empty, FIFO half full, end-of-burst, external
Trigger sources Compatible: External hardware/software (DIN0)

Enhanced: External trigger/gate (DIN1), edge/level, polarity/edge programmable.

A/D Triggering Modes Digital:

Software configurable for Edge (triggered) or level-activated (gated).

Programmable polarity (rising/falling edge trigger, high/low gate).

Pre-trigger:

Unlimited pre- and post-trigger samples. Total # of samples must be > 512.

A/D conversion time 3 µs
Throughput 333 kHz min
Differential Linearity error ±.75 LSB
Integral Linearity error ±.5 LSB

No missing codes guaranteed 12 bits
Gain drift (A/D specs) ±6 ppm/°C, all ranges
Zero drift (A/D specs) ±1 ppm/°C, all ranges
Input leakage current (@25 Deg C) 200 nA
Input impedance Min 10Meg Ohms
Absolute maximum input voltage ±15V

30

Analog Output:

Resolution 12 bits
Number of channels 2 Voltage Output
D/A type AD7237
Voltage Ranges ±10V, ±5V, 0 to 5V, 0 to 10V. Software-programmable

Offset error Adjustable to zero by potentiometer
Gain error Adjustable to zero by potentiometer
Differential nonlinearity ±1LSB max
Integral nonlinearity ±1LSB max
Monotonicity Guaranteed monotonic over temperature
D/A Gain drift ±15 ppm/°C max
D/A Bipolar offset drift ±5 ppm/°C max
D/A Unipolar offset drift ±3 ppm/°C max

D/A pacing Software
D/A trigger modes N/A
Data transfer Byte or word update
Throughput System dependent (software paced)
Settling time (20V step to ±½LSB) 5 µs typ, 8 µs max
Slew Rate 4V/µs typ

Current Drive ±2 mA min
Output short-circuit duration 25 mA indefinite
Output Coupling DC
Amp Output Impedance (AD711) 0.1 Ohms max

Miscellaneous Double-buffered output latches

Power up and reset, all DAC's cleared to 0 volts

Digital Input / Output

Digital Type Output: 74LS244

Input: 74LS273
Configuration Compatible: Two dedicated ports, 4 inputs and 4 outputs

Enhanced: Two dedicated ports, 8 inputs and 8 outputs
Output High 2.7 volts @ -0.4 mA min
Output Low 0.4 volts @ 8 mA min
Input High 2.0 volts min, 7 volts absolute max
Input Low 0.8 volts max, - 0.5 volts absolute min

31

Counter section

Counter type 82C54
Configuration 3 down-counters, 16 bits each

Counter 0

Compatible mode - Independent

Source: Programmable external (CTR0 CLK) or 100kHz internal source).

Gate: Available at connector (DIN2).

Output: Available at connector (CTR0 OUT).

Enhanced mode - ADC residual sample counter

Source: ADC Clock.

Gate: Internal use.

Output: End-of-Acquisition interrupt.

Counter 1 - ADC Pacer Lower Divider

Source: 10 MHz oscillator

Gate: Tied to Counter 2 gate, programmable source.

Output: Chained to Counter 2 Clock.

Counter 2 - ADC Pacer Upper Divider

Source: Counter 1 Output.

Gate: Tied to Counter 1 gate, programmable source.

Output: ADC Pacer clock, available at user connector.

Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min

Environmental

Operating temperature range 0 to 70°C
Storage temperature range - 40 to 100°C
Humidity 0 to 90% non-condensing

32

For your notes.

33

For your notes.

34

EC Declaration of Conformity

We, Measurement Computing Corp., Inc., declare under sole responsibility that the product:

CIO-DAS6402/12
CIO-DAS6402/16

to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied according to the
relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents:

EU EMC Directive 89/336/EEC: Essential requirements relating to electromagnetic compatibility.

EU 55022 Class B: Limits and methods of measurements of radio interference characteristics of information technology equipment.

EN 50082-1: EC generic immunity requirements.

IEC 801-2: Electrostatic discharge requirements for industrial process measurement and control equipment.

IEC 801-3: Radiated electromagnetic field requirements for industrial process measurements and control equipment.

IEC 801-4: Electrically fast transients for industrial process measurement and control equipment.

Carl Haapaoja, Director of Quality Assurance

12-Bit Analog I/O Board
16-Bit Analog I/O Board

DescriptionPart Number

Measurement Computing Corporation

10 Commerce Way

Suite 1008

Norton, Massachusetts 02766

[phone]

Fax: [phone]

E-mail: [e-mail]

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