Measurement CIO-DAS08JR16 User Manual

CIO-DAS08/JR/16

&

CIO-DAS08/JR/16-AO

Analog and Digital I/O Board

User’s Manual

Revision 4

October, 2001

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HM CIO-DAS08_JR_16-AO.lwp

TABLE OF CONTENTS

1 INTRODUCTION

1.1 DIGITAL OUTPUTS & INPUTS

1.2 ANALOG INPUTS AND OUTPUTS

2 SOFTWARE INSTALLATION
3 HARDWARE INSTALLATION

3.1 BASE ADDRESS

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3.2 SIMULTANEOUS TRANSFER JUMPER - CIO-DAS08/JR/16-AO ONLY

3.3 INSTALLING THE BOARD IN THE COMPUTER

4 CALIBRATION AND TEST
5 SIGNAL CONNECTIONS
6 REGISTER ARCHITECTURE

6.1 REGISTER LAYOUT

6.2 A/D DATA REGISTERS

6.3 STATUS AND CONTROL REGISTER

6.4 DIGITAL I/O CONTROL REGISTER

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6.5 D/A CONTROL REGISTERS ( CIO-DAS08/JR/16-AO ONLY)

7 SPECIFICATIONS

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1 INTRODUCTION

The CIO-DAS08/JR/16 combines analog inputs with digital input and output capability, while the CIO-DAS08/JR/16-AO version adds
two channels of analog output capability. The CIO-DAS08/JR/16 may be upgraded to a CIO-DAS08/JR/16-AO by purchasing and
installing the CIO-DUAL-DAC16 chip set.

1.1 DIGITAL OUTPUTS & INPUTS

There are eight inputs and eight outputs for sensing and controlling digital devices. They are port-addressable and are dedicated to
either input or output. The digital outputs and inputs are TTL level.

1.2 ANALOG INPUTS AND OUTPUTS

The CIO-DAS08/JR/16 provides up to eight single-ende d analog inputs. In addition to the inputs, the CIO-DAS08/JR/1 6-AO version
can supply two analog voltage outputs. Sixteen-bit resolution is provided for analog inputs and outputs. The range is ±5V bip olar for
analog inputs (and outputs if used).

2 SOFTWARE INSTALLATION

The board has a bank of switches and a jumper to set before installing the board in your computer. By far the simplest way to configure
your board is to use the InstaCal
how to configure the various switches and jumpers to match your application requirements, and will create a configuration file that
your application software (and the Universal Library) will refer to so the software you use will automatically know the exact
configuration of the board.

Please refer to the Software Installation Manual regarding the installation and operation of InstaCal. The following information is
provided as a matter of completeness, and will allow you to do the hardware configuration of the board if you do not have immediate
access to InstaCal and/or your computer

TM

program provided as part of your software package. InstaCalTM will show you all available options,

.

3 HARDWARE INSTALLATION

3.1 BASE ADDRESS

The base address of either versio nof the CIO-DAS08/JR/16 is set by switching
a bank of DIP switches. The bank of switches, labeled ADDRESS, is
numbered 9 to 3.

Ignore the word ON and the numbers printed on the switch

Board logic adds up the weights of individual switches to determine the base
address. A 'weight' is active when the switch is down. Shown to the right,
switches 9 and 8 are down, all others are up. Weights 200h and 100h are
active, totaling a 300h base address.

Figure 3-1 Base Address Switches

1

RANGE

070-071

Table 3-1. PC I/O Addresses

FUNCTIONHEX

CMOS RAM & NMI MASK (AT)

FUNCTIONHEX

RANGE

EGA2C0-2CF8237 DMA #1000-00F
EGA2D0-2DF8259 PIC #1020-021
GPIB (AT)2E0-2E78253 TIMER040-043
SERIAL PORT2E8-2EF8255 PPI (XT)060-063
SERIAL PORT2F8-2FF8742 CONTROLLER (AT)060-064
PROTOTYPE CARD300-30F
PROTOTTYPE CARD310-31FDMA PAGE REGISTERS080-08F
HARD DISK (XT)320-32F8259 PIC #2 (AT)0A0-0A1
PARALLEL PRINTER378-37FNMI MASK (XT)0A0-0AF
SDLC380-38F8237 #2 (AT)0C0-0DF
SDLC3A0-3AF80287 NUMERIC CO-P (AT)0F0-0FF
MDA3B0-3BBHARD DISK (AT)1F0-1FF
PARALLEL PRINTER3BC-3BFGAME CONTROL200-20F
EGA3C0-3CFEXPANSION UNIT (XT)210-21F
CGA3D0-3DFBUS MOUSE238-23B
SERIAL PORT3E8-3EFALT BUS MOUSE23C-23F
FLOPPY DISK3F0-3F7PARALLEL PRINTER270-27F
SERIAL PORT3F8-3FFEGA2B0-2BF

3.2 SIMULTANEOUS TRANSFER JUMPER - CIO-DAS08/JR/16-AO Only

The analog outputs can be j umpered so that new output d ata are held until bo th DAC channels have been lo aded with new digital data.
Then, the new data updates the voltage outputs occurs when any addresses are read.

Jx

Figure 3-2. Simultaneous XFER/Individual UPDATE Jumper

A single jumper sets the DACs for either simultaneous transfer (XFER) or individual UPDATEs (Figure 3-2).

Jx

3.3 INSTALLING THE BOARD IN THE COMPUTER

1. Turn the power off.

2. Remove the cover of your computer. Please be careful not to dislodge any of the cables installed on the boards in your computer as
you slide the cover off.

3. Locate an empty expansion slot in your computer.

4. Push the board firmly down into the expansion bus connecto r. If it is not seated fully it may fail to work and could short circuit the
PC bus power onto a PC bus signal. This could damage the motherboard in your PC as well as the CIO-DAS08/JR/16-AO.

2

4 CALIBRATION AND TEST

The board is supplied with software for calibration and test. You will find it in the InstaCal program under the CALIBRATE option.
Follow the instructions to guide you through the calibration sequence.

5 SIGNAL CONNECTIONS

The I/O connector is a 37-pin, D-type connector accessible from the rear of the PC through the expansion backplate.

The connector accepts female 37-pin, D-type connectors, such as on the C37FF-2, a 2-foot cable with connectors. For quick and easy
access to the board, use CIO-MINI37 screw terminal board.

Figure 5-1. I/O Signal Connector - CIO-DAS08/JR/16-AO

NOTE: Pins 18 and 19 (Analog Out 0 and Analog Out 1) are not used in the CIO-DAS08/JR/16 board version.

3

6 REGISTER ARCHITECTURE

All of the programmable functions are accessible through the control and data registers, which are described here. W e recommend
programming with the Universal Library and not by direct register programming.

6.1 REGISTER LAYOUT

The board is controlled and monitored by writing to and/or reading from eight consecutive 8-bit I/O addresses. The first address, or
BASE ADDRESS, is determined by setting a bank of DIP switches on the board.

A register is easy to read and write to. Most often, registe r manipulation is best left to ASSE MBLY la nguage progr ams as most of the
board’s possible functions are implemented in easy to use Universal Library routines. Note that an X is an unspecified bit. There is no
function associated with that bit position. All X bits should be masked out of reads.

To write to or read from a register in decimal or HEX, the following weights apply:

Table 6-1. Bit Weights

HEX VALUEDECIMAL VALUEBIT POSITION

110
221
442

883
10164
20325
40646
801287

The registers and their function are listed on the following table. Within each register are 8 bits which may constitute a byte of data or
eight individual bit set/read functions.

Table 6-2. Board Registers

WRITE FUNCTIONREAD FUNCTIONADDRESS

NoneA/D Bits 8 - 15 (LSB)BASE
Start 16 bit A/D conversionA/D Bits 0 (MSB) - 7BASE + 1
Set A/D channelA/D status & MUX AddressBASE + 2
Digital output, 8 bitsDigital input, 8 bitsBASE + 3
D/A 0 LSB ( CIO-DAS08/JR/16-AO only)BASE + 4
D/A 0 MSB ( CIO-DAS08/JR/16-AO only)BASE + 5
D/A 1 LSB ( CIO-DAS08/JR/16-AO only)BASE + 6
D/A 1 MSB ( CIO-DAS08/JR/16-AO only)BASE + 7

6.2 A/D DATA REGISTERS

BASE ADDRESS

01234567

A/D14A/D13A/D12A/D11A/D10A/D9A/D8

READ ONLY

A/D15

LSB

This register contains the least-significant eight bits of the analog input data from the A/D converter. These eight bits of analog input
data are combined with the eight bits of analog input data in BASE + 1, forming a complete 16-bit number.
The data is in the format 0 = minus full scale. 65535 = +FS.

4

BASE ADDRESS + 1

01234567

A/D7A/D6A/D5A/D4A/D3A/D2A/D1POL/OVR

MSB

READ: The most significant A/D byte is read.

WRITE: Any write to this register causes an immediate A/D conversion.
A note of caution: Read EOC between consecutive A/D conversions to avoid over-running the A/D converter.

POL/OVR: The POL/OVR bit indicates the polarity of the signal, and may be used to detect an overrange signal, and determine the
value of that signal up to 192 counts over full scale.

To understand the operation of this bit, lets examine the process of making an A/D conversion.

1. To initiate a conversion, a write operation is performed on Base +1. The value of the data written does not matter. It is the toggling
of the chip select line and the write signal that cause the conversion to start.

2. The End Of Conversion (EOC) bit must be monitored (bit 7, Base +2). To monitor this bit, read Base +2. Mask all but bit 7, and
test for true (1) or false (0). While the bit is true, conversion is in progress. When it goes false the conversion is complete.

3. To read the converted signal value, read the LSB from Base +0 and the MSB from Base +1. The first time Base +1 is read, bit 7
will contain the polarity of the signal; true (1) for positive and false (0) for negative.

4. To check for an overrange condition, read Base +1 a second time. If bit 7 is true (1), the signal exceeds the full scale of the input. If
false (0), the signal is within the range of the converter.

6.3 STATUS AND CONTROL REGISTER

BASE ADDRESS + 2

This address has two registers, one for reading and one for writing.

READ = STATUS

01234567

ChAdd0ChAdd1ChAdd2XXXXEOC

EOC = 1 the A/D is busy converting and data should not be read.

EOC = 0 the A/D is not busy and data can be read.

ChAdd 2 to ChAdd 0 is the current analog input multiplexer channel. The current channel is a binary-coded number between 0 and 7.

WRITE = CONTROL

0123456

ChAdd0ChAdd1ChAdd2XXXXEOC

ChAdd 2 to ChAdd 0. Set the current channel address by writing a binary-coded number between 0 and 7 to these three bits.

5

6.4 DIGITAL I/O CONTROL REGISTER

BASE ADDRESS + 3

This address contains two registers, one for outputs and one for inputs. The output register is latched and holds the last value written
to it. The input register is not latched . Eac h time the register is read, the current sta te of the inputs is passed through this p ort into the
computer.

WRITE = Set digital output port, all bits.

READ = Read digital input port, all bits

, and

update both D/As simultaneously with last values written to D/A output registers.

01234567

D0D1D2D3D4D5D6D7

6.5 D/A CONTROL REGISTERS ( CIO-DAS08/JR/16-AO only)

Each D/A receives its data from a pair of 8-bit write-only registers. These registers contain the high byte and the low byte of the D/A
16-bit data word. The value written to these two registers determines the voltage output of the D/A chip. When in individual update
mode, the D/A outputs are updated when the high byte for the channel is written.

When in simultaneous mode, the D/A outputs are updated with the values in the D/A output registers when any register from BASE +0
to BASE + 7 is read.

The D/A output range can generally be calculated as [(#/65536) * 10V] − 5V.

The #/65536 is a proportion of the Full Scale Range, which is +/-5V.

D/A 0 CONTROL REGISTERS

BASE ADDRESS + 4 DAC 0 LOW BYTE

01234567

DA1DA2DA3DA4DA5DA6DA7

DA0
LSB

BASE ADDRESS + 5 DAC 0 HIGH BYTE

MSB

D/A 1 CONTROL REGISTERS

BASE ADDRESS + 6 DAC 1 LOW BYTE

BASE ADDRESS + 7 DAC 1 HIGH BYTE

MSB

01234567

DA8DA9DA10DA11DA12DA13DA14DA15

01234567

DA1DA2DA3DA4DA5DA6DA7

6

DA0
LSB

01234567

DA8DA9DA10DA11DA12DA13DA14DA15

ANALOG INPUTS - Both Versions

Type TC-850 Integrating Converter
Resolution 16 bits, 65536 divisions of full scale
Number of Channels 8, single-ended
Range ±5V

A/D Conversion Time 30 ms
Throughput 30 Hz

Differential Linearity Error ± 0.5 LSB Max
Integral Linearity Error ± 1 LSB Max
No missing codes Guaranteed to 16 bits
Voltage Reference Warm Up 20 Minutes Minimum

30 Minutes Typical
Input Leakage Current 100 nA max @ 25 deg. C.
On Channel Impedance 10 Megohms
Overvoltage ± 30 Volts Continuous

ANALOG OUTPUTS - CIO-DAS08/JR/16-AO Only

7 SPECIFICATIONS

Type AD660
Number of Channels 2
Range ± 5V Bipolar Only
Resolution 16 Bits (1/65536)
Settling time +/-FS 13 µs Max to +/-0.0008% of full scale
Linearity ± 2 LSB
Monotonicity 15 Bits guaranteed over temp range
Offset error ± 7mV
Gain error ± 3mV Max
Output Current 5 mA Min
Miscellaneous Update DAC channels individually or simultaneously (jumper-selectable)

Double-buffered latch output

DIGITAL I/O

Output Type 74LS373
Input Type 74LS244
Output low 0.4V max @ 8 mA
Output high 2.7V min @ −0.4 mA

IP1 - IP3 low 0.8V max, −0.5V absolute min
IP1 - IP3 high 2V min, 7V absolute max

ENVIRONMENTAL

Operating Temperature 0 to 50 deg C
Storage Temperature −20 to 70 deg C
Humidity 0 to 90% non-condensing
Weight 5 oz

7

POWER CONSUMPTION - NO DACs

+5V Supply 310 mA typical / 510 mA max.
+12V Supply 25 mA typical / 36 mA max.

−12V Supply 16 mA typical / 25 mA max.

POWER CONSUMPTION - WITH DACs

+5V Supply 315 mA typical / 520 mA max.
+12V Supply 52 mA typical / 78 mA max.

−12V Supply 43 mA typical / 66 mA max.

NOTE Additional power will be drawn by user's connections to the power pins accessible on board connectors.

8

EC Declaration of Conformity

We, Measurement Computing Corp., declare under sole responsibility that the product:

CIO-DAS08/JR/16-AO
CIO-DAS08/JR/16

to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied according to
the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents:

EU EMC Directive 89/336/EEC: Essential requirements relating to electromagnetic compatibility.

EU 55022 Class B: Limits and methods of measurements of radio interference characteristics of information technology equipment.

EN 50082-1: EC generic immunity requirements.

IEC 801-2: Electrostatic discharge requirements for industrial process measurement and control equipment.

IEC 801-3: Radiated electromagnetic field requirements for industrial process measurements and control equipment.

IEC 801-4: Electrically fast transients for industrial process measurement and control equipment.

Carl Haapaoja, Director of Quality Assurance

Analog I/O and Digital I/O board
Analog Input and Digital I/O board

DescriptionPart Number

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