All data sheets are subject to change without notice
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4 Megabit (512K x 8-Bit) SRAM
32C408B
©2002 Maxwell Technologies
All rights reserved.
05.02.02 Rev 7
FEATURES:
• 512k x 8-bit CMOS architecture
•R
AD-PAK® technology hardened against natural space radi-
ation
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Single event effect:
- SEL
TH
: > 68 MeV/mg/cm
2
- SEUTH: < 3MeV/mg/cm
2
- SEU saturated cross section: 6E-9 cm2/bit
• Package:
-36 pin R
AD-PAK® flat pack
• Fast propagation time:
-20, 25, 30 ns maximum access time
• Single 5V +
10% power supply
• Low power dissipation:
- Standby: 60mA (TTL); 10mA (CMOS)
- Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30
ns)
• TTL compatible inputs and outputs
• Fully static operation
- No clock or refresh required
• Three state outputs
DESCRIPTION:
Maxwell Technologies’ 32C408B high-speed 4 Megabit SRAM
microcircuit features a greater than 100 krad (Si) total dose
tolerance, depending upon space mission. Using R
AD-PAK®
packaging technology, the 32C408B realizes higher density,
higher performance and lower power consumption, and is well
suited for high-speed system application. Its fully static design
eliminates the need for external clocks, while the CMOS circuitry reduces power consumption and provides higher reliability. The 32C408B is equipped with eight common input/
output lines, chip select and output enable, allowing for
greater system flexibility and eliminating bus contention.
Maxwell Technologies' patented R
AD-PAK packaging technol-
ogy incorporates radiation shielding in the microcircuit package. In a GEO orbit, R
AD-PAK can provides true greater than
100 krad (Si) total radiation dose tolerance; dependent upon
space mission. The patented radiation-hardened R
AD-PAK
technology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a
space mission. This product is available with packaging and
screening up to Class S.
NC
A18
A0
A1
A2
A3
A4
CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
I/O8
I/O7
Vss
Vcc
A14
A13
A12
A11
NC
A10
I/O5
I/O6
1 36
18 19
ROW
DECODER
INPUT
DATA
CONTROL
MEMORY MATRIX
1024 ROWS x 4096 COLUMNS
COLUMN I/O
COLUMN DECODER
CS
A13
A0A1A3
DQ0
DQ7
DQ0
DQ7
A14A15A16A17A18
A2
A12
A11
A10
A9
A8
A7
A6
A5
A4
WE
OE
32C408B
Logic Diagram