1
Memory
All data sheets are subject to change without notice
(858) 503-3300- Fax: (858) 503-3301- www.maxwell.com
1 Megabit (128K x 8-Bit) EEPROM
28C011T
©2001 Maxwell Technologies
All rights reserved.
12.19.01 Rev 7
1000580
FEATURES:
• 128k x 8-bit EEPROM
•R
AD-PAK® radiation hardened against natural space radia-
tion
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
- No Latchup > 120 MeV/mg/cm
2
- SEU > 90 MeV/mg/cm
2
read mode
• Package:
- 32-pin R
AD-PAK® flat pack package
- JEDEC-approved byte-wide pinout
• High speed:
- 120, 150, and 200 ns maximum access times available
• High endurance:
- 10,000 cycles/byte, 10-year data retention
• Page write mode:
- 1 to 128 byte page
• Low power dissipation
- 20 mW/MHz active (typical)
- 110 µW standby (maximum)
• Screening per TM 5004
• QCI per TM5005
DESCRIPTION:
Maxwell Technologies’ 28C011T high-density 1 Megabit
(128K x 8-Bit) EEPROM microcircuit features a greater than
100 krad (Si) total dose tolerance, depending upon space mission. The 28C011T is capable of in-system electrical byte and
page programmability. It has a 128-byte page programming
function to make its erase and write operations faster. It also
features Data
Polling and a Ready / Busy signal to indicate the
completion of erase and programming operations. In the
28C011T, hardware data protection is provided with the RES
pin, in addition to noise protection on the WE signal and write
inhibit on power on and off. Software data protection is implemented using the JEDEC optional standard algorithm.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or
space mission. In a GEO orbit, R
AD-PAK provides greater than
100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S.
High Voltage
Generator
Control Logic Timing
Address
Buffer and
Latch
Y Decoder
X Decoder
Y Gating
Memory Array
I/O Buffer and
Input Latch
Data Latch
V
CC
V
SS
RES
OE
CE
WE
RES
A0
A6
A7
A16
I/O0 I/O7 RDY/Busy
Logic Diagram