MAXWELL 28C011TRPFB15, 28C011TRPFB12, 28C011TRT2FI15, 28C011TRT2FI12, 28C011TRT2FE20 Datasheet

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1
Memory
All data sheets are subject to change without notice
(858) 503-3300- Fax: (858) 503-3301- www.maxwell.com
1 Megabit (128K x 8-Bit) EEPROM
28C011T
©2001 Maxwell Technologies
All rights reserved.
1000580
FEATURES:
• 128k x 8-bit EEPROM
•R
AD-PAK® radiation hardened against natural space radia-
tion
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
- No Latchup > 120 MeV/mg/cm
2
- SEU > 90 MeV/mg/cm
2
read mode
• Package:
- 32-pin R
AD-PAK® flat pack package
- JEDEC-approved byte-wide pinout
• High speed:
- 120, 150, and 200 ns maximum access times available
• High endurance:
- 10,000 cycles/byte, 10-year data retention
• Page write mode:
- 1 to 128 byte page
• Low power dissipation
- 20 mW/MHz active (typical)
- 110 µW standby (maximum)
• Screening per TM 5004
• QCI per TM5005
DESCRIPTION:
Maxwell Technologies’ 28C011T high-density 1 Megabit
(128K x 8-Bit) EEPROM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mis­sion. The 28C011T is capable of in-system electrical byte and page programmability. It has a 128-byte page programming function to make its erase and write operations faster. It also features Data
Polling and a Ready / Busy signal to indicate the completion of erase and programming operations. In the 28C011T, hardware data protection is provided with the RES pin, in addition to noise protection on the WE signal and write inhibit on power on and off. Software data protection is imple­mented using the JEDEC optional standard algorithm.
Maxwell Technologies' patented RAD-PAK® packaging tech­nology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while provid­ing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, R
AD-PAK provides greater than
100 krad (Si) radiation dose tolerance. This product is avail­able with screening up to Class S.
High Voltage
Generator
Control Logic Timing
Address
Buffer and
Latch
Y Decoder
X Decoder
Y Gating
Memory Array
I/O Buffer and
Input Latch
Data Latch
V
CC
V
SS
RES
OE
CE
WE
RES
A0
A6
A7
A16
I/O0 I/O7 RDY/Busy
Logic Diagram
Memory
2
All data sheets are subject to change without notice
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
28C011T
12.19.01 Rev 7
1000580
TABLE 1. 28C011T PINOUT DESCRIPTION
PIN SYMBOL DESCRIPTION
12-4, 27, 26, 23,
25, 4,28, 3, 31, 2
A0-A16 Address
13-21 I/O 0 - 7 Data Input/Output
24 OE
Output Enable
22 CE
Chip Enable
29 WE
Write Enable
32 V
CC
Power Supply
16 V
SS
Ground
1 RDY/BUSY
Ready/Busy
30 RES
Reset
TABLE 2. 28C011T ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS
Supply Voltage (Relative to VSS)V
CC
-0.6 +7.0 V
Input Voltage (Relative to V
SS
)V
IN
-0.5
1
1. VIN min = -3.0V for pulse width < 50ns.
+7.0 V
Operating Temperature Range T
OPR
-55 +125
°
C
Storage Temperature Range T
STG
-65 +150
°
C
TABLE 3. DELTA LIMITS
PARAMETER VARIATION
ICC1 ±10%
I
CC
2 ±10%
I
CC
3 ±10%
I
LI
±10%
I
LO
±10%
Memory
3
All data sheets are subject to change without notice
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
28C011T
12.19.01 Rev 7
1000580
TABLE 4. 28C011T RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN MAX UNITS
Supply Voltage V
CC
4.5 5.5 V
Input Voltage
RES
_PIN
V
IL
-0.3
1
1. VIL min = 1.0V for pulse width < 50 ns
0.8 V
V
IH
2.2 VCC +0.3
V
H
VCC -0.5 VCC +1
Thermal Impedance — Flat Package
Θ
JC
-- 2.17 °C/W
Operating Temperature Range T
OPR
-55 +125
°
C
TABLE 5. 28C011T CAPACITANCE
(TA = 25 °C, f = 1 MHZ)
P
ARAMETER SYMBOL MIN MAX UNITS
Input Capacitance: VIN = 0V
1
1. Guaranteed by design.
C
IN
-- 6 pF
Output Capacitance: V
OUT
= 0V
1
C
OUT
-- 12 pF
TABLE 6. 28C011T DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
P
ARAMETER TEST CONDITION SYMBOL MIN MAX UNITS
Input Leakage Current VCC = 5.5V, VIN = 5.5V I
IL
-- 2
1
1. ILI on RES = 100 uA max.
µA
Output Leakage Current V
CC
= 5.5V, V
OUT
= 5.5V/0.4V I
LO
-- 2 µA
Standby V
CC
Current
CE = V
CC
ICC1 -- 20 µA
CE
= V
IH
ICC2 -- 1 mA
Operating V
CC
Current I
OUT
= 0mA, Duty = 100%, Cycle = 1µs at
V
CC
= 5.5V
ICC3 -- 15 mA
I
OUT
= 0mA, Duty = 100%, Cycle = 150ns at
V
CC
= 5.5V
-- 50
Input Voltage
RES
_PIN
V
IL
-- 0.8 V
V
IH
2.2 --
V
H
VCC -0.5 --
Output Voltage I
OL
= 2.1 mA V
OL
-- 0.4 V
I
OH
= -0.4 mA V
OH
2.4 --
Memory
4
All data sheets are subject to change without notice
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
28C011T
12.19.01 Rev 7
1000580
TABLE 7. 28C011T AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
1
(VCC = 5V + 10%, TA = -55 TO +125 °C)
1. Test conditions: Input pulse levels - 0.4V to 2.4V; input rise and fall times < 20ns; output load - 1 TTL gate + 100pF (including scope and jig); reference levels for measuring timing - 0.8V/1.8V.
P
ARAMETER SYMBOL MIN MAX UNITS
Address Access Time CE
= OE = VIL, WE = V
IH
-120
-150
-200
t
ACC
--
--
--
120 150 200
ns
Chip Enable Access Time OE
= VIL, WE = V
IH
-120
-150
-200
t
CE
--
--
--
120 150 200
ns
Output Enable Access Time CE
= VIL, WE = V
IH
-120
-150
-200
t
OE
0 0 0
75 75
100
ns
Output Hold to Address Change CE
= OE = VIL, WE = V
IH
-120
-150
-200
t
OH
0 0 0
--
--
--
ns
Output Disable to High-Z
2
CE = VIL, WE = V
IH
-120
-150
-200
CE
= OE = VIL, WE = V
IH
-120
-150
-200
2. t
DF
and t
DFR
are defined as the time at which the output becomes an open circuit and data is no longer driven.
t
DF
t
DFR
0 0 0
0 0 0
50 50 60
300 350 450
ns
RES
to Output Delay
3
CE = OE = VIL, WE = V
IH
-120
-150
-200
3. Guaranteed by design.
t
RR
0 0 0
400 450 650
ns
Memory
5
All data sheets are subject to change without notice
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
28C011T
12.19.01 Rev 7
1000580
TABLE 8. 28C011T AC ELECTRICAL CHARACTERISTICS FOR BYTE ERASE AND BYTE WRITE OPERATIONS
(VCC = 5V + 10%, TA = -55 TO +125 °C)
P
ARAMETER SYMBOL
MIN
1
MAX UNITS
Address Setup Time
-120
-150
-200
t
AS
0 0 0
--
--
--
ns
Chip Enable to Write Setup Time (WE
controlled)
-120
-150
-200
t
CS
0 0 0
--
--
--
ns
Write Pulse Width CE
controlled
-120
-150
-200
WE
controlled
-120
-150
-200
t
CW
t
WP
200 250 350
150 250 350
--
--
--
--
--
--
ns
Address Hold Time
-120
-150
-200
t
AH
150 150 200
--
--
--
ns
Data Setup Time
-120
-150
-200
t
DS
75 120 200
--
--
--
ns
Data Hold Time
-120
-150
-200
t
DH
10
10
20
--
--
--
ns
Chip Enable Hold Time (WE
controlled)
-120
-150
-200
t
CH
0 0 0
--
--
--
ns
Write Enable to Write Setup Time (CE
controlled)
-120
-150
-200
t
WS
0 0 0
--
--
--
ns
Write Enable Hold Time (CE
controlled)
-120
-150
-200
t
WH
0 0 0
--
--
--
ns
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