Transceiver Control Connections: .................................................................................................................................6
System Set-Up / Powering Up ........................................................................................................................... 7
MPIO Pins and Test Points ...........................................................................................................................................9
Power ............................................................................................................................................................................9
Table 7: Test Points.............................................................................................................................................. 9
Table 8: XR17V358IB-0A-EVB Bill of Materials.................................................................................................13
Table 9: XR17V358IB-E8-EVB Bill of Materials..................................................................................................15
Table 10: XR17V354IB-0A-EVB Bill of Materials................................................................................................ 17
November 2018001UMR00v
Page 6
XR17V354 and XR17V358 Evaluation Board User ManualIntroduction
Introduction
The XR17V354 and XR17V358 evaluation boards provide a platform to evaluate the features and performance of the
XR17V354 and XR17V358. The XR17V354 and XR17V358 are 4-channel and 8-channel PCIe UARTs, respectively. They
are available in the same package and are pin compatible, therefore they utilize the same evaluation board. The evaluation
board revision is 4.0. This user manual gives an overview of the evaluation board and its available configurations. The
available configurations are summarized in the ordering information section.
Please refer to the XR17V354 and XR17V358 datasheets for additional information about these devices.
Reference Documentation
Please refer to the XR17V354 and XR17V358 datasheets for additional information about these devices.
Figure 1: Top View of the XR17V358IB-E8-EVB
November 2018001UMR001
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XR17V354 and XR17V358 Evaluation Board User ManualReference Documentation
Figure 2: Bottom View of the XR17V358IB-E8-EVB
Figure 3: Top View of the XR17V358IB-0A-EVB
Figure 4: Bottom View of the XR17V358IB-0A-EVB
November 2018001UMR002
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XR17V354 and XR17V358 Evaluation Board User ManualOrdering Information
Ordering Information
Table 1: Evaluation Board Ordering Part Number
Evaluation BoardDescription
XR17V354IB-0A-EVBA single 4-channel XR17V354 PCIe UART and four SP339 Transceivers are installed.
XR17V354IB-E4-EVB
XR17V354IB-E8-EVB
XR17V358IB-0A-EVBA single 8-channel XR17V358 PCIe UART and eight SP339 Transceivers are installed.
XR17V358IB-E4-EVB
XR17V358IB-E8-EVB
1. Refer to www.exar.com/XR17V354 and www.exar.com/XR17V358 for most up-to-date Ordering Information.
Two 4-channel XR17V354 PCIe UARTs and eight SP339 Transceivers are installed in a master / slave
configuration.
A master 4-channel XR17V354 PCIe UART, a slave 8-channel XR17V358 PCIe UART and twelve SP339
Transceivers are installed.
A master 8-channel XR17V358 PCIe UART, a slave 4-channel XR17V354 PCIe UART and twelve SP339
Transceivers are installed.
Two 8-channel XR17V358 PCIe UARTs and sixteen SP339 Transceivers are installed in a master / slave
configuration.
November 2018001UMR003
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XR17V354 and XR17V358 Evaluation Board User ManualEvaluation Board Overview
XR17V358/354
(Master)
XR17V358/354
(Slave)
CLK+
CLK-
RX+
RX-
TX+
TX-
D[7:0]
CLK
INT
SEL
MODE
PRES
MODE
PRES
X
4
(
)
XR17V358/354
(Master)
X
(
)
XR17V358/3 54
(Slave)
CLK+
CLK-
RX+
RX-
TX+
TX-
D[7:0]
CLK
INT
SEL
MODE
PRES
MODE
PRES
3.3 V
PCIe Bus
Expansion
Interface
Evaluation Board Overview
This evaluation board has a x1 PCIe connector and will work in any x1, x4 or x16 PCI slot. Up to 16 UART ports can be
tested on this evaluation board when 2 XR17V358 are installed. The PCI interface of the master device is connected
directly to the PCIe connector. The master device communicates with the slave device via MaxLinear’s proprietary
expansion interface, illustrated in Figure 5. The PCIe interface on the slave device is not used and should be unconnected.
R17V358/35
Master
R17V358/354
Slave
Figure 5: PCIe and Expansion Interface
With the configuration shown below, the XR17V35x Windows device driver allows the Device Manager / Port Settings tab
to control the transceiver modes, slew and termination settings. A block diagram of the XR17V358IB-E8-EVB that uses this
configuration is shown in Figure 6. The device Manager / Port Settings tab is shown in Figure 8.
MPIO Connections:
MPIO3 of both XR17V35x master and slave are pulled-up. Optionally, they connect to the EN pins of their respective
transceivers.
MPIO1 of master XR17V35x is connected to CS of first XRA1405
MPIO2 of master XR17V35x is connected to CS of second XRA1405
MPIO1 of slave XR17V35x is connected to CS of third XRA1405
MPIO2 of slave XR17V35x is connected to CS of fourth XRA1405
Optional: MPIO3 of master is connected to EN pin of transceivers on master ports and MPIO3 of slave is connected to EN
pin of transceivers on slave ports. These MPIO3 pins are pulled up and the Port Settings tab cannot be used to disable the
transceivers.
SPI Interface:
EECK pin of master XR17V35x is connected to SCL pin of all XRA1405
EEDI pin of master XR17V35x is connected to SI pin of all XRA1405
EEDO pin of master XR17V35x is connected to SO pin of all XRA1405
November 2018001UMR004
Page 10
XR17V354 and XR17V358 Evaluation Board User ManualSPI Interface:
PCIe
Bus
Expansion
Interface
ExpansionInterface
XR17V358
Master
XRA1405
XRA1405
Ch 1 SP339
Ch 3 SP339
UART
Channels
1-8
UART
Channels
9-16
EN
TERM
SLEW
MODE1
MODE0
P0-4
P4-7
P8-11
P12-15
Ch 2 SP339
EN
TERM
SLEW
MODE1
MODE0
CS
EN
TERM
SLEW
MODE1
MODE0
Ch 4 SP339
EN
TERM
SLEW
MODE1
MODE0
SPI
Interface
3.3V
EN_M
EN_M
EN_M
EN_M
EN_M
CS
Ch 5 SP339
Ch 6 SP339
Ch 7 SP339Ch 8 SP339
Ch 9 SP339Ch 10 SP339
Ch 11 SP339Ch 12 SP339
Ch 13 SP339Ch 14 SP339
Ch 15 SP339Ch 16 SP339
CS
CS
EN_S
(Ch 9-16)
To DB68
EECK
EEDI
EEDO
MPIO4-15
MPIO3
MPIO2
MPIO1
MPIO4-15
MPIO3
MPIO2
MPIO1
SCL
SI
SO
XRA1405
XRA1405
3.3V
Expansion
Interface
XR17V358
Slave
UART
Channels
9-16
MPIO4-15
MPIO3
MPIO2
MPIO1
Figure 6: XR17V358IB-E8-EVB Block Diagram
November 2018001UMR005
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XR17V354 and XR17V358 Evaluation Board User ManualTransceiver Control Connections:
Transceiver Control Connections:
The XRA1405 outputs are sequentially (P0 to P15) connected to the MODE0, MODE1, SLEW and TERM pins of each
SP339 transceiver as shown in Table 2:
Table 2: XRA1405 to SP339 Connections
XRA1405 #XRA1405 Pin
P0
P1MODE1P1MODE1
P2SLEWP2SLEW
P3TERMP3TERM
P4
P5MODE1P5MODE1
P6SLEWP6SLEW
1 (Master)
2 (Master)
P7TERMP7TERM
P8
P9MODE1P9MODE1
P10SLEWP10SLEW
P11TERMP11TERM
P12
P13MODE1P13MODE1
P14SLEWP14SLEW
P15TERMP15TERM
P0
P1MODE1P1MODE1
P2SLEWP2SLEW
P3TERMP3TERM
P4
P5MODE1P5MODE1
P6SLEWP6SLEW
P7TERMP7TERM
P8
P9MODE1P9MODE1
P10SLEWP10SLEW
P11TERMP11TERM
P12
P13MODE1P13MODE1
P14SLEWP14SLEW
P15TERMP15TERM
SP339
Channel /
COM Port
1
2
3
4
5
6
7
8
SP339 PinXRA1405 #XRA1405 Pin
MODE0
MODE0P4
MODE0P8
MODE0P12
MODE0
MODE0P4
MODE0P8
MODE0P12
3 (Slave)
4 (Slave)
P0
P0
SP339
Channel /
COM Port
9
10
11
12
13
14
15
16
SP339 Pin
MODE0
MODE0
MODE0
MODE0
MODE0
MODE0
MODE0
MODE0
November 2018001UMR006
Page 12
XR17V354 and XR17V358 Evaluation Board User ManualSystem Set-Up / Powering Up
System Set-Up / Powering Up
Jumpers
Jumpers are factory installed per Table 3 to configure the EVB for operation. Jumpers may be added or removed per the
description. Refer to the product Data Sheets for additional information.
Table 3: Factory Settings
JumperLabelFactory SettingDescription
J1No jumperMaster ENIR# disabled
J41No jumperMaster EN485# disabled
J38No jumperSlave ENIR# disabled
J32No jumperSlave EN485# disabled
J37No jumperTransmit data to IR module not populated
J39No jumperReceive data to IR module not populated
XR17V354IB-0A-EVBNo jumperMaster PRES slave not present
For RS-232 mode, signals on the evaluation board go to the SCSI type ultra micro DB68 connector. Figure 7 shows the
DB68 connector on the board, and Table 4 shows the pin-out. The evaluation boards come with fan-out cables.
Figure 7: DB68 Connector
November 2018001UMR007
Page 13
XR17V354 and XR17V358 Evaluation Board User ManualPin-out Connectors
Table 4: DB68 Pin-out
Pin NumberSignal NamePin NumberSignal NamePin NumberSignal NamePin NumberSignal Name
1RXD718RXD335RXD852RXD4
2CT719CT336CT853CT4
3RIN720RIN337RIN854RIN4
4RT721RT338RT855RT4
5DCD722DCD339DCD856DCD4
6DT723DT340DT857DT4
7DS724DS341DS858DS4
8TXD725TXD342TXD859TXD4
9GND26GND43GND60GND
10TXD527TXD144TXD661TXD2
11DS528DS145DS662DS2
12DT529DT146DT663DT2
13DCD530DCD147DCD664DCD2
14RT531RT148RT665RT2
15RIN532RIN149RIN666RIN2
16CT533CT150CT667CT2
17RXD534RXD151RXD668RXD2
For RS-422/485 mode, signals on the evaluation board go to headers. Table 5 shows the header name for each channel;
Table 6 shows the pin-out used for each RS485/422 header.
Table 5: RS485/422 Headers for Each Channel
Channel
Number
Master 1J48 9 (Slave 1)J50
Master 2J4910 (Slave 2)J55
Master 3J8911 (Slave 3)J56
Master 4J9012 (Slave 4)J58
Master 5J9113 (Slave 5)J51
Master 6J9214 (Slave 6)J57
Master 7J9315 (Slave 7)J59
Master 8J9416 (Slave 8)J62
Header
Number
Channel
Number
Header
Number
Table 6: RS485/422 Header Pin-Out
Pin
Number
1TX- / RX-TX-DCD
2TX+ / RX+TX+RXD
3-RX+TXD
4-RX-DT
5--DS
6--RT
7--CT
8--RIN
RS485
Half Duplex
RS485 / RS422
Full Duplex
RS-232
Test Point
November 2018001UMR008
Page 14
XR17V354 and XR17V358 Evaluation Board User ManualMPIO Pins and Test Points
MPIO Pins and Test Points
The MPIO pins of both the master and slave devices are connected to test points or test headers on the evaluation board.
Refer to page 6 of the evaluation board schematic and Table 7 below for details. Note that an external pullup is
recommended for each unused MPIO pins configured as an input.
TP321V2 Buck Output (Master) Regulated 1.2 V output
TP331V2 Buck Output (Slave)Regulated 1.2 V output
TP34MPIO0 (Master)Timer output (when enabled)
TP35MPIO0 (Slave)Timer output (when enabled)
TP36MPIO4 (Master)General Purpose MPIO Test Point
TP37MPIO5 (Master)General Purpose MPIO Test Point
TP38MPIO4 (Slave)General Purpose MPIO Test Point
TP39MPIO5 (Slave)General Purpose MPIO Test Point
CC
Power
Power is connected when the PCIe board is plugged into the computer’s PCIe bus. Each XR17V354 and XR17V358 has
an internal buck regulator that is powered by the PCIe bus 3.3V supply and produces a 1.2V output. This 1.2V output may
be used to drive the 1.2V power required by the same XR17V35x, or alternatively the 1.2V may be supplied externally. If
using an external 1.2V supply, a 250ohm pull-down resistor is recommended on the VCC12 pin per the January 2012
Errata.
The PWRGD of each XR17V35x illuminates an LED when its buck regulator is within regulation.
Software
Software Drivers
Custom software drivers for Windows and Linux are available from MaxLinear at www.exar.com/design-tools/software-
drivers. For Linux, please refer to Application Note AN-225 Installing and Testing a PCI / PCIe UART Serial Port Using a
Custom MaxLinear Driver in Linux.
November 2018001UMR009
Page 15
XR17V354 and XR17V358 Evaluation Board User ManualSoftware
Windows Device Manager / Port Settings Tab
After loading the Windows driver, access the Device Manager as shown in Figure 8 (right side). From there, open the
ExarMPIO-Access Device as shown in Figure 8 (left side) to see the Port Settings. Here the transceiver mode, slew rate
and RS-485 receiver termination enable can be selected. See the SP339E datasheet for more. Click on the Expansion
Device Ports button on the lower right to see the slave ports for E4 and E8 EVBs. For 0A EVBs, there are no Expansion
Device Ports.
1. Loopback mode occurs at the transceiver, not at the UART.
2. Slew control applies to RS-232, RS485 Half and Full Duplex. Term applies to RS-485 Half and Full Duplex. See SP339 datasheet for more.
Figure 8: Device Manager / Port Setting tab example
After the ports are set, they can be tested using any serial testing tool or MaxLinear’s Super GUI which can be found from
the XR17V358 product page, under Design Tools / Evaluation Hardware and Software, Software Drivers.
Please note: When designing your own board, all hardware connections listed in the Evaluation Board Overview section
are required for the MaxLinear custom driver to enable the COM GPIO settings in Figure 8. If any of these connections are
missing, this tab will be blank.
November 2018001UMR0010
Page 16
XR17V354 and XR17V358 Evaluation Board User ManualXR17V354 and XR17V358 EVB Schematics
XR17V354 and XR17V358 EVB Schematics
The schematic for the XR17V358IB-E8-EVB can be found on www.exar.com/XR17V358 under the documentation tab,
under schematics. The XR17V358IB-0A-EVB uses the same schematic, except the slave components are not populated.
The XR17V358IB-E4-EVB uses the same schematic, except the slave PCIe UART is the XR17V354 (the XR17V358 is pin
compatible to the XR17V354) and the transceivers for channels 5-8 are not populated.
For the XR17V354 EVBs, again the pin compatibility with the XR17V358 is used. The slave components on the
XR17V354IB-0A-EVB are not populated, the XR17V354 is installed as the master and the master‘s channel 5-8
transceivers are not populated. For the XR17V354IB-E4-EVB, a master XR17V354 and a slave XR17V354 is installed;
channel 5-8 transceivers are not populated. For the XR17V354IB-E8-EVB, a master XR17V354 is installed and its channel
5-8 transceivers are not populated.
See the Bill of Materials section for more regarding populated components for XR17V354IB-0A-EVB, XR17V358IB-0AEVB and XR17V358IB-E8-EVB. See product page for design guidelines for the XR17V354 and XR17V358.
November 2018001UMR0011
Page 17
XR17V354 and XR17V358 Evaluation Board User ManualXR17V354EVB / XR17V358EVB PCB
XR17V354EVB / XR17V358EVB PCB
Figure 9: XR17V354 / XR17V358 EVB Top Silkscreen
November 2018001UMR0012
Page 18
XR17V354 and XR17V358 Evaluation Board User ManualXR17V354 / XR17V358 EVB Bill of Materials
1611TP1, TP16, TP20, TP27, TP31, TP32, TP34, TP36, TP37 TEST POINT PC MINI
171U2Quad PCI Express UART
184U11, U16, U24, U25RS232/RS485/RS422
CAP CER 0.1UF 16V X7R
0402
0603
0805
1411
0603
SMD 0603
SINGLE STR 2 POS
RTANG 68POS PCB
SINGLE STR 8 POS
SINGLE STR 4POS
0805 1LN
MOHM SMD
1/10W 0402
RES SMD 4.7K OHM 1%
1/10W 0402
1/10W 0402
.040"D YELLOW
Transceiver with
Internal Termination
Wurth
885012205037
Wurth
855012106006
Wurth
885012107006
Kemet
T491B106K016AT
Wurth
885012206076
Lite-on
LTST-C190CKT
Wurth
62000211121
TE Connectivity, Amp
5796055-1
Wurth
62000811121
Wurth
62000411121
Wurth
742792096
Wurth
744029004
Panasonic
ERJ-2RKF4750X
Panasonic
ERJ-2RKF4701X
Panasonic
ERJ-2RKF1910X
Keystone
5004
MaxLinear
XR17V354IB176-F
MaxLinear
SP339EER1-L
November 2018001UMR0017
Page 23
XR17V354 and XR17V358 Evaluation Board User ManualDisclaimer
Table 10: XR17V354IB-0A-EVB Bill of Materials
ItemQtyReference DesignatorDescriptionManufacturer / Part Number
193U14XRA1405_QFN24
201U30IC EEPROM 1K SPI 2MHZ
8TSSOP
MaxLinear
XRA1405IL24-F
Microchip
AT93C46E-TH-B
MaxLinear, Inc.
5966 La Place Court, Suite 100
Carlsbad, CA 92008
760.692.0711 p.
760.444.8598 f.
www.maxlinear.com
The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by
MaxLinear, Inc. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this
guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be
reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or
otherwise), or for any purpose, without the express written permission of MaxLinear, Inc.
Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
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potential liability of MaxLinear, Inc. is adequately protected under the circumstances.
MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except
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