MAXLINEAR SP 3232 EEYL Datasheet

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Page 1

True +3.0V to +5.5V RS-232 Transceivers

V-

SHDN

C1+

V+

C1-

C2+

C2-

R1IN

GND

T1OUT

R2IN

SP3222E

T2OUT

T2IN

T1IN

R1OUT

nSOIC

R2OUT

FEATURES

■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply

■ Minimum 120kbps Data Rate Under Full

Load

■ 1µA Low Power Shutdown with

Receivers active (SP3222E)

■ Interoperable with RS-232 down to a +2.7V power source

■ Enhanced ESD Specications:

+15kV Human Body Model +15kV IEC61000-4-2 Air Discharge +8kV IEC61000-4-2 Contact Discharge

SP3222E/SP3232E

Now Available in Lead Free Packaging

Note: See page 6 for other pinouts

DESCRIPTION

The SP3222E/SP3232E series is an RS-232 transceiver solution intended for portable or hand-held applications such as notebook or palmtop computers. The SP3222E/SP3232E series has a high-efciency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump allows the SP3222E/SP3232E series to deliver

true RS-232 performance from a single power supply ranging from +3.0V to +5.5V. The

SP3222E/SP3232E are 2-driver/2-receiver devices. This series is ideal for portable or hand-held applications such as notebook or palmtop computers. The ESD tolerance of the

SP3222E/SP3232E devices are over +/-15kV for both Human Body Model and IEC61000-4-2 Air discharge test methods. The SP3222E device has a low-power shutdown mode where

the devices' driver outputs and charge pumps are disabled. During shutdown, the supply current falls to less than 1µA.

MODEL Power

SP3222E +3.0V to +5.5V 2 2 4 Capacitors Yes Yes 18, 20

SP3232E +3.0V to +5.5V 2 2 4 Capacitors No No 16

Supplies

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

RS-232

Drivers

RS-232

Receivers

External

Components

SELECTION TABLE

Shutdown TTL

3-State

# of

Pins

Page 2

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect reliability and cause permanent damage to the

device.

VCC.......................................................-0.3V to +6.0V

V+ (NOTE 1).......................................-0.3V to +7.0V

V- (NOTE 1)........................................+0.3V to -7.0V

V+ + |V-| (NOTE 1)...........................................+13V

ICC (DC VCC or GND current).........................+100mA

Input Voltages

TxIN, EN, SHDN...........................-0.3V to Vcc + 0.3V

RxIN...................................................................+15V

Power Dissipation per package

20-pin SSOP (derate 9.25mW/oC above +70oC)..............750mW

18-pin SOIC (derate 15.7mW/oC above +70oC)..............1260mW

20-pin TSSOP (derate 11.1mW/oC above +70oC).............890mW

16-pin SSOP (derate 9.69mW/oC above +70oC)...............775mW

16-pin PDIP (derate 14.3mW/oC above +70oC)...............1150mW

16-pin Wide SOIC (derate 11.2mW/oC above +70oC)........900mW

16-pin TSSOP (derate 10.5mW/oC above +70oC)..............850mW

16-pin nSOIC (derate 13.57mW/oC above +70oC)...........1086mW

Output Voltages

TxOUT.............................................................+13.2V

RxOUT, .......................................-0.3V to (VCC +0.3V)

Short-Circuit Duration

TxOUT....................................................Continuous

Storage Temperature......................-65°C to +150°C

NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.

ELECTRICAL CHARACTERISTICS

Unless otherwise noted, the following specications apply for VCC = +3.0V to +5.5V with T

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

DC CHARACTERISTICS

Supply Current 0.3 1.0 mA no load, VCC = 3.3V,

= 25oC, TxIN = GND or V

AMB

Shutdown Supply Current 1.0 10 µA SHDN = GND, VCC = 3.3V,

= 25oC, TxIN = Vcc or GND

AMB

LOGIC INPUTS AND RECEIVER OUTPUTS

Input Logic Threshold LOW 0.8 V TxIN, EN, SHDN, Note 2

Input Logic Threshold HIGH 2.0 Vcc V Vcc = 3.3V, Note 2

Input Logic Threshold HIGH 2.4 Vcc V Vcc = 5.0V, Note 2

Input Leakage Current +0.01 +1.0 µA TxIN, EN, SHDN,

= +25oC, VIN = 0V to V

AMB

Output Leakage Current +0.05 +10 µA Receivers disabled, V

Output Voltage LOW 0.4 V I

Output Voltage HIGH VCC -0.6 VCC -0.1 V I

= 1.6mA

OUT

= -1.0mA

OUT

DRIVER OUTPUTS

Output Voltage Swing +5.0 +5.4 V All driver outputs loaded with 3kΩ to

GND, T

= +25oC

AMB

= T

OUT

to T

MIN

= 0V to V

MAX

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Page 3

Unless otherwise noted, the following specications apply for VCC = +3.0V to +5.5V with T Typical values apply at VCC = +3.3V or +5.0V and T

= 25°C.

AMB

ELECTRICAL CHARACTERISTICS

AMB

= T

MIN

to T

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

DRIVER OUTPUTS (continued)

Output Resistance 300 Ω VCC = V+ = V- = 0V, T

Output Short-Circuit Current +35 +60 mA V

OUT

= 0V

OUT

=+2V

Output Leakage Current +25 µA VCC = 0V or 3.0V to 5.5V,

= +12V, Drivers disabled

OUT

RECEIVER INPUTS

Input Voltage Range -15 +15 V

Input Threshold LOW 0.6 1.2 V Vcc = 3.3V

Input Threshold LOW 0.8 1.5 V Vcc = 5.0V

Input Threshold HIGH 1.5 2.4 V Vcc = 3.3V

Input Threshold HIGH 1.8 2.4 V Vcc = 5.0V

Input Hysteresis 0.3 V

Input Resistance 3 5 7 kΩ

TIMING CHARACTERISTICS

Maximum Data Rate 120 235 kbps RL = 3kΩ, CL = 1000pF, one

driver switching

Driver Propagation Delay, t

PHL

PLH

Receiver Propagation Delay, t

PHL

PLH

1.0 µs RL = 3kΩ, CL = 1000pF

0.3 µs Receiver input to Receiver

output, CL = 150pF

0.3 µs Receiver input to Receiver

output, CL = 150pF

Receiver Output Enable Time 200 ns

Receiver Output Disable Time 200 ns

Driver Skew 100 500 ns | t

Receiver Skew 200 1000 ns | t

PHL

- t

PLH

|, T

AMB

= 25°C

Transition-Region Slew Rate 30 V/µs Vcc = 3.3V, RL = 3kΩ,

CL = 1000pF, T measurements taken from -3.0V

= 25°C,

AMB

to +3.0V or +3.0V to -3.0V

MAX

NOTE 2: Driver input hysteresis is typically 250mV.

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Page 4

-2

-4

-6

Transmitter Output Voltage [V]

Load Capacitance [pF]

Vout+ Vout-

500

1000

1500

2000

TYPICAL PERFORMANCE CHARACTERISTICS

Slew Rate [V /µs ]

Load Capacitance [pF]

+Slew

-Slew

0 500

1000

1500

2000

2330

Suppl y Current [mA]

Load Capacitance [pF]

118KHz 60KHz 10KHz

0 500

1000

1500

2000

2330

Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 120kbps data rate, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and T

= +25°C.

AMB

Figure 1. Transmitter Output Voltage vs Load

Capacitance for the SP3222E and SP3232E

Figure 3. Supply Current VS. Load Capacitance

when Transmitting Data

Figure 2. Slew Rate vs Load Capacitance for the SP3222E and SP3232E

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Page 5

PIN FUNCTION

PIN NUMBER

NAME FUNCTION

Receiver Enable. Apply Logic LOW for normal operation. Apply logic HIGH to disable the receiver outputs (high-Z state)

C1+ Positive terminal of the voltage doubler charge-pump capacitor 2 2 1

V+ +5.5V output generated by the charge pump 3 3 2

C1- Negative terminal of the voltage doubler charge-pump capacitor 4 4 3

C2+ Positive terminal of the inverting charge-pump capacitor 5 5 4

C2- Negative terminal of the inverting charge-pump capacitor 6 6 5

V- -5.5V output generated by the charge pump 7 7 6

T1OUT RS-232 driver output. 15 17 14

T2OUT RS-232 driver output. 8 8 7

R1IN RS-232 receiver input 14 16 13

R2IN RS-232 receiver input 9 9 8

R1OUT TTL/CMOS receiver output 13 15 12

R2OUT TTL/CMOS receiver output 10 10 9

T1IN TTL/CMOS driver input 12 13 11

T2IN TTL/CMOS driver input 11 12 10

GND Ground 16 18 15

+3.0V to +5.5V supply voltage 17 19 16

Shutdown Control Input. Drive HIGH for normal device operation.

SHDN

Drive LOW to shutdown the drivers (high-Z output) and the onboard power supply

N.C. No Connect - 11, 14 -

Table 1. Device Pin Description

SP3222E SP3232E

SOIC SSOP

TSSOP

1 1 -

18 20 -

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Page 6

V-

SHDN

C1+

V+

C1-

C2+

C2-

N.C.

R1IN

GND

T1OUT

N.C.

R2IN

R2OUT

SP3222E

T2OUT

T1IN

T2IN

R1OUT

SSOP/TSSOP

V-

SHDN

C1+

V+

C1-

C2+

C2-

R1IN

GND

T1OUT

R2IN

SP3222E

T2OUT

T2IN

T1IN

R1OUT

nSOIC

R2OUT

V-

C1+

V+

C1-

C2+

C2-

R1IN

R2IN

GND

T1OUT

T2IN

SP3232E

T1IN

R1OUT

R2OUT

T2OUT

PINOUT

Figure 4. Pinout Congurations for the SP3222E

Figure 5. Pinout Conguration for the SP3232E

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Page 7

SP3222E

GND

T1IN

T2IN

T1OUT

T2OUT

C1+

C1-

C2+

C2-

V+

V-

0.1µF

0.1µ F

0.1µF

*C3

0.1µF

RS-232 OUTPUTS

RS-232 INPUTS

LOGIC

INPUTS

5kΩ

R1IN

R1OUT

5kΩ

R2IN

R2OUT

LOGIC

OUTPUTS

SHDN

*can be returned to either VCC or GND

SSOP

TSSOP

SP3222E

GND

T1IN

T2IN

T1OUT

T2OUT

C1+

C1-

C2+

C2-

V+

V-

0.1µF

*C3

0.1µF

RS-232 OUTPUTS

RS-232 INPUTS

LOGIC

INPUTS

5kΩ

R1IN

R1OUT

5kΩ

R2IN

R2OUT

LOGIC

OUTPUTS

SHDN

*can be returned to either VCC or GND

WSOIC

SP3232E

GND

T1IN

T2IN

T1OUT

T2OUT

C1+

C1-

C2+

C2-

V+

V-

0.1µF

*C3

RS-232 OUTPUTS

RS-232 INPUTS

LOGIC

INPUTS

5kΩ

R1IN

R1OUT

5kΩ

R2IN

R2OUT

LOGIC

OUTPUTS

*can be returned to either VCC or GND

0.1µF

TYPICAL OPERATING CIRCUITS

Figure 6. SP3222E Typical Operating Circuits

Figure 7. SP3232E Typical Operating Circuit

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Page 8

The SP3222E/SP3232E transceivers

meet the EIA/TIA-232 and ITU-T V.28/V.24

communication protocols and can be imple-

mented in battery-powered, portable, or

hand-held applications such as notebook or palmtop computers. The SP3222E/SP3232E devices feature Exar's proprietary on-board

charge pump circuitry that generates ±5.5V

for RS-232 voltage levels from a single

+3.0V to +5.5V power supply. This series is ideal for +3.3V-only systems, mixed +3.3V to +5.5V systems, or +5.0V-only systems that require true RS-232 performance. The

SP3222E/SP3232E devices can operate

at a typical data rate of 235kbps when fully

loaded.

The SP3222E and SP3232E are 2-driver/2- receiver devices ideal for portable or handheld applications. The SP3222E features a

1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in

shutdown mode, allowing external devices

such as modems to be monitored using only 1µA supply current.

THEORY OF OPERATION

The SP3222E/SP3232E series is made up

of three basic circuit blocks:

1. Drivers

2. Receivers

3. The Exar proprietary charge pump

Drivers

The drivers are inverting level transmitters

that convert TTL or CMOS logic levels to +5.0V EIA/TIA-232 levels with an inverted

sense relative to the input logic levels.

Typically, the RS-232 output voltage swing

is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected

against innite short-circuits to ground without degradation in reliability. Driver outputs will meet EIA/TIA-562 levels of +/-3.7V with supply voltages as low as 2.7V.

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DESCRIPTION

The drivers can guarantee a data rate of

120kbps fully loaded with 3kΩ in parallel with 1000pF, ensuring compatability with

PC-to-PC communication software.

The slew rate of the driver is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Para-

graph 5). The transition of the loaded output

from HIGH to LOW also meet the monotonicity requirements of the standard.

Figure 8 shows a loopback test circuit used to test the RS-232 Drivers. Figure 9 shows the test results of the loopback circuit with all drivers active at 120kbps with RS-232 loads in parallel with a 1000pF capacitor. Figure 10 shows the test results where one driver was active at 235kbps and all drivers loaded with an RS-232 receiver in parallel with 1000pF capacitors. A solid RS-232 data transmis-

sion rate of 120kbps provides compatibility with many designs in personal computer

peripherals and LAN applications.

The SP3222E driver's output stages are turned off (tri-state) when the device is in

shutdown mode. When the power is off, the

SP3222E device permits the outputs to be

driven up to +/-12V. The driver's inputs do

not have pull-up resistors. Designers should connect unused inputs to Vcc or GND.

In the shutdown mode, the supply current falls to less than 1µA, where SHDN = LOW. When the SP3222E device is shut down,

the device's driver outputs are disabled (tristated) and the charge pumps are turned off

with V+ pulled down to Vcc and V- pulled to GND. The time required to exit shutdown is typically 100µs. Connect SHDN to Vcc if the

shutdown mode is not used.

Page 9

Figure 8. SP3222E/SP3232E Driver Loopback Test

T[ ]

T1 IN

T1 OUT

R1 OUT

Ch1

Ch3

5.00V

Ch2

5.00V M 2.50 µs

Ch1

5.00V

T[ ]

T1 IN

T1 OUT

R1 OUT

Ch1

Ch3

5.00V

Ch2

5.00V M 5.00µs

Ch1

5.00V

SP3222E SP3232E

GND

TxIN

TxOUT

C1+

C1-

C2+

C2-

V+

V-

0.1µF

LOGIC

INPUTS

5kΩ

RxIN

RxOUT

LOGIC

OUTPUTS

EN*

*SHDN

1000pF

* SP3222E only

Circuit

DESCRIPTION

Receivers

The Receivers convert EIA/TIA-232 levels to TTL or CMOS logic output levels. The

SP3222E receivers have an inverting tri-state

output. These receiver outputs (RxOUT)

are tri-stated when the enable control EN =

HIGH. In the shutdown mode, the receivers

can be active or inactive. EN has no effect on TxOUT. The truth table logic of the SP3222E driver and receiver outputs can be found in Table 2.

SHDN EN TxOUT RxOUT

0 0 Tri-state Active

0 1 Tri-state Tri-state

1 0 Active Active

1 1 Active Tri-state

Table 2. SP3222E Truth Table Logic for Shutdown

and Enable Control

Since receiver input is usually from a transmission line where long cable lengths and

system interference can degrade the signal, the inputs have a typical hysteresis margin

of 300mV. This ensures that the receiver

is virtually immune to noisy transmission

lines. Should an input be left unconnected,

an internal 5kΩ pulldown resistor to ground

will commit the output of the receiver to a

HIGH state.

Figure 9. Loopback Test results at 120kbps

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Figure 10. Loopback Test results at 235kbps

Charge Pump

The charge pump is an Exar-patended

design (U.S. 5,306,954) and uses a unique approach compared to older less-efcient designs. The charge pump still requires four

external capacitors, but uses a four-phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal

power supply consists of a regulated dual

charge pump that provides output voltages

of +/-5.5V regardless of the input voltage (Vcc) over the +3.0V to +5.5V range.

Page 10

DESCRIPTION

In most circumstances, decoupling the power supply can be achieved adequately using a 0.1µF bypass capacitor at C5 (refer to gures 6 and 7). In applications that are sensitive to power-supply noise, decouple

Vcc to ground with a capacitor of the same

value as charge-pump capacitor C1. Physically connect bypass capcitors as close to the IC as possible.

The charge pump operates in a discontinu-

ous mode using an internal oscillator. If the

output voltages are less than a magnitude

of 5.5V, the charge pump is enabled. If the

output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows.

Phase 1

— VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC.

is then switched to GND and the charge

–

in C

is transferred to C

nected to VCC, the voltage potential across

–

. Since C

is con-

capacitor C2 is now 2 times VCC.

Phase 2

— VSS transfer — Phase two of the clock connects the negative terminal of C2 to the V storage capacitor and the positive terminal of

C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND.

Phase 4

— VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge

pump cycle to begin again. The charge pump cycle will continue as long as the

operational conditions for the internal oscillator are present.

Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent

inefciencies in the design.

The clock rate for the charge pump typically operates at greater than 250kHz. The external capacitors can be as low as 0.1µF with

a 16V breakdown voltage rating.

Phase 3

— VDD charge storage — The third phase of

the clock is identical to the rst phase — the

charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since

is at VCC, the voltage potential across C2

is 2 times VCC.

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Page 11

VCC = +5V

VSS Storage Capacitor

VDD Storage Capacito

+ +

–

––

-5.5V

VCC = +5V

–5V –5V

+5V

VSS Storage Capacitor

VDD Storage Capacitor

+ +

–

––

Figure 11. Charge Pump — Phase 1

VCC = +5V

–5V –5V

+5V

VSS Storage Capacitor

VDD Storage Capacitor

+ +

–

––

VCC = +5V

VSS Storage Capacitor

VDD Storage Capacito

+ +

–

––

+5.5V

Ch1 2.00V Ch2 2.00V M 1.00µ s Ch1 5.48V

T[ ]

+6V

a) C

b) C2-

GND

-6V

Figure 12. Charge Pump — Phase 2

DESCRIPTION

Figure 13. Charge Pump Waveforms

Figure 14. Charge Pump — Phase 3

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Figure 15. Charge Pump — Phase 4

Page 12

ESD TOLERANCE

Device Under

Test

DC Power

Source

SW1

SW2

The SP3222E/SP3232E series incorpo-

rates ruggedized ESD cells on all driver

output and receiver input pins. The ESD structure is improved over our previous

family for more rugged applications and

environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up.

DESCRIPTION

the system is required to withstand an amount of static electricity when ESD is applied to

points and surfaces of the equipment that

are accessible to personnel during normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit

for IEC61000-4-2 is shown on Figure 17. There are two methods within IEC61000-4-2,

the Air Discharge method and the Contact Discharge method.

There are different methods of ESD testing

applied:

a) MIL-STD-883, Method 3015.7 b) IEC61000-4-2 Air-Discharge c) IEC61000-4-2 Direct Contact

The Human Body Model has been the generally accepted ESD testing method

for semi-conductors. This method is also

specied in MIL-STD-883, Method 3015.7

for ESD testing. The premise of this ESD test

is to simulate the human body’s potential to store electro-static energy and discharge it

to an integrated circuit. The simulation is

performed by using a test model as shown in Figure 16. This method will test the IC’s capability to withstand an ESD transient

during normal handling such as in manu-

facturing areas where the ICs tend to be handled frequently.

The IEC-61000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed

to the outside environment and human pres-

ence. The premise with IEC61000-4-2 is that

With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to nd an unpleasant zap just before the person touches the back panel. The high energy

potential on the person discharges through

an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the

discharge current rather than the discharge voltage. Variables with an air discharge such

as approach speed of the object carrying the ESD potential to the system and humidity

will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed.

The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability

of the ESD arc. The discharge current rise

time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the

Figure 16. ESD Test Circuit for Human Body Model

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Page 13

Figure 17. ESD Test Circuit for IEC61000-4-2

and

add up to 330Ω for IEC61000-4-2.

Device Under

Test

DC Power

Source

SW1

SW2

Contact-Discharge Model

t = 0ns t = 30ns

15A

30A

I →

t →

DESCRIPTION

equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and nally to the IC.

The circuit models in Figures 16 and 17 rep-

resent the typical ESD testing circuit used for

all three methods. The CS is initially charged

with the DC power supply when the rst switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored

in the capacitor is then applied through RS, the current limiting resistor, onto the device

under test (DUT). In ESD tests, the SW2

switch is pulsed so that the device under test receives a duration of voltage.

For the Human Body Model, the current

limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For

IEC-61000-4-2, the current limiting resistor

(RS) and the source capacitor (CS) are 330Ω

an 150pF, respectively.

The higher CS value and lower RS value in

the IEC61000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on.

The lower current limiting resistor increases the current charge onto the test point.

Figure 18. ESD Test Waveform for IEC61000-4-2

DEVICE PIN HUMAN BODY IEC61000-4-2 TESTED MODEL Air Discharge Direct Contact Level

Driver Outputs +15kV +15kV +8kV 4 Receiver Inputs +15kV +15kV +8kV 4

Table 3. Transceiver ESD Tolerance Levels

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

Page 14

PACKAGE: 20 PIN SSOP

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

Page 15

PACKAGE: 16 PIN SSOP

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

Page 16

PACKAGE: 16 PIN PDIP

▲

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

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PACKAGE: 16 PIN WSOIC

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

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PACKAGE: 18 PIN WSOIC

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

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PACKAGE: 16 PIN nSOIC

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

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PACKAGE: 16 PIN TSSOP

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

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PACKAGE: 20 PIN TSSOP

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

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ORDERING INFORMATION

Part Number Temp. Range Package

SP3222ECA-L 0°C to +70°C 20 Pin SSOP

SP3222ECA-L/TR 0°C to +70°C 20 Pin SSOP

SP3222ECT-L 0°C to +70°C 18 Pin WSOIC

SP3222ECT-L/TR 0°C to +70°C 18 Pin WSOIC

SP3222ECY-L 0°C to +70°C 20 Pin TSSOP

SP3222ECY-L/TR 0°C to +70°C 20 Pin TSSOP

SP3222EEA-L -40°C to +85°C 20 Pin SSOP

SP3222EEA-L/TR -40°C to +85°C 20 Pin SSOP

SP3222EET-L -40°C to +85°C 18 Pin WSOIC

SP3222EET-L/TR -40°C to +85°C 18 Pin WSOIC

SP3222EEY-L -40°C to +85°C 20 Pin TSSOP

SP3222EEY-L/TR -40°C to +85°C 20 Pin TSSOP

Part Number Temp. Range Package

SP3232ECA-L 0°C to +70°C 16 Pin SSOP

SP3232ECA-L/TR 0°C to +70°C 16 Pin SSOP

SP3232ECN-L 0°C to +70°C 16 Pin NSOIC

SP3232ECN-L/TR 0°C to +70°C 16 Pin NSOIC

SP3232ECP-L 0°C to +70°C 16 Pin PDIP

SP3232ECT-L 0°C to +70°C 16 Pin WSOIC

SP3232ECT-L/TR 0°C to +70°C 16 Pin WSOIC

SP3232ECY-L 0°C to +70°C 16 Pin TSSOP

SP3232ECY-L/TR 0°C to +70°C 16 Pin TSSOP

SP3232EEA-L -40°C to +85°C 16 Pin SSOP

SP3232EEA-L/TR -40°C to +85°C 16 Pin SSOP

SP3232EEN-L -40°C to +85°C 16 Pin NSOIC

SP3232EEN-L/TR -40°C to +85°C 16 Pin NSOIC

SP3232EEP-L -40°C to +85°C 16 Pin PDIP

SP3232EET-L -40°C to +85°C 16 Pin WSOIC

SP3232EET-L/TR -40°C to +85°C 16 Pin WSOIC

SP3232EEY-L -40°C to +85°C 16 Pin TSSOP

SP3232EEY-L/TR -40°C to +85°C 16 Pin TSSOP

Note: "/TR" is for tape and Reel option. "-L" is for lead free packaging

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413

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REVISION HISTORY

DATE REVISION DESCRIPTION

08/22/05 -- Legacy Sipex Datasheet

12/08/10 1.0.0 Convert to Exar Format and update ordering information.

03/14/13 1.0.1 Correct type error to driver Transition-Region Slew Rate

conditions.

Notice

EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specic application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.

Datasheet March 2013

For technical questions please email Exar's Serial Technical Support group at: [email protected]

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3222E/SP3232E_101_031413