Maxim Integrated Producs DS28CN01U-A00+T, DS28CN01 Datasheet

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Abridged Data Sheet

www.maxim-ic.com

GENERAL DESCRIPTION

The DS28CN01 combines 1024 bits of EEPROM
with challenge-and-response authentication security
implemented with the Federal Information
Publications (FIPS) 180-1/180-2 and ISO/IEC 10118­3 Secure Hash Algorithm (SHA-1). The memory is
organized as four pages of 32 bytes each. Data
copy-protection and EPROM emulation features are
supported for each memory page. Each DS28CN01
has a guaranteed unique factory-programmed 64-bit
registration number. Communication with the
DS28CN01 is accomplished through an industry
standard I²C- and SMBus™-compatible interface.
The SMBus timeout feature resets the device’s
interface if a bus-timeout fault condition is detected.

APPLICATIONS

Printed Circuit Board (PCB) Unique Serialization
Accessory and Peripheral Identification
Equipment Registration and License Management
Network Node Identification
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection

TYPICAL OPERATING CIRCUIT

V

CC

RP R

VCC

SD
SCL

µC

GND

Registers, Modes, and Commands are capitalized for
clarity.

SMBus is a trademark of Intel Corp.

P

VCC

DS28CN01

SDA
SCL

D1
D0 GND

To additional
devices

DS28CN01

1Kbit I²C/SMBus EEPROM

with SHA-1 Engine

FEATURES

 1024 Bits of EEPROM Memory Partitioned

Into Four Pages of 256 Bits

 Dedicated Hardware-Accelerated SHA Engine

for Generating SHA-1 MACs

 EEPROM Memory Pages can be Individually

Copy-Protected or Put Into an EPROM Mode
(Program from 1 to 0 Only)

 Write Access Requires Knowledge of the

Secret and the Capability of Computing and
Transmitting a 160-Bit MAC as Authorization

 Unique, Factory-Programmed, and Tested

64-Bit Registration Number Assures Absolute
Traceability Because No Two Parts are Alike

 Endurance 200k Cycles at +25°C
 Serial Interface User Programmable for I²C

Bus and SMBus Compatibility

 Supports 100kHz and 400kHz I²C

Communication Speeds

 5.5V Tolerant Interface Pins
 Operating Range: 1.62V to 5.5V,

-40°C to +85°C

 8-Pin µSOP Package

ORDERING INFORMATION

PART TEMP RANGE

DS28CN01U-A00+

DS28CN01U-A00+T

+ Denotes a lead-free package.

-40°C to +85°C

-40°C to +85°C

Request full data sheet at:

www.maxim-ic.com/fullds/DS28CN01

PIN CONFIGURATION

AD0

1

AD1

2

NC

3

GND

4

µSOP

PIN-

PACKAGE

8 µSOP

8 µSOP
Tape-and­Reel

V

8

CC

7

NC

6

SCL

5

SDA

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REV: 061907

Abridged Data Sheet DS28CN01

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground -0.5V, +6V
Maximum Current Any Pin
Operating Temperature Range
Junction Temperature

±20mA

-40°C to +85°C

+150°C

Storage Temperature Range -55°C to +125°C
Soldering Temperature

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.

See IPC/JEDEC J-STD-020

ELECTRICAL CHARACTERISTICS (see Note 1)

(TA = -40°C to +85°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage V
Standby Current I

Operating Current I

Power-Up Wait Time t

CC

CCS

CCA

POIP

EEPROM

Programming Time t

Programming Current I

Endurance (Notes 3, 4, 5) N

Data Retention (Notes 6, 7, 8) t

PROG

PROG

CY

DR

SHA-1 Engine

SHA Computation Time t

SHA Computation Current I

CSHA

LCSHA

SCL, SDA, AD1, AD0 Pins (Note 9) (See Figure 3)

LOW Level Input Voltage V

HIGH Level Input Voltage V

Hysteresis of Schmitt Trigger
Inputs (Note 2)

LOW Level Output Voltage at
4mA Sink Current, Open Drain

Output Fall Time from V

with a Bus Capacitance

V

ILmax

IHmin

to

from 10pF to 400pF

IL

IH

V

HYS

V

OL

t

OF

(Notes 2, 10)
Pulse Width of Spikes that are
Suppressed by the Input Filter

t

SP

Input Current with an Input
Voltage Between 0.1V

0.9V

CCmax

CC

and

I

i

1.62 5.50 V
Bus idle, VCC = 5.5V 5.5 µA
Bus active at 400kHz,

= 5.5V

V

CC

500 µA

(Note 2) 5 µs

V

≥ 2.0V 10

CC

VCC < 2.0V 45

ms

VCC = 5.5V 1.2 mA
At +25°C 200k
At +85°C 50k

—

At +85°C 40 years

See full version of data
sheet
See full version of data
sheet

VCC ≥ 2.0V

VCC < 2.0V

VCC ≥ 2.0V

VCC < 2.0V

VCC ≥ 2.0V

VCC < 2.0V

VCC ≥ 2.0V
VCC < 2.0V

VCC ≥ 2.0V

VCC < 2.0V

ms

mA

-0.3

-0.3

0.7 ×
V

CC

0.8 ×
V

CC

0.05 ×
V

CC

0.1 ×
V

CC

20 +

0.1C

B

20 +

0.1C

B

0.3 × V

0.25 ×
V

CC

V

CCmax

+0.3V

V

CCmax

+0.3V

CC

0.4

0.2 × V

CC

250

300

V

V

V

V

ns

(Note 2) 50 ns

(Note 11) -10 +10 µA

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Abridged Data Sheet DS28CN01

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Capacitance C
SCL Clock Frequency f
Bus Timeout t

SCL

TIMEOUT

I

(Note 2) 10 pF
(Note 12)

400 kHz

(Note 12) 25 75 ms
Hold-Time (Repeated) START
Condition. After this Period, the

t

HD:STA

(Note 13) 0.6 µs
First Clock Pulse is Generated.

LOW Period of the SCL Clock
(Note 13)

HIGH Period of the SCL Clock t
Setup Time for a Repeated
START Condition

Data Hold Time
(Notes 14, 15)

Data Setup Time t
Setup Time for STOP Condition t
Bus Free Time Between a

STOP and START Condition
Capacitive Load for Each Bus
Line

V

≥ 2.7V

CC

t

LOW

HIGH

t

SU:STA

t

HD:DAT

SU:DAT

SU:STO

t

BUF

C

B

V

≥ 2.0V

CC

V

< 2.0V

CC

(Note 13)

(Note 13) 0.6 µs

V

≥ 2.7V

CC

V

≥ 2.0V

CC

V

< 2.0V

CC

(Notes 2, 13, 16)

(Note 13) 0.6 µs

(Note 13) 1.3 µs

B (Notes 2, 13) 400 pF

1.3

1.5

µs

1.9

0.6 µs

0.3 0.9

0.3 1.1

µs

0.3 1.5

100 ns

Note 1: Specifications at -40°C are guaranteed by design and characterization only and not production tested.
Note 2: Guaranteed by design, characterization and/or simulation only, and not production tested.
Note 3: This specification is valid for each 8-byte memory row.
Note 4: Write-cycle endurance is degraded as T
Note 5: Not 100% production-tested; guaranteed by reliability monitor sampling.
Note 6: Data retention is degraded as T
Note 7: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet

Note 8: EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
Note 9: All values are referred to V

Note 10: C
Note 11: The DS28CN01 does not obstruct the SDA and SCL lines if V

Note 12: The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 and SCL stays at the same logic level
Note 13: System requirement.

Note 14: The DS28CN01 provides a hold time of at least 300ns for the SDA signal (referred to the V
Note 15: The master can provide a hold time of 0ns minimum when writing to the device. This 0ns minimum is guaranteed by design,
Note 16:

limit at operating temperature range is established by reliability testing.

temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.

= total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall-times according to I²C-Bus

B

B

Specification v2.1 are allowed.

or SDA stays low for this interval, the DS28CN01 behaves as though it has sensed a STOP condition.

undefined region of the falling edge of SCL.

characterization and/or simulation only, and not production tested.
A Fast-Mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
(according to the Standard-mode I²C-bus specification) before the SCL line is released.

IHmin

A

and V

increases.

A

increases.

levels.

ILmax

is switched off.

CC

Rmax

of the SCL signal) to bridge the

IHmin

≥ 250ns must then be

SU:DAT

+ t

= 1000 + 250 = 1250ns

SU:DAT

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