Maxim Integrated Producs DS26528 Datasheet

www.maxim-ic.com

GENERAL DESCRIPTION

DS26528

Octal T1/E1/J1 Transceive

FEATURES

The DS26528 is a single-chip 8-port framer and line

interface unit (LIU) combination for T1, E1, and J1

applications. Each port is independently configurable,

supporting both long-haul and short-haul lines.

APPLICATIONS

Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment

FUNCTIONAL DIAGRAM

T1/E1/J1

NETWORK

DS26528

T1/J1/E1

Transceiver

BACKPLANE

TDM

§ Eight Complete T1, E1, or J1 Long-Haul/Short-

Haul Transceivers (LIU plus Framer)

§ Independent T1, E1, or J1 Selections for Each

Transceiver

§ Internal Software-Selectable Transmit- and

Receive-Side Termination for 100W T1 Twisted Pair, 110W J1 Twisted Pair, 120W E1 Twisted Pair, and 75W E1 Coaxial Applications

§ Crystal-Less Jitter Attenuators can be Selected

for Transmit or Receive Path. The Jitter Attenuator meets ETSI CTR 12/13, ITU G.736, G.742, G.823, and AT&T PUB 62411.

§ External Master Clock can be Multiple of

2.048MHz or 1.544MHz for T1/J1 or E1 operation. This Clock is Internally Adapted for T1 or E1 Usage in the Host Mode.

§ Receive Signal Level Indication from -2.5dB to

-36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments

§ Transmit Open and Short Circuit Detection

§ LIU LOS in Accordance with G.775, ETSI

300233, and T1.231

§ Transmit Synchronizer

§ Flexible Signaling Extraction and Insertion Using

Either the System Interface or Microprocessor Port

§ Alarm Detection and Insertion

§ T1 Framing Formats of D4, SLC-96, and ESF

§ J1 Support

§ E1 G.704 and CRC-4 Multiframe

§ T1 to E1 Conversion

Features continued on in Section 2

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS26528

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

1 of 262

-40°C to +85°C

256 TE-CSBGA

REV: 072304

DS26528 Octal T1/E1/J1 Transceiver

TABLE OF CONTENTS

1. DETAILED DESCRIPTION.................................................................................................8

2. FEATURE HIGHLIGHTS ....................................................................................................9

2.1 GENERAL..................................................................................................................................... 9

2.2 LINE INTERFACE ........................................................................................................................... 9

2.3 CLOCK SYNTHESIZER ................................................................................................................... 9

2.4 JITTER ATTENUATOR .................................................................................................................... 9

2.5 FRAMER/FORMATTER ................................................................................................................... 9

2.6 SYSTEM INTERFACE ................................................................................................................... 10

2.7 HDLC CONTROLLERS ................................................................................................................ 10

2.8 TEST AND DIAGNOSTICS ............................................................................................................. 11

2.9 CONTROL PORT ......................................................................................................................... 11

3. APPLICATIONS ...............................................................................................................11

4. SPECIFICATIONS COMPLIANCE...................................................................................12

5. ACRONYMS AND GLOSSARY .......................................................................................14

6. MAJOR OPERATING MODES.........................................................................................15

7. BLOCK DIAGRAMS.........................................................................................................15

8. PIN DESCRIPTIONS ........................................................................................................17

8.1 PIN FUNCTIONAL DESCRIPTION ................................................................................................... 17

9. FUNCTIONAL DESCRIPTION .........................................................................................23

9.1 PROCESSOR INTERFACE ............................................................................................................. 23

9.2 CLOCK STRUCTURE.................................................................................................................... 23

9.3 RESETS AND POWER-DOWN MODES ........................................................................................... 25

9.4 INITIALIZATION AND CONFIGURATION ........................................................................................... 26

9.5 GLOBAL RESOURCES.................................................................................................................. 26

9.6 PER-PORT RESOURCES.............................................................................................................. 26

9.7 DEVICE INTERRUPTS .................................................................................................................. 27

9.8 SYSTEM BACKPLANE INTERFACE ................................................................................................. 29

9.8.1 Elastic Stores ....................................................................................................................................... 29

9.8.2 IBO Multiplexer..................................................................................................................................... 32

9.8.3 H.100 (CT-Bus) Compatibility .............................................................................................................. 39

9.8.4 Transmit and Receive Channel Blocking Registers............................................................................. 40

9.8.5 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 40

9.8.6 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 40

9.9 FRAMERS................................................................................................................................... 41

9.9.1 T1 Framing........................................................................................................................................... 41

9.9.2 E1 Framing........................................................................................................................................... 44

9.9.3 T1 Transmit Synchronizer .................................................................................................................... 46

9.9.4 Signaling .............................................................................................................................................. 47

9.9.5 T1 Datalink ........................................................................................................................................... 52

9.9.6 E1 Datalink ........................................................................................................................................... 54

9.9.7 Maintenance and Alarms ..................................................................................................................... 55

9.9.8 E1 Automatic Alarm Generation .......................................................................................................... 58

9.9.9 Error Count Registers .......................................................................................................................... 59

9.9.10 DS0 Monitoring Function...................................................................................................................... 61

9.9.11 Transmit Per-Channel Idle Code Insertion........................................................................................... 62

9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 62

9.9.13 Per-Channel Loopback ........................................................................................................................ 62

9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 62

9.9.15 T1 Programmable In-Band Loop Code Generator............................................................................... 63

2 of 262

DS26528 Octal T1/E1/J1 Transceiver

9.9.16

Framer Payload Loopbacks ................................................................................................................. 65

9.10 HDLC CONTROLLERS ............................................................................................................. 66

9.10.1 Receive HDLC Controller ..................................................................................................................... 66

9.10.2 Transmit HDLC Controller.................................................................................................................... 69

9.10.3 FIFO Information .................................................................................................................................. 69

9.10.4 HDLC Transmit Example ..................................................................................................................... 69

9.11 LINE INTERFACE UNITS (LIU) ................................................................................................... 71

9.11.1 LIU Operation ....................................................................................................................................... 72

9.11.2 Transmitter ........................................................................................................................................... 73

9.11.3 Receiver ............................................................................................................................................... 76

9.11.4 Jitter Attenuator .................................................................................................................................... 78

9.11.5 LIU Loopbacks ..................................................................................................................................... 80

9.12 BIT ERROR RATE TEST FUNCTION (BERT) ............................................................................... 83

9.12.1 BERT Repetitive Pattern Set ............................................................................................................... 84

9.12.2 BERT Error Counter............................................................................................................................. 84

10. DEVICE REGISTERS .......................................................................................................85

10.1 REGISTER LISTINGS ................................................................................................................ 85

10.1.1 Global Register List.............................................................................................................................. 87

10.1.2 Framer Register List............................................................................................................................. 87

10.1.3 LIU and BERT Register List ................................................................................................................. 94

10.2 REGISTER BIT MAPS ............................................................................................................... 95

10.2.1 Global Register Bit Map ....................................................................................................................... 95

10.2.2 Framer Register Bit Map ...................................................................................................................... 96

10.2.3 LIU Register Bit Map .......................................................................................................................... 102

10.2.4 BERT Register Bit Map ...................................................................................................................... 103

10.3 GLOBAL REGISTER DEFINITIONS ............................................................................................ 104

10.4 FRAMER REGISTER DEFINITIONS............................................................................................ 118

10.4.1 Receive Register Definitions.............................................................................................................. 118

10.4.2 Transmit Register Definitions ............................................................................................................. 172

10.5 LIU REGISTER DEFINITIONS................................................................................................... 207

10.6 BERT REGISTER DEFINITIONS............................................................................................... 216

11. FUNCTIONAL TIMING ...................................................................................................224

11.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ........................................................................ 224

11.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS .................................................................. 229

11.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS........................................................................ 234

11.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS .................................................................. 236

12. OPERATING PARAMETERS.........................................................................................239

12.1 LINE INTERFACE CHARACTERISTICS ....................................................................................... 240

13. AC TIMING CHARACTERISTICS ..................................................................................241

13.1 MICROPROCESSOR BUS AC CHARACTERISTICS...................................................................... 241

13.2 JTAG INTERFACE TIMING ...................................................................................................... 250

13.3 SYSTEM CLOCK AC CHARACTERISTICS .................................................................................. 251

14. JTAG-BOUNDARY SCAN AND TEST ACCESS PORT................................................252

14.1 INSTRUCTION REGISTER........................................................................................................ 256

14.2 JTAG ID CODES................................................................................................................... 257

14.3 TEST REGISTERS .................................................................................................................. 257

14.4 BOUNDARY SCAN REGISTER .................................................................................................. 257

14.5 BYPASS REGISTER ................................................................................................................ 257

14.6 IDENTIFICATION REGISTER..................................................................................................... 257

15. DOCUMENT REVISION HISTORY ................................................................................261

16. PACKAGE INFORMATION............................................................................................262

3 of 262

DS26528 Octal T1/E1/J1 Transceiver

LIST OF FIGURES

Figure 7-1. Block Diagram ......................................................................................................................................... 15

Figure 7-2. Detailed Block Diagram ........................................................................................................................... 16

Figure 8-1. BGA Pinout.............................................................................................................................................. 22

Figure 9-1. Backplane Clock Generation................................................................................................................... 24

Figure 9-2. Device Interrupt Information Flow Diagram............................................................................................. 28

Figure 9-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 33

Figure 9-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...................................................................................... 34

Figure 9-5. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................... 35

Figure 9-6. RSYNC Input In H.100 (Ct-Bus) Mode.................................................................................................... 39

Figure 9-7. TSSYNCIO(Input Mode) Input In H.100 (CT-Bus) Mode ........................................................................ 40

Figure 9-8. CRC-4 Recalculate Method..................................................................................................................... 62

Figure 9-9. Receive HDLC Example.......................................................................................................................... 68

Figure 9-10. HDLC Message Transmit Example ....................................................................................................... 70

Figure 9-11. Basic Balanced Network Connections .................................................................................................. 71

Figure 9-12. Recommended Supply Decoupling....................................................................................................... 72

Figure 9-13. T1/J1 Transmit Pulse Templates .......................................................................................................... 74

Figure 9-14. E1 Transmit Pulse Templates ............................................................................................................... 75

Figure 9-15. Typical Monitor Application ................................................................................................................... 77

Figure 9-16. Jitter Attenuation ................................................................................................................................... 80

Figure 9-17. Analog Loopback................................................................................................................................... 80

Figure 9-18. Local Loopback ..................................................................................................................................... 81

Figure 9-19. Remote Loopback ................................................................................................................................. 81

Figure 9-20. Dual Loopback ...................................................................................................................................... 82

Figure 10-1. Register Memory Map for the DS26528................................................................................................ 86

Figure 11-1. T1 Receive Side D4 Timing ................................................................................................................ 224

Figure 11-2. T1 Receive Side ESF Timing .............................................................................................................. 224

Figure 11-3. T1 Receive Side Boundary Timing (elastic store disabled) ................................................................ 225

Figure 11-4. T1 Receive Side 1.544MHz Boundary Timing (e-store enabled)........................................................ 225

Figure 11-5. T1 Receive Side 2.048MHz Boundary Timing (e-store enabled)........................................................ 226

Figure 11-6. T1 Receive Side Interleave Bus Operation, BYTE Mode ................................................................... 227

Figure 11-7. T1 Receive Side Interleave Bus Operation, FRAME Mode ................................................................ 228

Figure 11-8. T1 Transmit Side D4 Timing ............................................................................................................... 229

Figure 11-9. T1 Transmit Side ESF Timing ............................................................................................................. 229

Figure 11-10. T1 Transmit Side Boundary Timing (e-store disabled) ..................................................................... 230

Figure 11-11. T1 Transmit Side 1.544MHz Boundary Timing (e-store enabled) .................................................... 230

Figure 11-12. T1 Transmit Side 2.048MHz Boundary Timing (e-store enabled) .................................................... 231

Figure 11-13. T1 Transmit Side Interleave Bus Operation, BYTE Mode ................................................................ 232

Figure 11-14. T1 Transmit Interleave Bus Operation, FRAME Mode ..................................................................... 233

Figure 11-15. E1 Receive Side Timing .................................................................................................................... 234

Figure 11-16. E1 Receive Side Boundary Timing (elastic store disabled) .............................................................. 234

Figure 11-17. E1 Receive Side 1.544MHz Boundary Timing (e-store enabled) ..................................................... 235

Figure 11-18. E1 Receive Side 2.048MHz Boundary Timing (e-store enabled) ..................................................... 235

Figure 11-19. E1 Transmit Side Timing ................................................................................................................... 236

Figure 11-20. E1 Transmit Side Boundary Timing (elastic store disabled) ............................................................. 236

Figure 11-21. E1 Transmit Side 1.544MHz Boundary Timing (e-store enabled) .................................................... 237

Figure 11-22. E1 Transmit Side 2.048MHz Boundary Timing (e-store enabled) .................................................... 237

Figure 11-23. E1 G.802 Timing ............................................................................................................................... 238

Figure 13-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 242

Figure 13-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 242

Figure 13-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 243

Figure 13-4. Motorola Bus Write Timing (BTS = 1) ................................................................................................. 243

Figure 13-5. Receive Framer Timing—Backplane (T1 Mode) ................................................................................. 245

Figure 13-6. Receive Side Timing, Elastic Store Enabled (T1 Mode) ..................................................................... 246

Figure 13-7. Receive Framer Timing—Line Side .................................................................................................... 246

Figure 13-8. Transmit Formatter Timing—Backplane ............................................................................................. 248

Figure 13-9. Transmit Formatter Timing, Elastic Store Enabled ............................................................................. 249

4 of 262

DS26528 Octal T1/E1/J1 Transceiver

Figure 13-10. Transmit Formatter Timing—Line Side ............................................................................................. 249

Figure 13-11. JTAG Interface Timing Diagram........................................................................................................ 250

Figure 14-1. JTAG Functional Block Diagram ......................................................................................................... 252

Figure 14-2. Tap Controller State Diagram ............................................................................................................. 255

5 of 262

DS26528 Octal T1/E1/J1 Transceiver

LIST OF TABLES

Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 12

Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 13

Table 8-1. Detailed Pin Descriptions ......................................................................................................................... 17

Table 9-1. Reset Functions........................................................................................................................................ 25

Table 9-2. Registers Related to the Elastic Store...................................................................................................... 29

Table 9-3. Elastic Store Delay After Initialization....................................................................................................... 30

Table 9-4. Registers related to the IBO Multiplexer................................................................................................... 32

Table 9-5. RSER Output Pin Definitions.................................................................................................................... 36

Table 9-6. RSIG Output Pin Definitions ..................................................................................................................... 36

Table 9-7. TSER Input Pin Definitions ....................................................................................................................... 37

Table 9-8. TSIG Input Pin Definitions ........................................................................................................................ 37

Table 9-9. RSYNC Input Pin Definitions .................................................................................................................... 38

Table 9-10. D4 Framing Mode................................................................................................................................... 42

Table 9-11. ESF Framing Mode ................................................................................................................................ 42

Table 9-12. SLC-96 Framing ..................................................................................................................................... 43

Table 9-13. E1 FAS/NFAS Framing .......................................................................................................................... 44

Table 9-14. Registers Related to Setting Up the Framer .......................................................................................... 45

Table 9-15. Registers Related to the Transmit Synchronizer.................................................................................... 46

Table 9-16. Registers Related to Signaling ............................................................................................................... 47

Table 9-17. Registers Related to SLC96 ................................................................................................................... 50

Table 9-18. Registers Related to T1 Transmit BOC.................................................................................................. 52

Table 9-19. Registers Related to T1 Receive BOC ................................................................................................... 52

Table 9-20. Registers Related to T1 Transmit FDL................................................................................................... 53

Table 9-21. Registers Related to T1 Receive FDL .................................................................................................... 54

Table 9-22. Registers Related to Maintenance and Alarms ...................................................................................... 56

Table 9-23. T1 Alarm Criteria .................................................................................................................................... 58

Table 9-24. T1 Line Code Violation Counting Options .............................................................................................. 59

Table 9-25. E1 Line Code Violation Counting Options .............................................................................................. 60

Table 9-26. T1 Path Code Violation Counting Arrangements ................................................................................... 60

Table 9-27. T1 Frames Out Of Sync Counting Arrangements .................................................................................. 61

Table 9-28. Registers Related to DS0 Monitoring ..................................................................................................... 61

Table 9-29. Registers Related to T1 In-Band Loop Code Generator ........................................................................ 63

Table 9-30. Registers Related to T1 In-Band Loop Code Detection ......................................................................... 64

Table 9-31. Register Related to Framer Payload Loopbacks ................................................................................... 65

Table 9-32. Registers Related to Control of DS26528 LIU........................................................................................ 72

Table 9-33. The Telecommunications Specification Compliance for DS26528 Transmitters ................................... 73

Table 9-34. Transformer Specifications..................................................................................................................... 73

Table 9-35. T1.231, G.775, and ETSI 300 233 Loss Criteria Specifications ............................................................. 77

Table 9-36. Jitter Attenuator Standards Compliance................................................................................................. 79

Table 10-1. Register Address Ranges (in Hex)......................................................................................................... 85

Table 10-2. Global Register List ................................................................................................................................ 87

Table 10-3. Framer Register List ............................................................................................................................... 87

Table 10-4. LIU Register List ..................................................................................................................................... 94

Table 10-5. BERT Register List ................................................................................................................................. 94

Table 10-6. Global Register Bit Map.......................................................................................................................... 95

Table 10-7. Framer Register Bit Map ........................................................................................................................ 96

Table 10-8. LIU Register Bit Map ............................................................................................................................ 102

Table 10-9. BERT Register Bit Map ........................................................................................................................ 103

Table 10-10. Backplane Reference Clock Select .................................................................................................... 107

Table 10-11. Master Clock Input Selection.............................................................................................................. 108

Table 10-12. Device ID Codes in this Product Family ............................................................................................. 111

Table 10-13. LIU Register Set ................................................................................................................................. 207

Table 10-14. Transmit Load Impedance Selection.................................................................................................. 208

Table 10-15. Transmit Pulse Shape Selection ........................................................................................................ 208

Table 10-16. Receive Level Indication .................................................................................................................... 213

Table 10-17. Receive Impedance Selection ............................................................................................................ 214

6 of 262

DS26528 Octal T1/E1/J1 Transceiver

Table 10-18. Receiver Sensitivity Selection with Monitor Mode Disabled............................................................... 215

Table 10-19. Receiver Sensitivity Selection with Monitor Mode Enabled ............................................................... 215

Table 10-20. BERT Register Set ............................................................................................................................. 216

Table 10-21. BERT Pattern Select .......................................................................................................................... 218

Table 10-22. BERT Error Insertion Rate.................................................................................................................. 219

Table 10-23. BERT Repetitive Pattern Length Select ............................................................................................. 219

Table 12-1. Transmitter Characteristics .................................................................................................................. 240

Table 12-2. Reciever Characteristics....................................................................................................................... 240

Table 13-1. AC Characteristics –Microprocessor Bus Timing ................................................................................. 241

Table 13-2. Receiver AC Characteristics ................................................................................................................ 244

Table 13-3. Transmit AC Characteristics................................................................................................................. 247

Table 14-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 256

Table 14-2. ID Code Structure................................................................................................................................. 257

Table 14-3. Boundary Scan Control Bits ................................................................................................................. 257

7 of 262

DS26528 Octal T1/E1/J1 Transceiver

1. DETAILED DESCRIPTION

The DS26528 is an 8-port monolithic device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic store, and a TDM backplane interface. The DS26528 is controlled via an 8-bit parallel port. Internal impedance matching is provided for both transmit and receive paths, reducing external component count.

The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX–1 line build-outs as well as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75W coax and 120W twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be placed in either transmit or receive data paths.

On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane interface section.

Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to manage the flow of data.

The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,

4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up to eight transceivers (single DS26528) to share a high-speed backplane. The DS26528 also contains an internal clock adapter useful for the creation of a synchronous, high-frequency backplane timing source.

The parallel port provides access for configuration and status of all the DS26528’s features. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection.

8 of 262

DS26528 Octal T1/E1/J1 Transceiver

2. FEATURE HIGHLIGHTS

2.1 General

§ 17mm x 17mm, 256-pin TE-CSBGA (1.00mm pitch)

§ 3.3V supply with 5V tolerant inputs and outputs

§ IEEE 1149.1 JTAG boundary scan

§ Development support will include evaluation kit, driver source code, and reference designs

2.2 Line Interface

§ Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz,

2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, or 16.384MHz.

§ Fully software configurable

§ Short- and long-haul applications

§ Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to

30dB, 0dB to 20dB, and 0dB to -15dB for T1

§ Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB increments

§ Internal receive termination option for 75±, 100W, 110W, and 120W lines

§ Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB

§ G.703 receive synchronization signal mode

§ Flexible transmit waveform generation

§ T1 DSX-1 line build-outs

§ T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB

§ E1 waveforms include G.703 waveshapes for both 75W coax and 120W twisted cables

§ Analog loss of signal detection

§ AIS generation independent of loopbacks

§ Alternating ones and zeros generation

§ Receiver power-down

§ Transmitter power-down

§ Transmitter short-circuit limiter with current limit exceeded indication

§ Transmit open-circuit-detected indication

2.3 Clock Synthesizer

§ Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz

§ Derived from user selected recovered receive clock

2.4 Jitter Attenuator

§ 32-bit or 128-bit crystal-less jitter attenuator

§ Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation

§ Can be placed in either the receive or transmit path or disabled

§ Limit trip indication

2.5 Framer/Formatter

§ Fully independent transmit and receive functionality

§ Full receive and transmit path transparency

§ T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008).

§ E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe

§ Transmit side synchronizer

§ Transmit midpath CRC recalculate (E1)

§ Detailed alarm and status reporting with optional interrupt support

9 of 262

DS26528 Octal T1/E1/J1 Transceiver

§ Large path and line error counters

- T1:- BPV, CV, CRC6, and framing bit errors

- E1: BPV, CV, CRC4, E-bit, and frame alignment errors

- Timed or manual update modes

§ DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths

- User defined

- Digital Milliwatt

§ ANSI T1.403-1999 Support

§ G.965 V5.2 link detect

§ Ability to monitor one DS0 channel in both the transmit and receive paths

§ In-Band Repeating Pattern Generators and Detectors

- Three independent Generators and Detectors

- Patterns from 1 to 8 bits or 16 bits in Length

§ Bit Oriented Code (BOC) support

§ Flexible signaling support

- Software or hardware based

- Interrupt generated on change of signaling data

- Optional receive signaling freeze on loss of frame, loss of signal, or frame slip

- Hardware pins provided to indicate Loss of Frame (LOF), Loss of Signal (LOS), Loss of Transmit Clock

(LOTC), or signaling freeze condition.

§ Automatic RAI generation to ETS 300 011 specifications

§ RAI-CI and AIS-CI support

§ Expanded access to Sa and Si bits

§ Option to extend carrier loss criteria to a 1ms period as per ETS 300 233

§ Japanese J1 support

§ Ability to calculate and check CRC6 according to the Japanese standard

§ Ability to generate Yellow Alarm according to the Japanese standard

§ T1 to E1 conversion

2.6 System Interface

§ Independent two-frame receive and transmit elastic stores

§ Independent control and clocking

§ Controlled slip capability with status

§ Minimum delay mode supported

§ Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz

§ Supports T1 to CEPT (E1) conversion

§ Programmable output clocks for fractional T1, E1, H0, and H12 applications

§ Interleaving PCM bus operation

§ Hardware signaling capability

§ Receive signaling reinsertion to a backplane multiframe sync

§ Availability of signaling in a separate PCM data stream

§ Signaling freezing

§ Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode

§ User-selectable synthesized clock output

2.7 HDLC Controllers

§ One HDLC controller engine for each T1/E1 port

§ Independent 64-byte Rx and Tx buffers with interrupt support

§ Access FDL, Sa, or single DS0 channel

§ Compatible with polled or interrupt driven environments

10 of 262

DS26528 Octal T1/E1/J1 Transceiver

2.8 Test and Diagnostics

§ IEEE 1149.1 Support

§ Per-channel programmable on-chip bit error-rate testing (BERT)

§ Pseudorandom patterns including QRSS

§ User-defined repetitive patterns

§ Daly pattern

§ Error insertion single and continuous

§ Total-bit and errored-bit counts

§ Payload error insertion

§ Error insertion in the payload portion of the T1 frame in the transmit path

§ Errors can be inserted over the entire frame or selected channels

§ Insertion options include continuous and absolute number with selectable insertion rates

§ F-bit corruption for line testing

§ Loopbacks (remote, local, analog, and per-channel loopback)

2.9 Control Port

§ 8-bit parallel control port

§ Intel or Motorola nonmultiplexed support

§ Flexible status registers support polled, interrupt, or hybrid program environments

§ Software reset supported

§ Hardware reset pin

§ Software access to device ID and silicon revision

3. APPLICATIONS

The DS26528 is useful in applications such as:

§ Routers

§ Channel Service Units (CSUs)

§ Data Service Units (DSUs)

§ Muxes

§ Switches

§ Channel Banks

§ T1/E1 Test Equipment

11 of 262

DS26528 Octal T1/E1/J1 Transceiver

4. SPECIFICATIONS COMPLIANCE

The DS26528 LIU meets all the latest relevant telecommunications specifications. Table 4-1 provides the T1 and E1 specifications and relevant sections that are applicable to the DS26528.

Table 4-1. T1-Related Telecommunications Specifications

ANSI T1.102- Digital Hierarchy Electrical Interface. AMI Coding. B8ZS Substitution Definition. DS1 Electrical Interface. Line rate +/- 32ppm; Pulse Amplitude between 2.4 to 3.6 V peak; Power Level between

12.6 to 17.9dbm; The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is greater than -26dB. The DSX-1 cable is restricted up to 655 feet. This specification also provides cable characteristics of DSX-Cross Connect cable ---22 AVG cables of 1000 feet. ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition. ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface

Description of the Measurement of the T1 Characteristics—100W. Pulse shape and template compliance according to T1.102; Power level 12.4 to 19.7dbm when all ones is transmitted. LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB and -15dB. Line rate is +/-32 ppm. Pulse Amplitude is 2.4 to 3.6V. AIS generation as unframed all ones is defined. The total cable attenuation is defined as 22dB. The DS26528 will function with up to -36dB cable loss. Note that the pulse template defined by T1.403 and T1.102 are different --- specifically at Times .61, -.27, -34 and .77. The DS26528 is complaint to both templates. Pub 62411 This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer characteristics are tighter than G.736 and Jitter Tolerance is tighter the G.823. (ANSI) “Digital Hierarchy – Electrical Interfaces” (ANSI) “Digital Hierarchy – Formats Specification” (ANSI) “Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring” (ANSI) “Network and Customer Installation Interfaces – DS1 Electrical Interface” (AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super frame Format” (AT&T) “High Capacity Digital Service Channel Interface Specification” (TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces” (TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”

12 of 262

DS26528 Octal T1/E1/J1 Transceiver

Table 4-2. E1-Related Telecommunications Specifications

ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048Kbit/s bit rate—2048 ±50ppm; The transmission media are 75W coax or 120W twisted pair; peak

to peak space voltage is ±0.237V; Nominal pulse width is 244 ns. Return loss 51 to 102Hz is 6dB, 102 to 3072 Hz is 8dB, 2048 to 3072 Hz is 14dB Nominal peak voltage is 2.37V for coax and 3V for twisted pair. The pulse template for E1 is defined in G.703. ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048Kbit/s The peak to peak jitter at 2048Kbit/s has to be less than 0.05 UI at 20 to 100Hz. Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided. ITUT G.742 Second Order Digital Multiplex Equipment Operating at 8448Kbit/s The DS26528 jitter attenuator is complaint with Jitter transfer curve for sinusoidal jitter input. ITUT G.772 This specification provides the method for using receiver for transceiver 0 as a monitor for the rest of the 7 transmitter/receiver combinations. ITUT G.775 A LOS detection criterion is defined. ITUT G.823 The control of jitter and wander within digital networks which are based on 2.048Kbit/s hierarchy G.823 provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and 100kHz. ETSI 300 233 This specification provides LOS and AIS signal criteria for E1 mode Pub 62411 This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer characteristics are tighter than G.736 and Jitter Tolerance is tighter then G.823. (ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488 and 44736Kbit/s Hierarchical Levels” (ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704” (ITU) “Characteristics of primary PCM Multiplex Equipment Operating at 2048Kbit/s” (ITU) Characteristics of a synchronous digital multiplex equipment operating at 2048Kbit/s” (ITU) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria” (ITU) “The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048Kbit/s Hierarchy” (ITU) “Primary Rate User-Network Interface – Layer 1 Specification” (ITU) “Error Performance Measuring Equipment Operating at the Primary Rate and Above” (ITU) “In-service code violation monitors for digital systems” (ETSI) “Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part 1/ Layer 1 specification” (ETSI) “Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital interfaces for equipment using the 2048Kbit/s-based plesiochronous or synchronous digital hierarchies” (ETSI) “Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate” (ETSI) “Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access” (ETSI) “Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2048 Kbit/s digital unstructured leased lines (D2048U) attachment requirements for terminal equipment interface” (ETSI) “Business Telecommunications (BTC); 2048 Kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface” (ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488 and 44736Kbit/s Hierarchical Levels” (ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704”

13 of 262

DS26528 Octal T1/E1/J1 Transceiver

5. ACRONYMS AND GLOSSARY

This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125ms T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last.

Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a

1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).

TIME SLOT NUMBERING SCHEMES

Channel

Phone

Channel

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

14 of 262

DS26528 Octal T1/E1/J1 Transceiver

6. MAJOR OPERATING MODES

The DS26528 has two major modes of operation: T1 mode and E1 mode. The mode of operation for each LIU is configured in the LTRCR

operation is a special case of T1 operating mode.

7. BLOCK DIAGRAMS

Figure 7-1. Block Diagram

DS26528

RTIP

RRING

TTIP

TRING

LIU #8

LIU #7

LIU #6

LIU #5

LIU #4

LIU #3

LIU #2

LINE

INTERFACE

UNIT

MICRO PROCESSOR

INTERFACE

CONTROLLER

PORT

FRAMER #8

FRAMER #7

FRAMER #6

FRAMER #5

FRAMER #4

FRAMER #3

FRAMER #2

T1/E1 F RAMER

HDLC

BERT

JTAG PORT

TEST

PORT

INTERFACE #8

INTERFACE #7

INTERFACE #6

INTERFACE #5

INTERFACE #4

INTERFACE #3

INTERFACE #2

BACKPLANE

INTERFACE

ELASTIC STORES

CLOCK

GENERATION

CLOCK

ADAP TER

RECEIVE

BACKPLANE

SIGNALS

TRANSMIT

BACKPLANE

SIGNALS

HARDWAR E

ALARM

INDICATORS

15 of 262

Figure 7-2. Detailed Block Diagram

JITTER ATTENUATOR

ENABLE

]

[

]

TRANSCEIVER #1 of 8:

TRANSMIT

LIU

Waveform

Shaper/Line

Driver

TTIPn

ANALOG

OUTPUTS

TRINGn

TRANSMIT

LLB

DS26528 Octal T1/E1/J1 Transceiver

BERT

Tx FRAMER:

B8ZS/ HDB3

Encode

FLB

RLB

Elastic

Store

HDLC

Tx Signaling/ Channel Blockin

System IF

KPL

NE INTERFA

PLB

TCLKn TSERn

TSYNCn

TSYSCLK

RSYSCLK

RTIPn

ANALOG

INPUTS

RRINGn

RECEIVE

LIU

Clock/Data

Recovery

DS26528

MICROPROCESSOR

INTERFACE

DB DSB

12:0

7:0

BTS

NTB

RB RWB

JTAG

PORT

JTDI

JTMS

JTCLK

JTRST

JTDO

RESET BLOCK

ESETB

Rx FRAMER:

B8ZS/ HDB3

Decode

Elastic

Store

BERT

HDLC

System IF

PRE-SCALER

BACKPLANE

GENERATOR

PLL

CLOCK

RSYNCn

RSERn RCLKn

Rx Signaling/ Channel Blockin

MCLK

TSSYNCIO BPCLK REFCLK

16 of 262

DS26528 Octal T1/E1/J1 Transceiver

8. PIN DESCRIPTIONS

8.1 Pin Functional Description

Table 8-1. Detailed Pin Descriptions

NAME PIN TYPE DESCRIPTION

ANALOG TRANSMIT

TTIP1 A1, A2

TTIP2 H1, H2

TTIP3 J1, J2

TTIP4 T1, T2

TTIP5 T15, T16

TTIP6 J15, J16

TTIP7 H15, H16

TTIP8 A15, A16 TRING1 A3, B3 TRING2 G3, H3 TRING3 J3, K3 TRING4 R3, T3 TRING5 R14,T14 TRING6 J14, K14 TRING7 G14, H14 TRING8 A14, B14

TXENABLE L13 I

Analog Output High-Z

Transmit Bipolar Tip for Transceiver 1 to 8. These pins are differential line driver tip outputs. These pins can be High-Z if:

If pin TXENABLE is low the TTIP/TRING will be High-Z. Note that if TXENABLE is low, the register settings for control of the TTIP/TRING are ignored and output is High-Z.

The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75W , E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination.

Transmit Bipolar Ring for Transceiver 1 to 8. These pins are differential line driver ring outputs. These pins can be High-Z if:

If pin TXENABLE is low the TTIP/TRING will be High-Z. Note that if TXENABLE is low, the register settings for control of the TTIP/TRING are ignored and output is High-Z.

The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination.

Transmit Enable. If this pin is pulled low, all the transmitter outputs (TTIP and TRING) are High-Z. The register settings for tri-state control of TTIP/TRING are ignored if TXEnable is low. If TXEnable is high, the particular driver can be tri-stated by the register settings.

ANALOG RECEIVE

RTIP1 C1

RTIP2 F1

RTIP3 L1

RTIP4 P1

RTIP5 P16

RTIP6 L16

RTIP7 F16

RTIP8 C16

RRING1 C2 RRING2 F2 RRING3 L2 RRING4 P2 RRING5 P15 RRING6 L15 RRING7 F15 RRING8 C15

TRANSMIT FRAMER

TSER1 F6 TSER2 E7 TSER3 R4 TSER4 N7 TSER5 M10 TSER6 L11 TSER7 F10 TSER8 D12 TCLK1 C5 TCLK2 D7 TCLK3 P5 TCLK4 L8 TCLK5 L10 TCLK6 N11 TCLK7 E10 TCLK8 B13

Analog

Input

Analog

Input

Receive Bipolar Tip for Transceiver 1 to 8. The differential inputs of RTIPn and RRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination via the LIU receive impedance and sensitivity monitor Register.

Receive Bipolar Ring for Transceiver 1 to 8. The differential inputs of RTIPn and RRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination via the LIU receive impedance and sensitivity monitor register.

Transmit NRZ Serial Data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.

In IBO Mode, data for multiple framers can be used in High Speed Multiplexed Scheme. This is described in Section 9.8.2 for each of the streams.

TSYSCLK is used as a reference when IBO is invoked. See Table 9-7

Transmit Clock. A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit side of the transceiver. TSER data is sampled on the falling edge of TCLK. TCLK is used to sample TSER when the elastic store is not enabled or IBO is not used.

. The table there presents the combination of framer data

17 of 262

DS26528 Octal T1/E1/J1 Transceiver

NAME PIN TYPE DESCRIPTION

Transmit System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz

TSYSCLK P13 I

TSYNC1 B4 TSYNC2 F7 TSYNC3 M6 TSYNC4 M7 TSYNC5 N10 TSYNC6 T12 TSYNC7 B11 TSYNC8 A13

TSSYNCIO N13 I/O

TSIG1 D5

TSIG2 A6

TSIG3 T4

TSIG4 R6

TSIG5 T10

TSIG6 R12

TSIG7 A11

TSIG8 C13

TCHBLK/CLK1 A5

TCHBLK/CLK2 C7

TCHBLK/CLK3 L7

TCHBLK/CLK4 P7

TCHBLK/CLK5 P9

TCHBLK/CLK6 P11

TCHBLK/CLK7 D10

TCHBLK/CLK8 E11

RECEIVE FRAMER

RSER1 E5 RSER2 D6 RSER3 N4 RSER4 N6 RSER5 M11 RSER6 M12 RSER7 B12 RSER8 F11

RCLK1 F4 RCLK2 G4 RCLK3 L4 RCLK4 M4 RCLK5 K13 RCLK6 J13 RCLK7 F13 RCLK8 E13

clock. Only used when the transmit-side elastic store function is enabled. Should be tied low in applications that do not use the transmit side elastic store. This is a common clock that is used for all 8 transmitters. The clock can be 4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used.

Transmit Synchronization. A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. This signal can also be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set to output double-wide pulses at signaling frames in T1 mode. The operation of this signal is synchronous with TCLK.

Transmit System Synchronization In. Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Note that if the elastic store is enabled, frame or multiframe boundary will be established for all 8 transmitters. Should be tied low in applications that do not use the transmit side elastic store. The operation of this signal is synchronous with TSYSCLK.

Transmit System Synchronization Out. If configured as an output, an 8kHz pulse synchronous to the BPCLK will be generated. This pulse in combination with Bpclk can be used as an IBO Master. The BPCLK can be sourced to RSYSCLK and TSYSCLK and TSSYNCIO as a source to RSYNC and TSSYNCIO of DS26528 or RSYNC and TSSYNC of other Dallas Semiconductor Parts.

Transmit Signaling. When enabled, this input samples signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. In IBO mode, the TSIG streams can run up to 16.384MHz. See

Table 9-8

Transmit Channel Block or Transmit Channel Block Clock. A dual function pin. TCHBLK is a user programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as Fractional T1, Fractional E1, 384 KBPS (H0), 768 KBPS or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning.

TCHCLK. TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. It can also be programmed to output a gated transmit bit clock controlled by TCHBLK. It is synchronous with TCLK when the transmit-side elastic store is disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.

Received Serial Data. Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.

When IBO mode is used, the RSER pins can output data for multiple framers. The RSER data is synchronous to RSYSCLK. This is described in Section 9.8.2

Receive Clock. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer. This clock is recovered from the signal at RTIP and RRING. RSER data is output on the rising edge of RCLK. RCLK is used to output RSER when the elastic store is not enabled or IBO is not used. When the elastic store is enabled or IBO is used the RSER is clocked by RSYSCLK.

or see Table 9-5.

18 of 262

DS26528 Octal T1/E1/J1 Transceiver

NAME PIN TYPE DESCRIPTION

Receive System Clock. 1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz or 16.384MHz

RSYSCLK L12 I

RSYNC1 A4 RSYNC2 B6 RSYNC3 N5 RSYNC4 T6 RSYNC5 R10 RSYNC6 P12 RSYNC7 C11

RSYNC8 D13 RM/RFSYNC1 C4 RM/RFSYNC2 C6 RM/RFSYNC3 P4 RM/RFSYNC4 P6 RM/RFSYNC5 P10 RM/RFSYNC6 N12 RM/RFSYNC7 D11 RM/RFSYNC8 E12

RSIG1 D4 RSIG2 E6 RSIG3 M5 RSIG4 R5 RSIG5 R11 RSIG6 R13 RSIG7 A12 RSIG8 F12

AL/RSIGF/

FLOS1

AL/RSIGF/

FLOS2

AL/RSIGF/

FLOS3

AL/RSIGF/

FLOS4

AL/RSIGF/

FLOS5

AL/RSIGF/

FLOS6

AL/RSIGF/

FLOS7

AL/RSIGF/

FLOS8 RLF/LTC1 D3 RLF/LTC2 E3 RLF/LTC3 M3 RLF/LTC4 N3 RLF/LTC5 N14 RLF/LTC6 M14 RLF/LTC7 E14 RLF/LTC8 D14

P14

L14

F14

C14

I/O

receive backplane clock. Only used when the receive side elastic store function is enabled. Should be tied low in applications that do not use the receive side elastic store. Multiple of

2.048MHz is expected when the IBO Mode is used. Note that RSYSCLK is used for all 8 transceivers.

Receive Synchronization. If the receive side elastic store is enabled, then this signal is used to input a frame or multiframe boundary pulse if set to output frame boundaries then RSYNC can be programmed to output double-wide pulses on signaling frames in T1 mode. In E1 Mode RSYNC out can be used to indicate CAS and CRC4 Multiframe. The DS26528 also has the facility to accept H.100 compatible synchronization signal.

Receive Multiframe or Frame Synchronization. A dual function pin to indicate Frame or Multiframe Synchronization. RFSYNC is an extracted 8 kHz pulse, one RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), which identifies multiframe boundaries. When the receive elastic store is enabled, the RMSYNC signal indicates the multiframe sync on the system (backplane) side of the Elastic Store. In E1 mode, will indicate either the CRC4 or CAS multiframe as determined by the RSMS2 control bit in RIOCR.1 Register.

Receive Signaling. Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. See Table 9-6

Analog Loss or Receive Signaling Freeze or Framer LOS. Analog LOS reflects the LOS (Loss of Signal) detected by the LIU front end and Framer LOS is LOS detection by the corresponding framer; the same pins can reflect Receive Signaling Freeze indications. This selection can be made by settings in Global Transceiver Control Register.

If Framer LOS is selected, this pin can be programmed to toggle high when the framer detects a loss of signal condition, or when the signaling data is frozen via either automatic or manual intervention. The indication is used to alert downstream equipment of the condition.

Receive Loss of Frame or Loss of Transmit Clock. This pin can also be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for approximately three clock periods.

19 of 262

DS26528 Octal T1/E1/J1 Transceiver

NAME PIN TYPE DESCRIPTION

RCHBLK/CLK1 E4

RCHBLK/CLK2 B5

RCHBLK/CLK3 L6

RCHBLK/CLK4 T5

RCHBLK/CLK5 T11

RCHBLK/CLK6 T13

RCHBLK/CLK7 C12

RCHBLK/CLK8 G13

BPCLK E8 O

MICROPROCESSOR INTERFACE

A12 C8 A11 A8 A10 B8

A9 F8 A8 B9 A7 A9 A6 C9 A5 D9 A4 E9 A3 F9 A2 B10 A1 A10 A0 C10 D7 T9 D6 N9 D5 M9 D4 R8 D3 T8 D2 P8 D1 L9 D0 N8

CSB

RDB/DSB

T7 I

M8 I

I/O

Receive Channel Block or Receive Channel Block Clock. Pin can be configured to output either RCHBLK or RCHCLK. RCHBLK is a user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning.

RCHCLK is a 192 kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.

Backplane Clock. Programmable clock output that can be set to 2.048MHz, 4.096MHz,

8.192MHz, or 16.384MHz. The reference for this clock can be RCLK from any of the LIU,

1.544MHz or 2.048MHz frequency derived from MCLK or an external reference clock. This allows for the IBO clock to reference from external source or T1J1E1 recovered clock or the MCLK oscillator.

Address12 to Address0. This bus selects a specific register in the DS26528 during read/write access. A12 is the MSB and A0 is the LSB.

Data7 to Data0. This 8-bit, bidirectional data bus is used for read/write access of the DS26528 information and control registers. D7 is the MSB and D0 is the LSB.

Chip Select Bar. This active-low signal is used to qualify register read/write accesses. The RDDSB and WRB signals are qualified with CSB.

Read Bar Data or Strobe Bar. This active-low signal along with CSB qualifies read access to one of the DS26528 registers. The DS26528 drives the data bus with the contents of the addressed register while RDB and CSB are both low.

WRB/RWB

INTB

BTS M13 I

SYSTEM INTERFACE

MCLK B7 I

R7 I

R9 U

Write Bar/Read-Write Bar. This active-low signal along with CSB qualifies write access to one of the DS26528 registers. Data at D[7/0] is written into the addressed register at the rising edge of WRB while CSB is low.

Interrupt Bar. This active-low, open-drain output is asserted when an unmasked interrupt event is detected. INTB will be deasserted when all interrupts have been acknowledged and serviced. Extensive Mask bits are provided at the global level, framer, LIU, and BERT level.

Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus timing. This pin controls the function of the RDDSB, and WRB pins.

Master Clock. This is an independent free-running clock whose input can be a multiple of

2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to 2.048MHz. Note that TCLK has to be 2.048MHz for E1 and 1.544MHz for T1/J1 operation. See Table 10-11

20 of 262

DS26528 Octal T1/E1/J1 Transceiver

NAME PIN TYPE DESCRIPTION

RESETB

J12 I

REFCLKIO A7 I/O

TEST

DIGIOEN D8

JTRST L5

JTMS K4

Pullup

JTCLK F5 I

JTDI H4

JTDO J4

Pullup

High-Z

POWER SUPPLIES

B1, B16, G1,

ATVDD

G16, K1, K16, R1,

—

R16

B2, B15, G2,

ATVSS

G15, K2, K15, R2,

—

R15

D1, D16, E1,

ARVDD

E16, M1,

M16, N1,

—

N16

D2, D15, E2,

ARVSS

E15, M2,

M15, N2,

—

N15

ACVDD H7 —

Reset Bar. Active-low reset. This input forces the complete DS26528 reset. This includes reset of the registers, framers, and LIUs.

Reference Clock Input/Output

Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate the

backplane clock. This allows for the users to synchronize the system backplane with the reference clock. The other options for the backplane clock reference are LIU-received clocks or MCLK.

Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference clock. This allows for multiple DS26528 to share the same reference for generation of the backplane clock. Hence, in a system consisting of multiple DS26528s, one can be a master and others a slave using the same Reference Clock.

Digital Enable. When this pin and JTRST are pulled low all Digital I/O pins are placed in a high-impedance state. If this pin is High the Digital I/O pins operate normally. This pin has to be connected to V

for normal operation.

JTAG Reset. JTRST is used to asynchronously reset the test access port controller. After power up, JTRST must be toggled from low to high. This action will set the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled HIGH internally via a 10kW resistor operation. If boundary scan is not used, this pin should be held low.

JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10k pull up resistor.

JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.

JTAG Data In. Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor.

JTAG Data Out. Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.

3.3V Analog Transmit Power Supply. These V

inputs are used for the transmit LIU

sections of the DS26528.

Analog Transmit V

3.3 V Analog Receive Power Supply. This V

. These pins are used for transmit analog VSS.

inputs are used for the Receive LIU

sections of the DS26528.

Analog Receive V

Analog Clock Conversion V

. These pins are used for analog VSS for the receivers.

. This VDD inputs are used for the clock conversion unit of

the DS26528.

ACVSS J7 —

DVDD

DVDDIO

G5–G12, H8,

H5, H6, H10,

H11

—

Analog Clock V

3.3V Power Supply for Digital Framers

3.3V Power Supply for I/Os

H12, H13,

DVSS

J8, J9, K5–

-—

Digital Ground for the Framers

K12

DVSSIO

J5, J6, J10,

J11

-—

Digital Ground for the I/Os

. This pin is used for clock converter analog VSS.

21 of 262

DS26528 Octal T1/E1/J1 Transceiver

Figure 8-1. BGA Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

TTIP1 TTIP1 TRING1 RSYNC1 TCHBLK1 TSIG2 REFCLKIO A11 A7 A1 TSIG7 RSIG7 TSYNC8 TRING8 TTIP8 TTIP8

ATVDD ATVSS TRING1 TSYNC1 RCHBLK2 RSYNC2 MCLK A10 A8 A2 TSYNC7 RSER7 TCLK8 TRING8 ATVSS ATVDD

RTIP1 RRING1 ALRSIGF1 RMRFSYNC1 TCLK1 RMRFSYNC2 TCHBLK2 A12 A6 A0 RSYNC7 RCHBLK7 TSIG8 ALRSIGF8 RRING8 RTIP8

ARVDD ARVSS RLFLTC1 RSIG1 TSIG1 RSER2 TCLK2 DIGIOEN A5 TCHBLK7 RMRFSYNC7 TSER8 RSYNC8 RLFLTC8 ARVSS ARVDD

ARVDD ARVSS RLFLTC2 RCHBLK1 RSER1 RSIG2 TSER2 BPCLK A4 TCLK7 TCHBLK8 RMFSYC8 RCLK8 RLFLTC7 ARVSS ARVDD

RTIP2 RRING2 ALRSIGF2 RCLK1 JTCLK TSER1 TSYNC2 A9 A3 TSER7 RSER8 RSIG8 RCLK7 ALRSIGF7 RRING7 RTIP7

ATVDD ATVSS TRING2 RCLK2 DVDD DVDD DVDD DVDD DVD D DVDD DVDD DVDD RCHBLK8 TRING7 ATVSS ATVDD

TTIP2 TTIP2 TRING2 JTDI DVDDIO DVDDIO ACVDD DVDD DVDD DVDDIO DVDDIO DVSS DVSS TRING7 TTIP7 TTIP7

TTIP3 TTIP3 TR ING3 JTDO DVSSIO DVSSIO ACVSS DVSS DVSS DVSSIO DVSSIO

ATVDD ATVSS TRING3 JTMS DVSS DVSS DVSS DVSS DVSS D VSS DVSS DVSS RCLK5 TRING6 ATVSS ATVDD

RTIP3 RRING3 ALRSIGF3 RCLK3 JTRST RCHBLK3 TCHBLK3 TCLK4 D1 TCLK5 TSER6 RSYSCLK TXENABLE ALRSIGF6 RRING6 RTIP6

WRB/

RWB

CSB

RDB/

D5 TSER5 RSER5 RSER6 BTS RLFLTC6 ARVSS ARVDD

DSB

INTB

D3 D7 TSIG5 RCHBLK5 TSYNC6 RCHBLK6 TRING5 TTIP5 TTIP5

RSYNC5 RSIG5 TSIG6 RSIG6 TRIN G5 ATVSS ATVDD

ARVDD ARVSS RLFLTC 3 RCLK4 RSIG3 TSYNC3 TSYNC4

ARVDD ARVSS RLFLTC4 RSER3 RSYNC3 RSER4 TSER4 D0 D6 TSYNC5 TCLK6 RMRFSYNC6 TSSYNCIO RLFLTC5 ARVSS ARVDD

RTIP4 RRING4 ALRSIGF4 RMRFSYNC3 TCLK3 RMRFSYNC4 TCHBLK4 D2 TCHBLK5 RMRFSYNC5 TCHBLK6 RSYNC6 TSYSCLK ALRSIGF5 RRING5 RTIP5

ATVDD ATVSS TRING4 TSER3 RSIG 4 TSIG4

TTIP4 TTIP4 TRING4 TSIG3 RCHBLK4 RSYNC4

RESETB

RCLK6 TRING6 TTIP6 TTIP6

22 of 262

DS26528 Octal T1/E1/J1 Transceiver

9. FUNCTIONAL DESCRIPTION

9.1 Processor Interface

Microprocessor control of the DS26528 is accomplished through the 28 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the Bus Type Select (BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 13-1 When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in Figure 13-3 address space is mapped through the use of 13 address lines, A0–A12. Multiplexed Mode is not supported on the processor interface.

and Figure 13-2.

and Figure 13-4. The

The Chip Select Bar ( microprocessor port. With Intel timing selected, the Read Bar ( read and write operations and latch data data through the interface. With Motorola timing selected, the Read-Write

RWB) pin is used to indicate read and write operations while the Data Strobe Bar (DSB) pin is used to latch

Bar ( data through the interface.

The interrupt output pin ( maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input.

The device has a bulk write mode that allows a microprocessor to write all eight internal transceivers with each bus write cycle. By setting the BWE bit (GTCR1 at the same time. The BWE bit must be cleared before normal write operation is resumed. This function is useful for device initialization.

The register map is shown in Figure 10-1

CSB) pin must be brought to a logic low level to gain read and write access to the

RDB) and Write Bar (WRB) pins are used to indicate

INTB) is an open-drain output that will assert a logic-low level upon a number of software

.2), each port write cycle will write to all eight framers, LIUs, or BERTs

9.2 Clock Structure

The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1 and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.

9.2.1.1 Backplane Clock Generation

The DS26528 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see Figure

9-1

). The Global Transceiver Control Register (GTCCR ) is used to control the backplane clock generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can be an output sourcing MCLKT1 or MCLKE1 as shown in Figure 9-1

This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26528 and other IBO equipped devices as an “IBO Bus Master.” Hence the DS26528 will provide the 8 KHZ Sync Pulse and 4,8,16MHz clock. This can be used by the link layer devices and frames connected to the IBO Bus.

23 of 262

Figure 9-1. Backplane Clock Generation

BPREFSEL3:0

RCLK1

RCLK2

RCLK3

RCLK4

RCLK5

RCLK6

RCLK7

RCLK8

Pre

MCLK

Scaler

PLL

MCLKT1

MCLKE1

REFCLKIO

DS26528 Octal T1/E1/J1 Transceiver

BPCLK1:0

BFREQSEL

Multiplexor

Clock

CLK

GEN

REFCLKI O

TSSYNCIO

BPCLK

The reference clock for the Backplane Clock generator can be:

· External Master Clock. A pre-scaler can be used to generate T1 or E1 Frequency

· External Reference Clock REFCLKIO. This allows for multiple DS26528 to use the Backplane Clock from a

common reference.

· Internal LIU recovered RCLKs 1 to 8.

· The Clock Generator can be used to generate BPCLK of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz for

the IBO.

· If MCLK or RCLKs are used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz

clock for external use.

24 of 262

DS26528 Octal T1/E1/J1 Transceiver

9.3 Resets and Power-Down Modes

A hardware reset is issued by forcing the RESETB pin to logic low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing reserved locations to 00h.

Table 9-1. Reset Functions

RESET FUNCTION LOCATION COMMENTS

Hardware Device Reset RESETB Pin

Hardware JTAG Reset JTRST Pin Resets the JTAG test port.

Global Framer and BERT Resets

Global LIU Resets GLSRR.0 - .7

Framer Receive Reset RMMR.1

Framer Transmit Reset TMMR.1

HDLC Receive Reset RHC.6

HDLC Transmit Reset THC1.5

Elastic Store Receive Reset RESCR.2

Elastic Store Transmit Reset TESCR.2

GFSRR

.0 - .7

Transition to a logic 0 level resets the DS26528.

Writing to these bits resets the associated Framer and BERT (transmit & receive).

Writing to these bits resets the associated Line Interface Unit.

Writing to this bit resets the Receive Framer.

Writing to this bit resets the Transmit Framer.

Writing to this bit resets the Receive HDLC controller.

Writing to this bit resets the Transmit HDLC controller.

Writing to this bit resets the Receive Elastic Store.

Writing to this bit resets the Transmit Elastic Store.

Bit Oriented Code Receive Reset

Loop Code Integration Reset

Spare Code Integration Reset T1RSCD1

The DS26528 has several features included to reduce power consumption. The individual LIU transmitters can be powered down by setting the TPDE bit in the LIU maintenance control register (LMCR the transmit LIU results in a High-Z state for the corresponding TTIP and TRING pins, and reduced operating current. The RPDE in the LMCR

The TE (Transmit Enable) bit in the LMCR them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for equipment protection switching applications.

T1RBOCC

T1RDNCD1

T1RUPCD1

Writing to this bit resets the Receive BOC controller.

Writing to these registers resets the programmable in-band code integration period.

Writing to this register resets the programmable in-band code integration period.

25 of 262

). Note that powering down

9.4 Initialization and Configuration

EXAMPLE DEVICE INITIALIZATION SEQUENCE:

DS26528 Octal T1/E1/J1 Transceiver

STEP 1: Reset the device by pulling the reset bits outlined in Section 9.3

STEP 2: Check the Device ID in the IDR register

STEP 3: Write the GTCCR follows this write with at least a 300ns delay in order to allow the clock system to properly adjust.

STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register locations.

STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR registers for each framer. Set the FRM_EN bit to 1 in the TMMR Signaling in E1 mode, program the E1TAF Control Registers (TCR1 – TCR4). Configure the framer Receive Control Registers (RCR1 – RCR3). Configure other framer features as appropriate.

STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR Configure the Line Build Out for each LIU. Configure other LIU features as appropriate. Set the TE (Transmit Enable) bit to turn on the TTIP and TRING outputs.

STEP 7: Configure the Elastic Stores, HDLC Controller, and BERT as needed.

STEP 8: Set the INIT_DONE bit in the TMMR

. Clear all reset bits. Allow time for the reset recovery.

RESETB pin low, applying power to the device, or by using the software

and RMMR

and RMMR registers. If using Software Transmit

and E1TNAF registers as required. Configure the framer Transmit

and RMMR registers for each framer.

9.5 Global Resources

All eight framers share a common microprocessor port. All ports share a common MCLK, and there is a common software configurable BPCLK output. A set of Global registers are located at 0F0h–0FFh and include Global resets, global interrupt status, interrupt masking, clock configuration, and the Device ID registers. See the Global Register Definitions in Table 10-6

. A common JTAG controller is used for all ports.

9.6 Per-Port Resources

Each port has an associated Framer, LIU, BERT, Jitter Attenuator, and Transmit/Receive HDLC controller. Each of the per-port functions has its own register space.

26 of 262

DS26528 Octal T1/E1/J1 Transceiver

9.7 Device Interrupts

Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of

information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Interrupt Information registers GFISR, GLISR, and GBISR to quickly identify which of the eight transceivers is(are) causing the interrupt(s). The host can then read the specific transceiver’s Interrupt Information registers (TIIR, RIIR) and the Latched Status Registers (LLSR, BLSR RIIR is the source, the host will then read Transmit Latched Status or the Receive Latched Status Registers for the source of the interrupt. All Interrupt Information Register bits are real-time bits that will clear once the appropriate interrupt has been serviced and cleared, as long as no additional, un-masked interrupt condition is present in the associated status register. All Latched Status bits must be cleared by the host writing a “1” to the bit location of the interrupt condition that has been serviced. Latched Status bits that have been masked via Interrupt Mask registers will be masked from the Interrupt Information Registers. The Interrupt Mask register bits prevent individual Latched Status conditions from generating an interrupt, but they do not prevent the Latched Status bits from being set. Therefore, when servicing interrupts, the user should XOR the Latched Status with the associated Interrupt Mask in order to exclude bits for which the user wished to prevent interrupt service. This architecture allows the application host to periodically poll the latched status bits for non-interrupt conditions, while using only one set of registers.

) to further identify the source of the interrupt(s). If TIIR or

27 of 262

Figure 9-2. Device Interrupt Information Flow Diagram

Receive Remote Alarm Indication Clear 7 Receive Alarm Condition Clear 6 Receive Loss of Signal Clear 5 Receive Loss of Frame Clear 4 Receive Remote Alarm Indication 3 Receive Alarm Condition 2 Receive Loss of Signal 1 Receive Loss of Frame 0

Receive Signal All Ones 3 Receive Signal All Zeros 2 Receive CRC4 Multiframe 1 Receive Align Frame 0

Loss of Receive Clk Clear / Loss of Receive Clk Clear 7 Spare Code Detected Condition Clear / - 6 Loop Down Code Clear / V52 Link Clear 5 Loop Up Code Clear / Receive Distant MF Alarm Clear 4 Loss of Receive Clk / Loss of Receive Clk 3 Spare Code Detect / - 2 Loop Down Detect / V52 Link Detect 1 Loop Up Detect / Receive Distant MF Alarm Detect 0

Receive Elastic Store Full 7 Receive Elastic Store Empty 6 Receive Elastic Store Slip 5 Receive Signaling Change of State (Enable in RSCSE1-4) One Second Timer 2 Timer 1 Receive Multiframe 0

Receive FIFO Overrun 5 Receive HDLC Opening Byte 4 Receive Packet End 3 Receive Packet Start 2 Receive Packet High Watermark 1 Receive FIFO Not Empty 0

Receive RAI-CI 5 Receive AIS-CI 4 Receive SLC-96 Alignment 3 Receive FDL Register Full 2 Receive BOC Clear 1 Receive BOC 0

Transmit Elastic Store Full 7 Transmit Elastic Store Empty 6 Transmit Elastic Store Slip 5 Transmit SLC96 Multiframe 4 Transmit Pulse Density Violation / Transmit Align Frame 3 Transmit Multiframe 2 Loss of Transmit Clock Clear 1 Loss of Transmit Clock 0

Transmit FDL Register Empty 4 Transmit FIFO Underrun 3 Transmit Message End 2 Transmit FIFO Below Low Watermark 1 Transmit FIFO Not Full Set 0

- -

- Loss of Frame 1 Loss of Frame Synchronization 0 Jitter Attenuator Limit Trip Clear 7

Open Circuit Detect Clear 6 Short Circuit Detect Clear 5 Loss of Signal Detect Clear 4 Jitter Attenuator Limit Trip 3 Open Circuit Detect 2 Short Circuit Detect 1 Loss of Signal Detect 0

BERT Bit Error Detected 6 BERT Bit Counter Overflow 5 BERT Error Counter Overflow 4 BERT Receive All Ones 3 BERT Receive All Zeros 2 BERT Receive Loss of Synchronization 1 BERT in Synchronization 0

RIM1

RLS1

RLS

RIM2

RIM3

RLS3

RIM4

RLS4

RIM5

RLS5

RIM7

RLS7

TIM1

TLS1

TIM2

TLS2

TIM3

TLS3

LLSR

LSIMR

BSIM

BLSR

Interrupt Status

Registers

Interrupt Mask

Registers

RIIR

Framers 2-8 LIUs 2-8 BERTs 2-8

TIIR

DS26528 Octal T1/E1/J1 Transceiver

Drawing Legend:

6 5 4 3 2 1 0

GFIMR

GFISR1

GLIMR

GLISR1

GTCR1.0

Interrupt Pin

GBIMR

GBISR1

28 of 262

DS26528 Octal T1/E1/J1 Transceiver

9.8 System Backplane Interface

The DS26528 provides a versatile Backplane interface that can be configured to:

· Transmit and Receive 2 Frame Elastic Stores

· Mapping of T1 channels into a 2.048MHz backplane

· IBO mode for multiple framers to share the backplane signals

· Transmit and receive channel blocking capability

· Fractional T1/E1/J1 support

· Hardware-based (through the backplane interface) or processor-based signaling

· Flexible backplane clock providing frequencies of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz

· Backplane clock and frame pulse (TSSYNIO) generator

9.8.1 Elastic Stores

The DS26528 contains dual, two-frame elastic stores for each framer; one for the receive direction, and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive side elastic stores can be enabled/disabled independently of each other. Also, the transmit or receive elastic store can interface to either a

1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic store. Since the DS26528 has a common TSYSCLK and RSYSCLK for all eight ports, the backplane signals in each direction must be synchronous for all ports on which the elastic stores are enabled. However, the transmit and receive signals are not required to be synchronous to each other. The TIOCR and RIOCR settings should be identical for all ports on which the elastic stores are enabled.

The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26528 is in the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked) backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the elastic stores will manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane.

If the elastic store is enabled while in E1 mode, then either CAS or CRC4 multiframe boundaries will be indicated via the RMSYNC output as controlled by the RSMS2 control bit (RIOCR

.1). If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then the RBCS registers will determine which channels of the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the RSER data and set to one. Also, in 1.544MHz applications, the RCHBLK output will not be active in Channels 25 through 32 (or in other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data will be repeated at RSER and the RLS4 then a full frame of data will be deleted and the RLS4

.5 and RLS4.6 bits will be set to a one. If the buffer fills,

.5 and RLS4.7 bits will be set to a one.

The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the Interleave Bus Option (IBO), which is discussed in Section 9.8.2

. The registers related to the Elastic Stores are

shown in the following table.

Table 9-2. Registers Related to the Elastic Store

Receive I/O Configuration Register (RIOCR) 084 Sync and Clock Selection for the Receiver Receive Elastic Store Control Register (RESCR) 085 Receive Elastic Store Control Receive Latched Status Register 4 ( RLS4) 093 Receive Elastic Store Empty full status Receive Interrupt Mask Register 4(RIM4) 0A3 Receive Interrupt Mask for Elastic Store

Transmit Elastic Store Control Register (TESCR) 185

Transmit Latched Status Register 1 (TLS1) Transmit Interrupt Mask Register 1 ( TIM1)

190 Transmit Elastic Store Latched Status 1A0 Transmit Elastic Store Interrupt Mask

Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer N = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8.

Transmit elastic control such as minimum mode

29 of 262

DS26528 Octal T1/E1/J1 Transceiver

9.8.1.1 Elastic Stores Initialization

There are two elastic store initializations that may be used to improve performance in certain applications, Elastic Store Reset and Elastic Store Align. Both of these involve the manipulation of the elastic store’s read and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align bit is used to 'center' the read/write pointers to the extent possible.

Table 9-3. Elastic Store Delay After Initialization

INITIALIZATION

Receive Elastic Store Reset RESCR.2 N bytes < Delay < 1 Frame + N bytes Transmit Elastic Store Reset TESCR.2 N bytes < Delay < 1 Frame + N bytes Receive Elastic Store Align RESCR.3 ½ Frame < Delay < 1 ½ Frames Transmit Elastic Store Align TESCR.3 ½ Frame < Delay < 1 ½ Frames

N = 9 for RSZS = 0 N = 2 for RSZS = 1

9.8.1.2 Minimum Delay Mode

Elastic store minimum delay mode may be used when the elastic store’s system clock is locked to its network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RESCR.1 enable the receive elastic store minimum delay mode. When enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode and TSYNC must be configured as an output when transmit minimum delay mode is enabled. In this mode the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNCIO (frame input mode). The slip zone select bit (RSZS at RESCR.4) must be set to ‘1’. All of the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2) should be toggled from a zero to a one to insure proper operation

BIT

DELAY

9.8.1.3 Additional Receive Elastic Store Information

If the receive side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system clock applications, see Section 9.8.2 providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries. If Signaling Reinsertion is enabled, the robbed-bit signaling data is realigned to the multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic store via the RFSYNC output whether the elastic store is enabled or not. Multiframe boundaries will always be indicated via the RMSYNC output. If the elastic store is enabled, then RMSYNC will output the multiframe boundary on the backplane side of the elastic store. When the device is receiving T1 and the backplane is enabled for 2.048MHz operation, the RMSYNC signal will output the T1 multiframe boundaries as delayed through the elastic store. When the device is receiving E1 and the backplane is enabled for 1.544MHz operation, the RMSYNC signal will output the E1 multiframe boundaries as delayed through the elastic store.

If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then they can use the backplane blank channel select registers (RBCS1-4) to determine which channels will have the data output at RSER forced to all ones.

. The user has the option of either

9.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane

Setting the TSCLKM bit in TIOCR.4 will enable the transmit elastic store to operate with a 2.048MHz backplane (32 time slots / frame). In this mode the user can chose which of the backplane channels on TSER will be mapped into the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1 associated bit location will force the transmit elastic store to ignore backplane data for that channel. Typically the

30 of 262

-4). A logic '1' in the

+ 232 hidden pages