Maxim Integrated Ultra-High-Speed Flash Microcontroller User Manual
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DECREMENT
PORTS
8051 MICROPROCESSOR
FLASH MEMORY SRAM
1
5
25
0
33
ULTRA-HIGH-SPEED
FLASH
MICROCONTROLLER
ORIGINAL
8051
MIPS
ULTRA-HIGH-SPEED FLASH MICROCONTROLLER USER’S GUIDE
The Ultra-High-Speed Flash Microcontroller User’s Guide should be used in conjunction with the data sheet(s) for all ultra-high-speed flash microcontrollers.
Rev: 11; 11/11
Ultra-High-Speed Flash
REVI S ION
NUMBER
REVI S ION
DATE
SECTION
NUMBER
DESCRIPTION
PAGES
CHANGED
0 1/01 — Init i a l relea se. —
1 10/02 — Corrected some t ypo s.
2 12/02 — Changed title to refle ct “ f las h ” and removed “DS89C 42 0 ” referenc e. Al l
3 8/03 — Made documen t un iver s a l to a l l Dal l a s u ltr a-h igh-speed mi cro co ntro l lers. Al l
4 Clarif i ed t hat t h e C T M bit is c leared in stop mode. 14
5 Corrected cycle time s for ADDC A, R n instr uc t io n . 50
4 2/04
15 In the C o m ma nd Summar ies secti o n , c larifi ed t ha t PMR SFR i s not disp la yed i n ROM loader. 133
5 8/04 4 Added FCNTL and FDATA to the Specia l-Fu n ct i o n Regis t er Lo ca t io n s tabl e. 14, 15
6 12/04 15 Changed the ACK /N A K re sp on ses in th e Co mmand Summar ie s sec t io n . 136
15
In the Com ma nd Summ ar ie s se c t i o n , c l ar ified tha t th e boot loader K co m ma nd does not erase t h e opt ion
control regi ster, whic h co ntr o l s the defaul t state o f t h e en ab le watchdog tim er bit.
136
15
Remo ved infor mat ion pertain ing to the paral lel programming m ode and inst e ad referred interest ed partie s to
contact microcon tro l ler t ec h n i c a l sup port directl y for more informa t io n .
138
7 10/05
4 Added Rev i sio n ID SFR. 14, 15, 26
12 Cl ari f i ed t he sele c t i o n of the sh ift c lo ck frequenc y for Mode 0 (fir st paragraph, last sent en c e). 116
8 3/07
14
In Instr uct ion Set Deta i l s for the D at a Tr an sf er tab le secti o n , changed "=" to " " for XCH A, Rn ; XCH a, direct;
XCH A, @R i ; and XCHD A, @R i; and changed ORLC, bit (72h) D7 from 1 to 0 in the Bo o lea n Variab le
Manipu l a t ion tab le sect i o n ; ch a nged the i n structi o n code for JZ rel (60h) D7 from 1 to 0 and D6 and D5 from
0 to 1 and for JNZ rel (70h) D7 from 1 to 0 and D6, D5, and D4 from 0 to 1; ch anged the JNB bi t, re l (30h) D5
from 0 to 1 and CJ NE A, d irect, r e l (B5 h) D6 from 0 to 1.
128, 12 9,
130
9 6/07 4 Corrected bi t na m e headings f or the R MS[2:0] tab le . 32
10 3/08 4 Corrected formatting errors. 23, 24
11 11/11 4 Corrected the T i m er 1 a nd 0 bit d e scr iptions for the CKMOD regist er ( swapped 1 and 0 for respecti ve t im er s) 4–21
Microcontroller User’s Guide
REVISION HISTORY
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the
circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _______________________________________________________ 1
© 2011 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 1: INTRODUCTION
Maxim’s ultra-high-speed flash microcontroller is an 8051-compatible microcontroller that provides improved performance and power
consumption when compared to the original 8051 version. It retains instruction set and object code compatibility with the 8051, yet performs the same operations in fewer clock cycles. Consequently, greater throughput is possible for the same crystal speed. As an alternative, the device can be run at a reduced frequency to save power. The more efficient design allows a much slower crystal speed to
get the same results as an original 8051, using much less power.
The fundamental innovation of the ultra-high-speed flash microcontroller is the use of only one clock per instruction cycle compared
with 12 for the original 8051. This results in up to 12 times improvement in performance over the original 8051 architecture and up to
four times improvement over other Maxim high-speed microcontrollers. The device provides several peripherals and features in addition to all of the standard features of an 80C32. These include 16kB/32kB/64kB of on-chip flash memory, 1kB of on-chip RAM, four 8-bit
I/O ports, three 16-bit timer/counters, two on-chip UARTs, dual data pointers, an on-chip watchdog timer, five levels of interrupt priority,
and a crystal multiplier. The device provides 256 bytes of RAM for variables and stack; 128 bytes can be reached using direct or indirect
addressing, or using indirect addressing only.
In addition to improved efficiency, it can operate at a maximum clock rate of 33MHz. Combined with the 12 times performance, this
allows for a maximum performance of 33 million instructions per second (MIPS). This level of computing power is comparable to many
16-bit processors, but without the added expense and complexity if implementing a 16-bit interface.
The device incorporates a power-management mode that allows the device to dynamically vary the internal clock speed from 1 clock
per cycle (default) to 1024 clocks per cycle. Because power consumption is directly proportional to clock speed, the device can reduce
its operating frequency during periods of little switchback. This greatly reduces power consumption. The switchback feature allows the
device to quickly return to highest speed operation upon receipt of an interrupt or serial port activity, allowing the device to respond to
external events while in power-management mode.
Maxim Integrated
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Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 2: ORDERING INFORMATION
The ultra-high-speed flash microcontroller family follows the part numbering convention shown below. Note that not all combinations of
devices may be currently available. Contact a Maxim sales office for up-to-date details.
DS89C420-QCL
SPEED: L 33MHz
TEMPERATURE: C 0°C to +70°C
N -40°C to+85°C
M PDIP
PACKAGE: Q PLCC
E Thin Quad Flat Pack (TQFP)
OPERATING VOLTAGE: 0 +5V
MEMORY TYPE: 9 Flash
Maxim Integrated
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Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 3: ARCHITECTURE
This section contains the following information:
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Data Pointer(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Timer/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
Scratchpad Registers (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Working Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
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Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 3: ARCHITECTURE
The architecture is based on the industry-standard 87C52 and executes the standard 8051 instruction set. The core is an accumulator-based architecture using internal registers for data storage and peripheral control. This section provides a brief description of each
architecture feature. Details concerning the programming model, instruction set, and register description are provided in Section 4.
ALU
The ALU is responsible for math functions, comparisons, and general decision making. The ALU is not used explicitly by software.
Instruction decoding prepares the ALU automatically and passes it the appropriate data. The ALU primarily uses two special-function
registers (SFRs) as the source and destination for all operations. These are the accumulator and B register. The ALU also provides status information in the program status register. The SFRs are described in the following pages.
Special-Function Registers
All peripherals and operations that are not explicitly controlled by instructions are controlled through SFRs. All SFRs are described in
Section 4. The most commonly used registers that are basic to the architecture are also described in the following pages.
Accumulator
The accumulator is a source and destination for many operations involving math, data movement, and decisions. Although it can be
bypassed, most high-speed instructions require the use of the accumulator (A or ACC) as one argument.
B Register
The B register is used as the second 8-bit argument in multiply and divide operations. When not used for these purposes, the B register can be used as a general-purpose register.
Program Status Word
The program status word holds a selection of bit flags that include the carry flag, auxiliary carry flag, general-purpose flag, register
bank select, overflow flag, and parity flag.
Data Pointer(s)
The data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions. This address can point to a
data memory location, either on- or off-chip, or a memory-mapped peripheral. When moving data from one memory area to another or
from memory to a memory-mapped peripheral, a pointer is needed for both the source and destination. The user can select the active
pointer through a dedicated SFR bit (Sel = DPS.0), or can activate an automatic toggling feature for altering the pointer selection (TSL
= DPS.5). An additional feature, if selected, provides automatic incrementing or decrementing of the current DPTR.
Stack Pointer
The stack pointer denotes the register location at the top of the stack, which is the last used value. The user can place the stack anywhere in the scratchpad RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers.
I/O Ports
Four 8-bit I/O ports are available. Each I/O port is represented by an SFR location, and can be written or read. The I/O port has a latch
that contains the value written by software. In general, software reads the state of external pins during a read operation.
Timer/Counters
Three 16-bit timer/counters are available. Each timer is contained in two SFR locations that can be written or read by software. The
timers are controlled by other SFRs described in Section 4.
UARTs
The two UARTs are controlled and accessed by SFRs. Each UART has an address that is used to read and write the UART. The same
address is used for both read and write operations, which are distinguished by the instruction. Each UART is controlled by its own SFR
control register.
Maxim Integrated
Ultra-High-Speed Flash
Microcontroller User’s Guide
Scratchpad Registers (RAM)
The high-speed core provides 256 bytes of scratchpad RAM for general-purpose data and variable storage. The first 128 bytes are
directly available to software. The second 128 are available through indirect addressing. Selected portions of this RAM have other
optional functions.
Stack
The stack is a RAM area that stores return address information during calls and interrupts. The user can also place variables on the
stack when necessary. The stack pointer designates the RAM location that is the top of the stack. Thus, depending on the value of the
stack pointer, the stack can be located anywhere in the 256 bytes of RAM. A common location would be in the upper 128 bytes of
RAM, as these locations are accessible through indirect addressing only.
Working Registers
The first 32 bytes of the scratchpad RAM can be used as four banks of eight working registers for high-speed data movement. Using
four banks, software can quickly change context by changing to a different bank. In addition to the accumulator, the working registers
are commonly used as data source or destination. Some of the working registers can also be used as pointers to other RAM locations
(indirect addressing).
Program Counter
The program counter (PC) is a 16-bit value that designates the next program address to be fetched. On-chip hardware automatically
increments the PC value to move to the next program memory location.
Address/Data Bus
The device addresses a 64kB program and 64kB data memory area that resides in a combination of internal and external memory. When
external memory is accessed, ports 0 and 2 are used as a multiplexed address and data bus. Three external memory bus structures
are supported. The nonpage mode (traditional 8051) bus structure provides the address MSB on port 2 and multiplexes port 0 between
address LSB and data. The page mode 1 bus structure uses port 0 exclusively for data and multiplexes port 2 between address MSB
and address LSB. The page mode 2 bus structure uses port 0 exclusively for address LSB and multiplexes port 2 between address MSB
and data. These addressing modes are detailed later.
Watchdog Timer
The watchdog timer provides a supervisory function for applications that cannot afford to run out of control. The watchdog timer is a
programmable, free-running timer. If allowed to reach the termination of its count, if enabled, the watchdog resets the CPU software
must prevent this by clearing or resetting the watchdog prior to its timeout.
Power Monitor
A bandgap reference and analog circuitry are incorporated to monitor the power-supply conditions. When VCCbegins to drop out of
tolerance, the power monitor issues an optional early warning power-fail interrupt. If power continues to fall, the power monitor invokes
a reset condition. This remains until power returns to normal operating voltage. The power monitor also functions on power-up, holding the microcontroller in a reset state until power is stable.
Interrupts
The device is capable of evaluating 13 interrupt sources simultaneously. Each interrupt has an associated interrupt vector, flag, priority, and enable. These interrupts can be globally enabled or disabled.
Timing Control
The microcontroller provides an on-chip oscillator for use with an external crystal. This can be bypassed by injecting a clock source
into the XTAL1 pin. The clock source is used to create machine cycle timing (four clocks), ALE, PSEN, watchdog, timer, and serial baudrate timing. In addition, an on-chip ring oscillator can be used to provide an approximately 10MHz clock source. A frequency multiplier feature is included, which can be selected by SFR control to multiply the input clock source by either two or four. This allows lower
frequency (and cost) crystals to be used while still allowing internal operation up to the full 33MHz limit.
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Microcontroller User’s Guide
Flash Memory
On-chip program memory is implemented in flash memory. This can be programmed in-system with the standard 5V VCCsupply
through a serial port (in-system) using a built-in program memory loader, or by a standard flash or EPROM programmer. Full programming details are given in Section 15.
A memory management unit (MMU) and other hardware supports any of the three programming methods. The MMU controls program
and data memory access, and provides sequencing and timing controls for programming of the on-chip program memory
also a separate security flash block that is used to support a standard three-level lock, a 64-byte encryption array, and other flash
options.
The full on-chip program memory range can be fetched by the processor automatically. Reset routines and all interrupt vectors are
located in the lower 128 bytes of the on-chip program memory area.
. There is
Maxim Integrated
Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 4: PROGRAMMING MODEL
This section contains the following information:
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Bit Addressable Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Working Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Register Indirect with Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Page Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Program Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
Special-Function Register Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13
Port 0 (P0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13
Data Pointer Low 0 (DPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13
Data Pointer High 0 (DPH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
Data Pointer Low 1 (DPL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
Data Pointer High 1 (DPH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
Data Pointer Select (DPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
Power Control (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-15
Timer/Counter Control (TCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-16
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Microcontroller User’s Guide
Timer Mode Control (TMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17
Timer 0 LSB (TL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17
Timer 1 LSB (TL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18
Timer 0 MSB (TH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18
Timer 1 MSB (TH1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18
Clock Control (CKCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18
Port 1 (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20
External Interrupt Flag (EXIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20
Timer and Serial Port Clock Mode Register (CKMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-21
Serial Port 0 Control (SCON0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22
Serial Data Buffer 0 (SBUF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
Revision ID (RID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
Address Control (ACON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
Port 2 (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24
Interrupt Enable (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24
Slave Address Register 0 (SADDR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25
Slave Address Register 1 (SADDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25
Port 3 (P3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25
Interrupt Priority 1 (IP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-26
Interrupt Priority 0 (IP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-27
Slave Address Mask Enable Register 0 (SADEN0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-27
Slave Address Mask Enable Register 1 (SADEN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-28
Serial Port 1 Control (SCON1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-28
Serial Data Buffer 1 (SBUF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29
ROM Size Select (ROMSIZE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29
Power Management Register (PMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-30
Status Register (STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-32
Timed Access Register (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-32
Timer 2 Control (T2CON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-33
Timer 2 Mode (T2MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-34
Timer 2 Capture LSB (RCAP2L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-34
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Microcontroller User’s Guide
Timer 2 Capture LSB (RCAP2H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-34
Timer 2 LSB (TL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-35
Timer 2 MSB (TH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-35
Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-35
Watchdog Control (WDCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-36
Accumulator (A or ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-37
Extended Interrupt Enable (EIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-37
B Register (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-38
Extended Interrupt Priority 1 (EIP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-38
Extended Interrupt Priority 0 (EIP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-39
LIST OF FIGURES
Figure 4-1. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
Figure 4-2. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
Figure 4-3. Scratchpad Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
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LIST OF TABLES
Table 4-1. Instructions that Affect Flag Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
Table 4-2. Special-Function Register Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11
Table 4-3. Special-Function Register Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12
Table 4-4. Port 0 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13
Table 4-5. Timer 1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17
Table 4-6. Timer 0 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17
Table 4-7. Watchdog Interrupt Flag Timeout Periods (in Oscillator Clocks) . . . . . . . . . . . . . . . . .4-18
Table 4-8. Timer Operation (in Oscillator Clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19
Table 4-9. MOVX Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19
Table 4-10. Serial Port Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22
Table 4-11. Memory Access Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
Table 4-12. Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24
Table 4-13. Most Significant Priority Select Bit Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-26
Table 4-14. Least Significant Priority Select Bit Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-27
Table 4-15. Serial Port 1 Modes and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-28
Table 4-16. On-Chip ROM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-30
Table 4-17. Serial Port Operation (in Oscillator Clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-31
Table 4-18. Data Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-31
Table 4-19. Register Bank Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-35
Table 4-20. Most Significant Priority Select Bit Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-38
Table 4-21. Least Significant Priority Select Bit Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-39
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Microcontroller User’s Guide
SECTION 4: PROGRAMMING MODEL
This section provides a programmer’s overview of the ultra-high-speed microcontroller core. It includes information on the memory
map, on-chip RAM, SFRs, and instruction set. The programming model of the ultra-high-speed microcontroller is very similar to that of
the industry-standard 80C52. The memory map is identical. It uses the same instruction set, with improved instruction timing. Several
new SFRs have been added.
Memory Organization
The ultra-high-speed flash microcontroller, like the 8052, uses several distinct memory areas. These areas include registers, program
memory, and data memory. Registers serve to control on-chip peripherals and as RAM. Note that registers (on-chip RAM) are separate from data memory. Registers are divided into three categories including directly addressed on-chip RAM, indirectly addressed onchip RAM, and SFRs. The program and data memory areas are discussed in the Memory Map section. The registers are discussed in
the Register Map section.
Memory Map
The ultra-high-speed microcontroller uses a memory-addressing scheme that separates program memory from data memory. Each
area is 64kB beginning at address 0000h and ending at FFFFh, as shown in Figure 4-1. The program and data segments can overlap
since they are accessed in different ways. Program memory is fetched by the microcontroller automatically. These addresses are never
written by software. In fact, there are no instructions that allow the program area to be written. There is one instruction (MOVC) that is
used to explicitly read the program area. This is commonly used to read lookup tables. The data memory area is accessed explicitly
using the MOVX instruction. This instruction provides multiple ways of specifying the target address. It is used to access the 64kB of
data memory.
The address and data range of devices with on-chip program and data memory overlap the 64k memory space. When on-chip memory is enabled, accessing memory in the on-chip range causes the device to access internal memory. Memory accesses beyond the
internal range are addressed externally through ports 0 and 2.
The ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the
device to act as a bootstrap loader for an external flash or nonvolatile SRAM. Secondly, this method can also be used to increase the
amount of available program memory from 64kB to 80kB without bank switching. For more information on this feature, see Section 6.
Pr
ogram and data memory can also be increased beyond the 64kB limit using bank-switching techniques. This is described in
Application Note 81: Memory Expansion with the High-Speed Microcontroller Family.
Register Map
The register map is illustrated in Figure 4-2. It is entirely separate from the program and data memory areas mentioned above. A separate class of instructions is used to access the registers. There are 256 potential register location values. In practice, the ultra-highspeed microcontroller has 256 bytes of scratchpad RAM and up to 128 SFRs. This is possible since the upper 128 scratchpad RAM
locations can only be accessed indirectly. That is, the contents of a working register (R0 or R1) or the stack pointer designates the RAM
location. A direct reference to one of the lower 128 addresses (0h-7Fh) accesses the scratchpad RAM. A direct reference to one of the upper
128 addresses (80h-FFh) must be an SFR access. In contrast, indirect references can access the entire scratchpad RAM range (0h-FFh).
Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data contents are small. When off-chip RAM is needed, the scratchpad area still provides the fastest general-purpose access. Within the 256
bytes of RAM, there are several special purpose areas. These are described as follows:
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Ultra-High-Speed Flash
FFh
7Fh
FFh
7Fh
255
128
INDIRECT
RAM
DIRECT
RAM
DIRECT
SPECIAL
FUNCTION
REGISTERS
0000h
FFFFh 64k
PROGRAM
MEMORY
DATA
MEMORY
0000h
INDIRECT RAM
FFh
7Fh
DIRECT RAM
BANK 3
2Fh
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 56 55 54 53 52 51 50
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 333 32 31 30
2F 2E 2D 2C 2B 2A 29 28
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
17 16 15 14 13 12 11 10
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh
18h
17h
10h
0Fh
08h
07h
00h
BANK 2
BANK 1
BANK 0
MSB LSB
Microcontroller User’s Guide
Figure 4-1. Memory Map
Figure 4-3. Scratchpad Register Addressing
Maxim Integrated
Figure 4-2. Register Map
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Bit Addressable Locations
In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM
and SFR area. In the scratchpad RAM area, registers 20h to 2Fh are bit addressable. This provides 128 (16 x 8) individual bits available to software. A bit access is distinguished from a full register access by the type of instruction. Addressing modes are discussed
later in this section. In the SFR area, any register location ending in a 0 or 8 is bit addressable. Figure 4-3 shows details of the on-chip
RAM addressing, including the locations of individual RAM bits.
Working Registers
As part of the lower 128 bytes of RAM, there are four banks of working registers (8 bytes each). The working registers are general-purpose
RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently
selected bank is used by any instruction using R0–R7. This allows software to change context by simply switching banks. This is controlled through the program status word register in the next SFR area. The working registers also allow their contents to be used for
indirect addressing of the upper 128 bytes of RAM. Thus, an instruction can designate the value stored in R0 (for example) to address
the upper RAM. This value might be the result of another calculation.
Stack
Another use of the scratchpad area is for the programmer’s stack. This area is selected using the stack pointer (SP;81h) SFR. Whenever
a call or interrupt is invoked, the return address is placed on the stack. It also is available to the programmer for variables, etc. Since
the stack can be moved, there is no fixed location within the RAM designated as stack. The stack pointer defaults to 07h upon reset.
The user can then move it as needed. A convenient location would be the upper RAM area (>7Fh), since this is only available indirectly. The SP points to the last used value. Therefore, the next value placed on the stack is put at SP + 1. Each PUSH or CALL increments the SP by the appropriate value. Each POP or RET decrements as well.
Addressing Modes
The DS89C420 uses the standard 8051 instruction set that is supported by a wide range of third-party assemblers and compilers. Like
the 8051, the DS89C420 uses three memory areas. These are program memory, data memory, and registers. The program and data
areas are 64kB each. They extend from 0000h to FFFFh. The register areas are located between 00h and FFh, but do not overlap with
the program and data segments. This is because the ultra-high-speed flash microcontroller uses different modes of addressing to
reach each memory segment. These modes are described below.
Program memory is the area from which all instructions are fetched. It is inherently read only. This is because the 8051 instruction set
provides no instructions that write to this area. Read/write access is for data memory and registers only. No special action is required
to fetch from program memory. Each instruction fetch is performed automatically by the on-chip CPU. In versions that contain on-chip
memory, the hardware decides whether the fetch is on-chip or off-chip based on the address. Explicit addressing modes are needed
for the data memory and register areas. These modes determine which register area is accessed or if off-chip data memory is used.
The ultra-high-speed microcontroller supports eight addressing modes:
• Register addressing
• Direct addressing
• Register indirect addressing
• Immediate addressing
• Register indirect addressing with displacement
• Relative addressing
• Page addressing
• Extended addressing
Five of the eight addressing modes are used to address operands. The remainder are used for program control and branching. When
writing assembly language instructions that use arguments, the convention is “destination, source.” Each mode of addressing is summarized on the following pages. Note that many instructions (such as ADD) have multiple-addressing modes available.
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Register Addressing
Register addressing is used for operands that are located in one of the eight working registers (R7–R0). The eight working registers
can be located in one of four working register banks found in the lower 32 bytes of scratchpad RAM, as determined by the current register bank-select bits. A register bank is selected using two bits in the program status word (PSW;D0h). This addressing mode is powerful, since it uses the active bank without knowing which bank is selected. Thus, one instruction can have multiple uses by simply
switching banks. Register addressing is also a high-speed instruction, requiring only one machine cycle. Two examples of register
addressing are provided below:
ADD A, R4 ;Add register R4 to Accumulator
INC R2 ;Increment the value in register R2
In the first case, the value in R4 is the source of the operation. In the latter, R2 is the destination. These instructions do not consider
the absolute address of the register. They act on whichever bank has been selected.
Any working register can also be accessed by direct addressing. In order to do this, the absolute address must be specified.
Direct Addressing
Direct addressing is the mode used to access the entire lower 128 bytes of scratchpad RAM and the SFR area. It is commonly used
to move the value in one register to another. Two examples are shown below:
MOV 72h, 74h ;Move the value in register 74 to
;register 72.
MOV 90h, 20h ;Move the value in register 20 to
;the SFR at 90h (Port 1)
Note that there is no instruction difference between a RAM access and an SFR access. The SFRs are register locations above 7Fh.
Direct addressing also extends to bit addressing. There is a group of instructions that explicitly use bits. The addr
vided to such an instruction is the bit location, rather than the register address. Registers between 20h and 2Fh contain bits that are
individually addr
SETB 00h ;Set bit 00 in the RAM. This is the
MOV C, 0B7h ;Move the contents of bit B7 to the
essable. SFRs that end in 0 or 8 are bit addressable. An example of direct bit addressing is as follows:
;LSb of the register at address 20h
;as shown earlier in this section.
;Carry flag. Bit B7 is the MSb of
;register B0 (Port 3).
ess information pro-
Register Indirect Addressing
This mode is used to access the scratchpad RAM locations above 7Fh. It can also be used to reach the lower RAM (0h–7Fh), if needed. The address is supplied by the contents of the working register specified in the instruction. Thus, one instruction can be used to
reach many values by altering the contents of the designated working register. Note that, in general, only R0 and R1 can be used as
pointers. An example of register indirect addressing follows:
ANL A, @R0 ;Logical AND the Accumulator
;with the contents of the register
;pointed to by the value stored in R0.
This mode is also used for stack manipulation. This is because all stack references are directed by the value in the stack pointer register. The push and pop instructions use this method of addressing. An example is as follows:
PUSH A ;Saves the contents of the
;accumulator on the stack.
Register indirect addressing is used for all off-chip data memory accesses. These involve the MOVX instruction. The pointer registers
can be R0, R1, DPTR0 and DPTR1. Both R0 and R1 reside in the working register ar
reference a 256-byte area of off-chip data memory. When using this type of addressing, the upper addr
value in the port 2 latch. This value must be selected by software prior to the MOVX instruction. An example is as follows:
MOVX @R0, A ;Write the value in the accumulator
;to the address pointed to by R0 in
;the page pointed to by P2.
Maxim Integrated
ea of the scratchpad RAM. They can be used to
ess byte is supplied by the
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The 16-bit data pointers (DPTRs) can be used as an absolute off-chip reference. This gives access to the entire 64kB data memory
map. An example is as follows:
MOVX @DPTR, A ;Write the value in the accumulator
;to the address referenced by the
;selected data pointer.
Immediate Addressing
Immediate addressing is used when one of the operands is predetermined and coded into the software. This mode is commonly used
to initialize SFRs and to mask particular bits without affecting others. An example is as follows:
ORL A, #40h ;Logical OR the Accumulator with 40h.
Register Indirect with Displacement
Register indirect addressing with displacement is used to access data in lookup tables in program memory space. The location is created using a base address with an index. The base address can be either the PC or the DPTR. The index is the accumulator. The result
is stored in the accumulator. An example is as follows:
MOVC A, @A +DPTR ;Load the accumulator with the contents
of program memory
;pointed to by the contents of the DPTR
plus the value in
;the accumulator.
Relative Addressing
Relative addressing is used to determine a destination address for the conditional branch. Each of these instructions includes an 8-bit
value that contains a two’s complement address offset (-127 to +128), which is added to the PC to determine the destination address.
This destination is branched to when the tested condition is true. The PC points to the program memory location immediately following the branch instruction when the offset is added. If the tested condition is not true, the next instruction is performed. An example is
as follows:
JZ $–20 ;Branch to the location (PC+2)–20
;if the contents of the accumulator = 0.
Page Addressing
Page addressing is used by the branching instructions to specify a destination address within the same 2kB block as the next contiguous instruction. The full 16-bit address is calculated by taking the five highest-order bits for the next instruction (PC + 2) and
concatenating them with the lowest order 11-bit field contained in the current instruction. An example is as follows:
0870h ACALL 100h ;Call to the subroutine at address 100h
plus the
;current page address.
In this example, the current page address is 800h, so the destination address is 900h.
Extended Addressing
Extended addressing is used by the branching instructions to specify a 16-bit destination address within the 64kB address space. The
destination address is fixed in the software as an absolute value. An example is as follows:
LJMP 0F732h ;Jump to address 0F732h.
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INSTRUC TION FLAGS INSTRUCTION FLAGS
C OV AC C OV AC
ADD X X X CLR C 0
ADDC X X X C PL C X
SUBB X X X ANL C , bit X
MUL 0 X ANL C, bit X
DIV 0 X ORL C, bit X
DA X ORL C, bit X
RRC X MOV C, bit X
RLC X CJNE X
SETB C 1 — —
Microcontroller User’s Guide
Program Status Flags
All program status flags are contained in the program status word at SFR location D0h. It contains flags that reflect the status of the CPU
and the result of selected operations. The flags are summarized below. The following table shows the instructions that affect each flag.
Bit Description*:
PSW.7 C
Carry Set when the previous operation resulted in a carry (during addition) or a borrow (during subtraction). Otherwise
cleared.
PSW.6 AC
Auxiliary Carry Set when the previous operation resulted in a carry (during addition) or a borrow (during subtraction) from the
high-order nibble. Otherwise cleared.
PSW.2 OV
Overflow For addition, OV is set when a carry is generated into a high order bit (bit 6 or bit 7), but not a carry out of the
same high-order bit. For subtraction, OV is set if a borrow is needed into a high order bit (bit 6 or bit 7), but not
into the other high-order bit. For multiplication, OV is set when the product exceeds FFh. For division, OV is
always cleared.
PSW.0 P
Parity Set to logic 1 to indicate an odd number of ones in the accumulator (odd parity). Cleared for an even number of
ones. This produces even parity.
*All of these bits are cleared to a logic 0 for all resets.
Table 4-1. Instructions that Affect Flag Settings
Note: X indicates the modification is according to the result of the instruction.
Special-Function Register Locations
The ultra-high-speed flash microcontroller, like the 8051, uses SFRs to control peripherals and modes. In many cases, an SFR controls
individual functions or report status on individual functions. The SFRs reside in register locations 80h–FFh and are reached using direct
addressing. SFRs that end in 0 or 8 are bit addressable.
All standard SFR locations from the original 8051 are duplicated, with several additions. Tables are provided to illustrate the locations
of the SFRs and the default reset conditions of all SFR bits. Detailed descriptions of each SFR follow.
Maxim Integrated
4-10
REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P0 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
SP 81h
DPL 82h
DPH 83h
DPL1 84h
DPH1 85h
DPS 86h ID1 ID0 TSL AID — — — SEL
PCON 87h SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE
TCON 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h GATE C/T M1 M0 GATE C/T M1 M0
TL0 8Ah
TL1 8Bh
TH0 8Ch
TH1 8Dh
CKCON 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0
P1 90h P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
EXIF 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS
CKMOD 96h T2MH T1MH T0MH
SCON0 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0
SBUF0 99h
RID 9Ah
ACON 9Dh PAGEE PAGES1 PAGES0
P2 A0h P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
IE A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
SADDR0 A9h
SADDR1 AAh
P3 B0h P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
IP1 B1h — MPS1 MPT2 MPS0 MPT1 MPX1 MPT0 MPX0
IP0 B8h — LPS1 LPT2 LPS0 LPT1 LPX1 LPT0 LPX0
SADEN0 B9h
SADEN1 BAh
SCON1 C0h SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
SBUF1 C1h
ROMSIZE C2h PRAME RMS2 RMS1 RMS0
PMR C4h CD1 CD0 SWB CTM 4X/
2X
ALEON DME1 DME0
STATUS C5h PIS2 PIS1 PIS0 — SPTA1 SPRA1 SPTA0 SPRA0
TA C7h
T2CON C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/
T2
CP/
RL2
T2MOD C9h — — — — — — T2OE DCEN
RCAP2L CAh
RCAP2H CBh
TL2 CCh
TH2 CDh
PSW D0h CY AC F0 RS1 RS0 OV F1 P
FCNTL D5h
FBUSY
FERR FC3 FC2 FC1 FC0
FDATA D6h
WDCON D8h SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT
ACC E0h
EIE E8h — — — EWDI EX5 EX4 EX3 EX2
B F0h
EIP1 F1h MPWDI MPX5 MPX4 MPX3 MPX2
EIP0 F8h — — — LPWDI LPX5 LPX4 LPX3 LPX2
Ultra-High-Speed Flash
Microcontroller User’s Guide
Table 4-2. Special-Function Register Locations
Note: Shaded bits are timed-access protected.
4-11
Maxim Integrated
Ultra-High-Speed Flash
REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P0 80h 1 1 1 1 1 1 1 1
SP 81h 0 0 0 0 0 1 1 1
DPL 82h 0 0 0 0 0 0 0 0
DPH 83h 0 0 0 0 0 0 0 0
DPL1 84h 0 0 0 0 0 0 0 0
DPH1 85h 0 0 0 0 0 0 0 0
DPS 86h 0 0 0 0 0 1 0 0
PCON 87h 0 0 Special Special 0 0 0 0
TCON 88h 0 0 0 0 0 0 0 0
TMOD 89h 0 0 0 0 0 0 0 0
TL0 8Ah 0 0 0 0 0 0 0 0
TL1 8Bh 0 0 0 0 0 0 0 0
TH0 8Ch 0 0 0 0 0 0 0 0
TH1 8Dh 0 0 0 0 0 0 0 0
CKCON 8Eh 0 0 0 0 0 0 0 1
P1 90h 1 1 1 1 1 1 1 1
EXIF 91h 0 0 0 0 Special Special Special 0
CKMOD 96h 1 1 0 0 0 1 1 1
SCON0 98h 0 0 0 0 0 0 0 0
SBUF0 99h 0 0 0 0 0 0 0 0
RID 9Ah Special Special Special Special S pecial Special Special Special
ACON 9Dh 0 0 0 1 1 1 1 1
P2 A0h 1 1 1 1 1 1 1 1
IE A8h 0 0 0 0 0 0 0 0
SADDR0 A9h 0 0 0 0 0 0 0 0
SADDR1 AAh 0 0 0 0 0 0 0 0
P3 B0h 1 1 1 1 1 1 1 1
IP1 B1h 1 0 0 0 0 0 0 0
IP0 B8h 1 0 0 0 0 0 0 0
SADEN0 B9h 0 0 0 0 0 0 0 0
SADEN1 BAh 0 0 0 0 0 0 0 0
SCON1 C0h 0 0 0 0 0 0 0 0
SBUF1 C1h 0 0 0 0 0 0 0 0
ROMSIZE C2h 1 1 1 1 0 1 0 1
PMR C4h 1 0 0 0 0 0 0 0
STATUS C5h 0 0 0 1 0 0 0 0
TA C7h 1 1 1 1 1 1 1 1
T2CON C8h 0 0 0 0 0 0 0 0
T2MOD C9h 1 1 1 1 1 1 0 0
RCAP2L CAh 0 0 0 0 0 0 0 0
RCAP2H CBh 0 0 0 0 0 0 0 0
TL2 CCh 0 0 0 0 0 0 0 0
TH2 CDh 0 0 0 0 0 0 0 0
PSW D0h 0 0 0 0 0 0 0 0
FCNTL D5h 1 0 1 1 0 0 0 0
FDATA D6h 0 0 0 0 0 0 0 0
WDCON D8h 0 Special 0 Special 0 Special Special 0
ACC E0h 0 0 0 0 0 0 0 0
EIE E8h 1 1 1 0 0 0 0 0
B F0h 0 0 0 0 0 0 0 0
EIP1 F1h 1 1 1 0 0 0 0 0
EIP0 F8h 1 1 1 0 0 0 0 0
Microcontroller User’s Guide
Table 4-3. Special-Function Register Reset Values
Maxim Integrated
4-12
76543210
SFR 82h DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
SFR 81h SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 RW-1 RW-1
76543210
SFR 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1
PAGEE PAGES PORT 0 FUNCTION
0 XX General-Purpose I/O (code execution < ROMSIZE.2-0)
0 XX Multiplexed Address LSB / Data (code execution > ROMSIZE.2-0)
1 00, 01, 10 Data
1 11 Address LSB
Ultra-High-Speed Flash
Microcontroller User’s Guide
Special-Function Registers
Most of the unique features of the ultra-high-speed microcontroller family are controlled by bits in SFRs located in unused locations in the 8051 SFR map. This allows for increased functionality while maintaining complete instruction set compatibility.
The description for each bit indicates its read and write access, as well as its state after a power-on reset.
Port 0 (P0)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
P0.7–0
Bits 7–0
Port 0. This port functions according to the table below where PAGEE = ACON.7 and PAGES =
ACON.6-5.
Table 4-4. Port 0 Function
When serving as general-purpose I/O (GPIO), the por
a 1 to one of the bits of this register configures the associated port 0 pin as an input. All read operations, with the exception of read-modify-write instructions, leave the port latch unchanged. During
external memory addressing and data memory write cycles, the port has high-and-low drive capability. During external memory data read cycles, the port is held in a high-impedance state.
Stack Pointer (SP)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
SP.7–0
Bits 7–0
Stack Pointer. This stack pointer is written by software to identify the location where the stack
begins. The stack pointer is incremented before every PUSH operation and is decremented following every POP operation. This register defaults to 07h after reset.
t is open-drain and requires pullups. Writing
Data Pointer Low 0 (DPL)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
DPL.7–0
Bits 7–0
4-13
Data Pointer LOW 0. This register is the low byte of the standard 80C32 16-bit data pointer. DPL
and DPH are used to point to nonscratchpad data RAM.
Maxim Integrated
76543210
SFR 86h ID1 ID0 TSL AID — — — SEL
RW-0 RW-0 RW-0 R-0 R-0 R-1 R-0 RW-0
76543210
SFR 85h DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
SFR 84h DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DL1H.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Data Pointer High 0 (DPH)
7 6543210
SFR 83h DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Ultra-High-Speed Flash
Microcontroller User’s Guide
DPH.7–0
Bits 7–0
Data Pointer High 0. This register is the high byte of the standard 80C32 16-bit data pointer. DPL
and DPH are used to point to nonscratchpad data RAM.
Data Pointer Low 1 (DPL1)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
DPL1.7–0
Bits 7–0
Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL
bit (DPS.0) is set, DPL1 and DPH1 are used in place of DPL and DPH during DPTR operations.
Data Pointer High 1 (DPH1)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
DPH1.7–0
Bits 7–0
Data Pointer Low 1. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL
bit (DPS.0) is set, DPL1 and DPH1 are used in place of DPL and DPH during DPTR operations.
Data Pointer Select (DPS)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
ID1
Bit 7
ID0
Bit 6
Maxim Integrated
Increment/Decrement Select for DPTR1. This bit determines the effect of the INC DPTR instruction on DPTR1 when selected (SEL = 1) as the active data pointer.
0 = INC DPTR increments DPTR1 (default)
1 = INC DPTR decrements DPTR1
Increment/Decrement Select for DPTR. This bit determines the effect of the INC DPTR instruction on DPTR when selected (SEL = 0) as the active data pointer
0 = INC DPTR increments DPTR (default)
1 = INC DPTR decrements DPTR
.
4-14
76543210
SFR 87h SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE
RW-0 RW-0 RW-0* RW-0* RW-0 RW-0 RW-0 RW-0
Ultra-High-Speed Flash
Microcontroller User’s Guide
TSL
Bit 5
AID
Bit 4
Bits 3, 2, 1
SEL
Bit 0
Power Control (PCON)
Toggle Select. When clear (= 0), DPTR-related instructions do not affect the SEL bit. When set
(= 1), the SEL bit is toggled following execution of any of the below DPTR-related instructions:
INC DPTR
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
Autoincrement/Decrement Enable. When set, the active data pointer is automatically incremented or decr
DPTR-related instructions:
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
Reserved. These bits read 010b.
Data Pointer Select. This bit selects the active data pointer.
0 = Instructions that use the DPTR use DPL and DPH.
1 = Instructions that use the DPTR use DPL1 and DPH1.
emented (as determined by ID1, ID0 bit settings) following execution of any of the below
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description
SMOD_0
Bit 7
SMOD0
Bit 6
OFDF
Bit 5
OFDE
Bit 4
GF1
Bit 3
GF0
Bit 2
Serial Port 0 Baud Rate Doubler Enable. This bit enables/disables the serial baud rate doubling
function for Serial Port 0.
0 = Serial Port 0 baud rate is that defined by baud rate generation equation.
1 = Serial Port 0 baud rate is double that defined by baud rate generation equation.
Framing Error Detection Enable. When clear (= 0), SCON1.7 and SCON0.7 serve as mode select
bit SM0 for the r
Framing Error has been detected.
Oscillator Fail Detect Flag. When OFDE = 1, this flag will be set if a reset condition is generated
due to oscillator failure. This bit is cleared on a power-on reset and is unchanged by other reset
sources. This bit must be clear
Oscillator Fail Detect Enable. When set (= 1), the oscillator fail detect circuitry and flag generation are enabled. An oscillator fail detection occurs if the crystal oscillator falls below ~20kHz. An
oscillator fail detection does not occur if the oscillator is halted through softwar
bit (PCON.1) or when running from the internal ring oscillator source. When clear (= 0), the oscillator fail detect circuitry is disabled.
General-Purpose User Flag 1. This is a general-purpose flag for software control.
General-Purpose User Flag 0. This is a general-purpose flag for software contr
espective serial ports. When set (= 1), SCON1.7 and SCON0.7 report whether a
ed by software.
e setting of the STOP
ol.
4-15
Maxim Integrated
Ultra-High-Speed Flash
7 6 5 4 3 2 1 0
SFR 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Microcontroller User’s Guide
STOP
Bit 1
IDLE
Bit 0
Stop Mode Select. Setting this bit stops program execution, halts the CPU oscillator and internal
timers, and places the CPU in a low-power mode. This bit always be reads as a 0. Setting this bit
causes the CTM bit (PMR.4) to be cleared. Setting both the STOP bit and the IDLE bit causes the
device to enter stop mode; however, doing this is not advised.
Idle Mode Select. Setting this bit stops program execution but leaves the CPU oscillator, timers,
serial ports, and interrupts active. This bit is always read as a 0. Setting both the STOP bit and the
IDLE bit causes the device to enter stop mode; however, doing this is not advised.
Timer/Counter Control (TCON)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
TF1
Bit 7
TR1
Bit 6
TF0
Bit 5
TR0
Bit 4
IE1
Bit 3
IT1
Bit 2
IE0
Bit 1
IT0
Bit 0
Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined
by the current mode. This bit can be cleared by software and is automatically cleared when the
CPU vectors to the Timer 1 interrupt service routine.
0 = No Timer 1 overflow has been detected.
1 = Timer 1 has overflowed its maximum count.
Timer 1 Run Control. This bit enables/disables the operation of Timer 1.
0 = Timer 1 is halted.
1 = Timer 1 is enabled.
Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined
by the current mode. This bit can be cleared by software and is automatically cleared when the
CPU vectors to the Timer 0 interrupt service routine or by software.
0 = No Timer 0 overflow has been detected.
1 = Timer 0 has overflowed its maximum count.
Timer 0 Run Control. This bit enables/disables the operation of Timer 0.
0 = Timer 0 is halted.
1 = Timer 0 is enabled.
Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected.
If IT1 = 1, this bit r
service routine. If IT1 = 0, this bit inversely reflects the state of the INT1 pin.
Interrupt 1 Type Select. This bit selects whether the INT1 pin detects edge- or level-triggered
interrupts.
0 = INT1 is level triggered.
1
= INT1 is edge triggered.
Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected.
If IT0 = 1, this bit remains set until cleared in softwar
service routine. If IT0 = 0, this bit inversely reflects the state of the INT0 pin.
Interrupt 0 Type Select. This bit selects whether the INT0 pin detects edge- or level-triggered
interrupts.
0 = INT0 is level triggered.
1 = INT0 is edge triggered.
emains set until cleared in software or until the start of the External Interrupt 1
e or until the start of the External Interrupt 0
Maxim Integrated
4-16
M1
M0
MODE
0 0 Mode 0: 8 bits with 5-bit prescale
0 1 Mode 1: 16 bits
1 0 Mode 2: 8 bits with autoreload
1 1 Mode 3: Timer 0 is two 8-bit counters
7 6 5 4 3 2 1 0
SFR 8Ah TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
7 6 5 4 3 2 1 0
SFR 89h GATE C/T M1 M0 GATE C/T M1 M0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
M1
M0
MODE
0
0 Mode 0: 8 bits with 5-bit prescale
0 1 Mode 1: 16 bits
1
0 Mode 2: 8 bits with autoreload
1
1 Mode 3: Timer 1 is halted, but holds its count
Ultra-High-Speed Flash
Microcontroller User’s Guide
Timer Mode Control (TMOD)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
GATE
Bit 7
C/T
Bit 6
M1, M0
Bits 5, 4
GATE
Bit 3
C/T
Bit 2
M1, M0
Bits 1, 0
Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
0 = Timer 1 clocks when TR1 = 1, regardless of the state of INT.
1 = Timer 1 clocks only when TR1 = 1 and INT1 = 1.
Timer 1 Counter/Timer Select.
0 = Timer 1 is incremented by internal clocks.
1 = Timer 1 is incremented by pulses on T1 when TR1 (TCON.6) is 1.
Timer 1 Mode Select. These bits select the operating mode of Timer 1.
Table 4-5. Timer 1 Mode Selection
Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
0 = Timer 0 clocks when TR0 = 1, regardless of the state of INT0.
1 = Timer 0 clocks only when TR0 = 1 and INT0 = 1.
Timer 0 Counter/Timer Select.
0 = Timer incremented by internal clocks.
1 = Timer 1 is incremented by pulses on T0 when TR0 (TCON.4) is 1.
Timer 0 Mode Select. These bits select the operating mode of Timer 0. When Timer 0 is in mode
3, TL0 is star
then provided by the Timer 1 mode selection.
ted/stopped by TR0 and TH0 is started/stopped by TR1. Run control from Timer 1 is
Table 4-6. Timer 0 Mode Selection
Timer 0 LSB (TL0)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
TL0.7–0
Bits 7–0
4-17
Timer 0 LSB. This register contains the least significant byte of Timer 0.
Maxim Integrated
76543210
SFR 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1
4X/2X CD1:0 WD1 :0 = 00 W D1:0 = 01 WD1:0 = 10 WD1:0 = 11
1 00 2
15
2
18
2
21
2
24
0 00 2
16
2
19
2
22
2
25
X 01 2
17
2
20
2
23
2
26
X 10 2
17
2
20
2
23
2
26
X 11 2
27
2
30
2
33
2
36
7 6 5 4 3 2 1 0
SFR 8Dh TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
7 6 5 4 3 2 1 0
SFR 8Ch TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Timer 1 LSB (TL1)
7 6 5 4 3 2 1 0
SFR 8Bh TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Ultra-High-Speed Flash
Microcontroller User’s Guide
TL1.7–0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
Bits 7–0
Timer 0 MSB (TH0)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
TH0.7–0
Timer 0 MSB. This register contains the most significant byte of Timer 0.
Bits 7–0
Timer 1 MSB (TH1)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
TH1.7–0
Timer 1 MSB. This register contains the most significant byte of Timer 1.
Bits 7–0
Clock Control (CKCON)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
WD1, WD0
Bits 7, 6
Watchdog Timer Mode Select 1-0. These bits determine the watchdog timer timeout period for
the watchdog timer. The timer divides the crystal (or external oscillator) frequency by a programmable value as shown on the next page. The divider value is expressed in crystal (oscillator)
cycles. The settings of the system clock control bits 4X/2X (PMR.3) and CD1:0 (PMR.7-6) affect the
clock input to the watchdog timer and therefore its timeout period as shown below. All watchdog
timer reset timeouts follow the setting of the interrupt flag by 512 system clocks.
Table 4-7. Watchdog Interrupt Flag Timeout Periods (in Oscillator Clocks)
Maxim Integrated
4-18
MD2, MD1, MD0 STRETCH VALUE MOVX DURATION
000 0 2 machine cycles
001 1
3 machine cycles
(default)
010 2 4 machine cycles
011 3 5 machine cycles
100 4 9 machine cycles
101 5 10 machine cycles
110 6 11 machine cycles
111 7 12 machine cycles
OSCILLATOR CLOCKS
PER TIMER (0, 1, 2) CLOCK
TxMH, TxM =
OSCILLATOR CLOCKS PER
TIMER 2 CLOCK (BAUD RATE GEN)
T2MH, T2M =
4X/2X CD1:0
00 01 1X XX
1 00 12 1 0.25 2
0 00 12 2 0.5 2
X 01 12 4 1 2
X 10 12 4 1 2
X 11 3072 1024 1024 2048
Ultra-High-Speed Flash
Microcontroller User’s Guide
T2M
Bit 5
T1M
Bit 4
T0M
Bit 3
MD2, MD1, MD0
Bits 2, 1, 0
Timer 2 Clock Select. This bit controls the input clock that drives Timer 2. This bit has no effect
when the timer is in baud rate generator or clock output modes. See Timer Operation table.
Timer 1 Clock Select. This bit controls the input clock that drives Timer 1. See Timer Operation
table.
Timer 0 Clock Select. This bit contr
ols the input clock that drives Timer 0. See Timer Operation
table.
Table 4-8. Timer Operation (in Oscillator Clocks)
Stretch MOVX Select 2-0. These bits select the time by which external MOVX cycles are to be
stretched. This allows slower memory or peripherals to be accessed without using ports or manual software intervention. The RD or WR strobe is stretched by the specified interval, which is transparent to the software except for the increased time to execute to MOVX instruction. All internal
MOVX instructions are executed at the two machine cycle rate (0 stretch) independent of these bit
settings.
Table 4-9. MOVX Instruction
4-19
Maxim Integrated
76543210
SFR 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS
RW-0 RW-0 RW-0 RW-0 R-* R-* RW-* RT-0
Port 1 (P1)
76543210
SFR 90h
P1.7
INT5
P1.6
INT4
P1.5
INT3
P1.4
INT2
P1.3
TXD1
P1.2
RXD1
P1.1
T2EX
P1.0
T2
RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Ultra-High-Speed Flash
Microcontroller User’s Guide
P1.7–0
Bits 7–0
General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all
the pins have an alternative function listed below. Each of the functions is controlled by several
other SFRs. The associated Port 1 latch bit must contain a logic 1 before the pin can be used in its
alternate function capacity.
INT5
External Interrupt 5. A falling edge on this pin causes an external interrupt 5 if enabled.
Bit 7
INT4
External Interrupt 4. A rising edge on this pin causes an external interrupt 4 if enabled.
Bit 6
INT3
External Interrupt 3. A falling edge on this pin causes an external interrupt 3 if enabled.
Bit 5
INT2
External Interrupt 2. A rising edge on this pin causes an exter
Bit 4
TXD1
Bit 3
RXD1
Bit 2
T2EX
Bit 1
Serial Port 1 Transmit. This pin transmits the serial port 1 data in serial port modes 1, 2, 3 and
emits the synchr
Serial Port 1 Receive. This pin receives the serial port 1 data in serial port modes 1, 2, 3 and is a
bidirectional data transfer pin in serial port mode 0.
Timer 2 Capture/Reload T
ters to be transferred into the captur
reload mode, a 1-to-0 transition on this pin reloads the Timer 2 registers with the value in RCAP2L
and RCAP2H if enabled by EXEN2 (T2CON.3).
T2
Bit 0
Timer 2 External Input. A 1-to-0 transition on this pin causes T
depending on the timer configuration.
External Interrupt Flag (EXIF)
nal interrupt 2 if enabled.
onizing clock in serial port mode 0.
rigger. A 1-to-0 transition on this pin causes the value in the T2 regis-
e registers if enabled by EXEN2 (T2CON.3). When in auto-
imer 2 increment or decrement bit
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset,* = See description.
IE5
Bit 7
IE4
Bit 6
IE3
Bit 5
IE2
Bit 4
Maxim Integrated
External Interrupt 5 Flag. This bit is set when a falling edge is detected on INT5. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 4 Flag. This bit is set when a rising edge is detected on INT4. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 3 Flag. This bit is set when a falling edge is detected on INT3. This bit must be
clear
ed manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 2 Flag. This bit is set when a rising edge is detected on INT2. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt if enabled.
4-20
7 6 5 4 3 2 1 0
SFR 96h — — T2MH T1MH T0MH — — —
RW-1 RW-1 RW-0 RW-0 RW-0 RW-1 RW-1 RW-1
Ultra-High-Speed Flash
Microcontroller User’s Guide
CKRY
Bit 3
RGMD
Bit 2
RGSL
Bit 1
BGS
Bit 0
Clock Ready. This bit indicates the status of the startup period for the crystal oscillator or crystal
multiplier warm-up period. This bit is cleared after a reset or when exiting STOP mode. It is also
cleared when the clock multiplier is enabled (setting of PMR.4 = 1). Once CKRY is cleared, a
65,536 clock count must take place before CKRY is set and the lockout preventing modification of
CD1:CD0 is removed. Once CKRY is set (= 1), the clock multiplier can then be selected as the
clock source or switchover from the ring oscillator to the crystal oscillator can occur.
Ring Mode Status. This status bit indicates the current clock source for the device. This bit is
cleared to 0 after a power-on reset and unchanged by all other forms of reset.
0 = Device is operating from the external crystal or oscillator.
1 = Device is operating fr
Ring Oscillator Select. When set (= 1), this bit enables operation using the on-chip ring oscillator
as the clock source until the oscillator warm-up period has completed (CKRY = 1). Using the ring
oscillator to resume from stop mode allows almost instantaneous startup. This bit is cleared to 0
after a power-on reset and unchanged by all other forms of reset.
0
= Device operation is held until completion of the crystal oscillator warm-up delay period.
1 = The device begins operating from the ring oscillator and switch over to the crystal oscillator
upon completion of the warm-up delay period.
Bandgap Select. This bit enables/disables the bandgap reference during stop mode. Disabling
the bandgap reference provides significant power savings in stop mode but sacrifices the ability
to perform a power-fail interrupt or power-fail reset while stopped. This bit can only be modified with
a timed access procedure.
0 = The bandgap reference is disabled in stop mode but functions during normal operation.
1 = The bandgap reference operates in stop mode.
om the ring oscillator.
Timer and Serial Port Clock Mode Register (CKMOD)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Bits 7, 6
T2MH
Bit 5
T1MH
Bit 4
T0MH
Bit 3
Bits 2–0
Reserved.
Timer 2 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 2, and the T2M bit (CKCON.5) setting is ignored. When clear (= 0), the input clock
for Timer 2 is selected using the T2M bit.
Timer 1 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 1, and the T1M bit (CKCON.4) setting is ignored. When clear (= 0), the input clock
for Timer 1 is selected using the T1M bit.
Timer 0 Clock Mode High-Speed Select. When set (= 1), the system clock is used as the input
clock for Timer 0, and the T0M bit (CKCON.3) setting is ignored. When clear (= 0), the input clock
for Timer 0 is selected using the T0M bit.
Reserved. Read data is 1.
4-21
Maxim Integrated
Serial Port 0 Control (SCON0)
7 6 5 4 3 2 1 0
SFR 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
SM0 SM1 SM2 MO DE F U N C TION LENG TH (BITS) PERIOD
0 0 0 0 Synchronous 8 See PMR register
0 0 1 0 Synchronous 8 See PMR register
0 1 X 1 Asynchronous 10 Timer 1 or 2 baud rate equation
1 0 0 2 Asynchronous 11 See P MR register
1 0 1 2
Asynchronous with multiprocessor
communication
11 See PMR register
1 1 0 3 Asynchronous 11 Timer 1 or 2 baud rate equation
1 1 1 3
Asynchronous with multiprocessor
communication
11 Timer 1 or 2 baud rate equation
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Ultra-High-Speed Flash
Microcontroller User’s Guide
SM0–2
Bits 7, 6, 5
Serial Port Mode. These bits control the mode of serial port 0. In addition the SM0 and SM2_0 bits
have secondary functions as shown.
Table 4-10. Serial Port Mode Functions
SM0/FE_0
Bit 7
SM1_0
Bit 6
SM2_0
Bit 5
REN_0
Bit 4
TB8_0
Bit 3
RB8_0
Bit 2
TI_0
Bit 1
Maxim Integrated
Framing Error Flag. When SMOD0 (PCON.6) = 0, this bit is used as a mode select bit (SM0) for
serial port 0. When SMOD0 (PCON.6) = 1, this bit becomes a framing error (FE) bit, which reports
detection of an invalid stop bit. When used as FE, this bit must be cleared in software. Once the
SMOD0 bit is set, modifications to this bit do not affect the serial port mode settings. Although
accessed from the same register, the data for bits SM0 and FE are stored internally in different
physical locations.
No Alternate Function.
Multiple CPU Communications. The function of this bit is dependent on the serial port 0 mode.
Mode 0: Selects period for synchronous serial port 0 data transfers.
Mode 1: When set, r
eception is ignored (RI_0 is not set) if invalid stop bit received.
Modes 2/3: When this bit is set, multiprocessor communications are enabled in modes 2 and 3.
This prevents the RI_0 bit from being set, and an interrupt being asserted, if the 9th bit received is not 1.
Receiver Enable. This bit enables/disables the serial port 0 receiver shift r
0 = Serial por
t 0 reception disabled.
egister.
1 = Serial port 0 receiver enabled (modes 1, 2, 3). Initiate synchronous reception (mode 0).
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port 0
modes 2 and 3.
9th Received Bit State. This bit identifies that state of the 9th reception bit of r
ial por
t 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop
bit. RB8_0 is not used in mode 0.
Transmitter Interrupt Flag. This bit indicates that data in the serial port 0 buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes,
this bit is set at the end of the last data bit. This bit must be manually cleared by software.
eceived data in ser-
4-22
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