Maxim Integrated MAXREFDES5 User Manual
Santa Fe (MAXREFDES5#) Nexys 3
Quick Start Guide
Rev 1; 2/14
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Santa Fe (MAXREFDES5#) Nexys 3 Quick Start Guide
Table of Contents
1. Required Equipment ................................................................................................. 3
2. Overview ................................................................................................................... 3
3. Included Files ........................................................................................................... 5
4. Procedure ................................................................................................................. 6
5. Code Documentation .............................................................................................. 18
6. Appendix A: Project Structure and Key Filenames ................................................. 19
7. Trademarks ............................................................................................................ 19
8. Revision History ...................................................................................................... 20
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Santa Fe (MAXREFDES5#) Nexys 3 Quick Start Guide
1. Required Equipment
• PC with Windows® OS with Xilinx® ISE®/SDK version 13.4 or later and two USB
ports
• License for Xilinx EDK/SDK version 13.4 or later
• Santa Fe (MAXREFDES5#) board
• Nexys™3 development kit
• Industrial sensor or signal source
2. Overview
Below is a high-level overview of the steps required to quickly get the Santa Fe design
running by downloading and running the FPGA project. Detailed instructions for each
step are provided in the following pages. The Santa Fe (MAXREFDES5#) subs ystem
reference design will be referred to as Santa Fe throughout this document.
1) Connect the Santa Fe board to the JB1 port of a Nexys 3 development kit as
shown in Figure 1. Ensure the connector is aligned as shown in Figure 2.
2) Download the latest RD5V01_00.ZIP file located at the Santa Fe page.
3) Extract the RD5V01_00.ZIP file to a directory on your PC.
4) Open the Xilinx SDK.
5) Download the bitstream (.BIT) file to the board. This bitstream contains the FPGA
hardware design and software bootloader.
6) Open a terminal program to communicate with FPGA board.
7) Use Xilinx SDK to download and run the executable file (.ELF) on the
MicroBlaze™.
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Santa Fe (MAXREFDES5#) Nexys 3 Quick Start Guide
Figure 1. Santa Fe Board Connected to Nexys 3 Development Kit
Figure 2. Pmod™ Connector Alignment
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Santa Fe (MAXREFDES5#) Nexys 3 Quick Start Guide
3. Included Files
The top level of the hardware design is a Xilinx ISE Project Navigator Proj ect (.XISE) for
Xilinx ISE version 13.4. The Verilog-based HDL design instantiates the MicroBlaze core,
the support hardware required to run the MicroBlaze, a nd the peripherals that interface
to the Pmod ports. This is supplied as a Xi linx software development kit (SDK) project
that includes a demonstration software application to evalu ate the Santa Fe subsystem
reference design. The lower level c-code driver routines are portable to the user ’s own
software project.
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Figure 3. Block Diagram of FPGA Hardware Design
Santa Fe (MAXREFDES5#) Nexys 3 Quick Start Guide
4. Procedure
1. Connect the Santa Fe board to the JB1 port of a Nexys 3 development kit as
shown in Figure 1. Power up the Nexys 3 de velopm ent kit. The Santa Fe board is
completely powered from the Nexys 3 development kit and no external power is
required.
2. Download the latest RD5V01_00.ZIP file at
www.maximintegrated.com/AN5561. All files available for download are
available at the bottom of the page.
3. Extract the RD5V01_00.ZIP file to a directory on your PC. The location is
arbitrary but the path prior to where you extract t he .ZIP file must not exceed 82
characters due to the Windows 250-character total path limitation. For example,
this 90-character preceding path would be an example of a path that would be
too long:
C:\0123456789\0123456789\0123456789\0123456789\0123456789\0123456789\
0123456789\0123456789\0123456789\RD5V01_00.ZIP
(This path is too long.)
In addition, the Xilinx tools require the path to not contain any spaces.
C:\Do Not Use Spaces In The Path\RD5V01_00.ZIP
(This path has spaces.)
For the purposes of this document, it will be C:\designs\maxim\RD5V01_00\.
See Appendix A: Project Structure and Key Filenames in this document for
the project structure and key filenames.
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