Maxim Integrated MAXREFDES30 User Manual

Petaluma (MAXREFDES30#) ZedBoard

Quick Start Guide

Rev 0; 2/14

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Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide

Table of Contents

1. Required Equipment ................................................................................................. 3

2. Overview ................................................................................................................... 3

3. Included Files ........................................................................................................... 5

4. Procedure ................................................................................................................. 6

5. Code Documentation .............................................................................................. 19

6. Appendix A: Project Structure and Key Filenames ................................................. 20

7. Trademarks ............................................................................................................ 20

8. Revision History ...................................................................................................... 21

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Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide

1. Required Equipment

• PC with Windows® OS with Xilinx® ISE®/SDK version 14.2 or later and two USB
ports (Refer to Xilinx AR# 51895 if you installed ISE WebPackTM design software
on your PC.)

• License for Xilinx EDK/SDK version 14.2 or later (free WebPack license is OK)

• Petaluma (MAXREFDES30#) board

• ZedBoardTM development kit

• Industrial sensor or signal source

2. Overview

Below is a high-level overview of the steps required t o quickly get the Petaluma design
running by downloading and running the FPGA project. Detailed instructions for each
step are provided in the following pages. The Petaluma (MAXREFDES30#)

subsystem reference design will be referred to as Petaluma throughout this
document.

1) Connect the Petaluma board to the J1 FMC connector of a ZedBoard as shown
in Figure 1.

2) Download the latest RD30V01_00.ZIP file located at the Petaluma page.

3) Extract the RD30V01_00.ZIP file to a directory on your PC.

4) Open the Xilinx SDK.

5) Download the bitstream (.BIT) file to the board. This bitstream contains the FPGA
hardware design and software bootloader.

6) Use Xilinx SDK to download and run the executable file (.ELF) on one of the two
ARM® CortexTM-A9 processors.

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Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide

Figure 1. Petaluma Board Connected to ZedBoard Development Kit

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Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide

3. Included Files

The top level of the hardware design is a Xilin x PlanAhead™ Project (.PRR) for Xilinx
PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides
FPGA/board net connectivity, and instantiates the wrapper t hat carries both the Zynq®
Processing System and AXI_MAX11046 custom IP core that interface to the FMC
connector. This is supplied as a Xilinx software development kit (SDK) project that
includes a demonstration software application to evaluate the Petaluma subsystem
reference design. The lower level c-code driver routines are portable to the user ’s own
software project.

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Figure 2. Block Diagram of FPGA Hardware Design

Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide

4. Procedure

1. Install a 2-pin h eader on the J18 connector on the ZedBoard if the 3V3 hea der is
missing.

2. Remove any shunt on 1V8 and 2V5 headers, and install a shunt on the 3V3
header.

3. Connect the Petaluma board to the J1 FMC connector of the ZedBoard as shown
in Figure 1.

4. Power up the ZedBoard by slidin g the SW8 switch on the ZedBoard to the ON
position.

5. Download the latest RD30V01_00.ZIP file at

www.maximintegrated.com/Petaluma

available at the bottom of the page.

6. Extract the RD30V01_00.ZIP file to a directory on your PC. The location is
arbitrary but the maximum path length limitation in Windows (260 characters)
should not be exceeded.

In addition, the Xilinx tools require the path to not contain any spaces.

C:\Do Not Use Spaces In The Path\RD30V01_00.ZIP

(This path has spaces.)

For the purposes of this document, it will be C:\designs\maxim\RD30V01_00\.
See Appendix A: Project Structure and Key Filenames in this document for
the project structure and key filenames.

. All files available for download are

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Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide

7. Open the Xilinx Software Development Kit (SDK) from the Windows Start
menu.

8. SDK will prompt for a workspace directory, which is the location where the
software project is located. For this example, it is:

C:\designs\maxim\RD30V01_00\RD6_ZED_V01_00\Design_Files\top.sdk\SDK\
SDK_Export

Click OK and SDK will open. The Xilinx SDK is based on an Eclipse™-based
IDE, so it will be a familiar flow for many software developers.

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