Maxim Integrated MAXREFDES14 User Manual
Sonoma (MAXREFDES14#) ZedBoard
Quick Start Guide
Rev 0; 9/13
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Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide
Table of Contents
1. Required Equipment ................................................................................................. 3
2. Overview ................................................................................................................... 3
3. Included Files ........................................................................................................... 5
4. Procedure ................................................................................................................. 6
5. Code Documentation .............................................................................................. 19
6. Appendix A: Project Structure and Key Filenames ................................................. 20
7. Trademarks ............................................................................................................ 20
8. Revision History ...................................................................................................... 21
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Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide
1. Required Equipment
• PC with Windows® OS with Xilinx® ISE®/SDK version 14.2 or later and two USB
ports (Refer to Xilinx AR# 51895 if you installed ISE WebPackTM design software
on your PC.)
• 120V AC power source or wall outlet
• AC load
• License for Xilinx EDK/SDK version 14.2 or later (Free WebPack license is OK)
• Sonoma (MAXREFDES14#) board
• ZedBoardTM development kit
2. Overview
Below is a high-level overview of the steps required to quickly get the Sonoma design
running by downloading and running the FPGA project. Detailed instructions for each
step are provided in the following pages. The Sonoma (MAXREFDES14#) subsystem
reference design will be referred to as Sonoma throughout this document.
1) Connect the Sonoma board to the JA1 port of a ZedBoard as shown in Figure 1.
Ensure the connector is aligned as shown in
2) Connect the power supply and the load to the Sonoma board.
3) Download the latest RD14V01_00.ZIP file located at the Sonoma page.
4) Extract the RD14V01_00.ZIP file to a directory on your PC.
5) Open the Xilinx SDK.
6) Download the bitstream (.BIT) file to the board. This bitstream contains the FPGA
hardware design and software bootloader.
7) Use Xilinx SDK to download and run the executable file (.ELF) on one of the two
ARM® CortexTM -A9 processors.
Figure 2.
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Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide
Figure 1. Sonoma Board Connected to ZedBoard Development Kit
Figure 2. Pmod™ Connector Alignment
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Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide
3. Included Files
The top level of the hardware design is a Xilinx PlanAhead Project (.prr) for Xilinx
PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides
FPGA/board net connectivity, and instantiates the wrapper that carries the Zynq®
Processing System. This is supplied as a Xilinx soft ware development kit (SDK) project
that includes a demons tration software application to evaluate the Sonoma subsystem
reference design. The lower level c-code driver routines are portable to the user ’s own
software project.
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Figure 3. Block Diagram of FPGA Hardware Design
Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide
4. Procedure
1. Connect the Sonoma board to the JA1 port of a ZedBoard as shown in Figure 1.
2. Connect J14 and J17 connectors of the ZedBoard to the computer with MicroUSB cables.
3. Connect the AC power supply and the load to the Sonoma board as shown in
Figure 4.
4. Power up t he ZedBoard by sliding the SW8 switch on the ZedBoard to the ON
position.
5. Download the latest RD14V01_00.ZIP file at
www.maximintegrated.com/sonoma. All files available for download are
available at the bottom of the page.
6. Extract the RD14V01_00.ZIP file to a directory on your PC. The location is
arbitrary but the maximum path length limitation in Windows (260 characters)
should not be exceeded.
In addition, the Xilinx tools require the path to not contain any spaces.
C:\Do Not Use Spaces In The Path\RD14V01_00.ZIP (This path has spaces.)
For the purposes of this document, it will be C:\designs\maxim\RD14V01_00\.
See Appendix A: Project Structure and Key Filenames in this document for
the project structure and key filenames.
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Figure 4. Sonoma Power and Load Connections
Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide
7. Open the Xilinx Software Development Kit (SDK) from the Windows Start
menu.
8. SDK will prompt for a workspace directory, which is the location where the
software project is located. For this example, it is:
C:\designs\maxim\RD14V01_00\RD14_ZED_V01_00\Design_Files\top.sdk\SDK\
SDK_Export
Click OK and SDK will open. The Xilinx SDK is based on an Eclipse™-based
IDE, so it will be a familiar flow for many software developers.
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