Maxim Integrated MAXQ8913 User Manual
For pricing, delivery, and
ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAXQ FAMILY USER’S GUIDE:
MAXQ8913 SUPPLEMENT
EVALUATION KIT AVAILABLE
OUTA
INA-
INA+
OUTB
INB-
INB+
OUTC
INC-
INC+
OUTD
IND-
IND+
REFA
AIN0
AIN1
DAC3
SINK1
AIN2
AIN3
AIN4
AIN5
AIN6
CURRENT SINK
MUX
8-BIT DAC
AIN2
AIN3
AIN4
AIN5
REFERENCE
REF
12-BIT
SAR DAC
TEMP
SENSOR
1.5V
AVDD
16-BIT RISC
AIN6
8-BIT
MAXQ20
CORE
AGND
10-BIT
DAC
10-BIT
DAC
CLASS
D-AMP
CONTROL
MAXQ8913
WATCHDOG
TIMER
1.8V CORE
LDO REG
POWER-ON
RESET,
BROWNOUT
MONITOR
DAC1
RIN+
RIN-
DAC2
LIN+
LIN-
SYNCIN
FAULT
SHDNR
SHDNL
REG18
DVDD
DGND
AVDD
AGND
RST
DAC4
SINK2
HFXIN
HFXOUT
CURRENT SINK
8-BIT DAC
FLASH
64KB
SRAM
4KB
UTILITY ROM
4KB
CLOCK GENERATOR
RC OSC, HF CRYSTAL OSC,
1MHz RING OSC
8-BIT
JTAG
4-WIRE
(SPI)
INTERFACE
I2C
USART
TIMER B
16 x 16
HARDWARE MULTIPLY
ACCUMULATE UNIT
PORT 0
AND
INTERRUPT
PORT 1
AND
INTERRUPT
P0.0/INT0/TCK
P0.1/INT1/TDI
P0.2/INT2/TMS
P0.3/INT3/TDO
P0.4/INT4/SSEL
P0.5/INT5/SCLK
P0.6/INT6/MOSI
P0.7/INT7/MISO
P1.0/INT8/SCL/TX
P1.1/INT9/SDA/RX
P1.2/INT10/TB0A
P1.3/INT11/TB0B
Rev 0; 8/09
MAXQ Family User’s Guide:
MAXQ8913 Supplement
TABLE OF CONTENTS
ADDENDUM TO SECTION 1: OVERVIEW 1-1
1.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
ADDENDUM TO SECTION 2: ARCHITECTURE 2-1
2.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.2 Harvard Memory Architecture
2.3 Register Space
2.4 Memory Organization
2.4.1 Register Space
2.4.2 Program Stack
2.4.3 Data SRAM
2.4.4 Program Flash
2.5 Program and Data Memory Mapping
2.6 Clock Generation
2.6.1 External High-Frequency Oscillator Circuit
2.6.2 Ring Oscillator
2.7 Interrupts
2.8 Reset Conditions
2.8.1 Power-On Reset
2.8.2 Watchdog Timer Reset
2.8.3 External Reset
2.9 Power-Management Features
2.9.1 Divide-by-256 Mode (PMM)
2.9.2 Switchback Mode
2.9.3 Stop Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
ADDENDUM TO SECTION 3: PROGRAMMING 3-1
ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS 4-1
4.1 System Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.1.1 Processor Status Flags Register (PSF, M8[04h])
4.1.2 Interrupt Mask Register (IMR, M8[06h])
4.1.3 System Control Register (SC, M8[08h])
4.1.4 Interrupt Identification Register (IIR, M8[0Bh])
4.1.5 System Clock Control Register (CKCN, M8[0Eh])
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES 5-1
ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE 6-1
6.1 GPIO and External Interrupt Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.1.1 Port 0 Direction Register (PD0, M0[10h])
6.1.2 Port 1 Direction Register (PD1, M0[11h])
ii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
TABLE OF CONTENTS (continued)
6.1.3 Port 0 Input Disable Register (PID0, M0[0Dh]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.1.4 Port 0 Output Register (PO0, M0[00h])
6.1.5 Port 1 Output Register (PO1, M0[01h])
6.1.6 Port 0 Input Register (PI0, M0[08h])
6.1.7 Port 1 Input Register (PI1, M0[09h])
6.1.8 External Interrupt Flag 0 Register (EIF0, M0[02h])
6.1.9 External Interrupt Flag 1 Register (EIF1, M0[04h])
6.1.10 External Interrupt Enable 0 Register (EIE0, M0[03h])
6.1.11 External Interrupt Enable 1 Register (EIE1, M0[05h])
6.1.12 External Interrupt Edge Select 0 Register (EIES0, M0[0Ah])
6.1.13 External Interrupt Edge Select 1 Register (EIES1, M0[0Bh])
6.2 Port Pin Examples
6.2.1 Port Pin Example 1: Driving Outputs on Port 0
6.2.2 Port Pin Example 2: Receiving Inputs on Port 0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULE 7-1
ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULE 8-1
ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULE 9-1
ADDENDUM TO SECTION 10: SERIAL I/O MODULE 10-1
10.1 Serial USART I/O Pins and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2 Serial USART Code Examples
10.2.1 Serial USART Example: Echo Characters in 10-Bit Asynchronous Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
. . . . . . . . . . . . . . . . . . . . . . . .10-1
ADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE 11-1
11.1 SPI Input/Output Pins and Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11.2 SPI Code Examples
11.2.1 SPI Example 1: Transmitting Data in Master Mode
11.2.2 SPI Example 2: Receiving Data in Slave Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
ADDENDUM TO SECTION 12: HARDWARE MULTIPLIER MODULE 12-1
12.1 Hardware Multiplier Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
12.2 Hardware Multiplier Code Examples
12.2.1 Hardware Multiplier Example: Multiply and Square/Accumulate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
ADDENDUM TO SECTION 13: 1-Wire BUS MASTER 13-1
ADDENDUM TO SECTION 14: REAL-TIME CLOCK MODULE 14-1
ADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP) 15-1
Maxim Integrated
iii
MAXQ Family User’s Guide:
MAXQ8913 Supplement
TABLE OF CONTENTS (continued)
ADDENDUM TO SECTION 16: IN-CIRCUIT DEBUG MODE 16-1
16.1 Register Read and Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
16.2 Data Memory Read Command
16.3 Data Memory Write Command
16.4 Program Stack Read Command
16.5 Read Register Map Command
ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) 17-1
17.1 JTAG Bootloader Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
17.2 Family 0 Commands (Not Password Protected)
17.3 Family 1 Commands: Load Variable Length (Password Protected)
17.4 Family 2 Commands: Dump Variable Length (Password Protected)
17.5 Family 3 Commands: CRC Variable Length (Password Protected)
17.6 Family 4 Commands: Verify Variable Length (Password Protected)
17.7 Family 5 Commands: Load and Verify Variable Length (Password Protected)
17.8 Family E Commands: Erase Fixed Length (Password Protected)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-6
. . . . . . . . . . . . . . . . . . . . . . . .17-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-7
ADDENDUM TO SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY 18-1
SECTION 19: ANALOG-TO-DIGITAL CONVERTER (SPECIFIC TO MAXQ8913) 19-1
19.1 Analog-to-Digital Converter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1
19.2 Analog-to-Digital Pins and Control Registers
19.2.1 Analog-to-Digital Converter Status Register (ADST, M4[06h])
19.2.2 ADC Conversion Sequence Address Register (ADADDR, M3[01h])
19.2.3 ADC Control Register (ADCN, M3[08h])
19.2.4 ADC Data Register (ADDATA, M3[09h])
19.2.5 ADC Data Buffer Registers (ADBUF[0] to ADBUF[15], ADDATA[00h] to ADDATA[0Fh])
19.2.6 ADC Conversion Configuration Registers (ADCFG[0] to ADCFG[7], ADDATA[10h] to ADDATA[17h]) 19-8
19.2.7 Temperature Sensor Enable Register (TEMPEN, M3[0Ch])
19.3 Analog-to-Digital Converter Code Examples
19.3.1 ADC Example 1: Single Conversion
19.3.2 ADC Example 2: Continuous Conversion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3
. . . . . . . . . . . . . . . . . . . . . . . . . . .19-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-7
. . . . . . . . . . .19-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-9
SECTION 20: DIGITAL-TO-ANALOG CONVERTERS (SPECIFIC TO MAXQ8913) 20-1
20.1 DAC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1
20.2 DAC Control Register Descriptions
20.2.1 DAC 1 Output Register (DAC1OUT, M3[02h])
20.2.2 DAC 2 Output Register (DAC2OUT, M3[03h])
20.2.3 DAC 3 Output Register (DAC3OUT, M3[04h])
20.2.4 DAC 4 Output Register (DAC4OUT, M3[05h])
20.2.5 Current Sink Control Register (ISINKCN, M3[07h])
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-3
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Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
TABLE OF CONTENTS (continued)
SECTION 21: TIMER/COUNTER B MODULE (SPECIFIC TO MAXQ8913) 21-1
21.1 Timer/Counter B Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1
21.1.1 Timer B Timer/Counter Capture/Reload Register (TBR, M2[07h])
21.1.2 Timer B Timer/Counter Compare Register (TBC, M2[0Bh])
21.1.3 Timer B Timer/Counter Control Register (TBCN, M2[06h])
21.1.4 Timer B Timer Value Register (TBV, M2[0Ah])
21.2 Timer/Counter B Operation
21.2.1 Timer B 16-Bit Timer/Counter Mode with Autoreload
21.2.2 Timer B 16-Bit Capture Mode
21.2.3 Timer B 16-Bit Up/Down Count with Autoreload Mode
21.2.4 Timer B Clock Output Mode
21.2.5 Timer B PWM/Output Control Functionality
21.2.6 16-Bit Up Count PWM/Output Control Mode
21.2.7 16-Bit Up/Down Count PWM/Output Control Mode
21.2.8 EXENB Control During PWM/Output Control Mode
21.3 Timer B Examples
21.3.1 Timer B Example: Reloading Timer Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-2
SECTION 22 : I2C BUS INTERFACE (SPECIFIC TO MAXQ8913) 22-1
22.1 I2C Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1
2
C Data Buffer Register (I2CBUF, M1[06h]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
2
22.1.1.1 I
22.1.1.2 I
2
2
2
2
2
2
C Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-7
2
2
2
2
C Data Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
2
C Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
C Status Register (I2CST, M3[01h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
C Interrupt Enable Register (I2CIE, M1[07h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3
C Control Register (I2CCN, M1[04h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4
C Clock Control Register (I2CCK, M1[0Ch]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-6
C Timeout Register (I2CTO, M1[0Dh]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-6
C Slave Address Register (I2CSLA, M1[0Eh]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-7
C Example 1: Master Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-7
C Example 2: Master Mode Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-8
C Example 3: Slave Mode Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-8
C Example 4: Slave Mode Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-9
22.2 I
22.1.1 I
22.1.2 I
22.1.3 I
22.1.4 I
22.1.5 I
22.1.6 I
22.1.7 I
2
22.2.1 I
22.2.2 I
22.2.3 I
22.2.4 I
SECTION 23: SUPPLY VOLTAGE MONITOR AND POWER CONTROL
(SPECIFIC TO MAXQ8913) 23-1
23.1 SVM and Power Control Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1
23.1.1 Power Control Register (PWCN, M0[0Ch])
23.1.2 Supply Voltage Monitor Register (SVM, M0[06h])
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2
Maxim Integrated
v
MAXQ Family User’s Guide:
MAXQ8913 Supplement
TABLE OF CONTENTS (continued)
SECTION 24: INPUT/OUTPUT AMPLIFIERS (SPECIFIC TO MAXQ8913) 24-1
24.1 Input/Output Amplifier Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1
24.2 Amplifier Control Register Descriptions
24.2.1 Amplifier Control Register (AMPCN, M3[06h])
24.2.2 Op Amp Control Register (OPMCN, M3[0Ah])
SECTION 25: UTILITY ROM (SPECIFIC TO MAXQ8913) 25-1
25.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1
25.2 In-Application Programming Functions
25.2.1 UROM_flashWrite
25.2.2 UROM_flashErasePage
25.2.3 UROM_flashEraseAll
25.3 Data Transfer Functions
25.3.1 UROM_moveDP0
25.3.2 UROM_moveDP0inc
25.3.3 UROM_moveDP0dec
25.3.4 UROM_moveDP1
25.3.5 UROM_moveDP1inc
25.3.6 UROM_moveDP1dec
25.3.7 UROM_moveBP
25.3.8 UROM_moveBPinc
25.3.9 UROM_moveBPdec
25.3.10 UROM_copyBuffer
25.4 Utility ROM Examples
25.4.1 Utility ROM Example 1: Reading Constant Word Data from Flash
25.4.2 Utility ROM Example 2: Reading Constant Byte Data from Flash (Indirect Function Call)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-7
. . . . . . . . . . .25-8
APPENDIX 1: MAXQ8913 DEVICE INCLUDE FILE FOR MAX-IDE A1-1
REVISION HISTORY R-1
vi
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
LIST OF FIGURES
Figure 2-1. MAXQ8913 System and Peripheral Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Figure 2-2. Memory Map When Executing from Program Flash Memory
Figure 2-3. Memory Map When Executing from Utility ROM
Figure 2-4. Memory Map When Executing from Data SRAM
Figure 2-5. MAXQ8913 Clock Sources
Figure 2-6. Power-On Reset Timing
Figure 2-7. External Reset Timing
Figure 19-1. ADC Block Diagram
Figure 21-1. Timer B Autoreload Mode Block Diagram
Figure 21-2. Timer B 16-Bit Capture Mode Block Diagram
Figure 21-3. Timer B 16-Bit Up/Down Count with Autoreload Mode Block Diagram
Figure 21-4. Timer B Clock Output Mode Block Diagram
Figure 21-5. Up-Count PWM/Output Control Mode Block Diagram
Figure 21-6. Timer B PWM/Output Control Mode Waveform (Count Up)
Figure 21-7. Timer B Up/Down-Count PWM/Output Control Mode Block Diagram
Figure 21-8. Timer B PWM/Output Control Mode Waveform (Up/Down Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10
Figure 25-1. Memory Map When Executing from Utility ROM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
. . . . . . . . . . . . . . . . . . . . . . . .21-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9
. . . . . . . . . . . . . . . . . . . . . . . . .21-10
Maxim Integrated
vii
MAXQ Family User’s Guide:
MAXQ8913 Supplement
LIST OF TABLES
Table 2-1. System Clock Generation and Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Table 2-2. Interrupt Sources and Control Bits
Table 2-3. System Power-Management Registers
Table 4-1. System Register Map
Table 4-2. System Register Bit Functions
Table 4-3. System Register Reset Values
Table 4-4. System Clock Modes
Table 5-1. Peripheral Register Map
Table 5-2. Peripheral Register Bit Functions
Table 5-3. Peripheral Register Bit Reset Values
Table 6-1. Port Pin Special and Alternate Functions
Table 6-2. P1[3:0] Input/Output States (in Standard Mode)
Table 6-3. P0[7:0] Input/Output States (in Standard Mode)
Table 10-1. Serial USART Input and Output Pins
Table 10-2. Serial USART Control Registers
Table 11-1. SPI Input and Output Pins
Table 11-2. SPI Control Registers
Table 12-1. Hardware Multiplier Control Registers
Table 16-1. Output from DebugReadMap Command
Table 17-1. Bootloader Status Codes
Table 17-2. Bootloader Status Flags
Table 18-1. Instruction Set Summary
Table 19-1. ADC Input and Power-Supply Pins
Table 19-2. ADC Control Registers
Table 19-3. ADC Sample Rates Using a 10MHz Crystal
Table 20-1. DAC Control Registers
Table 21-1. Type B Timer/Counter Input and Output Pins
Table 21-2. Type B Timer/Counter Control Registers
Table 21-3. Timer/Counter B Mode Summary
Table 21-4. Timer B PWM/Output Control Function
2
Table 22-1. I
Table 22-2. I
Table 24-1. Amplifier Control Registers
Table 25-1. Functions for MAXQ8913 Utility ROM
C Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1
2
C Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1
viii
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
ADDENDUM TO SECTION 1: OVERVIEW
This document is provided as a supplement to the MAXQ Family User’s Guide, covering new or modified features
specific to the MAXQ8913. This document must be used in conjunction with the MAXQ Family User’s Guide, available
on our website at www.maxim-ic.com/MAXQUG. Addenda are arranged by section number, which correspond to
sections in the MAXQ Family User’s Guide. Additions and changes, with respect to the MAXQ Family User’s Guide,
are contained in this document, and updates/additions are added when available.
M
The MAXQ8913 is a low-power, high-performance, 16-bit, RISC microcontroller based on the MAXQ
design. It is targeted specifically for dual-axis optical image stabilization (OIS) applications and includes a wide range
of peripherals including a 7-channel, 12-bit successive-approximation analog-to-digital converter (SAR ADC), two
10-bit and two 8-bit digital-to-analog converters (DACs), four op amps for ADC input conditioning, two programmable
current sinks, and support for an external D-class audio amplifier. The MAXQ8913 is uniquely suited for any application
that requires high performance and low-power operation.
1.1 References
Refer to the MAXQ Family User’s Guide for the following information:
• Description of the core architecture, instruction set, and memory mapping common to all MAXQ microcontrollers.
• Definitions and functions of the common system register set, including accumulators, data pointers, loop counters,
and general-purpose registers.
• Descriptions of common clock generation, interrupt handling, and reset/power-management modes.
• Descriptions and programming examples for common MAXQ peripherals found on the MAXQ8913 including the
serial universal synchronous/asynchronous receiver-transmitter (USART), SPIK interface, and hardware multiplier.
• Description of the test access port (TAP) and in-circuit debug interface.
• Description of the in-system programming mode.
The MAXQ8913 data sheet, which contains electrical/timing specifications and pin descriptions, is available at
www.maxim-ic.com/MAXQ8913.
Errata sheets for the MAXQ8913 and other MAXQ microcontrollers are available at www.maxim-ic.com/errata.
For more information on other MAXQ microcontrollers, development hardware and software, frequently asked questions, and software examples, visit the MAXQ page at www.maxim-ic.com/MAXQ.
architecture
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
Maxim Integrated
1-1
MAXQ Family User’s Guide:
MAXQ8913 Supplement
ADDENDUM TO SECTION 2: ARCHITECTURE
The MAXQ8913 shares the common architecture features with other members of the MAXQ microcontroller family.
Details are discussed in the following sections.
2.1 Instruction Set
This device uses the standard 16-bit MAXQ20 core instruction set as described in the MAXQ Family User’s Guide.
2.2 Harvard Memory Architecture
Program memory, data memory, and register space follow the Harvard architecture model. Each type of memory
is kept separate and is accessed by a separate bus, allowing different word lengths for different types of memory.
Registers can be either 8 bits or 16 bits in width. Program memory is 16 bits in width to accommodate the standard
MAXQ20 16-bit instruction set. Data memory is also 16 bits in width, but can be accessed in 8-bit or 16-bit modes for
maximum flexibility.
The MAXQ8913 includes a flexible memory-management unit (MMU) that allows code to be executed from either the
program flash, the utility ROM, or the internal data SRAM. Any of these three memory spaces can also be accessed in
data space at any time, with the single restriction that the physical memory area that is currently being used as program
space cannot be simultaneously read from in data space.
2.3 Register Space
The MAXQ8913 contains the standard set of MAXQ20 system registers as described in the MAXQ Family User’s Guide,
but with differences noted in this guide where they exist.
Peripheral register space (modules 0 to 3) contains registers that are used to access the following peripherals:
• 12-bit SAR ADC converter with up to seven single-ended or three differential input channels
• Four DAC output channels (two 10-bit, two 8-bit)
• Two programmable current sink outputs
• External D-amplifier support
• Internal temperature sensor (read through ADC channel 6)
• General-purpose 8-bit I/O ports (P0 and P1)
• External interrupts (up to 11)
• Programmable Type B timer/counter
• Serial USART interface
2
• I
C interface
• SPI interfaces (master/slave)
• Hardware multiplier/accumulator
The lower 8 bits of all registers in modules 0 to 3 (as well as the AP module M8) are bit addressable.
Maxim Integrated
2-1
OOh
O1h
O2h
O3h
O4h
O5h
O6h
O7h
O8h
O9h
0Ah
OBh
OCh
ODh
OEh
OFh
10h
REGISTER INDEX
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
REGISTER MODULE
M0 M1 M2 M3 M4 M8 M9
PO0
PO1
EIFO
EIEO
EIF1
EIE1
SVM
EIES0
EIES1
PWCN
PID0
PD0
PD1
SCON ADST
SBUF
SPICN0
SPIB0
I2CCN
I2CST
I2CBUF
I2CIE
SMD
SPICK0
I2CCK
I2CTO
I2CSLA
MCNT
MA
ADADDR
MB
DAC1OUT
DAC2OUT
MC2
DAC3OUT
MC1
DAC4OUT IC
MC0
TB0CN
PR
AMPCN IMR
TBOR
ISINKCN
ADCN SCPIO MC1R
ADDATAPI1 MC0R
TBOV
OPMCNSPICF0
TBOC
DACEN IIR
TEMPEN
AP A[O] IP
APC A[1]
PSF
CKCN
WDCN
MAXQ Family User’s Guide:
MAXQ8913 Supplement
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
M11
PFX
M12 M13 M14 M15
SP
IV
OFFS DP[O]
DPC
GR
LC[0] GRL
BPLC[1] DP[1]
GRS
GRH
GRXL
BP[OFFS]
RESERVED
OR
OP CODE
8-CHANNEL,
12-BIT
SAR ADC
PORT PINS
(GPIO)
DACs,
ANALOG
FUNCTIONS
Figure 2-1. MAXQ8913 System and Peripheral Register Map
2-2
INTERRUPT
CONTROL
HARDWARE
MULTIPLIER
SERIAL,
SPI, I
TIMERS
2
C
ACC
ARRAY,
CONTROL
OTHER
FUNCTIONS
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
2.4 Memory Organization
As with all MAXQ microcontrollers, the MAXQ8913 contains logically separate program and data memory spaces. All
memory is internal, and physical memory segments (other than the stack and register memories) can be accessed as
either program memory or as data memory, but not both at once.
The MAXQ8913 contains the following physical memory segments.
2.4.1 Register Space
As described in the MAXQ Family User’s Guide, register space on MAXQ microcontrollers consists of 16 register modules, each of which could contain up to 32 registers. Of these possible 16 register modules, only 11 are used on the
MAXQ8913: seven for system registers and four for peripheral registers.
2.4.2 Program Stack
The MAXQ8913 provides a 16 x 16 hardware stack to support subroutine calls and system interrupts. This stack is used
automatically by CALL/RET and PUSH/POP instructions, and can also be accessed directly through the SP register as
described in the MAXQ Family User’s Guide.
When using the in-circuit debugging features, one word of the stack must be reserved to store the return location when
execution branches into the debugging routines in the utility ROM. If in-circuit debug is not used, the entire stack is
available for application use.
2.4.3 Data SRAM
The MAXQ8913 contains up to 2048 words (4KB) of on-chip data SRAM, which can be mapped into either program or
data space. The contents of this SRAM are indeterminate after power-on reset, but are maintained during stop mode
and across non-POR resets.
When using the in-circuit debugging features, the highest 19 bytes of the SRAM must be reserved for saved state storage and working space for the debugging routines in the utility ROM. If in-circuit debug is not used, the entire SRAM
is available for application use.
2.4.4 Program Flash
The MAXQ8913 contains 32KWords (32K x 16) of flash memory, which normally serves as program memory. When
executing from the data SRAM or utility ROM, this memory is mapped to data space (as 32KWords or 64KB) and can
be used for lookup tables and similar functions.
Since program memory is mapped into data space starting at address 8000h, only half the available program memory
can be mapped into data space at one time when operating in byte-access mode. The CDA0 (code data access) bit
is used to control which half of program memory is available in data space as shown in Figure 2-3 and Figure 2-4, and
as described in the MAXQ Family User’s Guide. When operating in word-access mode, the entire 32KWord program
memory can be mapped into data space at once.
Flash memory mapped into data space can be read from directly, like any other type of data memory. However, writing
to flash memory must be done indirectly by calling the in-application functions provided by the utility ROM. See Section
25: Utility ROM for more details.
2.5 Program and Data Memory Mapping
Figures 2-2, 2-3, and 2-4 show the mapping of physical memory segments into the program and data memory space.
The mapping of memory segments into program space is always the same. The mapping of memory segments into
data space varies depending on which memory segment is currently being executed from.
In all cases, whichever memory segment is currently being executed from in program space may not be accessed in
data space.
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2-3
MAXQ Family User’s Guide:
MAXQ8913 Supplement
DATA SPACE
(BYTE MODE)
4K x 8
UTILITY ROM
4K x 8
DATA SRAM
EXECUTING FROM
PROGRAM
SPACE
2K x 16
DATA SRAM
2K x 16
UTILITY ROM
32K x 16
PROGRAM FLASH
FFFFh
A7FFh
A000h
87FFh
8000h
7FFFh
0000h
Figure 2-2. Memory Map When Executing from Program Flash Memory
DATA SPACE
(WORD MODE)
FFFFh FFFFh
8FFFh
8000h
0FFFh
0000h
2K x 16
UTILITY ROM
2K x 16
DATA SRAM
87FFh
8000h
07FFh
0000h
EXECUTING FROM
PROGRAM
SPACE
2K x 16
DATA SRAM
2K x 16
UTILITY ROM
16K x 16
PROGRAM FLASH
(PAGE 1)
16K x 16
PROGRAM FLASH
(PAGE 0)
DATA SPACE
(BYTE MODE, CDA0 = 0)
FFFFh FFFFh
A7FFh
A000h
87FFh
8000h
7FFFh
4000h
3FFFh
0000h
32K x 8
LOWER HALF
(PAGE 0) OF
PROGRAM FLASH
MEMORY
8000h
0FFFh
4K x 8
DATA SRAM
0000h
DATA SPACE
(BYTE MODE, CDA0 = 1)
32K x 8
UPPER HALF
(PAGE 1) OF
PROGRAM FLASH
MEMORY
4K x 8
DATA SRAM
FFFFh
8000h
0FFFh
0000h
DATA SPACE
(WORD MODE)
FFFFh
32K x 16
PROGRAM FLASH
8000h
07FFh
2K x 16
DATA SRAM
0000h
Figure 2-3. Memory Map When Executing from Utility ROM
2-4
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
EXECUTING FROM
PROGRAM
SPACE
2K x 16
DATA SRAM
2K x 16
UTILITY ROM
16K x 16
PROGRAM FLASH
(PAGE 1)
16K x 16
PROGRAM FLASH
(PAGE 0)
DATA SPACE
(BYTE MODE, CDA0 = 0)
FFFFh FFFFh
A7FFh
A000h
87FFh
4K x 8
UTILITY ROM
8000h
7FFFh
4000h
3FFFh
0000h
32K x 8
LOWER HALF
(PAGE 0) OF
PROGRAM FLASH
MEMORY
8000h
7FFFh
0000h
DATA SPACE
(BYTE MODE, CDA0 = 1)
4K x 8
UTILITY ROM
32K x 8
UPPER HALF
(PAGE 1) OF
PROGRAM FLASH
MEMORY
FFFFh
8000h
7FFFh
0000h
DATA SPACE
(WORD MODE)
FFFFh
87FFh8FFFh8FFFh
2K x 8
UTILITY ROM
8000h
7FFFh
32K x 16
PROGRAM FLASH
0000h
Figure 2-4. Memory Map When Executing from Data SRAM
2.6 Clock Generation
All functional modules in the MAXQ8913 are synchronized to a single system clock. This system clock can be generated from one of the following clock sources:
• External high-frequency clock
• Internal high-frequency oscillator using external crystal or resonator circuit
• Internal 1MHz ring oscillator
The MAXQ8913 does not support an external RC relaxation oscillator circuit or the 32kHz crystal input described in
the MAXQ Family User’s Guide.
The following registers and bits are used to control clock generation and selection. For more information, see the register descriptions in this guide and in the MAXQ Family User’s Guide.
2.6.1 External High-Frequency Oscillator Circuit
The high-frequency oscillator operates as described in Section 2.7: Clock Generation of the MAXQ Family User’s
Guide. If used, the external crystal or resonator circuit for this oscillator should be connected between the HFXIN and
HFXOUT pins.
The high-frequency oscillator can be disabled by setting HFXD (PWCN.0) to 1; this is only allowed if the high-frequency
oscillator is not currently being used as the clock source (RGMD and RGSL must both equal 1). In this configuration,
an external clock can be used to directly drive HFXIN; refer to the MAXQ8913 data sheet for more details.
Maxim Integrated
2-5
MAXQ Family User’s Guide:
MAXQ8913 Supplement
POWER-ON
RESET
STOP
CRYSTAL KLL
HF
CRYSTAL
1MHz
INTERNAL
RING OSC
ENABLE
RESET XDOG COUNT
XDOG
STARTUP
TIMER
CLK INPUT
MUX
GLITCH-FREE
XDOG DONE
MAXQ8913
CLOCK
DIVIDER
GLITCH-FREE
DIV 1
DIV 2
SELECTOR
MUX
DIV 4
DIV 8
PMM
DEFAULT
RING SELECT
RESET DOG
WATCHDOG
TIMER
ENABLE
CLOCK
GENERATION
RWT
RESET
WATCHDOG RESET
WATCHDOG INTERRUPT
SYSTEM CLOCK
SWB
SWITCHBACK SOURCES
RESET
STOP
STOP
POWER-ON
RESET
INPUT
CRYSTAL
MONITOR
ENABLE
RGMD
POWER-ON RESET
XDOG DONE
RGSL
Figure 2-5. MAXQ8913 Clock Sources
2.6.2 Ring Oscillator
The MAXQ8913 contains an internal ring oscillator that can optionally be used as a system clock. The ring oscillator
operates at a frequency of approximately 1MHz (refer to the MAXQ8913 data sheet for details).
On power-on reset, the ring oscillator is automatically enabled as the system clock source while the high-frequency
oscillator warms up. Once the warmup count for the high-frequency oscillator has completed, the clock source switches to the high-frequency oscillator automatically. If no external crystal or resonator circuit is provided at HFXIN, the
switchover never occurs, and the clock runs from the ring oscillator indefinitely.
To explicitly select the ring oscillator as the system clock source, the RGSL bit (CKCN.6) must be set to 1. Setting this
bit switches over the system clock source to the ring oscillator following a 10-cycle delay of the 1MHz ring clock. The
RGMD (CKCN.5) bit indicates the current system clock source. If the ring oscillator is currently providing the system
clock, RGMD reads as 1; otherwise, RGMD reads as 0.
2-6
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
Table 2-1. System Clock Generation and Control Registers
REGISTER ADDRESS BIT(S) FUNCTION
000: System clock = high-frequency clock divided by 1.
001: System clock = high-frequency clock divided by 2.
010: System clock = high-frequency clock divided by 4.
011: System clock = high-frequency clock divided by 8.
1xx: System clock = high-frequency clock/256.
CKCN M8[0Eh]
[2:0]—PMME,
CD[1:0]
CKCN M8[0Eh] 5—RGMD
CKCN M8[0Eh] 6—RGSL
PWCN M0[0Ch] 0—HFXD
0: System clock is being provided by an external source.
1: System clock is being provided by the ring oscillator.
0: Selects an external source for system clock generation.
1: Selects the ring oscillator for system clock generation.
0: High-frequency oscillator operates normally (default).
1: Disables the high-frequency oscillator, allowing an external clock to be
provided at HFXIN.
Because the RGSL bit is cleared by power-on reset only, if this bit is set before entering stop mode, the ring oscillator
is still used as the system clock source when stop mode is exited. In this case, a 10-ring oscillator cycle warmup delay
is required when exiting stop mode before execution resumes using the ring oscillator as the system clock source.
When the system clock source is switched back from the ring oscillator to the high-frequency oscillator by clearing
RGSL to 0, the ring oscillator is still used as the system clock source until the warmup period has completed for the
high-frequency oscillator. This is reflected by the value of the RGMD bit, which remains at 1 until the warmup for the
high-frequency oscillator has completed and the clock switches over, at which point RGMD switches to 0.
2.7 Interrupts
In general, interrupt handling on the MAXQ8913 operates as described in the MAXQ Family User’s Guide. All interrupt
sources have the same priority, and all interrupts cause program execution to branch to the location specified by the
Interrupt Vector (IV) register, which defaults to 0000h.
Table 2-2 lists all possible interrupt sources for the MAXQ8913, along with their corresponding module interrupt enable
bits, local interrupt enable bits, and interrupt flags.
• Each module interrupt enable bit, when cleared to 0, blocks interrupts originating in that module from being acknowledged. When the module interrupt enable bit is set to 1, interrupts from that module are acknowledged (unless all
interrupts have been disabled globally).
• Each local interrupt enable bit, when cleared to 0, disables the corresponding interrupt. When the local interrupt-
enable bit is set to 1, the interrupt is triggered whenever its interrupt flag is set to 1 by hardware or by software.
• Each interrupt flag bit, when set to 1, causes its corresponding interrupt to trigger. Interrupt flag bits are typically set
by hardware and must be cleared by software (generally in the interrupt handler routine).
Note that for an interrupt to fire, the following five conditions must exist:
• Interrupts must be enabled globally by setting IGE (IC.0) to 1.
• The module interrupt enable bit for the interrupt source’s module must be set to 1.
• The local interrupt enable bit for the specific interrupt source must be set to 1.
• The interrupt flag for the interrupt source must be set to 1. Typically, this is done by hardware when the condition
that requires interrupt service occurs.
• The interrupt-in-service (INS) bit must be cleared to 0. This bit is set automatically upon vectoring to the interrupt
handler (IV) address and cleared automatically upon exit (RETI/POPI), so the only reason to clear this bit manually
(inside the interrupt handler routine) is to allow nested interrupt handling.
Maxim Integrated
2-7
MAXQ Family User’s Guide:
MAXQ8913 Supplement
Table 2-2. Interrupt Sources and Control Bits
INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG
Watchdog Interrupt IMS (IMR.7) EWDI (WDCN.6) WDIF (WDCN.3)
External Interrupt 0 (P0.0) IM0 (IMR.0) EX0 (EIE0.0) IE0 (EIF0.0)
External Interrupt 1 (P0.1) IM0 (IMR.0) EX1 (EIE0.1) IE1 (EIF0.1)
External Interrupt 2 (P0.2) IM0 (IMR.0) EX2 (EIE0.2) IE2 (EIF0.2)
External Interrupt 3 (P0.3) IM0 (IMR.0) EX3 (EIE0.3) IE3 (EIF0.3)
External Interrupt 4 (P0.4) IM0 (IMR.0) EX4 (EIE0.4) IE4 (EIF0.4)
External Interrupt 5 (P0.5) IM0 (IMR.0) EX5 (EIE0.5) IE5 (EIF0.5)
External Interrupt 6 (P0.6) IM0 (IMR.0) EX6 (EIE0.6) IE6 (EIF0.6)
External Interrupt 7 (P0.7) IM0 (IMR.0) EX7 (EIE0.7) IE7 (EIF0.7)
External Interrupt 8 (P1.0) IM0 (IMR.0) EX8 (EIE1.0) IE8 (EIF1.0)
External Interrupt 9 (P1.1) IM0 (IMR.0) EX9 (EIE1.1) IE9 (EIF1.1)
External Interrupt 10 (P1.2) IM0 (IMR.0) EX10 (EIE1.2) IE10 (EIF1.2)
External Interrupt 11 (P1.3) IM0 (IMR.0) EX11 (EIE1.3) IE11 (EIF1.3)
Supply Voltage Monitor Interrupt IM0 (IMR.0) SVMIE (SVM.2) SVMI (SVM.3)
Serial Port Receive IM1 (IMR.1) ESI (SMD.2) RI (SCON.0)
Serial Port Transmit IM1 (IMR.1) ESI (SMD.2) TI (SCON.1)
SPI Mode Fault Interrupt IM1 (IMR.1) ESPII (SPICF.7) MODF (SPICN.3)
SPI Write Collision Interrupt IM1 (IMR.1) ESPII (SPICF.7) WCOL (SPICN.4)
SPI Receive Overrun Interrupt IM1 (IMR.1) ESPII (SPICF.7) ROVR (SPICN.5)
SPI Transfer Complete Interrupt IM1 (IMR.1) ESPII (SPICF.7) SPIC (SPICN.6)
2
C START Condition Interrupt IM1 (IMR.1) I2CSRI (I2CST.0) I2CSRIE (I2CIE.0)
I
2
C Transmit Complete Interrupt IM1 (IMR.1) I2CTXI (I2CST.1) I2CTXIE (I2CIE.1)
I
2
C Receive Ready Interrupt IM1 (IMR.1) I2CRXI (I2CST.2) I2CRXIE (I2CIE.2)
I
2
C Clock Stretch Interrupt IM1 (IMR.1) I2CSTRI (I2CST.3) I2CSTRIE (I2CIE.3)
I
2
C Timeout Interrupt IM1 (IMR.1) I2CTOI (I2CST.4) I2CTOIE (I2CIE.4)
I
2
C Slave Address Match Interrupt IM1 (IMR.1) I2CAMI (I2CST.5) I2CAMIE (I2CIE.5)
I
2
C Arbitration Loss Interrupt IM1 (IMR.1) I2CALI (I2CST.6) I2CALIE (I2CIE.6)
I
2
C NACK Interrupt IM1 (IMR.1) I2CNACKI (I2CST.7) I2CNACKIE (I2CIE.7)
I
2
C General Call Address Interrupt IM1 (IMR.1) I2CGCI (I2CST.8) I2CGCIE (I2CIE.8)
I
2
C Receiver Overrun Interrupt IM1 (IMR.1) I2CROI (I2CST.9) I2CROIE (I2CIE.9)
I
2
C STOP Condition Interrupt IM1 (IMR.1) I2CSPI (I2CST.11) I2CSPIE (I2CIE.11)
I
Type B Timer—External Trigger IM2 (IMR.2) EXFB (TBCN.6) ETB (TBCN.1)
Type B Timer—Overflow IM2 (IMR.2) TFB (TBCN.7) ETB (TBCN.1)
ADC Data Available Interrupt IM3 (IMR.3) ADDAIE (ADCN.5) ADDAI (ADST.5)
Amplifier Interrupt IM3 (IMR.3) AMPIE (AMPCN.4) AMPIF (AMPCN.5)
2.8 Reset Conditions
There are four possible reset sources for the MAXQ8913. While in the reset state, the enabled system clock oscillator
continues running, but no code execution occurs. Once the reset condition has been removed or has completed, code
execution resumes at address 8000h for all reset types.
2-8
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
SUPPLY AT
V
DVDD
V
RST
T1
1MHz
RING OSCILLATOR
INTERNAL
RESET
RGMD
Figure 2-6. Power-On Reset Timing
T1 = STARTUP TIME PLUS 10 RING OSCILLATOR CYCLES
T2
T2 = 8192 EXTERNAL OSCILLATOR CYCLES
2.8.1 Power-On Reset
When power is first applied to the MAXQ8913, or when the supply voltage at DVDD drops below the V
processor is held in a power-on reset state. See Figure 2-6. For the MAXQ8913 to exit power-on reset, the following
two conditions must apply:
• The supply voltage at DVDD is above the power-on reset level V
RST.
• The ring oscillator has completed a 10-cycle delay.
level, the
RST
2.8.2 Watchdog Timer Reset
The watchdog timer on the MAXQ8913 functions as described in the MAXQ Family User’s Guide.
2.8.3 External Reset
External reset through the RST input is a synchronous reset source. After the external reset low has been removed and
sampled, execution resumes following a delay of four clock cycles, as shown in Figure 2-7.
Maxim Integrated
2-9
CLOCK
RST
RESET SAMPLING
INTERNAL RESET
Figure 2-7. External Reset Timing
MAXQ Family User’s Guide:
MAXQ8913 Supplement
FIRST
INSTRUCTION
FETCH
2.9 Power-Management Features
The MAXQ8913 provides the following features to assist in power management:
• Divide-by-256 (PMM) mode to reduce current consumption.
• Switchback mode to exit PMM mode automatically when rapid processing is required.
• Ultra-low-power stop mode.
• Selective regulator and brownout detection disable during stop mode.
Table 2-3 shows the system registers and bits used to control power-management features. For more information, see
the register descriptions in this document and in the MAXQ Family User’s Guide.
Table 2-3. System Power-Management Registers
REGISTER ADDRESS BIT FUNCTION
00: System clock = selected clock source divided by 1.
CKCN M8[0Eh] [1:0]—CD[1:0]
CKCN M8[0Eh] 2—PMME
CKCN M8[0Eh] 3—SWB
CKCN M8[0Eh] 4—STOP When set to 1, causes the processor to enter stop mode.
PWCN M0[0Ch] 0—HFXD
PWCN M0[0Ch] 6—REGEN
PWCN M0[0Ch] 7—BOD
01: System clock = selected clock source divided by 2.
10: System clock = selected clock source divided by 4.
11: System clock = selected clock source divided by 8.
0: System clock is determined by the settings of CD[1:0].
1: System clock = selected clock source divided by 256.
When set to 1, enables automatic switchback from PMM (divide-by-256
mode) to normal clock-divide mode under certain conditions.
0: Enables the high-frequency oscillator.
1: Disables the high-frequency oscillator, allowing an external clock to be
provided at HFXIN.
0: Internal regulator is shut down during stop mode.
1: Internal regulator remains powered on during stop mode.
0: Brownout detection remains enabled during stop mode.
1: Brownout detection is enabled during stop mode.
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Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
2.9.1 Divide-by-256 Mode (PMM)
In this power-management mode, all operations continue as normal, but at a reduced clock rate (the selected clock
source divided by 256).
This power-management mode is entered by setting the PMME bit (CKCN.2) to 1 and CD[1:0] to 0. When PMM mode
is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation reverts to divideby-1 mode.
2.9.2 Switchback Mode
As described in the MAXQ Family User’s Guide, switchback mode is used to provide an automatic exit from powermanagement mode when a higher clock rate is required to respond to I/O, such as USART activity, SPI activity, or an
external interrupt.
Switchback mode is enabled when the SWB (CKCN.3) bit is set to 1 and the PMME (CKCN.2) bit is set to 1 (the system
is in the PMM mode). If switchback is enabled, the PMME bit is cleared (causing the system to exit power-management
mode) when any of the following conditions occur:
• An external interrupt condition occurs on an INTn pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the RX pin and the USART is enabled to receive data.
• The SBUF register is written to transmit a byte over the USART.
• The SPIB register is written to transmit a byte with the SPI interface enabled in master mode.
• The SSEL signal is asserted low with the SPI interface enabled in slave mode.
• A START condition occurs on the I
• The supply voltage drops below the supply voltage monitor (SVM) threshold, and the SVM interrupt is triggered.
• An ADC conversion is initiated by setting ADCONV to 1.
• Active debug mode is entered either by a breakpoint match or direct issuance of the debug command from back-
ground mode.
As described in the MAXQ Family User’s Guide, if any of these conditions is true (a switchback source is active) and
the SWB bit has been set, the PMME bit cannot be set to enter power-management mode.
2
C bus and the I2C START interrupt is triggered.
2.9.3 Stop Mode
Stop mode disables all clocked circuits within the MAXQ8913 and halts the processor completely. All on-chip clocks,
timers, serial ports, and other peripherals are stopped, and no code execution occurs. Once in stop mode, the
MAXQ8913 is in a near-static state, with power consumption determined largely by leakage currents.
Stop mode is invoked by setting the STOP bit to 1. The MAXQ8913 enters stop mode immediately when the STOP bit
is set. Entering stop mode does not affect the setting of the clock control bits; this allows the system to return to its
original operating frequency following stop mode removal.
The processor exits stop mode if any of the following conditions occur. In order to exit stop mode by means of an interrupt, the interrupt must be enabled globally, by module, and locally prior to entering stop mode.
• External reset (from the RST pin)
• Power-on/brownout reset
• External interrupt
2
• I
C START interrupt
• Supply voltage monitor interrupt (SVMSTOP must be set to 1)
Note that exiting stop mode through external reset or power-on reset causes the processor to undergo a normal reset
cycle, as opposed to resuming execution at the point at which it entered stop mode. Exiting stop mode by means of an
interrupt causes the processor to vector to the interrupt handler routine at IV. Following the completion of the interrupt
handler, execution resumes at the instruction following the one that caused the entry into stop mode.
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MAXQ Family User’s Guide:
MAXQ8913 Supplement
When the processor exits stop mode, program execution resumes using the previously selected clock source following a 10-ring oscillator cycle delay plus any additional delay time required to enable the internal regulator and other
circuitry (refer to the IC data sheet for details).
• If RGSL = 1, the processor continues running from the ring oscillator indefinitely.
• If RGSL = 0, the processor continues running from the ring oscillator until the high-frequency clock source completes
its warmup count (8192 cycles for external crystal oscillator, 10 cycles for external clock input), at which point it
switches over to the high-frequency clock automatically.
2-12
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
ADDENDUM TO SECTION 3: PROGRAMMING
Refer to Section 3: Programming of the MAXQ Family User’s Guide for examples of general program operations involv-
ing the MAXQ core. The MAXQ8913 contains the MAXQ20 (16-bit accumulator version) of the MAXQ core.
Maxim Integrated
3-1
MAXQ Family User’s Guide:
MAXQ8913 Supplement
ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS
Refer to Section 4: System Register Descriptions of the MAXQ Family User’s Guide for functional descriptions of the
registers and bits in Table 4-1.
Table 4-1. System Register Map
CYCLES
TO
READ
1 1 00h AP
1 1 01h APC
1 1 02h —
1 1 03h —
1 1 04h PSF
1 1 05h IC
1 1 06h IMR
1 1 07h —
1 2 08h SC
1 2 09h —
1 2 0Ah —
1 2 0Bh IIR
1 2 0Ch —
1 2 0Dh —
1 2 0Eh CKCN
1 2 0Fh WDCN
Note: Register names that appear in italics indicate read-only registers. Register names that appear in bold indicate 16-bit registers. All other registers are 8 bits in width.
CYCLES
TO
WRITE
REGISTER
INDEX
AP
(M8)
A
(M9)
A[0] PFX[0] IP
A[1] PFX[1]
A[2] PFX[2]
A[3] PFX[3]
A[4] PFX[4]
A[5] PFX[5]
A[6] PFX[6]
A[7] PFX[7]
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
PFX
(M11)
— — —
— — — GRH —
— — —
— — —
— — — — —
— — — — —
— — — — —
— — — — —
(M12)
IP
—
—
— — OFFS
— —
— —
—
—
SP
(M13)
— — —
SP
IV
LC[0]
LC[1] BP DP[1]
DPC
(M14)
— —
— —
DPC
GR
GRL —
GRS
GRXL
BP[OFFS]
DP
(M15)
DP[0]
—
—
—
—
—
Table 4-2. System Register Bit Functions
REG
AP — — — — AP (4 bits)
APC CLR IDS — — — MOD2 MOD1 MOD0
PSF Z S — GPF1 GPF0 OV C E
IC — — — — — — INS IGE
IMR IMS — — — IM3 IM2 IM1 IM0
SC TAP — — CDA0 — — PWL —
IIR IIS — — — II3 II2 II1 II0
CKCN — RGSL RGMD STOP SWB PMME CD1 CD0
WDCN POR EWDI WD1 WD0 WDIF WTRF EWT RWT
A[0:15] A[0:15] (16 bits)
PFX PFX (16 bits)
IP IP (16 bits)
SP — — — — — — — — — — — — SP (4 bits)
IV IV (16 bits)
LC[0] LC[0] (16 bits)
LC[1] LC[1] (16 bits)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT
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4-1
MAXQ Family User’s Guide:
MAXQ8913 Supplement
Table 4-2. System Register Bit Functions (continued)
REG
OFFS OFFS (8 bits)
DPC — — — — — — — — — — — WBS2 WBS1 WBS0 SDPS1 SDPS0
GR GR (16 bits)
GRL GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0
BP BP (16 bits)
GRS GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8
GRH GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8
GRXL GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0
BP[OFFS] BP[OFFS] (16 bits)
DP[0] DP[0] (16 bits)
DP[1] DP[1] (16 bits)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 4-3. System Register Reset Values
REG
AP 0 0 0 0 0 0 0 0
APC 0 0 0 0 0 0 0 0
PSF 0 0 0 0 0 0 0 0
IC 0 0 0 0 0 0 0 0
IMR 0 0 0 0 0 0 0 0
SC 1 0 0 0 0 0 s 0
IIR 0 0 0 0 0 0 0 0
CKCN 1 s s 0 0 0 0 0
WDCN s s 0 0 0 s s 0
A[0:15] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PFX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IP
SP 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
IV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LC[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LC[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFS 0 0 0 0 0 0 0 0
DPC 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
GR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GRL 0 0 0 0 0 0
BP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GRH 0 0 0 0 0 0 0 0
GRXL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BP[OFFS] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DP[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DP[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: Bits marked as “s” have special behavior upon reset; see the register descriptions for details.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT
BIT
0 0
4-2
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
4.1 System Register Descriptions
This section details the functionality of any system register contained in the MAXQ8913 that operates differently from its
description in the MAXQ Family User’s Guide. Addresses for all system and peripheral registers are given as “Mx[yy],”
where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Fields
in the bit definition tables are defined as follows:
• Name: Symbolic names of bits or bit fields in this register.
• Reset: The value of each bit in this register following a standard reset. If this field reads “unchanged,” the given bit
is unaffected by standard reset. If this field reads “s,” the given bit does not have a fixed 0 or 1 reset value because
its value is determined by another internal state or external condition.
• POR: If present this field defines the value of each bit in this register following a power-on reset (as opposed to a
standard reset). Some bits are unaffected by standard resets and are set/cleared by POR only.
• Access: Bits can be read-only (r) or read/write (rw). Any special restrictions or conditions that could apply when
reading or writing this bit are detailed in the bit description.
4.1.1 Processor Status Flags Register (PSF, M8[04h])
Bit #
Name Z S — GPF1 GPF0 OV C E
Reset 0 0 0 0 0 0 0 0
Access r r r rw rw rw rw rw
7 6 5 4 3 2 1 0
This register operates as described in the MAXQ Family User’s Guide, with the exception that the overflow bit (OV)
can be written by software.
4.1.2 Interrupt Mask Register (IMR, M8[06h])
Bit #
Name IMS — — — IM3 IM2 IM1 IM0
Reset 0 0 0 0 0 0 0 0
Access rw r r r rw rw rw rw
The first four bits in this register are interrupt mask bits for modules 0 to 3, one bit per module. The eighth bit, IMS,
serves as a mask for any system module interrupt sources. Setting a mask bit allows the enabled interrupt sources for
the associated module or system (with IMS) to generate interrupt requests. Clearing the mask bit effectively disables
all interrupt sources associated with that module or, in the case of IMS, all system interrupt sources. The IMR register
is intended to facilitate user-definable interrupt prioritization.
Bit 7: System Module Interrupt Mask (IMS)
Bits 6:4: Reserved
Bit 3: Module 3 Interrupt Mask (IM3)
Bit 2: Module 2 Interrupt Mask (IM2)
Bit 1: Module 1 Interrupt Mask (IM1)
Bit 0: Module 0 Interrupt Mask (IM0)
7 6 5 4 3 2 1 0
Maxim Integrated
4-3
4.1.3 System Control Register (SC, M8[08h])
MAXQ Family User’s Guide:
MAXQ8913 Supplement
Bit #
Name TAP — — CDA0 — — PWL —
Reset 1 0 0 0 0 0 Unchanged 0
POR 1 0 0 0 0 0 1 0
Access rw r r r r r rw r
Bit 7: Test Access (Debug) Port Enable (TAP)
0 = Debug port functions are disabled, and P0.0 to P0.3 can be used as general-purpose I/O pins.
1 = Port pins P0.0 to P0.3 are enabled to act as debug port (JTAG) inputs and outputs.
Bits 6:5, 3:2, 0: Reserved
Bit 4: Code Data Access (CDA0). Setting this bit to 0 or 1 enables access to either the low or high page of program
memory in data space when accessing data in byte mode, as shown in Figure 2-3 and Figure 2-4. When accessing
data space in word mode, the setting of this bit has no effect.
Bit 1: Password Lock (PWL). This bit defaults to 1 on power-on reset only. When this bit is 1, it requires a 32-byte
password to be matched with the password in the program space (words 10h to 1Fh) before allowing access to the
ROM loader’s utilities for read/write of program memory and debug functions. Clearing this bit to 0 disables the password protection to the ROM loader.
7 6 5 4 3 2 1 0
4.1.4 Interrupt Identification Register (IIR, M8[0Bh])
Bit #
Name IIS — — — II3 II2 II1 II0
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
7 6 5 4 3 2 1 0
The first three bits in this register indicate interrupts pending in modules 0 to 3, one bit per module. The eighth bit, IIS,
indicates a pending system interrupt (from the watchdog timer or other system function). The interrupt pending flags
are set only for enabled interrupt sources waiting for service. The interrupt pending flag is cleared when the pending
interrupt source(s) within that module are disabled or when the interrupt flag(s) are cleared by software.
Bit 7: Interrupt Pending Flag for System Modules (IIS)
Bits 6:4: Reserved
Bit 3: Interrupt Pending Flag for Module 3 (II3)
Bit 2: Interrupt Pending Flag for Module 2 (II2)
Bit 1: Interrupt Pending Flag for Module 1 (II1)
Bit 0: Interrupt Pending Flag for Module 0 (II0)
4-4
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
4.1.5 System Clock Control Register (CKCN, M8[0Eh])
Bit #
Name — RGSL RGMD STOP SWB PMME CD1 CD0
Reset 1 0 0 0 0 0 0 0
Access r rw r rw rw rw rw* rw*
*Unrestricted read access. This bit can only be modified when PMME = 0.
The CKCN register bit settings determine the system clock source and clock divider as described in Table 4-4.
Bit 7: Reserved
Bit 6: Ring Oscillator Select (RGSL)
0 = Selects the high-frequency clock source (external crystal/resonator or external clock input) as the system clock source.
1 = Selects the ring oscillator as the system clock source.
Bit 5: Ring Oscillator Mode (RGMD). This read-only status bit indicates the clock source that is currently being used.
0 = The high-frequency clock (external crystal or external clock input) is currently being used as the system clock
source, because the ring oscillator is not selected (RGSL = 0).
1 = The ring oscillator is currently being used as the system clock source. This is either because it is selected as the
clock source (RGSL = 1), or because the high-frequency clock source is in the process of warming up.
Bit 4: Stop-Mode Select (STOP). Setting this bit to 1 causes the processor to enter stop mode. This does not change
the currently selected clock-divide ratio.
Bit 3: Switchback Enable (SWB). Setting this bit to 1 enables switchback mode. If power-management mode (divide
by 256) is active and switchback is enabled, the PMME bit is cleared to 0 when any of the following conditions occur.
• An external interrupt is generated based on an edge detect.
• The serial port is enabled to receive data and detects a low condition on its data receive pin.
• The serial port has a byte written to its buffer register by software.
• The SPI interface is enabled in master mode, and the SPIB register is written by software.
• The SPI interface is enabled is slave mode, and an external master drives the SSEL line low.
• A START condition occurs on the I
• The power supply drops below the SVM threshold, causing an SVM interrupt to be generated.
• An ADC conversion is initiated by software by setting the ADCONV bit to 1.
• Debug mode is entered through command entry or a breakpoint match.
Triggering a switchback condition only clears the PMME bit; the settings of CD0 and CD1 remain the same. When
power-management mode is active, the SWB bit cannot be set to 1 as long as any of the above conditions are true.
Bit 2: Power-Management Mode Enable (PMME)
Bits 1:0: Clock Divide 1:0 (CD[1:0]). These three bits control the divide ratio or enable power-management mode for
the system clock as shown in Table 4-4. CD0 and CD1 can always be read, and they can be written as long as PMME
= 0.
Setting the PMME bit to 1 activates PMM mode. While PMME is set to 1, CD0 and CD1 cannot be changed; their values
determine the clock-divide ratio that is used when the processor exits power-management mode.
7 6 5 4 3 2 1 0
2
C bus, causing an I2C START interrupt to be generated.
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4-5
MAXQ Family User’s Guide:
MAXQ8913 Supplement
Table 4-4. System Clock Modes
RGMD SWB PMME CD1 CD0 SYSTEM CLOCK SWITCHBACK
0 0 0 0 0 High-frequency clock/1 —
0 0 0 0 1 High-frequency clock/2 —
0 0 0 1 0 High-frequency clock/4 —
0 0 0 1 1 High-frequency clock/8 —
0 0 1 X X High-frequency clock/256 Not Active
0 1 1 X X High-frequency clock/256 Active
1 0 0 0 0 Ring oscillator clock/1 —
1 0 0 0 1 Ring oscillator clock/2 —
1 0 0 1 0 Ring oscillator clock/4 —
1 0 0 1 1 Ring oscillator clock/8 —
1 0 1 X X Ring oscillator clock/256 Not Active
1 1 1 X X Ring oscillator clock/256 Active
4-6
Maxim Integrated
MAXQ Family User’s Guide:
MAXQ8913 Supplement
ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES
Table 5-1. Peripheral Register Map
CYCLES
TO READ
1 1 00h PO0 SCON MCNT
1 1 01h PO1 SBUF
1 1 02h EIF0 SPICN
1 1 03h EIE0
1 1 04h EIF1
1 1 05h EIE1
1 1 06h
1 1 07h —
1 2 08h PI0 SMD
1 2 09h PI1
1 2 0Ah EIES0 SPICF
1 2 0Bh EIES1 SPICK
1 2 0Ch PWCN
1 2 0Dh PID0 I2CTO
1 2 0Eh —
1 2 0Fh — — — — — —
2 2 10h PD0 — — — — —
2 2 11h PD1 — — — — —
2 2 12h
2 2 13h
2 2 14h
2 2 15h
2 2 16h
2 2 17h
2 2 18h
2 2 19h
2 2 1Ah
2 2 1Bh
2 2 1Ch
2 2 1Dh
2 2 1Eh
2 2 1Fh
Note: Register names that appear in italics indicate registers in which all bits are read-only. Register names that appear in bold
indicate 16-bit registers. All other registers are 8 bits in width.
CYCLES
TO WRITE
REGISTER
INDEX
M0 M1 M2 M3 M4 M5
MA ADADDR
MB DAC1OUT
SPIB MC2 DAC2OUT
I2CCN MC1
I2CST MC0
SVM I2CBUF TBCN
I2CIE TBR ISINKCN
MC1R ADCN
PR MC0R ADDATA
TBV
TBC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CCK
I2CSLA
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— TEMPEN — —
— — — —
— — — —
ADST
DAC3OUT — —
DAC4OUT — —
AMPCN — —
OPMCN — —
DACEN — —
— —
— —
— —
— —
— —
— —
— —
Maxim Integrated
5-1
MAXQ Family User’s Guide:
MAXQ8913 Supplement
Table 5-2. Peripheral Register Bit Functions
I2C
GCEN
I2C
GCI
I2C
GCIE
BIT
SVM
SVMI SVMIE
STOP
STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN
I2C
I2C
I2C
I2C
I2CEAI2C
STOP
START
I2C
NACKI
I2C
NACKIE
I2C
ALI
I2C
ALIE
ACK
I2C
AMI
I2C
AMIE
STRS
I2C
TOI
I2C
TOIE
MODE
I2C
STRI
I2C
STRIE
RXIE
— CHR CKPHA CKPOL
I2C
RXI
I2C
SVM
RDY
I2C
MST
I2C
TXI
I2C
TXIE
SVMEN
SRIE
REG
PO0 PO0 (8 bits)
PO1 — — — — PO1 (4 bits)
EIF0 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
EIE0 EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0
EIF1 — — — — IE11 IE10 IE9 IE8
EIE1 — — — — EX11 EX10 EX9 EX8
SVM — — — — SVTH (4 bits) — — —
PI0 PI0 (8 bits)
PI1 — — — — PI1 (4 bits)
EIES0 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0
EIES1 — — — — IT11 IT10 IT9 IT8
PWCN BOD REGEN — — — — — HFXD
PID0 PID0 (8 bits)
PD0 PD0 (8 bits)
PD1 — — — PD1 (5 bits)
SCON SM0/FE SM1 SM2 REN TB8 RB8 TI RI
SBUF SBUF (8 bits)
SPICN
SPIB SPIB (16 bits)
I2CCN
I2CST
I2CBUF — — — — — — I2CBUF (10 bits)
I2CIE — — — —
SMD — — — — — ESI SMOD FEDE
PR PR (16 bits)
SPICF ESPII SAS — —
SPICK SPICK (8 bits)
I2CCK I2CCKH (8 bits) I2CCKL (8 bits)
I2CTO I2CTO (8 bits)
I2CSLA — — — — — — I2CSLA (10 bits)
MCNT OF MCW CLD SQU OPCS MSUB MMAC SUS
MA MA (16 bits)
MB MB (16 bits)
MC2 MC2 (16 bits)
MC1 MC1 (16 bits)
MC0 MC0 (16 bits)
TBCN C/TB — — TBCS TBCR TBPS2 TBPS1 TBPS0 TFB EXFB TBOE DCEN EXENB TRB ETB CP/RLB
TBR TB0R (16 bits)
MC1R MC1R (16 bits)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C
RST
I2C
BUS
— — — — —
I2C
BUSY
— —
I2C
SPI
I2C
SPIE
SCL
I2C
—
I2C
STREN
I2C
ROI
I2C
ROIE
I2C
EN
I2C
SRI
I2C
5-2
Maxim Integrated
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