Maxim Integrated MAXQ2000 User Manual
For pricing, delivery, and
ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Rev 3; 6/07
ADDENDUM TO SECTION 1: OVERVIEW 7
References 7
ADDENDUM TO SECTION 2: ARCHITECTURE 7
Instruction Set 7
Harvard Memory Architecture 7
Register Space 7
Memory Organization 9
Register Space 9
Program Stack 9
Data SRAM 9
Program Flash 9
Program and Data Memory Mapping 9
Clock Generation 11
External High-Frequency Oscillator Circuit or Clock 12
Internal Ring Oscillator 12
External 32kHz Crystal Oscillator Circuit or Clock 13
Interrupts 13
Reset Conditions 16
Power-On Reset 16
Watchdog Timer Reset 16
External Reset 16
17 x 8 DISPLAY
This document is provided as a supplement to the MAXQ Family User’s Guide, covering new or modified features specific to the MAXQ2000. This document
must be used in conjunction with the MAXQ Family User’s Guide, available from Dallas Semiconductor. Addenda are arranged by section number, which
correspond to sections in the MAXQ Family User’s Guide. Additions and changes, with respect to the MAXQ Family User’s Guide, are contained in this document. This document is a work in progress, and updates/additions are added when available.
RAM
132-SEGMENT
LCD CONTROLLER/
DRIVER
RTC
1-WIRE MASTER
TIMER/PWM
JTAG DEBUG
16-BIT MAXQ™
RISC CPU
16 x 16 HARDWARE
MULTIPLY
SERIAL UART
SPI INTERFACE
32k x 16 FLASH ROM
(64kBytes)
1k x 16 DATA RAM
(2kBytes)
MAXQ2000
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Power Management Features 17
Divide-by-256 Mode (PMM1) 17
32kHz Mode (PMM2) 18
Switchback Mode 18
Stop Mode 18
ADDENDUM TO SECTION 3: PROGRAMMING 19
ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS 19
ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES 26
ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE
(GPIO AND EXTERNAL INTERRUPTS) 33
ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULE 49
ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULE 49
ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULE 49
Using the 32kHz Alternate Timer Clock Source 49
Timer 2 Example: Triggering a Periodic Interrupt 50
ADDENDUM TO SECTION 10: SERIAL I/O (UART) MODULE 51
Serial UART Example: Asynchronous 10-Bit Output at 115,200 Baud 51
ADDENDUM TO SECTION 11: SERIAL PERIPHERAL
INTERFACE (SPI) MODULE 52
SPI Example: Enabling Master Mode 52
ADDENDUM TO SECTION 12: HARDWARE MULTIPLIER MODULE 53
Multiplier Example: 16-Bit Unsigned Multiplication 53
ADDENDUM TO SECTION 13: 1-WIRE BUS MASTER 54
1-Wire Example: Reset and Presence Detect 55
ADDENDUM TO SECTION 14: REAL-TIME CLOCK MODULE 55
Real-Time Clock Example: Starting and Setting the Clock 55
ADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP) 56
ADDENDUM TO SECTION 16: IN-CIRCUIT DEBUG MODE 56
Register Read and Write Commands 56
Data Memory Read Command 56
Data Memory Write Command 56
Program Stack Read Command 56
Read Register Map Command 56
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ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) 57
Bootloader Protocol 58
Family 0 Commands (Not Password Protected) 59
Family 1 Commands: Load Variable Length (Password Protected) 61
Family 2 Commands: Dump Variable Length (Password Protected) 62
Family 3 Commands: CRC Variable Length (Password Protected) 62
Family 4 Commands: Verify Variable Length (Password Protected) 63
Family 5 Commands: Load and Verify Variable Length (Password Protected) 63
Family 6 Commands: Erase Variable Length (Password Protected) 63
Family E Commands: Erase Fixed Length (Password Protected) 64
ADDENDUM TO SECTION 18: MAXQ FAMILY INSTRUCTION
SET SUMMARY 64
LCD CONTROLLER (SPECIFIC TO MAXQ2000) 66
LCD Controller Features 66
LCD Controller Operation Modes 73
LCD Drive Voltages 73
Selecting the LCD Mode 73
Segment Pin Configuration 74
LCD Internal Adjustable Contrast Resistor 74
LCD Frame Frequency 75
LCD Display Memory 75
Display Waveform Generation 80
LCD Controller Static Drive Example 80
LCD Controller 1/2 Duty Cycle Drive Example 82
LCD Controller 1/3 Duty Cycle Drive Example 83
LCD Controller 1/4 Duty Cycle Drive Example 85
LCD Controller Example: Initializing the LCD Controller 86
UTILITY ROM (SPECIFIC TO MAXQ2000) 87
In-Application Programming Features 87
Data Transfer Functions 88
ROM Example 1: Calling a Utility ROM Function Directly 91
ROM Example 2: Calling a Utility ROM Function Indirectly 92
REVISION HISTORY 93
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Maxim Integrated
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
Figure 1. MAXQ2000 System and Peripheral Register Map 8
Figure 2. Memory Map When Executing from Application Flash/ROM 10
Figure 3. Memory Map When Executing from Utility ROM 10
Figure 4. Memory Map When Executing from Data SRAM 11
Figure 5. MAXQ2000 Clock Sources 12
Figure 6. MAXQ2000 Power-On Reset 16
Figure 7. MAXQ2000 External Reset 17
Figure 8. LCD Controller Block Diagram 66
Figure 9. LCD Drive Voltage Generation 73
Figure 10. LCD Internal and External Display Contrast Adjustment 74
Figure 11. Sample 7-Segment LCD Display 80
Figure 12. Static Drive Example Display Connection 80
Figure 13. Static Drive Example Waveform Timing 81
Figure 14. 1/2 Duty Drive Example Display Connection 82
Figure 15. 1/2 Duty Drive Example Waveform Timing 83
Figure 16. 1/3 Drive Example Display Connection 83
Figure 17. 1/3 Duty Drive Example Waveform Timing 84
Figure 18. 1/4 Duty Drive Example Display Connection 85
Figure 19. 1/4 Duty Drive Example Waveform Timing 86
LIST OF FIGURES
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Table 1. System Clock Generation and Control Registers 12
Table 2. MAXQ2000 Interrupt Sources and Control Bits 14
Table 3. System Power Management Registers 17
Table 4. System Register Map 19
Table 5. System Register Bit Functions 20
Table 6. System Register Reset Values 21
Table 7. Peripheral Register Map 26
Table 8. Peripheral Register Bit Functions 27
Table 9. Peripheral Register Bit Reset Values 30
Table 10. Port Pin Special Functions (68-Pin Package) 33
Table 11. Port Pin Special Functions (56-Pin Package) 35
Table 12. MAXQ2000 Port Pin Input/Output States 36
Table 13. Type 2 Timer/Counter Input and Output Pins 49
Table 14. Type 2 Timer/Counter Control Registers 49
Table 15. Serial UART Input and Output Pins 51
Table 16. Serial UART Control Registers 51
Table 17. SPI Input and Output Pins 52
Table 18. SPI Interface Control Registers 52
Table 19. Hardware Multiplier Control Registers 53
Table 20. 1-Wire Master Input and Output Pins 54
Table 21. 1-Wire Interface Control Registers 54
Table 22. 1-Wire Master Register Bit Functions 54
Table 23. 1-Wire Master Register Bit Reset Values 54
Table 24. Real-Time Clock Control Registers 55
Table 25. Output From DebugReadMap Command 57
Table 26. Bootloader Status Codes 58
Table 27. Bootloader Status Flags 60
Table 28. PCFn Bit Functions for 68-Pin Package 67
Table 29. PCFn Bit Functions for 56-Pin Package 67
Table 30. LCD Display Modes 73
Table 31. LCD Frame Frequencies (Hz) 75
MAXQ Family User’s Guide:
MAXQ2000 Supplement
LIST OF TABLES
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
Table 32. LCD Display Memory Map (Static, 56-Pin Package) 76
Table 33. LCD Display Memory Map (1/2 Duty, 56-Pin Package) 76
Table 34. LCD Display Memory Map (1/3 Duty, 56-Pin Package) 77
Table 35. LCD Display Memory Map (1/4 Duty, 56-Pin Package) 77
Table 36. LCD Display Memory Map (Static, 68-Pin Package) 78
Table 37. LCD Display Memory Map (1/2 Duty, 68-Pin Package) 78
Table 38. LCD Display Memory Map (1/3 Duty, 68-Pin Package) 79
Table 39. LCD Display Memory Map (1/4 Duty, 68-Pin Package) 79
Table 40. Static Drive Example Common Signal Selection 81
Table 41. Static Drive Example Register Content 81
Table 42. 1/2 Duty Drive Example Common Signal Selection 82
Table 43. 1/2 Duty Drive Example Register Content 82
Table 44. 1/3 Duty Drive Example Common Signal Selection 84
Table 45. 1/3 Duty Drive Example Register Content 84
Table 46. 1/4 Duty Drive Example Common Signal Selection 85
Table 47. 1/4 Duty Drive Example Register Content 85
Table 48. Utility ROM User Functions (for Utility ROM Version 1.01) 87
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ADDENDUM TO SECTION 1: OVERVIEW
The MAXQ2000 is a low-power, high-performance 16-bit RISC microcontroller based on the MAXQ™ architecture. It includes support
for integrated, in-system-programmable flash memory and a wide range of peripherals including an LCD driver supporting up to x4
multiplexed displays. The MAXQ2000 is ideally suited for battery-powered, portable applications such as blood glucose monitoring,
medical instrumentation, environmental data logging, and industrial control.
References
Refer to the MAXQ Family User’s Guide (www.maxim-ic.com/user guides) for the following information.
• Description of the core architecture, instruction set, and memory mapping common to all MAXQ microcontrollers.
• Definitions and functions of the common system register set, including accumulators, data pointers, loop counters, and general-purpose registers.
• Descriptions of common clock generation, interrupt handling, and reset/power management modes.
• Descriptions and programming examples for common peripherals including Timer/Counter types 0/1/2, serial UART, SPI™ interface,
hardware multiplier, 1-Wire
®
bus master, and the real-time clock.
•Description of the Test Access Port (TAP) and in-circuit debug interface.
• Description of the in-system programming mode.
The online MAXQ2000 QuickView page contains information and data sheet links for all parts in the MAXQ2000 family.
For more information on other MAXQ microcontrollers, development hardware and software, frequently asked questions and software
examples, visit the MAXQ home page at www.maxim-ic.com/MAXQ.
For general questions and discussion of the MAXQ platform, visit our discussion board at http://discuss.dalsemi.com.
ADDENDUM TO SECTION 2: ARCHITECTURE
The MAXQ2000 shares the following common architectural features with other members of the MAXQ microcontroller family.
Instruction Set
The MAXQ2000 uses the standard 16-bit MAXQ instruction set as described in the MAXQ Family User’s Guide.
Harvard Memory Architecture
Program memory, data memory, and register space on the MAXQ2000 follow the Harvard architecture model. Each type of memory is
kept separate and is accessed by a separate bus, allowing different word lengths for different types of memory. Registers may be either
8 or 16 bits in width. Program memory is 16 bits in width to accommodate the standard MAXQ 16-bit instruction set. Data memory is
also 16 bits in width but can be accessed in 8-bit or 16-bit modes for maximum flexibility.
The MAXQ2000 includes a flexible memory management unit (MMU), which allows code to be executed from either the program
flash/ROM, the utility ROM, or the internal data SRAM. Any of these three memory spaces may also be accessed in data space at any
time, with the single restriction that whichever physical memory area is currently being used as program space cannot be read from
in data space.
Register Space
The MAXQ2000 contains the standard set of system registers as described in the MAXQ Family User’s Guide; differences are noted in
this guide where they exist. Peripheral register space (modules 0 through 4) on the MAXQ2000 contains registers that are used to
access the following peripherals:
• General-purpose 8-bit I/O ports (P0 through P7)
• External interrupts (up to 14)
• Three programmable Type 2 timer/counters
• Serial UART interfaces (2) and SPI
• Hardware Multiplier
• Real-Time Clock
MAXQ Family User’s Guide:
MAXQ2000 Supplement
MAXQ is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
• 1-Wire Interface Master
• LCD Controller (up to 132 segments)
The lower 8 bits of all registers in modules 0 through 4 (as well as the AP module M8) are bit addressable.
Figure 1. MAXQ2000 System and Peripheral Register Map
M0 M1 M2 M3 M4 M8 M9 M11 M12 M13 M14 M15
REAL-TIME
CLOCK
OWA
OWD
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
RESERVED
OR
OP CODE
PO0
PO4
PO1
PO5
PO2
PO6
PO3
PO7
PI0
PI4
PI1
PI5
PI2
PI6
PI3
PI7
PD0
PD4
PD1
PD5
PD2
PD6
PD3
PD7
RCNT
RTSS
RTSH
RTSL
RSSA
RASH
RASL
INTERRUPT
CONTROL
EIF0
EIF1
EIE0
EIE1
EIES0
EIES1
MA
MB
MC2
MC1
MC0
SERIAL
AND
SPI
LCD
CONTROLLER
TIMERS
ACC
ARRAY,
CONTROL
OTHER
FUNCTIONS
SCON0
SBUF0
SMD0
PR0
SPIB
SCON1
SBUF1
SMD1
PR1
SPICN
SPICF
SPICK
LCD15
LCD14
LCD13
LCD12
LCD11
LCD10
LCD9
LCD8
LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
LCD16
LCFG
LCRA
T2CNA0 T2CNA1
T2H0 T2H1
T2RH0 T2RH1
T2CH0 T2CH1
T2CNA2
T2H2
T2RH2
T2CH2
T2CNB1
T2V1
T2R1
T2C1
T2CNB0 T2CNB2
T2V0 T2V2
T2R0 T2R2
T2C0 T2C2
T2CFG0 T2CFG1
T2CFG2
AP
APC
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
IP
SP
LC0
LC1
OFFS
DPC
GR
GRL
BP
GRS
GRH
GRXL
BP[offs]
DP0
DP1
PSF
CKCN
WDCN
SC
IC
IMR
IIR
IV
REGISTER MODULE
REGISTER INDEX
MC0R
PORT PINS
(GPIO)
HARDWARE
MULTIPLIER
MCNT
MC1R
PFX
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Memory Organization
As with all MAXQ microcontrollers, the MAXQ2000 contains logically separate program and data memory spaces. All memory is internal, and physical memory segments (other than the stack and register memories) can be accessed as either program memory or as
data memory, but not both at once. The MAXQ2000 contains the following physical memory segments.
Register Space
As described in the MAXQ Family User’s Guide, register space on MAXQ microcontrollers consists of 16 register modules, each of
which can contain up to 32 registers. Of these possible 16 register modules, only 12 are used on the MAXQ2000—seven for system
registers and five for peripheral registers.
Program Stack
The MAXQ2000 provides a 16 x 16 hardware stack to support subroutine calls and system interrupts. This stack is used automatically by
CALL and RET instructions, and can also be accessed indirectly through the SP register as described in the MAXQ Family User’s Guide.
When using the in-circuit debugging features of the MAXQ2000, one word of the stack must be reserved to store the return location
when execution branches into the debugging routines in the utility ROM. If in-circuit debug will not be used, the entire stack is available for application use.
Data SRAM
The MAXQ2000 contains 1024 words (2kBytes) of on-chip data SRAM that can be mapped into either program or data space. The contents of this SRAM are indeterminate after power-on reset, but are maintained during Stop mode and across non-POR resets, as long
as the VDDsupply stays within the acceptable range.
When using the in-circuit debugging features of the MAXQ2000, the top 19 bytes (bytes 0x7ED to 0x7FF) of the SRAM must be
reserved for saved state storage and working space for the debugging routines in the utility ROM. If in-circuit debug will not be used,
the entire SRAM is available for application use.
Program Flash
The MAXQ2000 contains 32k x 16 of flash memory, which normally serves as program memory. When executing from the data SRAM or
utility ROM, this memory is mapped to data space (as 32kWords or 64kBytes) and can be used for lookup tables and similar functions.
Flash memory mapped into data space can be read from directly, like any other type of data memory. However, writing to flash memory
must be done indirectly by calling the in-application functions provided by the utility ROM. See the Utility ROM section for more details.
Program and Data Memory Mapping
Figures 2, 3, and 4 show the mapping of physical memory segments into the program and data memory space. The mapping of memory segments into program space is always the same. The mapping of memory segments into data space varies depending on which
memory segment is currently being executed from.
In all cases, whichever memory segment is currently being executed from in program space cannot be accessed in data space.
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Maxim Integrated
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
32k x 16
PROGRAM FLASH
OR MASKED ROM
PROGRAM
SPACE
EXECUTING FROM
DATA SPACE
(BYTE MODE)
DATA SPACE
(WORD MODE)
0000h
7FFFh
2k x 16
UTILITY ROM
87FFh
1k x 16
DATA SRAM
A000h
8000h
A3FFh
4k x 8
UTILITY ROM
8FFFh
8000h
2k x 8
DATA SRAM
0000h
07FFh
2k x 16
UTILITY ROM
87FFh
8000h
1k x 16
DATA SRAM
0000h
003FFh
Figure 2. Memory Map When Executing from Application Flash/ROM
Figure 3. Memory Map When Executing from Utility ROM
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PROGRAM
SPACE
1k x 16
DATA SRAM
2k x 16
UTILITY ROM
EXECUTING FROM
32k x 16
PROGRAM FLASH
OR MASKED ROM
A3FFh
A000h
87FFh
8000h
7FFFh
0000h
(BYTE MODE)
PROGRAM FLASH
OR MASKED ROM
DATA SPACE
64k x 8
PAGE 0
(IF CDA0 = 0)
PAGE 1
(IF CDA0 = 1)
2k x 8
DATA SRAM
FFFFh
8000h
07FFh
0000h
DATA SPACE
(WORD MODE)
32k x 16
PROGRAM FLASH
OR MASKED ROM
PAGES 0 AND 1
1k x 16
DATA SRAM
FFFFh
8000h
03FFh
0000h
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Clock Generation
All functional modules in the MAXQ2000 are synchronized to a single system clock. This system clock can be generated from one of
five possible sources (Figure 5):
• Internal ring oscillator
• Internal high-frequency oscillator using external crystal or resonator circuit
• External high-frequency clock signal
• Internal 32kHz oscillator using external crystal or resonator circuit
• External 32kHz clock signal
The MAXQ2000 does not provide the option for an external RC relaxation oscillator circuit.
Table 1 shows the registers and bits used to control clock generation and selection. For more information, see the register descriptions
in this guide and the MAXQ Family User’s Guide.
32k x 16
PROGRAM FLASH
OR MASKED ROM
PROGRAM
SPACE
EXECUTING FROM
DATA SPACE
(BYTE MODE)
DATA SPACE
(WORD MODE)
0000h
7FFFh
2k x 16
UTILITY ROM
87FFh
1k x 16
DATA SRAM
A000h
8000h
A3FFh
4k x 8
UTILITY ROM
8FFFh
8000h
64k x 8
PROGRAM FLASH
OR MASKED ROM
PAGE 0
(IF CDA0 = 0)
PAGE 1
(IF CDA0 = 1)
0000h
7FFFh
2k x 16
UTILITY ROM
87FFh
8000h
32k x 16
PROGRAM FLASH
OR MASKED ROM
PAGES 0 AND 1
0000h
7FFFh
Figure 4. Memory Map When Executing from Data SRAM
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
Table 1. System Clock Generation and Control Registers
External High-Frequency Oscillator Circuit or Clock
The high-frequency oscillator is the default source for system clock generation. This oscillator operates as described in the “Clock
Generation” section of Section 2: Architecture in the MAXQ Family User’s Guide. When using an external crystal or resonator circuit,
the circuit should be connected between the HFXIN and HFXOUT. When using an external clock signal to drive the high-frequency
clock, the external clock signal should be connected to the HFXIN pin, and the HFXOUT pin should be left unconnected.
Internal Ring Oscillator
The MAXQ2000 provides an internal ring oscillator that can be used as an alternate source for the system clock. This oscillator, which
requires no external components, typically runs at an 8MHz frequency. The exact frequency of the ring oscillator is not fixed and will
vary from part to part due to process variations, as well as over temperature and supply voltage for any given part.
REGISTER ADDRESS BIT FUNCTION
CKCN M8[0Eh]
Selects clock divide-by-1 (00), -2 (01), -4 (10), or -8 (11) mode.
CKCN M8[0Eh] 2 (PMME)
If set to 0, selects normal clock divide mode (as determined by CD[1:0]). If set to 1, selects
either divide-by-256 mode (when CD[1:0]=00) or 32kHz mode (when CD[1:0]=11).
CKCN M8[0Eh] 5 (RGMD)
Read-only. Indicates if ring oscillator (1) or external crystal/clock (0) is being used to provide
the system clock.
CKCN M8[0Eh] 6 (RGSL) Selects ring oscillator (1) or external crystal/clock (0) as the clock source.
RCNT M0[19h] 14 (X32D)
Disables (1) or enables (0) the internal 32kHz oscillator. If the 32kHz oscillator is disabled,
the RTC can be driven externally by a 32kHz clock input signal.
MAXQ2000
GLITCH-FREE
MUX
GLITCH-FREE
MUX
DIV 1
DIV 2
DIV 4
DIV 8
32kHz
PMM
CLOCK
DIVIDER
SELECTOR
WAKE-UP
ALARM
TIMERS
DEFAULT
RING SELECT
WATCHDOG
TIMER
RESET DOG
RWT
RESET
POWER-ON
RESET
STOP
STOP
POWER-ON
RESET
SWB
INTERRUPT/SERIAL PORT
RESET
STOP
RGSL
XDOG DONE
RGMD
POWER-ON RESET
WATCHDOG RESET
CLOCK
GENERATION
SYSTEM CLOCK
ENABLE
WATCHDOG INTERRUPT
RING
ENABLE
32kHz
CRYSTAL
CRYSTAL
MONITOR
ENABLE
INPUT
HF
CRYSTAL
CRYSTAL KLL
XDOG
STARTUP
TIMER
CLK INPUT
RESET XDOG COUNT
XDOG DONE
Figure 5. MAXQ2000 Clock Sources
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[1:0] to CD[1:0]
To select the ring oscillator as the system clock source, the RGSL bit (CKCN.6) must be set to 1. Setting this bit immediately switches
over the system clock source to the ring oscillator. The RGMD (CKCN.5) bit indicates the current system clock source. If the ring oscillator is currently providing the system clock, RGMD equals 1; otherwise, RGMD equals 0.
Because the RGSL bit is cleared by power-on reset only, if this bit is set before entering Stop mode, the ring oscillator will still be used
as the system clock source when Stop mode is exited. In this case, a 4-cycle warmup delay is required when exiting Stop mode before
execution resumes using the ring oscillator as the system clock source.
When the system clock source is switched back from the ring oscillator to the high-frequency oscillator by clearing RGSL to zero, the
ring oscillator will still be used as the system clock source until the warmup period has completed for the high-frequency oscillator. This
will be reflected by the value of the RGMD bit, which remains at 1 until the warmup for the high-frequency oscillator has completed
and the clock switches over, at which point RGMD switches to 0.
External 32kHz Crystal Oscillator Circuit or Clock
The MAXQ2000 provides a 32kHz clock for use by the real-time clock module. This clock can be generated either by the internal 32kHz
crystal oscillator (using an external crystal) or by an external source. The 32kHz clock is also usable as a system clock source, a clock
for the LCD controller, and as an alternate Timer 2 clock.
The 32kHz crystal amplifier is switched off by default on power-on reset. With this crystal amplifier disabled, the 32kHz clock must be
provided directly by an external source. To use the 32kHz crystal amplifier to generate the 32kHz clock, the amplifier must be turned
on by setting the X32D (RCNT.14) bit to 0 and a 32.768kHz, 6pF crystal should be connected between the 32KIN and 32KOUT pins.
To use the 32kHz clock as a source for the system clock, Power Management Mode 2 must be entered by setting PMME, CD1, and
CD0 to 1. See the Power Management Features section for more details.
Interrupts
In general, interrupt handling on the MAXQ2000 operates as described in the MAXQ Family User’s Guide. All interrupt sources have
the same priority, and all interrupts cause program execution to branch to the location specified by the Interrupt Vector (IV) register,
which defaults to 0000h.
Table 2 lists all possible interrupt sources for the MAXQ2000, along with their corresponding module interrupt enable bits, local interrupt enable bits, and interrupt flags.
• Each module interrupt enable bit, when cleared to 0, will block interrupts originating in that module from being acknowledged.
When the module interrupt enable bit is set to 1, interrupts from that module are acknowledged (unless the interrupts have been
disabled globally).
• Each local interrupt enable bit, when cleared to 0, will disable the corresponding interrupt. When the local interrupt enable bit is set
to 1, the interrupt will be triggered whenever the interrupt flag is set to 1 (either by software or hardware).
• All interrupt flag bits cause the corresponding interrupt to trigger when the bit is set to 1. These bits are typically set by hardware
and must be cleared by software (generally in the interrupt handler routine).
Note that for an interrupt to fire, the following five conditions must exist:
•Interrupts must be enabled globally by setting IGE (IC.0) to 1.
• The module interrupt enable bit for that interrupt source’s module must be set to 1.
• The local interrupt enable bit for that specific interrupt source must be set to 1.
• The interrupt flag for that interrupt source must be set to 1. Typically, this is done by hardware when the condition that requires interrupt service occurs.
• The Interrupt In Service (INS) bit must be cleared to 0. This bit is set automatically upon vectoring to the interrupt handler (IV) address
and cleared automatically upon exit (RETI/POPI), so the only reason to clear this bit manually (inside the interrupt handler routine) is
to allow nested interrupt handling.
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Maxim Integrated
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
Table 2. MAXQ2000 Interrupt Sources and Control Bits
INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG
Watchdog Interrupt IMS (IMR.7) EWDI (WDCN.6) WDIF (WDCN.3)
External Interrupt 0 IM0 (IMR.0) EX0 (EIE0.0) IE0 (EIF0.0)
External Interrupt 1 IM0 (IMR.0) EX1 (EIE0.1) IE1 (EIF0.1)
External Interrupt 2 IM0 (IMR.0) EX2 (EIE0.2) IE2 (EIF0.2)
External Interrupt 3 IM0 (IMR.0) EX3 (EIE0.3) IE3 (EIF0.3)
External Interrupt 4 IM0 (IMR.0) EX4 (EIE0.4) IE4 (EIF0.4)
External Interrupt 5 IM0 (IMR.0) EX5 (EIE0.5) IE5 (EIF0.5)
External Interrupt 6 IM0 (IMR.0) EX6 (EIE0.6) IE6 (EIF0.6)
External Interrupt 7 IM0 (IMR.0) EX7 (EIE0.7) IE7 (EIF0.7)
External Interrupt 8 IM1 (IMR.1) EX8 (EIE1.0) IE8 (EIF1.0)
External Interrupt 9 IM1 (IMR.1) EX9 (EIE1.1) IE9 (EIF1.1)
External Interrupt 10* IM1 (IMR.1) EX10 (EIE1.2) IE10 (EIF1.2)
External Interrupt 11* IM1 (IMR.1) EX11 (EIE1.3) IE11 (EIF1.3)
External Interrupt 12 IM1 (IMR.1) EX12 (EIE1.4) IE12 (EIF1.4)
External Interrupt 13 IM1 (IMR.1) EX13 (EIE1.5) IE13 (EIF1.5)
External Interrupt 14 IM1 (IMR.1) EX14 (EIE1.6) IE14 (EIF1.6)
External Interrupt 15 IM1 (IMR.1) EX15 (EIE1.7) IE15 (EIF1.7)
RTC Time-of-Day Alarm IM0 (IMR.0) ADE (RCNT.1) ALDF (RCNT.6)
RTC Subsecond Alarm IM0 (IMR.0) ASE (RCNT.2) ALSF (RCNT.7)
Serial Port 0 Receive IM2 (IMR.2) ESI (SMD0.2) RI (SCON0.0)
Serial Port 0 Transmit IM2 (IMR.2) ESI (SMD0.2) TI (SCON0.1)
Serial Port 1 Receive IM3 (IMR.3) ESI (SMD1.2) RI (SCON1.0)
Serial Port 1 Transmit IM3 (IMR.3) ESI (SMD1.2) TI (SCON1.1)
SPI Mode Fault IM3 (IMR.3) ESPII (SPICF.7) MODF (SPICN.3)
SPI Write Collision IM3 (IMR.3) ESPII (SPICF.7) WCOL (SPICN.4)
SPI Receive Overrun IM3 (IMR.3) ESPII (SPICF.7) ROVR (SPICN.5)
SPI Transfer Complete IM3 (IMR.3) ESPII (SPICF.7) SPIC (SPICN.6)
Timer 0–Low Compare IM3 (IMR.3) ET2L (T2CNB0.7) T2CL (T2CNB0.0)
Timer 0–Low Overflow IM3 (IMR.3) ET2L (T2CNB0.7) TF2L (T2CNB0.2)
Timer 0–Capture/Compare IM3 (IMR.3) ET2 (T2CNA0.7) TCC2 (T2CNB0.1)
Timer 0–Overflow IM3 (IMR.3) ET2 (T2CNA0.7) TF2 (T2CNB0.3)
Timer 1–Low Compare IM4 (IMR.4) ET2L (T2CNB1.7) T2CL (T2CNB1.0)
Timer 1–Low Overflow IM4 (IMR.4) ET2L (T2CNB1.7) TF2L (T2CNB1.2)
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
Table 2. MAXQ2000 Interrupt Sources and Control Bits (continued)
INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG
Timer 1–Capture/Compare IM4 (IMR.4) ET2 (T2CNA1.7) TCC2 (T2CNB1.1)
Timer 1–Overflow IM4 (IMR.4) ET2 (T2CNA1.7) TF2 (T2CNB1.3)
Timer 2–Low Compare IM4 (IMR.4) ET2L (T2CNB2.7) T2CL (T2CNB2.0)
Timer 2–Low Overflow IM4 (IMR.4) ET2L (T2CNB2.7) TF2L (T2CNB2.2)
Timer 2–Capture/Compare IM4 (IMR.4) ET2 (T2CNA2.7) TCC2 (T2CNB2.1)
Timer 2–Overflow IM4 (IMR.4) ET2 (T2CNA2.7) TF2 (T2CNB2.3)
1-Wire Presence Detect*
IM3 (IMR.3);
EOWMI (OWD[5].7)
EPD (OWD[3].0) PD (OWD[2].0)
1-Wire Transmit Buffer Empty*
IM3 (IMR.3);
EOWMI (OWD[5].7)
ETBE (OWD[3].2) TBE (OWD[2].2)
1-Wire Transmit Shift Register Empty*
IM3 (IMR.3);
EOWMI (OWD[5].7)
ETMT (OWD[3].3) TEMT (OWD[2].3)
1-Wire Receive Buffer Full*
IM3 (IMR.3);
EOWMI (OWD[5].7)
ERBF (OWD[3].4) RBF (OWD[2].4)
1-Wire Receive Shift Register Full*
IM3 (IMR.3);
EOWMI (OWD[5].7)
ERSF (OWD[3].5) RSRF (OWD[2].5)
1-Wire Short*
IM3 (IMR.3);
EOWMI (OWD[5].7)
EOWSH (OWD[3].6) OW_SHORT (OWD[2].6)
1-Wire Low*
IM3 (IMR.3);
EOWMI (OWD[5].7)
EOWL (OWL[3].7) OW_LOW (OWD[2].7)
* External Interrupts 10, external interrupt 11, and 1-Wire are only available on the 68-pin (RAX) version of the MAXQ2000.
Note 1: For 1-Wire Master interrupts to be received, both IM3 and EOWMI must be set to 1.
Note 2: The notation OWD[n] refers to accessing the OWD register with the OWA register set to n.
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
Reset Conditions
There are three possible reset sources for the MAXQ2000. While in the reset state, the enabled system clock oscillator continues running, but no code execution occurs. Once the reset condition has been removed or has completed, code execution resumes at
address 8000h for all reset types.
Power-On Reset
When power is first applied to the MAXQ2000, or when the internal supply voltage VDDdrops below the minimum allowed value, the
processor is held in a power-on reset state (Figure 6). For the MAXQ2000 to exit power-on reset, the following two conditions must apply:
•V
DD
is within the acceptable range for that power supply (see data sheet for values).
• The ring oscillator has completed 65,536 cycles (delay for power supply to stabilize).
Note that since the MAXQ2000 has no brownout reset function, the power-on reset is only guaranteed to occur if V
DD
drops all the way
to ground before rising again. Brownout events where VDDdrops partially (but remains above ground) and then rises back into the
acceptable range are not guaranteed to trigger a power-on reset and can result in unpredictable device behavior.
If the V
DDIO
power supply drops to ground, a power-on reset is not triggered. However, this causes all port pins driven by V
DDIO
to
drop to ground. Additionally, the 32kHz oscillator only operates when V
DDIO
is within acceptable limits.
Watchdog Timer Reset
The watchdog timer on the MAXQ2000 functions as described in the MAXQ Family User’s Guide. When running at 14MHz, the maximum watchdog time period before reset is approximately 150ms.
Since the RGSL bit is cleared to 0 on power-on reset only, it is possible to exit a watchdog reset with the clock source set to the highfrequency oscillator. In this case, execution resumes running from the ring oscillator, and the switchover to the high-frequency oscillator occurs automatically when the 65,536-cycle warmup delay for that oscillator has completed.
External Reset
External reset via RESET is a synchronous reset source. After the external reset low has been removed and sampled, execution
resumes (running from the ring oscillator) following a delay of four ring-oscillator cycles, as shown in Figure 7.
Since the RGSL bit is cleared to 0 on power-on reset only, it is possible to exit an external reset with the clock source set to the highfrequency oscillator. In this case, execution resumes running from the ring oscillator, and the switchover to the high-frequency oscillator occurs automatically when the 65,536-cycle warmup delay for that oscillator has completed.
V
DD(MIN)
T1
RING
OSCILLATOR
INTERNAL
RESET
T2
(T1 = STARTUP TIME FOR RING OSCILLATOR)
(T2 = 65,536 RING OSCILLATOR CYCLES, OR 8.192ms AT 8MHz)
Figure 6. MAXQ2000 Power-On Reset
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Power Management Features
The MAXQ2000 provides the following features to assist in power management.
• Divide-by-256 (PMM1) and 32kHz (PMM2) modes to reduce current consumption.
• Switchback mode to exit PMM modes automatically when rapid processing is required.
• Ultra-low-power Stop mode.
Table 3 shows the system registers and bits used to control power management features. For more information, refer to the register
descriptions in the MAXQ Family User’s Guide.
Table 3. System Power Management Registers
Divide-by-256 Mode (PMM1)
In this power management mode, all operations continue as normal but at a reduced clock rate (the high-frequency system clock divided by 256). This power management mode affects module clock rates as follows.
•Program execution occurs at the high-frequency clock rate divided by 256.
• The RTC module continues to operate using its originally selected clock, which is either the 32kHz clock or the high-frequency clock
divided by 128, as selected by the ACS bit (RCNT.13).
• The LCD module continues to operate using its originally selected clock, which is either the 32kHz clock or the high-frequency clock
divided by 128, as selected by the LCCS bit (LCRA.6).
• All other functional modules (timers, UARTs, SPI) operate at the high-frequency clock rate divided by 256.
MAXQ Family User’s Guide:
MAXQ2000 Supplement
CLOCK
RESET
RESET
SAMPLING
INTERNAL
RESET
FIRST
INSTRUCTION
FETCH
Figure 7. MAXQ2000 External Reset
REGISTER ADDRESS BIT FUNCTION
CKCN M8[0Eh]
Selects clock divide-by-1 (00), -2 (01), -4 (10), or -8 (11) mode. When PMM mode is
enabled, selects divide-by-256 (00) or 32kHz (11) mode.
CKCN M8[0Eh] 2 (PMME) Selects PMM mode (when set to 1) or normal clock divide mode (when set to 0).
CKCN M8[0Eh] 3 (SWB)
When set to 1, enables automatic switchback from PMM (divide-by-256 mode) to normal
clock divide mode under certain conditions.
CKCN M8[0Eh] 4 (STOP) When set to 1, causes the processor to enter Stop mode.
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[1:0] to CD[1:0]
MAXQ Family User’s Guide:
MAXQ2000 Supplement
This power management mode is entered by setting the PMME bit (CKCN.2) to 1 while the CD1 and CD0 (CKCN[1:0]) bits are both
cleared to 0. When PMM1 mode is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation will
revert to the mode indicated by the values of the CD1 and CD0 bits, which in this case will be the standard divide-by-1 clock mode.
32kHz Mode (PMM2)
In this power management mode, all operations continue as normal using the 32kHz clock as the system clock source. This power
management mode affects module clock rates as follows.
•Program execution occurs at the 32kHz clock rate.
• The RTC module continues to operate using its originally selected clock, which is either the 32kHz clock or the high-frequency clock
divided by 128, as selected by the ACS bit (RCNT.13).
• The LCD module continues to operate using its originally selected clock, which is either the 32kHz clock or the high-frequency clock
divided by 128, as selected by the LCCS bit (LCRA.6).
• All other functional modules (timers, UARTs, SPI) operate at the 32kHz clock rate.
This power management mode is entered by setting the PMME bit (CKCN.2) to 1 while the CD1 and CD0 (CKCN[1:0]) bits are both
set to 1. When PMM2 mode is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation will revert
to the mode indicated by the values of the CD1 and CD0 bits, which in this case will be the divide-by-8 clock mode.
When PMM2 mode is entered, the high-frequency oscillator is automatically disabled unless Switchback has been enabled by setting
the SWB bit to 1. If Switchback is not being used, the LCD module and RTC module should both be set to use the 32kHz clock (not
HFClk / 128) before PMM2 mode is entered.
Switchback Mode
As described in the MAXQ Family User’s Guide, Switchback mode provides automatic exit from power management mode when a
higher clock rate is required to respond to I/O, such as UART activity, SPI activity, or an external interrupt.
Switchback mode is enabled when the SWB (CKCN.3) bit is set to 1 and the PMME (CKCN.2) bit is set to 1(the system is in either the
PMM1 or PMM2 modes). If Switchback is enabled, the PMME bit will be cleared (causing the system to exit power management mode)
when any of the following conditions occur.
• An external interrupt condition occurs on an INTx pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the RXD0 or RXD1 pin and the corresponding UART is enabled to receive data. If PMM2 mode is
exited in this manner, the first character read by the UART will be received incorrectly.
• The SBUF0 or SBUF1 register is written to transmit a byte and the corresponding UART is enabled to transmit data.
• The SPIB register is written to send an outgoing byte through the SPI interface and transmission is enabled.
• An active-low transition occurs on the SSEL pin when the SPI interface is configured for slave mode.
•A Time-of-Day alarm is generated by the RTC module.
• Active debug mode is entered either by a breakpoint match or direct issuance of the Debug command from background mode.
As described in the MAXQ Family User’s Guide, if any of these conditions are true (a Switchback source is active) and the SWB bit has
been set, the PMME bit cannot be set to enter power management mode.
Stop Mode
Stop mode disables all circuits within the MAXQ2000 except for the 32kHz crystal amplifier and any circuitry that is clocked directly
by the 32kHz clock. All other on-chip clocks, timers, serial ports, and other peripherals are stopped, and no code execution occurs.
Once in Stop mode, the MAXQ2000 is in a mostly static state, with power consumption determined largely by leakage currents.
Stop mode is invoked by setting the STOP bit to 1. The MAXQ2000 enters Stop mode immediately when the STOP bit is set. Entering
Stop mode does not affect the setting of the clock control bits; this allows the system to return to its original operating frequency following Stop mode removal.
The processor exits Stop mode if any of the following conditions occur.
• External reset (from the RST pin)
•Power-on reset
• External interrupt (interrupt must be enabled prior to entering Stop mode)
•RTC time-of-day alarm
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Note that exiting Stop mode through external reset or power-on reset causes the processor to undergo a normal reset cycle, as
opposed to resuming execution at the point at which it entered Stop mode. Exiting Stop mode by means of an external interrupt or
time-of-day alarm causes the processor to resume execution at the instruction following the one that set the STOP bit.
When Stop mode is exited, processor execution resumes as follows.
• If the ring oscillator is selected as the system clock source (RGSL = 1), execution resumes using the ring oscillator as the system
clock following a delay of four ring cycles.
• If the high-frequency oscillator is selected as the system clock source (RGSL = 0), execution resumes using the ring oscillator as the
system clock following a delay of four ring cycles. After the high-frequency oscillator has completed its warmup period, the system
clock source switches over to the high-frequency clock automatically.
• If the 32kHz oscillator is selected as the system clock source, execution resumes using the 32kHz oscillator as the system clock fol-
lowing a delay of four ring cycles. For this to work properly, the 32kHz crystal amplifier must be enabled and running prior to entering Stop mode, or an external 32kHz clock must be provided immediately upon Stop mode exit (if X32D is set to 1).
ADDENDUM TO SECTION 3: PROGRAMMING
Refer to Section 3: Programming in the MAXQ Family User’s Guide for examples of general program operations involving the MAXQ
core. The MAXQ2000 contains the MAXQ20 (16-bit accumulator version) of the MAXQ core.
ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS
Refer to Section 4: System Register Descriptions in the MAXQ Family User’s Guide for functional descriptions of the registers and bits
listed in Tables 4, 5, and 6.
Table 4. System Register Map
Note: Register names that appear in italics indicate read-only registers. Register names that appear in bold indicate 16-bit registers. All other registers are 8
bits in width.
MAXQ Family User’s Guide:
MAXQ2000 Supplement
CYCLES TO
READ
CYCLES TO
WRITE
REGISTER
INDEX
AP (8h) A (9h) PFX (Bh) IP (Ch) SP (Dh) DPC (Eh) DP (Fh)
1 1 0xh AP A[0]
PFX IP
1 1 1xh APC A[1]
SP
1 1 2xh — A[2]
IV
1 1 3xh — A[3] Offs
DP[0]
1 1 4xh PSF A[4]
DPC
1 1 5xh IC A[5]
GR
1 1 6xh IMR A[6]
LC[0]
GRL
1 1 7xh — A[7]
LC[1] BP DP[1]
1 2 8xh SC A[8]
GRS
1 2 9xh — A[9] GRH
1 2 Axh — A[10]
GRXL
12BxhIIR A[11]
FP
1 2 Cxh — A[12]
1 2 Dxh — A[13]
1 2 Exh CKCN A[14]
1 2 Fxh WDCN A[15]
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
Table 5. System Register Bit Functions
REG
BIT 0
AP — — — — AP (4 bits)
APC
IDS — — —
MOD0
PSF ZS—
OV C E
IC ——
———INS
IGE
IMR
——
IM0
SC
——
—
—
IIR IIS — — II4 II3 II2 II1 II0
CKCN —
CD0
WDCN
RWT
A[0..15]
A[n] (16 bits)
PFX PFX (16 bits)
IP IP (16 bits)
SP ———————————— SP (4 bits)
IV IV (16 bits)
LC[0] LC[0] (16 bits)
LC[1] LC[1] (16 bits)
Offs Offs (8 bits)
DPC ———————————
SDPS0
GR GR (16 bits)
GRL
GR.0
BP BP (16 bits)
GRS
GR.8
GRH
GR.8
GRXL
GR.0
FP FP (16 bits)
DP[0] DP[0] (16 bits)
DP[1] DP[1] (16 bits)
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BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9
GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1
CLR
GPF1 GPF0
CGDS
IMS
TAP
RGSL RGMD STOP SWB PMME CD1
POR EWDI WD1 WD0 WDIF WTRF EWT
GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1
GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9
IM4 IM3 IM2 IM1
CDA0
WBS2 WBS1 WBS0 SDPS1
MOD2 MOD1
ROD PWL
Table 6. System Register Reset Values
MAXQ Family User’s Guide:
MAXQ2000 Supplement
REG
BIT 0
AP 00000000
APC 00000000
PSF 10000000
IC 00000000
IMR 00000000
SC 000000s 0
IIR 00000000
CKCN 0 ss00000
WDCN ss000ss0
0000000000000000
PFX 0000000000000000
IP 1000000000000000
SP 0000000000001111
IV 0000000000000000
LC[0] 0000000000000000
LC[1] 0000000000000000
Offs 00000000
DPC0000000000011100
GR 0000000000000000
GRL 00000000
BP 0000000000000000
GRS0000000000000000
GRH 00000000
GRXL 0000000000000000
FP 0000000000000000
DP[0] 0000000000000000
DP[1] 0000000000000000
Note: Bits marked as “s” have special behavior upon reset; see register descriptions for details.
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BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
A[0..15]
MAXQ Family User’s Guide:
MAXQ2000 Supplement
The following section details the functionality of any System Registers contained in the MAXQ2000 that operate differently from their
descriptions in the MAXQ Family User’s Guide.
Register Name: IMR
Register Description: Interrupt Mask Register
Register Address: AP[06h]
The first five bits in this register are interrupt mask bits for modules 0 through 4, one bit per module. The eighth bit, IMS, serves as a
mask for any system module interrupt sources. Setting a mask bit allows the enabled interrupt sources for the associated module or system (with IMS) to generate interrupt requests. Clearing the mask bit effectively disables all interrupt sources associated with that module or, in the case of IMS, all system interrupt sources. The IMR register is intended to facilitate user-definable interrupt prioritization.
Bit 0: (IMR.0) Module 0 Interrupt Mask (IM0)
Bit 1: (IMR.1) Module 1 Interrupt Mask (IM1)
Bit 2: (IMR.2) Module 2 Interrupt Mask (IM2)
Bit 3: (IMR.3) Module 3 Interrupt Mask (IM3)
Bit 4: (IMR.4) Module 4 Interrupt Mask (IM4)
Bits 5 and 6: (IMR.5 and IMR.6) Reserved
Bit 7: (IMR.7) System Module Interrupt Mask (IMS)
Register Name: SC
Register Description: System Control Register
Register Address: AP[08h]
Bit 0: (SC.0) Reserved
Bit 1: (SC.1) Password Lock (PWL). This bit defaults to 1 on power-on reset only. When this bit is 1, it requires a 32-byte password
to be matched with the password in the program space before allowing access to the ROM Loader’s utilities for read/write of program
memory and debug functions. Clearing this bit to 0 disables the password protection to the ROM Loader.
Bits 2 and 3: (SC.2 and SC.3) Reserved
Bit 4: (SC.4) Code Data Access Bit 0 (CDA0). If this bit is set to 0, the lower half of physical program memory will be visible in data
space (when not executing from physical program memory) in byte mode. If this bit is set to 1, the upper half of physical program memory will be visible in data space in byte mode. When accessing data space in word mode, this bit has no effect.
Bit # 76543210
Name IMS — — IM4 IM3 IM2 IM1 IM0
Reset 00000000
Access r/w r r r/w r/w r/w r/w r/w
Bit # 7 6 5 43210
Name TAP — — CDA0 — — PWL —
Reset 1 0 0 0 0 0 not set 0
POR 10000010
Access r/w r r r/w r r r/w r
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Bits 5 and 6: (SC.5 and SC.6) Reserved
Bit 7: (SC.7) Test Access (JTAG) Port Enable
0 = JTAG TAP functions are disabled and P4.0 through P4.3 can be used as general-purpose I/O pins.
1 = TAP special function pins P4.0 through P4.3 are enabled to act as JTAG inputs and outputs.
Register Name: IIR
Register Description: Interrupt Identification Register
Register Address: AP[0Bh]
The first five bits in this register indicate interrupts pending in modules 0 through 4, one bit per module. The eighth bit, IIS, indicates a
pending system interrupt (from the watchdog timer or other system function). The interrupt pending flags will be set only for enabled
interrupt sources waiting for service. The interrupt pending flag will be cleared when the pending interrupt source(s) within that module are disabled when the interrupt flag(s) are cleared by software.
Bit 0: (IIR.0) Interrupt Pending Flag for Module 0 (II0)
Bit 1: (IIR.1) Interrupt Pending Flag for Module 1 (II1)
Bit 2: (IIR.2) Interrupt Pending Flag for Module 2 (II2)
Bit 3: (IIR.3) Interrupt Pending Flag for Module 3 (II3)
Bit 4: (IIR.4) Interrupt Pending Flag for Module 4 (II4)
Bits 5 and 6: (IIR.5 and IIR.6) Reserved
Bit 7: (IIR.7) Interrupt Pending Flag for System Modules
Register Name: CKCN
Register Description: System Clock Control Register
Register Address: AP[0Eh]
The CKCN register bit settings determine the system clock source and clock divider as described in the following table.
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Bit # 76543210
Name IIS — — II4 II3 II2 II1 II0
Reset 0 0 0 00000
Access r r r rrrrr
Bit # 76543210
Name — RGSL RGMD STOP SWB PMME CD1 CD0
Reset 0 0 s 00000
Access r/w r/w r r/w r/w r/w special special
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
MAXQ2000 System Clock Modes
Bit 0: (CKCN.0) Clock Divide 0 (CD0); Bit 1: (CKCN.1) Clock Divide 1 (CD1); Bit 2: (CKCN.2) Power Management Mode Enable
(PMME). These three bits control the divide ratio or enable power management mode for the system clock as shown in the MAXQ2000
System Clock Modes table. CD0 and CD1 can always be read, and they can be written as long as PMME = 0.
Setting the PMME bit to 1 activates either the divide-by-256 power management mode or the 32kHz power management mode,
depending on the settings of CD1 and CD0. When PMME is set to 1, CD0 and CD1 cannot be changed; their values will determine the
clock divide ratio that is used when the processor exits power management mode. When the 32kHz power management mode is
active, the high-frequency oscillator amplifier is disabled unless Switchback is enabled.
RGMD SWB PMME
CD1
CD0 SYSTEM CLOCK HIGH-FREQUENCY OSCILLATOR SWITCHBACK
0 0 0 0 0 HFOsc / 1 Running N/A
0 0 0 0 1 HFOsc / 2 Running N/A
0 0 0 1 0 HFOsc / 4 Running N/A
0 0 0 1 1 HFOsc / 8 Running N/A
0 0 1 0 0 HFOsc / 256 Running Not Active
0 1 1 0 0 HFOsc / 256 Running Active
1 0 0 0 0 Ring / 1 Off or Warming Up N/A
1 0 0 0 1 Ring / 2 Off or Warming Up N/A
1 0 0 1 0 Ring / 4 Off or Warming Up N/A
1 0 0 1 1 Ring / 8 Off or Warming Up N/A
1 0 1 0 0 Ring / 256 Off or Warming Up N/A
x 0 1 1 1 32kHz Off Not Active
x 1 1 1 1 32kHz Running Active
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Bit 3: (CKCN.3) Switchback Enable (SWB). Setting this bit to 1 enables Switchback mode. If power management mode (either divide
by 256 or 32kHz) is active and Switchback is enabled, the PMME bit will be cleared to 0 when any of the following conditions occur.
• An external interrupt is generated based on an edge detect.
• Either serial port 0 or serial port 1 is enabled to receive data and detects a low condition on its data receive pin.
• Either serial port 0 or serial port 1 is enabled to transmit data has a byte written to its buffer register by software.
• The SPI module is enabled in slave mode and receives a slave select signal from the bus master.
• The SPI module is enabled to transmit data and has a byte written to its buffer register by software.
• A time-of-day interrupt occurs from the real-time clock.
• Debug mode is entered through command entry or a breakpoint match.
Triggering a Switchback condition only clears the PMME bit; the settings of CD0 and CD1 remain the same. This means that exiting
Switchback from divide-by-256 mode will revert to a divide by 1 mode, while exiting Switchback from 32kHz mode will revert to a divide
by 8 mode.
When either power management mode is active, the SWB bit may not be set to 1 as long as any of the above conditions are true.
Bit 4: (CKCN.4) Stop Mode Select (STOP). Setting this bit to 1 causes the processor to enter Stop Mode. This will not change the currently selected clock divide ratio.
Bit 5: (CKCN.5) Ring Oscillator Mode (RGMD). This read-only bit indicates the current oscillator source. If RGMD is set to 1, the internal ring oscillator is currently acting as the oscillator source for the system clock. (This can either be because RGSL = 1, or because
RGSL = 0, and the crystal warmup period has not yet completed.) If RGMD is cleared to 0, the external crystal oscillator is currently
acting as the oscillator source for the system clock (unless the PMM2 32kHz mode is active).
Bit 6: (CKCN.6) Ring Oscillator Select (RGSL). If this bit is set to 1, the ring oscillator will immediately begin sourcing the system
clock, and the high-frequency oscillator will be disabled (unless 32kHz mode and Switchback are enabled). Clearing this bit to 0
enables the high-frequency oscillator. Until the warmup period for the high-frequency oscillator has completed, the ring oscillator will
still provide the system clock source (indicated by RGMD = 1). Once the warmup period completes, the system clock source will automatically switch over to the high-frequency oscillator, and RGMD will go to 0.
Bit 7: (CKCN.7) Reserved
MAXQ Family User’s Guide:
MAXQ2000 Supplement
Maxim Integrated
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MAXQ Family User’s Guide:
MAXQ2000 Supplement
ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES
Refer to the MAXQ Family User’s Guide.
Table 7. Peripheral Register Map
CYCLES TO
READ
CYCLES TO
WRITE
REGISTER
INDEX
M0
(0h)
M1
(1h)
M2
(2h)
M3
(3h)
M4
(4h)
M5
(5h)
1 1 00h PO0 PO4 MCNT T2CNA0 T2CNA1 —
1 1 01h PO1 PO5
MA
T2H0 T2H1 —
1 1 02h PO2 PO6
MB
T2RH0 T2RH1 —
1 1 03h PO3 PO7
MC2
T2CH0 T2CH1 —
1 1 04h — —
MC1
— T2CNA2 —
1 1 05h — —
MC0 SPIB
T2H2 —
1 1 06h EIF0 EIF1 SCON0 SCON1 T2RH2 —
1 1 07h EIE0 EIE1 SBUF0 SBUF1 T2CH2 —
1 2 08h PI0 PI4 SMD0 SMD1 T2CNB1 —
1 2 09h PI1 PI5
PR0 PR1 T2V1
—
1 2 0Ah PI2 PI6 ——
T2R1
—
1 2 0Bh PI3 PI7
MC1R
—
T2C1
—
1 2 0Ch EIES0 EIES1
MC0R
T2CNB0 T2CNB2 —
1 2 0Dh — —
LCRA T2V0 T2V2
—
1 2 0Eh — — LCFG
T2R0 T2R2
—
1 2 0Fh — — LCD16
T2C0 T2C2
—
2 2 10h PD0 PD4 LCD0 T2CFG0 T2CFG1 —
2 2 11h PD1 PD5 LCD1 — T2CFG2 —
2 2 12h PD2 PD6 LCD2 — —
2 2 13h PD3 PD7 LCD3 OWA —
2 2 14h — — LCD4 OWD —
2 2 15h — — LCD5 SPICN —
2 2 16h — — LCD6 SPICF —
2 2 17h — — LCD7 SPICK —
2 2 18h — — LCD8 — —
2 2 19h
RCNT
— LCD9 — —
2 2 1Ah RTSS — LCD10 — —
2 2 1Bh
RTSH
— LCD11 ICDF —
2 2 1Ch
RTSL
— LCD12 — —
2 2 1Dh RSSA — LCD13 — —
2 2 1Eh RASH SVS LCD14 — —
2 2 1Fh
RASL
WKO LCD15 — —
Note: Register names in italics indicate read-only registers. Register names in bold indicate 16-bit registers. All other registers are 8 bits in width.
Maxim Integrated
26
MAXQ Family User’s Guide:
MAXQ2000 Supplement
REG BIT 15
BIT 0
PO0 PO0 (8 bits)
PO1 PO1 (8 bits)
PO2 PO2 (8 bits)
PO3 PO3 (8 bits)
EIF0 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
EIE0 EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0
PI0 PI0 (8 bits)
PI1 PI1 (8 bits)
PI2 PI2 (8 bits)
PI3 PI3 (8 bits)
EIES0 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0
PD0 PD0 (8 bits)
PD1 PD1 (8 bits)
PD2 PD2 (8 bits)
PD3 PD3 (8 bits)
RCNT WE
——— — —
RDY
ASE ADE
RTCE
RTSS RTSS (8 bits)
RTSH RTSH (16 bits)
RTSL RTSL (16 bits)
RSSA RSSA (8 bits)
RASH RASH (8 bits)
RASL RASL (16 bits)
PO4 — — — PO4 (5 bits)
PO5 PO5 (8 bits)
PO6 PO6 (8 bits)
PO7 — — — — — — PO7 (2 bits)
EIF1 IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8
EIE1 EX15 EX14 EX13 EX12
EX9 EX8
PI4 — — — PI4 (5 bits)
PI5 PI5 (8 bits)
PI6 PI6 (8 bits)
PI7 — — — — — — PI7 (2 bits)
EIES1 IT15 IT14 IT13 IT12 IT11 IT10 IT9 IT8
PD4 — — — PD4 (5 bits)
PD5 PD5 (8 bits)
Table 8. Peripheral Register Bit Functions
Maxim Integrated
27
BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
X32D ACS
ALSF ALDF RDYE
BUSY
EX11 EX10
MAXQ Family User’s Guide:
MAXQ2000 Supplement
REG BIT15
BIT14
BIT13
BIT12
BIT11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PD6
PD6 (8 bits)
PD7
— — — — — — PD7 (2 bits)
SVS
SV67
SV65 SV64 — — SV71
SV70
WKO
— — — — — WKL
WKE0
MCNT
OF — — SQU
CLD
SUS
MA
MA (16 bits)
MB
MB (16 bits)
MC2
MC2 (16 bits)
MC1
MC1 (16 bits)
MC0
MC0 (16 bits)
SCON0
SM1 SM2 REN TB8 RB8 TI RI
SBUF0
SBUF0 (8 bits)
SMD0
—————ESI0
FEDE0
PR0
PR0 (16 bits)
MC1R
MC1R (16 bits)
MC0R
MC0R (16 bits)
LCRA
———
LRIG
LRA0
LCFG
— — OPM DPE
LCD0
LCD0 (8 bits)
LCD1
LCD1 (8 bits)
LCD2
LCD2 (8 bits)
LCD3
LCD3 (8 bits)
LCD4
LCD4 (8 bits)
LCD5
LCD5 (8 bits)
LCD6
LCD6 (8 bits)
LCD7
LCD7 (8 bits)
LCD8
LCD8 (8 bits)
LCD9
LCD9 (8 bits)
LCD10
LCD10 (8 bits)
LCD11
LCD11 (8 bits)
LCD12
LCD12 (8 bits)
LCD13
LCD13 (8 bits)
LCD14
LCD14 (8 bits)
LCD15
LCD15 (8 bits)
LCD16
LCD16 (8 bits)
T2CNA0
ET2
TR2
SS2
G2EN
T2H0
T2V0.8
T2RH0
T2R0.15
T2R0.14
T2R0.13
T2R0.12
T2R0.11
T2R0.10
T2R0.9
T2R0.8
Table 8. Peripheral Register Bit Functions (continued)
Maxim Integrated
28
DUTY1 DUTY0 FRM3 FRM2 FRM1 FRM0 LCCS
SV66
WKE1
OPCS
SM0/FE
PCF3 PCF2 PCF1 PCF0
T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2V0.9
LRA4 LRA3 LRA2 LRA1
T2OE0 T2POL0 TR2L
CPRL2
MMAC
SMOD0
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