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MAX6340/MAX6421–
MAX6426
with Capacitor-Adjustable Reset Timeout Delay
Low-Power, SC70/SOT µP Reset Circuits
General Description
The MAX6340/MAX6421–MAX6426 low-power microprocessor supervisor circuits monitor system voltages from
1.6V to 5V. These devices perform a single function: they
assert a reset signal whenever the VCC supply voltage
falls below its reset threshold. The reset output remains
asserted for the reset timeout period after VCC rises
above the reset threshold. The reset timeout is externally
set by a capacitor to provide more flexibility.
The MAX6421/MAX6424 have an active-low, pushpull reset output. The MAX6422 has an active-high, pushpull reset output and the MAX6340/MAX6423/ MAX6425/
MAX6426 have an active-low, open-drain reset output.
The MAX6421/MAX6422/MAX6423 are offered in 4-pin
SC70 or SOT143 packages. The MAX6340/MAX6424/
MAX6425/MAX6426 are available in 5-pin SOT23-5
packages.
Applications
● Portable Equipment
● Battery-Powered Computers/Controllers
● Automotive
● Medical Equipment
● Intelligent Instruments
● Embedded Controllers
● Critical µP Monitoring
● Set-Top Boxes
● Computers
Benets and Features
● Monitor System Voltages from 1.6V to 5V
● Capacitor-Adjustable Reset Timeout Period
● Low Quiescent Current (1.6µA typ)
● Three RESET Output Options
Push-Pull RESET
Push-Pull RESET
Open-Drain RESET
● Guaranteed Reset Valid to VCC = 1V
● Immune to Short VCC Transients
● Small 4-Pin SC70, 4-Pin SOT143, and 5-Pin SOT23
Packages
● MAX6340 Pin Compatible with LP3470
● MAX6424/MAX6425 Pin Compatible with
NCP300–NCP303, MC33464/MC33465,
S807/S808/S809, and RN5VD
● MAX6426 Pin Compatible with PST92XX
● AEC-Q100 Qualified (MAX6340UK31/V+T)
Typical Operating Circuit, Selector Guide, and Ordering
Information appear at end of data sheet.
Pin Congurations
TOP VIEW
V
CC
14
MAX6421X
MAX6422X
MAX6423X
2
GND
SC70
( ) ARE FOR THE MAX6422
Pin Configurations continued at end of data sheet.
19-2440; Rev 9; 3/18
3
RESET
(RESET)
SRT
Page 2
MAX6340/MAX6421–
MAX6426
with Capacitor-Adjustable Reset Timeout Delay
Low-Power, SC70/SOT µP Reset Circuits
Absolute Maximum Ratings
All Voltages Referenced to GND
VCC .......................................................................-0.3V to +6.0V
SRT, RESET, RESET (push-pull) ............. -0.3V to (VCC + 0.3V)
RESET (open drain) .............................................-0.3V to +6.0V
Input Current (all pins) ...................................................... ±20mA
Output Current (RESET, RESET) .................................... ±20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Operating Temperature Range ......................... -40°C to +125°C
Storage Temperature Range ........................... .-65°C to +150°C
Junction Temperature ...................................................... +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Electrical Characteristics
(VCC = 1V to 5.5V, TA = T
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply Voltage RangeV
Supply CurrentI
VCC Reset Threshold AccuracyV
HysteresisV
VCC to Reset Delayt
Reset Timeout Periodt
V
Ramp CurrentI
SRT
V
Ramp Threshold
SRT
RAMP Threshold HysteresisV
RESET Output Voltage LowV
RESET Output Voltage High,
Push-Pull
RESET Output Leakage Current,
Open-Drain
RESET Output Voltage HighV
RESET Output Voltage LowV
Note 1: Devices production tested at +25°C. Overtemperature limits are guaranteed by design.
MIN
to T
, unless otherwise specified. Typical values are at VCC = 5V and TA = +25°C.) (Note 1)
MAX
CC
1.05.5V
VCC ≤ 5.0V2.54.2
CC
VCC ≤ 3.3V1.93.4
VCC ≤ 2.0V1.62.5
TA = +25°C VTH - 1.5% VTH + 1.5%
TH
HYST
RD
RP
RAMP
V
TH-RAMP
OL
V
OH
I
LKG
OH
OL
TA = -40°C to +125°C VTH - 2.5% VTH + 2.5%
4 x V
TH
VCC falling at 1mV/µs 80µs
C
= 1500pF3.004.3755.75
SRT
C
= 00.275
SRT
V
= 0 to 0.65V; VCC = 1.6V to 5V240nA
SRT
VCC = 1.6V to 5V (V
falling threshold33mV
RAMP
VCC ≥ 1.0V, I
VCC ≥ 4.5V, I
VCC ≥ 1.8V, I
VCC ≥ 4.5V, I
= 50µA0.3
SINK
= 1.2mA0.3
SINK
= 3.2mA0.4
SINK
SOURCE
SOURCE
SOURCE
rising)0.65V
RAMP
= 200µA0.8 x V
= 500µA0.8 x V
= 800µA0.8 x V
CC
CC
CC
VCC > VTH, reset not asserted1.0µA
VCC ≥ 1.0V, I
VCC ≥ 1.8V, I
VCC ≥ 2.7V, I
VCC ≥ 4.5V, I
VCC ≥ 1.8V, I
VCC ≥ 4.5V, I
SOURCE
SOURCE
SOURCE
SOURCE
SINK
SINK
SINK
= 1µA0.8 x V
= 150µA0.8 x V
= 500µA0.8 x V
= 800µA0.8 x V
CC
CC
CC
CC
= 500µA0.3
= 1.2mA0.3
= 3.2mA0.4
µA
V
mV
ms
VVCC ≥ 2.7V, I
VVCC ≥ 2.25V, I
V
VVCC ≥ 2.7V, I
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NORMALIZED RESET THRESHOLD
MAX6421/26 toc07
TRANSIENT DURATION (s)
RESET TIMEOUT PERIOD (
RESET TIMEOUT PERIOD (ms)
RESET TIMEOUT PERIOD (ms)
MAX6340/MAX6421–
MAX6426
Typical Operating Characteristics
(VCC = 5V, C
= 1500pF, TA = +25°C, unless otherwise noted.)
SRT
Low-Power, SC70/SOT µP Reset Circuits
with Capacitor-Adjustable Reset Timeout Delay
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
SUPPLY CURRENT (µA)
1.0
0.5
0
0213456
TA = +125°C
TA = +25°C
SUPPLY VOLTAGE (V)
RESET TIMEOUT PERIOD
vs. TEMPERATURE
600
550
µs)
500
450
400
350
300
250
200
-50025-25
50
TEMPERATURE (°C)
TA = -40°C
C
= 0
SRT
75 100 125
MAX6421/26 toc01
MAX6421/26 toc04
RESET TIMEOUT PERIOD vs. C
10,000
1000
100
10
1
0.1
0.0010.10.01110
C
(nF)
SRT
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
175
150
125
100
RESET OCCURS
75
ABOVE THE CURVE
50
25
0
04002006008001000
RESET THRESHOLD OVERDRIVE (mV)
100
VTH = 2.95V
SRT
MAX6421/26 toc02
1000
MAX6421/26 toc05
RESET TIMEOUT PERIOD
vs. TEMPERATURE
4.30
4.25
4.20
4.15
4.10
-500-2525 50 75 100 125
TEMPERATURE (°C)
C
VCC TO RESET DELAY
vs. TEMPERATURE (V
160
VCC FALLING AT 1mVs
150
140
130
120
110
TO RESET DELAY Sµs)
CC
100
V
90
80
-50025-25
TEMPERATURE (°C)
CC
50
FALLING)
75 100 125
SRT
= 1500pF
MAX6421/26 toc03
MAX6421/26 toc06
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1V/div
1V/div
POWER-UP/POWER-DOWN
CHARACTERISTIC
V
CC
RESET
400s/div
VTH = 1.6V
NORMALIZED RESET THRESHOLD
vs. TEMPERATURE
1.006
1.004
1.002
1.000
0.998
0.996
0.994
-5025 50-25 075 100 125
TEMPERATURE (°C)
MAX6421/26 toc08
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MAX6340/MAX6421–
MAX6426
with Capacitor-Adjustable Reset Timeout Delay
Low-Power, SC70/SOT µP Reset Circuits
Pin Description
PIN
MAX6421
MAX6422
MAX6423
SOT23SOT143SC70SOT23SOT23
13351SRT
21232, 3GNDGround
3——4—N.C.Not Internally Connected. Can be connected to GND
42125V
5
44
———RESET
MAX6424
MAX6425
14RESET
MAX6426
NAMEFUNCTIONMAX6340
Set Reset Timeout Input. Connect a capacitor between
SRT and ground to set the timeout period. Determine the
period as follows: tRP = 2.73 × 106 × C
CC
tRP in seconds and C
Supply Voltage and Reset Threshold Monitor Input
RESET changes from high to low whenever VCC drops
below the selected reset threshold voltage. RESET
remains low for the reset timeout period after VCC exceeds
the reset threshold
RESET changes from low to high whenever VCC drops
below the selected reset threshold voltage. RESET
remains high for the reset timeout period after VCC
exceeds the reset threshold
SRT
in farads
+ 275µs with
SRT
Detailed Description
Reset Output
The reset output is typically connected to the reset input of
a µP. A µP’s reset input starts or restarts the µP in a known
state. The MAX6340/MAX6421–MAX6426 µP supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout
conditions (see Typical Operating Characteristics).
RESET changes from high to low whenever VCC drops
below the threshold voltage. Once VCC exceeds the
threshold voltage, RESET remains low for the capacitor-adjustable reset timeout period.
The MAX6422 active-high RESET output is the inverse
logic of the active-low RESET output. All device outputs
are guaranteed valid for VCC > 1V.
The MAX6340/MAX6423/MAX6425/MAX6426 are opendrain RESET outputs. Connect an external pullup resistor
to any supply from 0 to 5.5V. Select a resistor value large
enough to register a logic low when RESET is asserted
and small enough to register a logic high while supplying all input current and leakage paths connected to the
RESET line. A 10kΩ to 100kΩ pullup is sufficient in most
applications.
3.3V
V
CC
LASER-TRIMMED
RESISTORS
V
REF
RESET
SRT
C
SRT
Figure 1. MAX6340/MAX6423/MAX6425/MAX6426 Open-Drain
RESET Output Allows Use with Multiple Supplies
TIMEOUT
MAX6340
MAX6423
MAX6425
MAX6426
RESET
N
GND
10kΩ
5.0V
5V
SYSTEM
Selecting a Reset Capacitor
The reset timeout period is adjustable to accommodate
a variety of µP applications. Adjust the reset timeout
period (tRP) by connecting a capacitor (C
SRT and ground. Calculate the reset timeout capacitor
as follows:
) between
SRT
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Page 5
MAX6340/MAX6421–
MAX6426
C
= (tRP - 275µs) / (2.73 5 106)
SRT
where tRP is in seconds and C
The reset delay time is set by a current/capacitor-controlled ramp compared to an internal 0.65V reference. An
internal 240nA ramp current source charges the external
capacitor. The charge to the capacitor is cleared when a
reset condition is detected. Once the reset condition is
removed, the voltage on the capacitor ramps according to
the formula: dV/dt = I/C. The C
0.65V to deassert the reset. C
(<10nA) type capacitor; ceramic is recommended.
Operating as a Voltage Detector
The MAX6340/MAX6421–MAX6426 can be operated in
a voltage detector mode by floating the SRT pin. The
reset delay times for VCC rising above or falling below the
threshold are not significantly different. The reset output
is deasserted smoothly without false pulses.
V
DD
MAX6340
MAX6423
MAX6425
MAX6426
RESET
N
GND
is in farads.
SRT
capacitor must ramp to
SRT
must be a low-leakage
SRT
V
CC
10kΩ
µP
RESET
with Capacitor-Adjustable Reset Timeout Delay
Low-Power, SC70/SOT µP Reset Circuits
Applications Information
Interfacing to Other Voltages for Logic
Compatibility
The open-drain outputs of the MAX6340/MAX6423/
MAX6425/MAX6426 can be used to interface to µPs with
other logic levels. As shown in Figure 1, the open-drain
output can be connected to voltages from 0 to 5.5V. This
allows for easy logic compatibility to various µPs.
Wired-OR Reset
To allow auxiliary circuitry to hold the system in reset,
an external open-drain logic signal can be connected
to the open-drain RESET of the MAX6340/MAX6423/
MAX6425/MAX6426, as shown in Figure 2. This configuration can reset the µP, but does not provide the reset
timeout when the external logic signal is released.
Negative-Going VCC Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervisors
are relatively immune to short-duration negative-going transients (glitches). The graph Maximum Transient
Duration vs. Reset Threshold Overdrive in the Typical Operating Characteristics shows this relationship.
The area below the curve of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative-going
pulse applied to VCC, starting above the actual reset
threshold (VTH) and ending below it by the magnitude
indicated (reset-threshold overdrive). As the magnitude of
the transient decreases (farther below the reset threshold), the maximum allowable pulse width decreases.
Typically, a VCC transient that goes 100mV below the
reset threshold and lasts 50µs or less does not cause a
reset pulse to be issued.
OPEN-DRAIN
LOGIC
N
Figure 2. Wired-OR Reset Circuit
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Ensuring a Valid RESET or RESET
Down to VCC = 0
When VCC falls below 1V, RESET/RESET current-sinking
(sourcing) capabilities decline drastically. In the case of
the MAX6421/MAX6424, high-impedance CMOS-logic
inputs connected to RESET can drift to undetermined
voltages. This presents no problems in most applications,
since most µPs and other circuitry do not operate with
VCC below 1V.
In those applications where RESET must be valid down
to zero, adding a pulldown resistor between RESET
and ground sinks any stray leakage currents, holding
RESET low (Figure 3). The value of the pulldown resis-
tor is not critical; 100kΩ is large enough not to load
RESET and small enough to pull RESET to ground. For
applications using the MAX6422, a 100kΩ pullup resis-
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Page 6
MAX6340/MAX6421–
MAX6426
Low-Power, SC70/SOT µP Reset Circuits
with Capacitor-Adjustable Reset Timeout Delay
V
CC
V
CC
MAX6421
MAX6424
RESET
GND
100k
Figure 3. Ensuring RESET Valid to VCC = 0
V
CC
100k
MAX6422
GND
V
RESET
CC
Figure 4. Ensuring RESET Valid to VCC = 0
tor between RESET and VCC holds RESET high when
VCC falls below 1V (Figure 4). Open-drain RESET versions are not recommended for applications requiring
valid logic for VCC down to zero.
Layout Consideration
SRT is a precise current source. When developing the
layout for the application, be careful to minimize board
capacitance and leakage currents around this pin. Traces
connected to SRT should be kept as short as possible.
Traces carrying high-speed digital signals and traces with
large voltage potentials should be routed as far from SRT
as possible. Leakage current and stray capacitance (e.g.,
a scope probe) at this pin could cause errors in the reset
timeout period. When evaluating these parts, use clean
prototype boards to ensure accurate reset periods.
Note: The MAX6340/MAX6421–MAX6426 are available with factory-trimmed
reset thresholds from 1.575V to 5.0V in approximately 0.1V increments.
Insert the desired nominal reset threshold suffix (from Table 1) into the
blanks. There are 50 standard versions with a required order increment
of 2500 pieces. Sample stock is generally held on standard versions
only (see Standard Versions Table). Required order increment is
10,000 pieces for nonstandard versions. Contact factory for availability.
All devices are available in tape-and-reel only.
Devices are available in both leaded and lead-free packaging.
“+” Denotes Lead(Pb)-free packages and “-” denotes leaded packages.
For top mark information, please go to https://www.maximinte-
grated.com/en/design/packaging/topmark/
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
4 SC70X4+121-009890-0187
4 SOT143U4+121-005290-0183
5 SOT23U5+221-005790-0174
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Chip Information
TRANSISTOR COUNT: 295
PROCESS: BiCMOS
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MAX6340/MAX6421–
MAX6426
with Capacitor-Adjustable Reset Timeout Delay
Low-Power, SC70/SOT µP Reset Circuits
Revision History
REVISION
NUMBER
53/14Added /V OPN to Ordering Information1
612/15
71/16
89/16Updated Table 16
93/18Updated Ordering Information table9
REVISION
DATE
DESCRIPTION
Added lead-free part numbers to Ordering Information table and removed top
mark information from Standard Versions table
Changed MAX6340UK_ _/V-T to MAX6340UK_ _/V+T in Ordering Information table
PAGES
CHANGED
1, 8
9
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.