Maxim Integrated MAX32600 User Manual

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Page 1

MAX32600

User’s Guide

April 2015

Page 2

MAX32600 User’s Guide Contents Contents

Contents

1 Main Page 2

1.1 Legal Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Revision Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Introduction 4

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Core and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Core Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.2 Generic Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.3 AHB Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.4 APB Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.5 Nested Vectored Interrupt Controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.6 ARM Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Power Supplies and Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 Digital Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.2 Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.3 Onboard Core Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.4 Onboard VUSB Voltage Regulator and Automatic Power Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.5 VRTC Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.6 Power Management Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.7 Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.1 External High Frequency Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.2 32kHz Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.3 48MHz USB Clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.4 Internal 24MHz Trimmed Relaxation Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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2.4.5 Cryptographic Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.1 Internal Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.2 2 KB Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.3 Internal Data SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.4 Peripheral Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.5 Flash Information Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.6 Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6 Analog Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.1 16-Bit ADC with PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.2 ADC/DAC Internal/External Reference and Programmable Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.3 12-Bit Voltage Output DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.4 8-Bit Voltage Output DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.5 Uncommitted Op Amps with Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.6 Uncommitted SPST Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.7 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7 Digital Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7.1 GPIO Pins w/Interrupt and Wakeup Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7.2 32-Bit Timer/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7.3 Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7.4 32-Bit Real Time Clock with Time of Day Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.5 SPI (three instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.6 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.7 USB 2.0 Device Slave with Integrated Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7.8 LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.8 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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2.8.1 Trust Protection Unit (TPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.8.2 AES Cryptographic Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.8.3 Battery-Backed AES Secure Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.8.4 Modular Arithmetic Accelerator (MAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.8.5 CRC Hardware Block with CRC16 and CRC32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.8.6 Code Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Memory, Register Mapping, and Access 23

3.1 Memory, Register Mapping, and Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Standard Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.1 Code Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.2 SRAM Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.3 Peripheral Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.4 External RAM Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.5 External Device Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.6 System Area (Private Peripheral Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.7 System Area (Vendor Deﬁned) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3 Device Memory Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3.1 Main Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.2 Instruction Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.3 Information Block Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.4 System SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.5 AES Key and Working Space Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.6 Modular Arithmetic Accelerator (MAA) Key and Working Space Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.7 TPU Memory Secure Key Storage Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4 AHB Bus Matrix and AHB Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.1 Core AHB Interface - I-Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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3.4.2 Core AHB Interface - D-Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.3 Core AHB Interface - System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.4 AHB Master - Peripheral Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.5 AHB Master - USB Endpoint Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 System Conﬁguration and Management 29

4.1 Power Ecosystem and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.1 Power Ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.2 Low Power Modes (LP0: STOP and LP1: STANDBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.2.1 Low Power Mode 0 (LP0: STOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.2.2 Low Power Mode 1 (LP1: STANDBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.2.3 Entering LP0: STOP or LP1: STANDBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.2.4 Wakeup Events from LP0: STOP and LP1: STANDBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.3 Low Power Modes (LP2: PMU and LP3: RUN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.3.1 Low Power Mode 2 (LP2: Peripheral Management Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.3.2 Low Power Mode 3 (LP3: RUN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.4 Power State Matrix Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.5 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.1.6 Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.7 Power Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.7.1 Power Mode Transitioning to Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.7.2 Supply Voltage Monitoring During LP0: STOP and LP1: STANDBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.7.3 SVM Periodic Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.1.7.4 First Boot Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.1.7.5 Brownout Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.1.8 Trickle Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.1.8.1 Trickle Charger Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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4.1.9 Low-Dropout Regulators (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1.9.1 1.8V LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1.9.2 3.3V USB LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1.10 Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.1.11 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.1.12 Registers (PWRMAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.1.12.1 Module PWRMAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.1.13 Registers (PWRSEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.1.13.1 Module PWRSEQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.2 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.3 Resets and Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.3.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.3.2 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.3.3 RTC POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.4 Registers (IOMAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.4.1 Module IOMAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.4.1.1 IOMAN_WUD_REQ0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.4.1.2 IOMAN_WUD_REQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.4.1.3 IOMAN_WUD_ACK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.4.1.4 IOMAN_WUD_ACK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.4.1.5 IOMAN_ALI_REQ0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.4.1.6 IOMAN_ALI_REQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.4.1.7 IOMAN_ALI_ACK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.4.1.8 IOMAN_ALI_ACK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

4.4.1.9 IOMAN_SPI0_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4.4.1.10 IOMAN_SPI0_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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4.4.1.11 IOMAN_SPI1_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.4.1.12 IOMAN_SPI1_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.4.1.13 IOMAN_SPI2_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.4.1.14 IOMAN_SPI2_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.4.1.15 IOMAN_UART0_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.4.1.16 IOMAN_UART0_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4.4.1.17 IOMAN_UART1_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

4.4.1.18 IOMAN_UART1_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.4.1.19 IOMAN_I2CM0_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.4.1.20 IOMAN_I2CM0_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.4.1.21 IOMAN_I2CS0_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.4.1.22 IOMAN_I2CS0_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.4.1.23 IOMAN_LCD_COM_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

4.4.1.24 IOMAN_LCD_COM_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

4.4.1.25 IOMAN_LCD_SEG_REQ0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

4.4.1.26 IOMAN_LCD_SEG_REQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

4.4.1.27 IOMAN_LCD_SEG_ACK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

4.4.1.28 IOMAN_LCD_SEG_ACK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.4.1.29 IOMAN_CRNT_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

4.4.1.30 IOMAN_CRNT_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.4.1.31 IOMAN_CRNT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

4.4.1.32 IOMAN_ALI_CONNECT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.4.1.33 IOMAN_ALI_CONNECT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.4.1.34 IOMAN_I2CM1_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

4.4.1.35 IOMAN_I2CM1_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

4.4.1.36 IOMAN_PADX_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

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5 Pin Conﬁgurations, Packages, and Special Function Multiplexing 165

5.1 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.2 Pin Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

5.2.1 Compact Package GPIO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

5.2.2 Standard Package GPIO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.3 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

5.4 GPIO Pins and Peripheral Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

5.5 Registers (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

5.5.1 Module GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

5.5.1.1 GPIO_FREE_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

5.5.1.2 GPIO_OUT_MODE_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

5.5.1.3 GPIO_OUT_VAL_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

5.5.1.4 GPIO_FUNC_SEL_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

5.5.1.5 GPIO_IN_MODE_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

5.5.1.6 GPIO_IN_VAL_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

5.5.1.7 GPIO_INT_MODE_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

5.5.1.8 GPIO_INTFL_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

5.5.1.9 GPIO_INTEN_Pn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

6 Peripheral Management Unit (PMU) 193

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6.2 PMU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.2.1 PMU Channel Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.2.2 PMU Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.3 PMU Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.3.1 PMU Op Code: MOVE (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.3.2 PMU Op Code: WRITE (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

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6.3.3 PMU Op Code: WAIT (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

6.3.4 PMU Op Code: JUMP (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.3.5 PMU Op Code: LOOP (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6.3.6 PMU Op Code: POLL (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

6.3.7 PMU Op Code: BRANCH (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.3.8 PMU Op Code: TRANSFER (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.4 Registers (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.4.1 Module PMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.4.1.1 PMUn_DSCADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

6.4.1.2 PMUn_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

6.4.1.3 PMUn_LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

6.4.1.4 PMUn_OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

6.4.1.5 PMUn_DSC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.4.1.6 PMUn_DSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.4.1.7 PMUn_DSC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.4.1.8 PMUn_DSC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

7 Communication Peripherals 216

7.1 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.1.1 I²C Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.1.2 I²C Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.1.3 I²C Port and Pin Conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.1.3.1 Compact Layout (7mm x 7mm) Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.1.3.2 Standard Layout (12mm x 12mm) Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

7.1.4 I²C Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

7.1.5 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

7.1.6 Peripheral Clock Selection and Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

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7.1.6.1 Peripheral Clock Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

7.1.7 Communication and Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.1.7.1 FIFO-Based I²C Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.1.8 Registers (I2CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.1.8.1 Module I2CM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

7.1.9 Registers (I2CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

7.1.9.1 Module I2CS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

7.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

7.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

7.2.2 SPI Port and Pin Conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

7.2.2.1 Compact Layout (7mm x 7mm) Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

7.2.2.2 Standard Layout (12mm x 12mm) Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

7.2.3 Clock Selection and Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

7.2.3.1 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

7.2.4 Conﬁguration Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

7.2.4.1 Static Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

7.2.4.2 Dynamic Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

7.2.5 SPI Fast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

7.2.6 Communication and Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

7.2.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

7.2.8 SPI: FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

7.2.9 Registers (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

7.2.9.1 Module SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

7.3 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.3.2 UART Port and Pin Conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

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7.3.2.1 Compact Layout Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.3.2.2 Standard Layout Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.3.3 Port Register Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

7.3.4 UART Clock Selection and Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

7.3.5 Format and Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

7.3.6 Transferring and Receiving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

7.3.7 UART: Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

7.3.8 Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

7.3.8.1 Clear to Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

7.3.8.2 Ready to Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.3.9 Registers (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.3.9.1 Module UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.4 USB Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

7.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

7.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

7.4.2.1 USB Reset Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

7.4.3 USB Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

7.4.3.1 Endpoint Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

7.4.3.2 Endpoint Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

7.4.4 Registers (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

7.4.4.1 Module USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

8 Analog Front End 340

8.1 AFE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

8.1.1 AFE Analog Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

8.2 AFE Reconﬁguration Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

8.2.1 AFE Reconﬁguration Matrix Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

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8.2.1.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

8.2.1.2 Op Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

8.2.1.3 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

8.2.2 Registers (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

8.2.2.1 Module AFE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

8.3 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

8.3.1 ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

8.3.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

8.3.3 ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

8.3.4 ADC Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

8.3.4.1 Peripheral Clock Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

8.3.4.2 Reference Voltage Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

8.3.4.3 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

8.3.4.4 Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

8.3.4.5 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

8.3.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

8.3.4.7 Programmable Gain Ampliﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

8.3.4.8 Sample Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

8.3.4.9 Start the Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

8.3.5 Registers (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

8.3.5.1 Module ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

8.4 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

8.4.1 DAC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

8.4.2 DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

8.4.3 DAC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

8.4.3.1 Common DAC Conﬁguration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

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8.4.3.2 Individual DAC Conﬁguration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

8.4.3.3 DAC Voltage Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

8.4.4 Additional Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

8.4.4.1 Reduced Power Level Modes for 12-bit DAC Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

8.4.4.2 Correcting for Distortion at High Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

8.4.5 Registers (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

8.4.5.1 Module DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

8.5 LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

8.5.1 LED Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

8.5.1.1 LED Driver Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

8.5.2 LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

8.5.2.1 Basic LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

8.5.2.2 Multiple LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

8.5.2.3 H-bridge LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

8.5.2.4 Independent Loop H-bridge LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

8.5.2.5 Integrated Feedback Loops LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

8.5.2.6 Internal Feedback with Common Sense Resistor LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

8.5.2.7 Double H-bridge LED Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

8.5.2.8 Multiple High Voltage LED Control Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

8.5.2.9 3x3 LED Matrix Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

8.5.3 Register Conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

8.5.3.1 Current Mode Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

8.5.4 Control Loop Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

8.5.5 Fault Detection Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

8.5.6 Timing Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

8.5.7 Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

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8.5.7.1 Design Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

8.5.7.2 Average and Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

9 Pulse Train Engine 489

9.1 Pulse Train Engine (PTE) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

9.2 Output Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

9.3 Pulse Train Peripheral Clock Rate Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

9.4 Enabling and Disabling Pulse Train Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

9.4.1 Master Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

9.4.2 Enabling and Disabling Individual Pulse Train Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

9.5 Pulse Train Engine Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

9.5.1 Pulse Train Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

9.5.2 Square Wave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

9.6 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

9.7 Registers (PT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

9.7.1 Module PT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

9.7.1.1 PTG_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

9.7.1.2 PTG_RESYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

9.7.1.3 PTn_RATE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

9.7.1.4 PTn_TRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

10 System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 498

10.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

10.1.1 System Clocks Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

10.1.1.1 External High-Frequency Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

10.1.1.2 32kHz Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

10.1.1.3 48MHz USB Clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

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10.1.1.4 48MHz Internal 24MHz Trimmed Relaxation Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

10.1.1.5 Cryptographic Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

10.1.2 System Clock Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

10.1.3 System Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

10.1.3.1 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

10.1.3.2 External High Frequency Clock (Crystal or Resonator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

10.1.3.3 External 32kHz Clock (Crystal or Resonator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

10.1.3.4 Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

10.1.3.5 Relaxation Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

10.1.3.6 Crypto Clock Relaxation Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

10.1.4 ADC Clock Source Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

10.1.5 Registers (CLKMAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

10.1.5.1 Module CLKMAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

10.2 Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

10.2.1 Watchdog Timers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

10.2.2 Clock Source Selection and Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

10.2.3 Watchdog Timer Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

10.2.3.1 Locking and Unlocking the Watchdog Timer Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

10.2.3.2 Enabling and Disabling the Watchdog Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

10.2.4 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

10.2.5 Registers (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

10.2.5.1 Module WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

10.3 Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

10.3.1 Real Time Clock Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

10.3.1.1 Real Time Clock Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

10.3.2 RTC Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

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10.3.3 RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

10.3.4 RTC Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

10.3.5 Registers (RTCTMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

10.3.5.1 Module RTCTMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

10.3.6 Registers (RTCCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

10.3.6.1 Module RTCCFG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

10.4 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

10.4.1 Timers/Counters Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

10.4.2 32-bit Mode Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

10.4.2.1 One-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

10.4.2.2 Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

10.4.2.3 Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

10.4.2.4 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

10.4.2.5 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

10.4.2.6 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

10.4.2.7 Gated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

10.4.2.8 Capture/Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

10.4.3 16 bit Mode Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

10.4.3.1 One-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

10.4.3.2 Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

10.4.4 Registers (TMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

10.4.4.1 Module TMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

11 Trust Protection Unit (TPU) 608

11.1 AES Cryptographic Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

11.1.1 Registers (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

11.1.1.1 Module AES Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

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11.2 Modular Arithmetic Accelerator (MAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

11.2.1 Registers (MAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

11.2.1.1 Module MAA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

11.3 Registers (TPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

11.3.1 Module TPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

11.3.1.1 TPU_PRNG_USER_ENTROPY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

11.3.1.2 TPU_PRNG_RND_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

11.3.1.3 TPU_TSR_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

11.3.1.4 TPU_TSR_CTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

11.3.1.5 TPU_TSR_CTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

11.3.1.6 TPU_TSR_SKS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

11.3.1.7 TPU_TSR_SKS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

11.3.1.8 TPU_TSR_SKS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

11.3.1.9 TPU_TSR_SKS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

12 CRC16 and CRC32 Hardware Accelerator 631

12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

12.2 CRC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

12.3 CRC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

12.4 CRC-16-CCITT Example Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

12.5 CRC-32 Example Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

12.6 Registers (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

12.6.1 Module CRC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

12.6.1.1 CRC_RESEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

12.6.1.2 CRC_SEED16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

12.6.1.3 CRC_SEED32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

12.6.1.4 CRC_DATA_VALUE16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

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12.6.1.5 CRC_DATA_VALUE32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

13 LCD Controller 635

13.1 LCD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

13.2 LCD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

13.3 LCD Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

13.3.1 LCD Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

13.3.2 LCD Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

13.3.3 LCD Conﬁguration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

13.3.4 LCD Internal Register Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

13.3.5 LCD Port Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

13.3.6 LCD Memory Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

13.4 Registers (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

13.4.1 Module LCD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

13.4.1.1 LCD_LCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

13.4.1.2 LCD_LCRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

13.4.1.3 LCD_LPCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

13.4.1.4 LCD_LCADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

13.4.1.5 LCD_LCDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

13.4.1.6 LCD_LPWRCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

14 Flash Controller and Instruction Cache 650

14.1 Registers (FLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

14.1.1 Module FLC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

14.1.1.1 FLC_FADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

14.1.1.2 FLC_FCKDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

14.1.1.3 FLC_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

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MAX32600 User’s Guide Contents Contents

14.1.1.4 FLC_INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

14.1.1.5 FLC_FDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

14.1.1.6 FLC_PERFORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

14.1.1.7 FLC_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

14.1.1.8 FLC_SECURITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

14.1.1.9 FLC_BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

14.1.1.10 FLC_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

14.1.1.11 FLC_CTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

14.1.1.12 FLC_INTFL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

14.1.1.13 FLC_INTEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

14.1.1.14 FLC_DISABLE_XR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

14.1.1.15 FLC_DISABLE_XR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

14.1.1.16 FLC_DISABLE_XR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

14.1.1.17 FLC_DISABLE_XR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

14.1.1.18 FLC_DISABLE_WE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

14.1.1.19 FLC_DISABLE_WE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

14.1.1.20 FLC_DISABLE_WE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

14.1.1.21 FLC_DISABLE_WE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

14.2 Registers (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

14.2.1 Module ICC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

14.2.1.1 ICC_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

14.2.1.2 ICC_MEM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

14.2.1.3 ICC_CTRL_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

14.2.1.4 ICC_INVDT_ALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Rev.1.3 April 2015 Maxim Integrated Page 1

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MAX32600 User’s Guide Main Page

1 Main Page

1.1 Legal Disclaimer

LIFE SUPPORT POLICY

MAXIM’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF MAXIM INTEGRATED PRODUCTS, INC.

As used herein

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a signiﬁcant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

Document Disclaimer

©2015 by Maxim Integrated, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. MAXIM INTEGRATED PRODUCTS, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTAT− ION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. MAXIM ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HER− EIN OR OTHERWISE. The information contained within this document has been veriﬁed according to the general principles of electrical and mechanical engineering or registered trademarks of Maxim Integrated Products, Inc. All other product or service names are the property of their respective owners.

2015 Maxim Integrated

1.2 Revision Information

Version Section Changes

1.2 Initial Public Release

1.3 2.2.6 Added the JTAG TAP device ID value.

4.4.1.36 IOMAN_PADX_CONTROL: Changed "three-state" to "High Impedance" when describing pin driver output states.

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MAX32600 User’s Guide Main Page 1.2 Revision Information

Version Section Changes

6.4.1.3 PMUn_LOOP: Corrected descriptions for counter_0 and counter_1 ﬁelds.

8.2.1 Graphic and label corrections to Figures 8.1, 8.2, 8.3, and 8.4.

8.2.2.1.4 AFE_CTRL2: Corrected ﬁeld and value descriptions for dacout_en0, dacout_en1, dacout_en2, and dacout_en3.

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Page 22

MAX32600 User’s Guide Introduction

2 Introduction

The MAX32600 User Guide is targeted to hardware, embedded ﬁrmware and application developers. This guide provides information on how to use and conﬁgure and use the MAX32600 memory, peripherals and registers. For ordering information, complete feature sets, package information, and electrical speciﬁcations, refer to the MAX32600 data sheet.

2.1 Overview

The MAX32600 is a low-power, mixed-signal microcontroller that variety of applications, including integration in wearable medical devices, pulse oximetry measurement, galvanic skin response measurement, and blood glucose metering. It is based on the ARM Cortex-M3 32-bit core targeted for a maximum operating frequency of 24MHz.

Application code on the MAX32600 runs from an onboard program ﬂash memory (64 KB to 256 KB), with 16 KB to 32 KB SRAM available for general application use. A 2 KB instruction cache improves execution throughput, and a transparent code scrambling interface is used to protect customer intellectual property residing in the program ﬂash memory.

Key analog peripherals on the MAX32600 include a 16-bit ADC with an onboard PGA/MUX front end. This ADC is designed to accept inputs from up to sixteen single-ended pins or eight differential pairs. For analog output functions, there are two 12-bit voltage output DACs, two 8-bit voltage output DACs, four uncommitted op amps, four SPST switches, and four uncommitted ground switches.

The MAX32600 includes a wide variety of digital communications and interface peripherals. An onboard LCD controller (available on the standard 12mm x 12mm package) can be used to direct drive up to 40 segments. Other communication peripherals include a USB 2.0 slave interface, three SPI master ports, master and slave I2C interfaces, and two UART ports.

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MAX32600 User’s Guide Introduction 2.1 Overview

Figure 2.1: Block Diagram

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MAX32600 User’s Guide Introduction 2.2 Core and Architecture

2.2 Core and Architecture

ARM®Cortex®-M3 Core

The MAX32600 is based on the ARM Cortex-M3 32-bit RISC CPU, which implements the ARMv7-M architectural proﬁle. The implementation of the Cortex-M3 core used in the MAX32600 is targeted for a maximum operating frequency of 24MHz and provides the following features.

• 32-bit data path with mixed 16-bit and 32-bit instructions (Thumb-2 instruction set)

• Single cycle multiplication and hardware-based division operations

• Nested vectored interrupt controller (NVIC) with multiple interrupt priority levels and nested interrupt support

• 4GB total memory space, shared by code memory, data memory, and peripheral registers

• Low power, highly energy efﬁcient core reduces power consumption

• Built-in debug functionality and tracing with JTAG port (connects to internal Debug Access Port)

• Power saving sleep mode(s)

2.2.1 Core Parameters

When the Cortex-M3 core is instantiated in a design, values must be selected for conﬁgurable parameters in the core. For the MAX32600 design, core parameters have been selected as shown below.

Parameter Value Description

NUM_IRQ 48 Number of Interrupts supported by the Cortex-M3

LVL_WIDTH 3 Speciﬁes the number of bits of interrupt priority levels supported. At a width of three, there are

eight levels supported. At a width of eight (the maximum allowed), 256 levels are supported.

MPU_PRESENT 0 The MPU (memory protection unit) is not included on this device.

BB_PRESENT 1 Bit-banding (memory mapped bit) operations are supported on this device.

AHB_CONST_CTRL 1 Speciﬁes whether the external AHB-Lite buses maintain control information during wait stated

transfers.

DEBUG_LVL 3 Full debug with data matching. All debug functionality is present including data matching for

watchpoint generation.

TRACE_LVL 0 Standard trace. ITM, TPIU, and DWT triggers and counters are present. ETM and HTM port

are not present.

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MAX32600 User’s Guide Introduction 2.2 Core and Architecture

Parameter Value Description

RESET_ALL_REGS 1 Registers are set to a known reset state.

JTAG_PRESENT 1 JTAG Debug Access Port is included on this design.

CLKGATE_PRESENT 1 Architectural gates are included to minimize dynamic power dissipation.

OBSERVATION 0 Additional features to observe processor internal state are not included.

WIC_PRESENT 0 The Wakeup Interrupt Controller (WIC) block is included on this design.

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MAX32600 User’s Guide Introduction 2.2 Core and Architecture

2.2.2 Generic Memory Map

Figure 2.2: Memory Map

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MAX32600 User’s Guide Introduction 2.2 Core and Architecture

2.2.3 AHB Buses

The standard ARM Advanced High Performance Bus (AHB-Lite version) is used for several different system bus masters on the MAX32600. All buses are 32-bits in width.

• I-Code: Performs instruction fetches from internal code memory regions. On the MAX32600, accesses to internal program ﬂash memory (for instruction

decoding purposes) are cached to improve execution throughput.

• D-Code: Performs data fetches from program ﬂash memory; this includes literal local constant fetches. These data fetches are not cached, unlike instruction

code fetches.

• System: Performs data read/write and bit-band operations on internal SRAM, and data read/write operations on peripherals (including bit-band operations)

and vendor deﬁned expansion devices in the system area.

Note Bit-band operations are translated internally by the ARM core into a read-modify-write sequence. Only the core itself (when performing instruction

execution) can read or write to locations using the bit-banding function. The bit-banding alias areas, although they are shown on the memory map, do not exist as separate logical mapped areas; they cannot be accessed by other AHB masters (e.g., the DMA master or the JTAG/PTP master), since they do not exist at this layer.

2.2.4 APB Buses

The External PPB (private peripheral bus) is a 32-bit bus based on the APB (Advanced Peripheral Bus) standard. It is intended for adding components to the private peripheral bus area which are not intended for general application use, since privileged operating mode is required to access this area. The MAX32600 does not currently map any non-core components to this bus area.

The majority of the digital and analog peripherals on the MAX32600 are controlled by registers that are memory mapped into the Peripheral region from address 0x4000_0000 to 0x400F_FFFF (in the bit-banding enabled region). These peripherals are connected to the CPU core using a lower-speed APB peripheral bus (connected to the System AHB-Lite bus through an AHB-to-APB bridge).

Peripherals which require higher speed access for large data transfers have control/buffer regions mapped to the AHB bus from address 0x4010_0000 to 0x401F_− FFFF. These regions are designed to allow more rapid data transfer directly through the AHB bus, without having to go through the AHB-to-APB bridge. Peripherals using this type of interface include SPI, I2C, DAC, ADC, AES, Micro MAA, CRC and USB.

2.2.5 Nested Vectored Interrupt Controller (NVIC)

The MAX32600 includes the standard Nested Vectored Interrupt Controller (NVIC) as implemented for the Cortex-M3 ARM core. The NVIC supports high-speed, deterministic interrupt response, interrupt masking, and multiple interrupt sources. External interrupts support rising or falling edge trigger mode as well as level triggered mode.

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MAX32600 User’s Guide Introduction 2.3 Power Supplies and Modes

With the core instantiation parameters given above, the NVIC will support up to 48 distinct interrupt sources (including internal and external interrupts), with programmable interrupt priority of eight priority levels (3-bit width).

2.2.6 ARM Debug

The MAX32600 includes the standard JTAG debug engine as implemented for the Cortex-M3 ARM core. The JTAG TAP interface is supported, but the serial wire interface is not.

Since this is a standard ARM core component, it is instantiated ‘as-is’ along with the rest of the Cortex-M3 core and cannot be modiﬁed to support special requirements for the MAX32600 design. Accordingly, there are two separate JTAG TAP engines on the MAX32600 - the ARM Debug JTAG and the Maxim Test JTAG. The two JTAG TAP ports share the same pins; the TSEL pin is used to switch access between the two of them.

The JTAG TAP device address for the MAX32600 is 0x4BA00477.

Standard features supported by the ARM JTAG debug engine include the ability to set up to six breakpoints and two watchpoints, access main system memory and peripheral registers even when the CPU is running, and pause, trace, or reset the CPU. Because the debug engine is coupled to the CPU only for clocking and reset purposes, if the debug engine pauses the CPU it is important to note that other peripherals and functions on the MAX32600 are not paused and continue to operate normally.

2.3 Power Supplies and Modes

2.3.1 Digital Supply Voltages

The MAX32600 operates from a main digital supply voltage of 1.8V to 3.6V (VDD). For portable electronic systems, this supply is typically provided by a battery. Generated supplies V powered/connected. V

and V

DDIO

is externally available to power GPIO and GPIO-multiplexed peripheral I/O. V

DDIO

are switched automatically to draw from V

REG18

when the USB power supply is present, and from VDDwhen USB is not

DDB

is internally regulated to 1.8V and provides power to

REG18

the digital core; it is also an external option to power GPIO. The POR, power-fail reset, and power fail warning functions all operate from the switched digital supply.

LCD outputs operate from their own dedicated boost converter output rail (V

LCD

2.3.2 Analog Supply Voltage

The analog functions on the MAX32600 (such as the ADC, DACs, operational ampliﬁers, and SPST switches) operate from a separate analog supply voltage rail which may vary from 2.3V to 3.6V (V is disconnected/unpowered). Four secondary analog power supplies (V

). This supply is switched automatically and is provided from either V

DDA3

DD3ADC

, V

DDA3ADC

, V

DDA3DAC

, V

DDA3REF

(when USB is present) or VDD(when USB

DDB

) are normally derived from V

. This topology

DDA3

enables optional external ﬁltering circuits.

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MAX32600 User’s Guide Introduction 2.3 Power Supplies and Modes

2.3.3 Onboard Core Voltage Regulator

The MAX32600 includes a dedicated onboard digital supply voltage regulator with a 1.8V nominal output voltage (V a ﬁxed low-voltage digital supply for the internal CPU core. This regulator derives its voltage output from the main digital supply voltage (VDD) or V

). This internal regulator is used to provide

REG18

DDB

when USB is

present.

2.3.4 Onboard VUSB Voltage Regulator and Automatic Power Switching

The MAX32600 includes a second onboard digital supply voltage regulator which is used when a powered USB bus has been connected to the device. This regulator takes the 5V (typical) supply from V from the external digital supply voltage to the V

and regulates it down to a nominal 3.3V output. Automatic power switching features allow the device to switch automatically

BUS

-derived 3.3V supply voltage when USB power is available. This ensures that when the device is connected

BUS

to USB, it uses the power supply available from that source, instead of running from the normal digital supply which will typically be a battery supply for portable applications.

2.3.5 VRTC Power Supply

A dedicated power supply is used to maintain the state and operation of the most critical components and memories, which can remain powered even when the rest of the device is shut down in the lowest possible power savings modes. The V used to wake the MAX32600 after a preset time interval) even when everything else has been powered down. The V

supply ensures that the Real Time Clock can continue running (and can be

RTC

supply is also used to maintain certain

RTC

critical battery-backed areas, such as the power sequencer and associated control registers, the tamper-detect-wiped "key of keys", and certain analog trim shadow registers.

2.3.6 Power Management Modes

Power management modes supported by the device include stop, standby, and active (PMU and run) modes. These four power modes are: LP0: STOP; LP1:

STANDBY; LP2: PMU; and LP3: RUN. The Wakeup Interrupt Controller (WIC) can be used to wake the device from power saving modes.

Individual power down and clock gating controls are provided as well. This allows user application-speciﬁc reductions in power consumption by disabling/powering down functions that are not currently in use.

2.3.7 Power Supply Monitoring

Several programmable supply voltage monitors are provided, which allow a power fail warning interrupt and/or a system reset to be triggered when the supply voltage drops below a preset level (depending on the type of power supply and ﬁrmware settings). Supply voltage monitors are available to measure the following supplies: V

, V

DDA3

RTC

, V

REG18

, and V

DD3

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MAX32600 User’s Guide Introduction 2.4 Clock Inputs

2.4 Clock Inputs

Conﬁguration of time delays are necessary to ensure that the MAX32600 always switches to a valid clock; reference the Clocks and Timers section for detailed information.

2.4.1 External High Frequency Crystal

The MAX32600 includes a high-frequency crystal oscillator circuit designed to operate with an external crystal. Fundamental mode crystals can be used with the oscillator circuit up to a frequency of 24MHz. External load capacitors are required depending on the crystal speciﬁcations.

An external clock source may also be used by the MAX32600 in place of a high-frequency crystal. For this conﬁguration, the external clock source (which must meet the electrical/timing requirements given in the datasheet) is connected to the part on the HFXIN pin and the HFXOUT pin is left ﬂoating.

2.4.2 32kHz Crystal Oscillator

A 32kHz crystal oscillator (with the 32kHz crystal connected between the 32KIN and 32KOUT pins) is used to generate the 32kHz clock that is used by the Real Time Clock module.

An external clock source may also be used by the MAX32600 in place of a 32kHz crystal. For this conﬁguration, the external clock source (which must meet the electrical/timing requirements given in the datasheet) is connected to the part on the 32KIN pin.

2.4.3 48MHz USB Clock PLL

The phase locked loop (PLL) clock generation circuit is used to generate a 48MHz clock which is required for proper operation of the USB device interface. If the USB interface will not be used, then use of the PLL is optional.

The PLL generates a 48MHz clock using a clock multiplier circuit, which has a 2X mode for use with a 24MHz crystal, a 4X mode for use with a 12MHz crystal, and a 6X mode for use with an 8MHz crystal. The output of the PLL can be used as a system clock source (after dividing it by two) with a 24MHz frequency.

2.4.4 Internal 24MHz Trimmed Relaxation Oscillator

An internal trimmed relaxation oscillator generates a 24MHz ( ± 1%) clock which can be used as a system clock source. If the USB interface will be used, the PLL is used to generate a 48MHz ( ± 0.25%) clock. The input clock to the PLL can be an external crystal, an external digital clock source, or the internal relaxation oscillator can be used if a 32kHz crystal is available to frequency trim the relaxation oscillator.

For optimal performance, the ADC requires a more stable clock source (with less jitter) than can be provided by the relaxation oscillator; the high frequency crystal oscillator must be used as a system clock source when the ADC is in use. However, in lower sample rate applications, the relaxation oscillator can be used as the ADC clock source.

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MAX32600 User’s Guide Introduction 2.5 Memory

2.4.5 Cryptographic Internal Oscillator

To reduce opportunities for timing-based analysis and fault injection (clock interference) attacks targeting the cryptographic and security functions of the device (such as the AES cryptographic engine, the uMAA, and other related functions), a dedicated on-chip oscillator is provided on the MAX32600 which can be used to supply a separate, isolated clock for use by these functions.

Decoupling these functions from the main system clock allows encryption and decryption operations to take a constant amount of time regardless of the current system clock rate, and also provides a more variable (and not externally observable) clock to reduce the opportunity for an attacker to perform power or timing analysis attacks against the cryptographic and security functions.

2.5 Memory

2.5.1 Internal Flash Program Memory

The MAX32600 includes from 64 KB to 256 KB (depending on the speciﬁc device production option) of internal ﬂash program memory. Internally, the ﬂash memory has a width of 64-bits. Flash memory must thus be programmed one 64-bit location at a time, which requires two programming operations of 32-bits each. The ﬂash is divided into logical pages; when erasing the ﬂash, it is possible to erase either a single page (page erase) or the entire ﬂash array (mass erase) in one operation.

For read access, the program ﬂash memory is mapped into the standard code space region beginning at address 0x0000_0000. Modifying the ﬂash memory array (either program or erase operations) is handled by the ﬂash controller peripheral.

The ﬂash controller also provides the ability to directly program a ﬂash location by writing a 32-bit value to the proper memory location using the AHB bus (as opposed to setting up the operation directly using the appropriate ﬂash controller peripheral registers). Whether the write operation is triggered by an AHB memory write or by writing a control sequence to the ﬂash controller registers, the same security and operational restrictions apply in either case. The operation proceeds in the same manner in both cases regardless of the method that was used to trigger it.

The beginning of program ﬂash memory (starting at address 0x0000_0000) is also the default location for the ARM exception/interrupt vector table. Since this table contains initialization information such as the reset vector address which is required for the system to properly initialize, this table must be loaded into the ﬂash in order for the MAX32600 to execute any application code.

The MAX32600 supports multiple size options for the ﬂash memory within the maximum possible space of 256 KB. The actual size of the memory is controlled by a trim option loaded from the ﬂash information block. When a size smaller than the maximum one is being used, the ﬂash controller will respond to attempts to access out-of-range addresses within the 256 KB range by setting an interrupt ﬂag and returning a ﬁxed "invalid access" data result pattern.

2.5.2 2 KB Instruction Cache

The 2 KB (512 x 32 or 256 x 64) instruction cache is used to cache the content of recently accessed locations in the program ﬂash array to improve execution throughput. Instruction fetches go to the instruction cache, which either returns the previously cached data (cache hit) or fetches the requested data from the ﬂash (cache miss) and stores it for future access.

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MAX32600 User’s Guide Introduction 2.5 Memory

Fetches between the instruction cache and the ﬂash memory go through the code descrambler, so that the content stored in the instruction cache has already been descrambled.

Code access to the internal data SRAM is not cached; instruction fetches from SRAM are always performed directly. Data fetches (D-Code, as opposed to I-Code fetches for the purposes of decoding instructions) are also not cached and are performed directly. This includes fetches of local constant literals that are used by certain ARM instruction op codes.

Firmware has the option to ﬂush the instruction cache manually at any point using a control register. When code mapped into a cached instruction space is updated (for example, if an in-application programming modiﬁcation is made to an executable area of program ﬂash), the cache should be ﬂushed to ensure that the latest version of the code will be accessible and that stale cache contents will not be used instead of the new ﬂash programmed values.

2.5.3 Internal Data SRAM

The internal data SRAM on the MAX32600 ranges from 16 KB to 32 KB in size and has a 32-bit internal width. It is mapped into the SRAM bit-banding access region beginning at address 0x2000_0000, and so it can be read/written either a full 32-bit word at a time, or a single bit at a time using the bit-band alias region (beginning at 0x2200_0000). The bit-banding function can only be used when the data SRAM is being accessed by the ARM core itself, since the ARM core handles the remapping from the bit-banding alias area to a read-modify-write sequence (or single read/mask/shift for a bit read function) of the standard memory area.

The data SRAM can be read or written freely by the application, and can be used for either code or data access. The contents of the data SRAM are not batterybacked. The data SRAM is also used to hold the stack.

The MAX32600 supports multiple SRAM memory sizes within the maximum allowed address space of 32 KB. When a smaller size than the maximum is used (such as 16 KB) attempts to access out-of-range addresses within the 32 KB maximum range will generate an AHB bus error. The effect of this error condition will be determined by the AHB master accessing the bus; for example, the ARM core will respond to this error condition by generating a MemFault system exception. Other bus masters (e.g., the DMA AHB bus master or the JTAG/PTP bus master) may respond differently or ignore the AHB error altogether; the exact results of this condition are determined by the designer of the AHB master interface block.

2.5.4 Peripheral Management Unit (PMU)

The PMU controller on the MAX32600 provides a generalized, ﬂexible mechanism to perform automatic read and/or write sequences to peripherals and areas of internal SRAM memory. The PMU controller includes multiple channels which can be connected to different peripherals or memory areas and is capable of operation during sleep mode.

Peripherals which can be read from or written to using PMU channels (accessing AHB mapped memory areas) include:

• The ADC

• Any of the four DAC instances

• Any of the UART instances

• Any of the SPI instances

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MAX32600 User’s Guide Introduction 2.5 Memory

• Any of the USB endpoint buffers (since they are stored in the main SRAM area)

• The CRC engine

The PMU controller can also be used to read from the program ﬂash memory or any peripheral register area which is normally accessible on the System bus. It does not, however, have access to the USB control register area mapped to the AHB bus.

2.5.5 Flash Information Block

The ﬂash information block on the MAX32600 allows production trim values and other nonvolatile information that will be written during the production process (e.g., device conﬁguration and test details / logging data) to be stored in a separate dedicated instance of internal ﬂash.

The ﬂash information block can be mapped to the AHB bus in the code space area, beginning at byte address location 0x0004_0000 (which is immediately following the maximum possible ﬂash memory address). This address location is constant even if a smaller ﬂash memory size option is being used by the device.

When the ﬂash information block is mapped to this memory region (between 0x0004_0000 and 0x0004_07FF), it can be accessed in the same manner as the main ﬂash; that is, it can be read from in code space (although accesses to it are not cached under any circumstances, and its contents are not subject to the scrambling/descrambling function used by the contents of the main program ﬂash memory). It is possible to write to locations in the ﬂash information block using either direct AHB writes (which will trigger a 32-bit write operation in the ﬂash controller) or by writing the appropriate sequence directly to the ﬂash controller registers.

However, this mapping of the ﬂash information block (and direct read/write access to its contents) is only intended for testing and trimming purposes during the factory production test sequence. Once production test of the MAX32600 has completed (or at least the last stage where trim operations are performed has been completed), a lock option setting will be set in the information block to prevent future modiﬁcations to the trim and option settings (except for those which are explicitly allowed to be set later by the user, such as the DSB access key and the auto-lock security option). Setting the info block lockout setting also removes the information block from the memory map, which means that the only way to view its contents after that point is by reading the copies of the info block settings that have been copied by the hardware into the trim shadow registers (which are mapped to a different area in the APB peripheral region).

The ﬂash controller automatically loads trim and other conﬁguration values from the appropriate locations in the ﬂash information block following any system reset. To prevent misconﬁguration of trim and other option settings in the case of a random (i.e., unprogrammed), blank, or corrupted information block, an "info block valid" ﬁeld is checked by the ﬂash controller before the remaining locations in the information block memory are scanned. If the info block valid ﬁeld (which is the ﬁrst addressed location in the information block array) does not match the predetermined "valid" key value (which is 0x12345678), the information block is presumed to be invalid, and instead of the trim registers being set to copies of the data contained in the information block, they are loaded with predetermined "default" values to prevent undesired or erratic system performance. These default values are designed to allow maximum access (with a minimum of security settings applied) for ease of testing and conﬁguration.

2.5.6 Flash Memory Controller

The ﬂash memory controller on the MAX32600 handles control and timing signals for programming and erase operations on both the main program ﬂash memory array and the ﬂash information block. The ﬂash information block is normally written during production test only, and is not generally intended to be modiﬁed by the

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MAX32600 User’s Guide Introduction 2.6 Analog Peripherals

user application. Two exceptions to this are the Destructive Security Bypass access key value and the Auto-Lock option value, which may be set by the user by means of a special procedure even after access to the rest of the information block has been locked out.

Functions provided by the ﬂash controller for use in normal operation include:

• Mass erase of main program ﬂash array

• Page erase of one page in the main program ﬂash array

• Write to one location (programmed 32-bits at a time) in the main program ﬂash array

• Special one-time writes by the user to the DSB Access Key and/or the Auto-Lock option values in the information block

2.6 Analog Peripherals

2.6.1 16-Bit ADC with PGA

The MAX32600 includes a 16-bit analog-to-digital converter (ADC) with a 16-channel analog input multiplexer, to allow selection of input from one of 16 input lines (single-ended mode) or two of eight input pairs (differential mode). The differential mode supports fully differential signal inputs.

The front end PGA allows programmable gain settings of 1X, 2X, 4X, and 8X before the input sample is converted.

The ADC reference voltage is selectable between V output levels - 1.024V, 1.5V, 2.048V, and 2.5V - based on the 1.23V reference bandgap.

2.6.2 ADC/DAC Internal/External Reference and Programmable Output Buffers

Two programmable reference levels (one used by the ADC, one used by the DACs) are included, and each can be individually set to one of four output levels - 1.024V,

1.5V, 2.048V, and 2.5V.

An external reference can also be provided at the REFADJ pin; if this feature is used, the external reference voltage will be used in place of the 1.23V bandgap output, and the programmable output levels for the ADC and DAC references will shift accordingly.

2.6.3 12-Bit Voltage Output DACs

The MAX32600 includes two 12-bit voltage output DACs (DAC0, DAC1) which output single-ended voltages. The reference used by these DACs is selectable between the DAC reference level and the ADC reference level.

Each DAC instance includes PMU channel access to allow output values to be loaded to the DAC directly from memory.

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and the dedicated ADC reference level. The ADC reference level can be set by software to one of four

AVDD

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MAX32600 User’s Guide Introduction 2.7 Digital Peripherals

2.6.4 8-Bit Voltage Output DACs

The MAX32600 includes two 8-bit voltage output DACs (DAC2, DAC3) which output single-ended voltages. The reference used by these DACs is selectable between the DAC reference level and the ADC reference level.

Each DAC instance includes PMU channel access to allow output values to be loaded to the DAC directly from memory.

2.6.5 Uncommitted Op Amps with Comparator Mode

The MAX32600 contains four uncommitted operational ampliﬁers. Any unused op amp should not be enabled. Each op amp may be switched between ampliﬁer and comparator mode under software control.

Each op amp contains an integrated internal switch that can be used to short the negative/inverting input pin to the output pin of the op amp under software control, putting the op amp in a voltage follower mode. In this conﬁguration, the op amp can be used as an output buffer for any of the four DAC outputs.

Any of the four DAC outputs may optionally be internally connected to the inverting or noninverting inputs of one or more of the four op amps, under software control.

2.6.6 Uncommitted SPST Analog Switches

The device contains four uncommitted SPST analog switches which can be opened and closed under software or pulse train control. All SPST switches are open by default following any reset or power-on reset.

The SPST switches support input voltages from ground to V

2.6.7 Temperature Sensor

The device includes an internal temperature sensor which can be read using the ADC. The MAX32600 also supports a mode for an external temperature sensor.

AVDD

2.7 Digital Peripherals

2.7.1 GPIO Pins w/Interrupt and Wakeup Capability

The device includes up to eight GPIO ports with eight pins per port for a total of 64 GPIO pins. Pins may be multiplexed with digital peripheral functions and/or LCD segment output lines. GPIO pins may be individually switched between GPIO and secondary/tertiary peripheral functions using the appropriate control registers.

All GPIO pins can be conﬁgured individually by ﬁrmware to act as external interrupt sources. All GPIO pins also have the option (which is separate from conﬁguring a GPIO pin to act as an external interrupt source) to be conﬁgured to provide wakeup source inputs to the Wakeup Interrupt Controller (WIC) to wake the device from power-saving modes.

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MAX32600 User’s Guide Introduction 2.7 Digital Peripherals

All GPIO pins support standard I/O operating modes - input/output mode select, strong drive high/low when in output mode, and selection of weak pullup or high impedance (three-state) when in input mode.

Certain GPIO pin pairs have current sink capability that allows them to drive an open drain output (optical LED drive) based on a DAC output.

2.7.2 32-Bit Timer/Counters

The device includes four 32-bit timer/counter modules with the following features:

• 32-bit up/down count with auto reload mode

• One-shot or continuous operation mode

• Programmable 16-bit prescaler

• PWM output generation mode

• Capture/compare modes

• External input pin for timer input, clock gating or capture, limited to an input frequency of 1/4 of the peripheral clock

• Timer output pin

• Timer interrupt

Each 32-bit timer/counter module also has the option to be split into two separate 16-bit timers (dual 16-bit timer mode) for a possible total eight timers in the system. Each 16-bit timer in this pair has the following features:

• 16-bit up/down count with auto reload mode

• One-shot or continuous operation mode

• Programmable 16-bit prescaler (setting is shared by both 16-bit timers in the pair)

• Timer interrupt (separate interrupt for each 16-bit timer in the pair)

2.7.3 Watchdog Timers

The MAX32600 includes two independent watchdog timers (WDT) with window support. The watchdog timers run independently from each other and the processor and have multiple clock source options for ensuring system stability. The watchdog uses a 32-bit timer with prescaler to generate the watchdog reset. When enabled, the watchdog timers must be fed/reset prior to timeout or within a speciﬁed window of time if window mode is enabled. Failure to do so before the watchdog times out will result in a watchdog reset event.

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MAX32600 User’s Guide Introduction 2.7 Digital Peripherals

The ﬁrst watchdog instance (WDT0) can be conﬁgured to trigger a system reset (reset of digital core) when it generates a watchdog reset. The second watchdog instance (WDT1) can be conﬁgured to generate a system reboot (equivalent to digital POR event) when it generates a watchdog reset.

The two watchdogs may be conﬁgured independently to use either the currently selected system clock or an external clock as the watchdog clock source. The external clock is selected separately (in system manager) and is the same for both watchdog instances.

2.7.4 32-Bit Real Time Clock with Time of Day Alarm

A binary real-time clock (RTC) keeps the time of day in absolute seconds with 1/256-second resolution. The 32-bit second counter can count up to approximately 140 years and be translated to calendar format by application software. A time-of-day alarm and independent sub-second alarm can cause an interrupt or wake the device from stop mode.

The independent sub-second alarm runs from the same RTC and allows the application to support interrupts with a minimum interval of approximately 3.9ms. This creates an additional timer that can be used to measure long periods of time without performance degradation.

2.7.5 SPI (three instances)

The integrated SPI controller provides an independent master-mode-only serial communication channel that communicates synchronously with peripheral devices in a single or multiple slave system. Depending on the other peripherals and GPIO pins that are in use by the application, up to two separate SPI ports are available for general use, with a third SPI instance reserved for Bluetooth module communication.

The SPI controllers support half- or full-duplex communications with single, dual, or quad data transmission modes, and can be operated in master mode only.In master mode, the SPI can transfer data at up to 24 MHz depending on the clock source. In addition, the SPI module supports conﬁguration of active SSEL state (active low or active high) through the slave active select. DMA is supported for both the transmit and receive buffers.

2.7.6 I²C

The microcontroller integrates an internal I2C bus master/slave for communication with a wide variety of other I2C-enabled peripherals. The I2C bus is a two-wire, bidirectional bus using a ground line and two bus lines: the serial data line (SDA) and the serial clock line (SCL). Both the SDA and SCL lines must be driven as open-collector/drain outputs. External resistors (RP) are required to pull the lines to a logic-high state.

The device supports both the master and slave protocols. In the master mode, the device has ownership of the I2C bus, drives the clock, and generates the START and STOP signals. This allows it to send data to a slave or receive data from a slave as required. In slave mode, the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I2C master device.

There are two instances of the I2C master interface and one instance of the I2C slave interface supported.

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MAX32600 User’s Guide Introduction 2.7 Digital Peripherals

2.7.7 USB 2.0 Device Slave with Integrated Transceiver

The integrated USB controller is compliant with the USB 2.0 speciﬁcation, providing full-speed operation as a USB peripheral device. Integrating the USB physical interface (PHY) allows direct connection to the USB cable, reducing board space and overall system cost. An integrated voltage regulator enables smart switching between the main supply and V

when connected to a USB host controller.

BUS

The USB Controller contains an integrated AHB bus master which it uses to write to and read from the buffers for each supported/active endpoint. These buffers are located in the standard system SRAM (in user-conﬁgurable locations), so they can also be accessed by ﬁrmware directly as well as by the USB DMA engine. A total of seven endpoint buffers are supported with conﬁgurable selection of IN or OUT in addition to endpoint 0, which is read-only.

2.7.8 LCD Controller

The MAX32600 incorporates an LCD controller with a boost regulator that interfaces to common low-voltage displays in the standard 12mm x 12mm package. By incorporating the LCD controller into the microcontroller, the design requires only an LCD glass rather than a considerably more expensive LCD module. Every character in an LCD glass is composed of one or more segments, each of which is activated by selecting the appropriate segment and common signal.

The microcontroller can multiplex combinations of up to 40 segment outputs (SEG0 to SEG39) and four common signal outputs (COM0 to COM3). Unused segment outputs can be used as general-purpose port pins. The segments are easily addressed by writing to dedicated display memory. Once the LCD controller settings and display memory have been initialized, the 21-byte display memory is periodically scanned, and the segment and common signals are generated automatically at the selected display frequency. No additional processor overhead is required while the LCD controller is running. Unused display memory can be used for general-purpose storage.

The design is further simpliﬁed and cost reduced by the inclusion of software-adjustable internal voltage-dividers to control display contrast, using either V

DDIO

or an

external voltage. If desired, contrast can also be controlled with an external resistor network.

The features of the LCD controller include the following:

• Automatic LCD segment and common-drive signal generation

• Integrated boost regulator ensures LCD operation down to 2V

• Flexible LCD clock source selection

• Adjustable frame frequency

• Internal voltage-divider resistors eliminate requirement for external components

• Internal adjustable resistor allows contrast adjustment without external components

Four display modes are supported by the LCD controller:

• Static (COM0)

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MAX32600 User’s Guide Introduction 2.8 Security Features

• 1/2 duty multiplexed with 1/2 bias voltages (COM [0:1])

• 1/3 duty multiplexed with 1/3 bias voltages (COM [0:2])

• 1/4 duty multiplexed with 1/3 bias voltages (COM [0:3])

Note Since the voltages available for LCD drive are V

require two of the LCD voltage output pins (V

LCD2

LCD

, V

LCD

and V

, V

) to be shunted together externally.

LCD1

LCD

, and V

ADJ

, the

-bias mode (which requires an output level of V

LCD

) will

2.8 Security Features

2.8.1 Trust Protection Unit (TPU)

The MAX32600 includes several cryptographic and security peripherals which are grouped together to form the Trust Protection Unit, or TPU. The TPU architecture includes cryptographic peripherals (such as the AES engine or the Micro MAA) as well as security features (such as the dynamic tamper sensor) which help to form a secure cryptographic boundary for protecting critical user information within the device.

2.8.2 AES Cryptographic Engine

Another component found in the TPU is an Advanced Encryption Standard (AES) cryptographic engine. This cryptographic engine allows 256-bit AES encryption and decryption operations to be performed in hardware without processor intervention.

The AES control register selects encryption or decryption mode, controls interrupt notiﬁcation of the processor upon an operation completion, and selects whether or not the key expansion (generation of ﬁrst/last round key) is performed before the encryption or decryption operation begins. For multiple-block encryption or decryption operations using a single key, the key expansion is performed on the ﬁrst block only, allowing subsequent operations to complete more quickly by reusing the previously generated round key information.

The working AES key, cryptographic working space, and input and output parameters (plaintext to ciphertext or vice versa) are stored in a dedicated internal AES memory. This memory is automatically cleared (rapid zeroization) in the event of a tamper response.

2.8.3 Battery-Backed AES Secure Key Storage

The battery-backed (by the V

supply voltage) RTC module contains a dedicated set of registers which can be used to store a master AES key or other critical

RTC

data. This master AES key can be generated by the device using a PRNG random number sequence, and is stored in a dedicated location in the RTC register area which will be automatically cleared (rapid zeroization) in the event of a tamper response.

This key is intended for use in encrypting other sensitive information that might be stored in other locations on the device (such as the main system SRAM or the program ﬂash memory) that will not be automatically wiped in the event of a tamper response. However, if this sensitive information has been encrypted before

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MAX32600 User’s Guide Introduction 2.8 Security Features

storage using an AES master key, then once a tamper response occurs and this master key has been deleted, the sensitive information will not be recoverable by an attacker at that point; even if the ciphertext version of the information can be recovered in some way, the key that was used to encrypt that data no longer exists.

Another potential use of this key would be to encrypt larger keys that might be stored in long-term, nonvolatile storage on the device (such as a public key, private key, or certiﬁcate, which might be stored in the main program ﬂash). By encrypting the larger keys with the AES master key, they may safely be stored in a nonsecure location such as the main SRAM or program ﬂash memory; if a tamper response occurs, the AES key will be wiped, effectively destroying the other encrypted keys or data as well since the encrypted information is now useless.

The Secure Key Storage area (which has a capacity of four 32-bit registers or 128 bits total) does not have to be used for an AES key, however; it can be used for any type of secure data that must be immediately erased in the event of a tamper response.

2.8.4 Modular Arithmetic Accelerator (MAA)

The MAA cryptographic module is considered to be another component of the TPU. It allows ﬁrmware to perform 512-bit large number modular arithmetic operations which can be used in turn to implement cryptographic algorithms such as RSA. The RSA set of cryptographic operations can be used for public/private cryptography operations.

The MAA operates from a dedicated internal register ﬁle memory which is used to store keys, input and output parameters, and for scratch working space. The MAA does not use the general purpose system SRAM to store data.

2.8.5 CRC Hardware Block with CRC16 and CRC32

A CRC hardware module is included to provide fast calculations and integrity checking of application software and data. The CRC module supports both CRC-16-− CCITT and CRC-32 polynomial modes. The CRC-16 operation completes in two clock cycles, while the CRC-32 operation requires four cycles.

Additional features of the CRC module include:

• Programmable start seed

• Programmable start address

• Programmable length

• Direct load or PMU-based memory load support

2.8.6 Code Scrambling

All application code and data loaded into the main program ﬂash memory is scrambled in both content and location by hardware before it is stored in the ﬂash. When data is retrieved from the ﬂash, it is descrambled before arriving at the program cache (for instruction fetches) or the main data bus (for data fetches). Both the scrambling and descrambling operations are transparent to the end user.

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MAX32600 User’s Guide Memory, Register Mapping, and Access

3 Memory, Register Mapping, and Access

3.1 Memory, Register Mapping, and Access Overview

The ARM Cortex-M3 architecture deﬁnes a standard memory space for uniﬁed code and data access. This memory space is addressed in units of single bytes but is most typically accessed in 32-bit (4-byte) units. It may also be accessed, depending on the implementation, in 8-bit (1-byte) or 16-bit (2-byte) widths. The total range of the memory space is 32-bits in width (4GB addressable total), from addresses 0x0000_0000 to 0xFFFF_FFFF.

It is important to note, however, that the architectural deﬁnition does not require the entire 4GB memory range to be populated with addressable memory instances.

Figure 3.1: Memory Map Diagram

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MAX32600 User’s Guide Memory, Register Mapping, and Access 3.2 Standard Memory Regions

3.2 Standard Memory Regions

A number of standard memory regions are deﬁned for the ARM Cortex-M3 architecture; the use of many of these is optional for the system integrator. At a minimum, the MAX32600, a Cortex-M3-based device, must contain some code and data memory for application code and variable/stack use, as well as certain components which are part of the instantiated core.

3.2.1 Code Space

The code space area of memory is designed to contain the primary memory used for code execution by the device. This memory area is deﬁned from byte address range 0x0000_0000 to 0x1FFF_FFFF (0.5GB maximum). Two different standard core bus masters are used by the Cortex-M3 core and ARM debugger to access this memory area. The I-Code AHB bus master is used for instruction decode fetching from code memory, while the D-Code AHB bus master is used for data fetches from code memory. This is arranged so that data fetches avoid interfering with instruction execution.

On the MAX32600, the code space memory area contains the main program ﬂash memory, which holds the majority of the instruction code that will be executed on the device. The program ﬂash is mapped from 0x0000_0000 to 0x0003_FFFF. This program memory area must also contain the default system vector table (located initially at address 0x0000_0000), which contains the reset vector for the device and the initial settings for all system exception handlers and interrupt handlers.

The code space memory on the MAX32600 also contains the mapping for the ﬂash information block, from 0x0004_0000 to 0x0004_07FF. However, this mapping is generally only present during production test; it is disabled once the information block has been loaded with valid data and the info block lockout option has been set. This memory is accessible for data reads only and cannot be used for code execution.

3.2.2 SRAM Space

The SRAM area of memory is intended to contain the primary SRAM data memory of the device and is deﬁned from byte address range 0x2000_0000 to 0x3FFF_− FFFF (0.5GB maximum). This memory can be used for general purpose variable and data storage, code execution, and the ARM Cortex-M3 stack.

This memory area contains the main system SRAM on the MAX32600, which is mapped from 0x2000_0000 to 0x2000_7FFF.

The entirety of the SRAM memory space on the MAX32600 is contained within the dedicated ARM Cortex-M3 SRAM bit-banding region from 0x2000_0000 to 0x200F_FFFF (1MB maximum for bit-banding). This means that the entire SRAM can be accessed using bit-banding operations when executing core instructions. This allows any single bit of 32-bit SRAM location to be set, cleared, or read individually by reading from or writing to a speciﬁed location in the bit-banding alias area.

The alias area for the SRAM bit-banding is located beginning at 0x2200_0000 and is a total of 32MB maximum, which allows the entire 1MB bit banding area to be accessed. Each location in the bit-banding alias area translates into a single bit access (read or write) in the bit-banding primary area. Reading from the location performs a single bit read, while writing either a 1 or 0 to the location performs a single bit set or clear.

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MAX32600 User’s Guide Memory, Register Mapping, and Access 3.2 Standard Memory Regions

Note The ARM Cortex-M3 core translates the access in the bit-banding alias area into the appropriate read cycle (for a single bit read) or a read-modify-

write cycle (for a single bit set or clear) of the bit-banding primary area. This means that bit-banding is a core function (i.e., not a function of the SRAM memory interface layer or the AHB bus layer), and thus is only applicable to accesses generated by the core itself. Reads/writes to the bit-banding alias area by other (non-ARM-core) bus masters such as the PMU AHB bus master will not trigger a bit-banding operation and will instead result in an AHB bus error.

The SRAM area on the MAX32600 can be used to contain executable code. Code stored in the SRAM is accessed directly for execution (using the system bus) and is not cached or code scrambled.

The SRAM is also where the ARM Cortex-M3 stack must be located, as it is the only general-purpose SRAM memory on the device. A valid stack location inside the SRAM must be set by the system exception table stored in the main program ﬂash.

The general purpose PMU engine and the function speciﬁc AHB bus master included in the USB peripheral block can both access the SRAM to use as general storage or working space. Speciﬁcally in the case of the USB interface, SRAM memory area can be used to store the descriptor table for the endpoint buffers as well as the endpoint buffers themselves.

3.2.3 Peripheral Space

The peripheral space area of memory is intended for mapping of control registers, internal buffers/working space, and other features needed for the ﬁrmware control of non-core peripherals. It is deﬁned from byte address range 0x4000_0000 to 0x5FFF_FFFF (0.5GB maximum). On the MAX32600, this includes such functions as the ADC/DAC, TPU (MAA, AES, etc.), UART interfaces, I²C, USB, etc.

As with the SRAM region, there is a dedicated 1MB area at the bottom of this memory region (from 0x4000_0000 to 0x400F_FFFF) that is used for bit-banding operations by the ARM core. Read/write operations in the peripheral bit-banding alias area (32MB in length, from 0x4200_0000 to 0x43FF_FFFF) are translated by the core into read/mask/shift or read/modify/write operation sequences to the appropriate location in the bit-banding area.

Note The bit-banding operation within peripheral memory space is, like bit-banding function in SRAM space, a core remapping function, and it is only

applicable to operations performed directly by the ARM core. If another memory bus master accesses the peripheral bit-banding region (e.g., the JTAG/PTP AHB master or the PMU AHB master), the bit-banding operation will not take place, and the bit-banding alias region will appear to be a non-implemented memory area (causing an AHB bus error).

On the MAX32600, access to the region that contains most peripheral registers (0x4000_0000 to 0x400F_FFFF) goes from the AHB bus through an AHB-to-APB bridge. This allows the peripheral blocks to operate on the slower, easier to handle APB bus matrix while also ensuring that peripherals with slower response times do not tie up bandwidth on the AHB bus, which must necessarily have a faster response time since it handles main application instruction and data fetching.

A secondary region within the peripheral memory space is set aside for other peripherals that require more rapid data transfer to implement direct access AHB slave instances (0x04010_0000 to 0x401F_FFFF). This area is used so that peripherals which have FIFOs or other functions requiring large amounts of data to be transferred quickly (such as the ADC and DACs) can beneﬁt from the more rapid transfers available on the AHB bus.

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MAX32600 User’s Guide Memory, Register Mapping, and Access 3.3 Device Memory Instances

3.2.4 External RAM Space

The external RAM space area of memory is intended for use in mapping off-chip external memory and is deﬁned from byte address range 0x6000_0000 to 0x9FF− F_FFFF (1GB maximum). The MAX32600 does not support external RAM space.

3.2.5 External Device Space

The external device space area of memory is intended for use in mapping off-chip device control functions onto the AHB bus and is deﬁned from byte address range 0xA000_0000 to 0xDFFF_FFFF (1GB maximum). The MAX32600 does not implement this memory area.

3.2.6 System Area (Private Peripheral Bus)

The system area (private peripheral bus) memory space contains register areas for functions that are only accessible by the ARM core itself (and the ARM debugger, in certain instances). It is deﬁned from byte address range 0xE000_0000 to 0xE00F_FFFF. This APB bus is restricted to core access; it cannot be accessed by other AHB memory masters, such as the DMA or the JTAG/PTP bus master.

In addition to being restricted to the core, application code is only allowed to access this area when running in the privileged execution mode (as opposed to the standard user thread execution mode). This helps ensure that critical system settings controlled in this area are not altered inadvertently or by errant code that should not have access to this area.

Core functions controlled by registers mapped to this area include the SysTick timer, debug and tracing functions, the NVIC (interrupt handler) controller, and the Flash Breakpoint controller.

3.2.7 System Area (Vendor Deﬁned)

The system area (vendor deﬁned) memory space is reserved for vendor (system integrator) speciﬁc functions that are not handled by another memory area. It is deﬁned from byte address range 0xE010_0000 to 0xFFFF_FFFF. The MAX32600 does not include this memory region.

3.3 Device Memory Instances

This section details physical memory instances on the MAX32600 (including main program ﬂash and SRAM instances) that are accessible as standalone memory regions using either the AHB or APB bus matrix. Memory areas which are only accessible via FIFO interfaces, or memory areas consisting of only a few registers for a particular peripheral, are not covered here.

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3.3.1 Main Program Flash Memory

The main program ﬂash memory is 256KB in size and consists of 2KB (or 512 instruction words) logical pages.

3.3.2 Instruction Cache Memory

The instruction cache is 2KB in size (64 rows x 256 bits) and is used to cache instructions from the main ﬂash memory after they have been descrambled. Note that the cache is used for instruction fetches only; data fetches from the ﬂash will always go directly to the ﬂash contents, bypassing the Instruction Cache Memory.

3.3.3 Information Block Flash Memory

The information block is a separate ﬂash instance with a single 2KB page. It is used to store trim settings (option conﬁguration and analog trim) as well as other device-speciﬁc information designed to be readable by ﬁrmware that needs to be preserved across main application ﬂash load/erase cycles.

3.3.4 System SRAM

The system SRAM is 32KB in size and can be used for general purpose data storage, the ARM system stack, USB data transfers (endpoints), and code execution if desired.

3.3.5 AES Key and Working Space Memory

The AES key memory and working space for AES operations (including input and output parameters) are located in a dedicated register ﬁle memory tied to the AES engine block. This AES memory is mapped into AHB space for rapid ﬁrmware access. In the event of a tamper detection, the AES memory will be automatically erased by hardware.

3.3.6 Modular Arithmetic Accelerator (MAA) Key and Working Space Memory

The MAA also contains a dedicated memory for key storage, input and output parameters for operations, and working space. It is mapped into the AHB memory space for ease of loading and unloading.

3.3.7 TPU Memory Secure Key Storage Area

The MAX32600 contains a specialized 128-bit memory that is designed to preserve a critical key (such as an AES key) even when the device is in the lowest power-saving state. As long as the RTC power supply is still available, this key will be retained, even if the AES block and the main SRAM are shut down completely. In the event of a tamper response, this key will be automatically erased by hardware.

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The Secure Key Storage Area consists of four V

-backed 32-bit registers: TPU_TSR_SKS0, TPU_TSR_SKS1, TPU_TSR_SKS2, and TPU_TSR_SKS3.

RTC

3.4 AHB Bus Matrix and AHB Bus Interfaces

This section details memory accessibility on the AHB bus matrix and the organization of AHB master and slave instances.

3.4.1 Core AHB Interface - I-Code

This AHB master is used by the ARM core for instruction fetching from the code space. This bus master has access to the main ﬂash program memory and the main system SRAM.

3.4.2 Core AHB Interface - D-Code

This AHB master is used by the ARM core for data fetches from the code space. This bus master has access to the main ﬂash program memory, the information block (when it is not locked), and the main system SRAM.

3.4.3 Core AHB Interface - System

This AHB master is used by the ARM core for other data read and write operations involving the system SRAM, the APB mapped peripherals (through the AHB-to-APB bridge), and AHB mapped peripheral and memory areas.

3.4.4 AHB Master - Peripheral Management Unit (PMU)

The PMU bus master has access to all off-core memory areas (equivalent to the System plus D-Code) with the exception of the USB AHB memory mapped area. The PMU bus master does not have access to the ARM Private Peripheral Bus area.

3.4.5 AHB Master - USB Endpoint Buffer Manager

The USB AHB bus master is used to manage endpoint buffers in the main system SRAM. It has access to the main system SRAM and ﬂash main memory.

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4 System Conﬁguration and Management

4.1 Power Ecosystem and Operating Modes

4.1.1 Power Ecosystem

The MAX32600 has multiple operating modes with many user conﬁgurable options offering signiﬁcant ﬂexibility in total power consumption. These options are stored in the data retention power domain registers and are continuously powered across all modes of operation. The registers dictate which analog and digital peripherals are intended to remain enabled during low power modes. Likewise, there are dedicated system registers that dictate the conﬁguration of features during run modes.

The MAX32600 supports four power modes, LP0: STOP; LP1: STANDBY; LP2: PMU; and LP3: RUN. The Power State Diagram shows a state diagram of these power modes.

The low power modes, LP0: STOP and LP1: STANDBY, are under the control of the Power Sequencer while LP2: PMU is controlled by the PMU, and the LP3: RUN mode is controlled by the ARM core.

The V supply.

When a wakeup event is detected, the MAX32600 exits the low power mode (LP0: STOP or LP1: STANDBY) and always enters LP3: RUN where ﬁrmware takes over control of the system and power states.

power pad (powered by battery or super cap) ensures that this domain is always on during battery change or other loss-of-power events on the main V

RTC

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Note Power mode transition restrictions dictate measurement sequences. Further transitioning information is found in the power mode sections below.

The following is a typical measurement sequence: LP0/LP1 → LP3 → LP2 → LP3 → LP0/LP1

Figure 4.1: Power State Diagram

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4.1.2 Low Power Modes (LP0: STOP and LP1: STANDBY)

Note Low Power Modes LP0 and LP1 can only transition to/from LP3: RUN; to enter LP2: PMU from one of these modes, the device must ﬁrst enter LP3:

Run.

4.1.2.1 Low Power Mode 0 (LP0: STOP)

LP0: STOP is the lowest power mode supported by the MAX32600: using as little as 850nA in normal operation and as little as 1.25uA with the RTC active. The core system registers and SRAM do not retain state and, upon exit from LP0: STOP, the system starts as if from a core reset. The sections of the MAX32600 that maintain state during LP0: STOP are:

• Power Sequencer

• Real-Time Clock (RTC)

• Data retention registers

• POR/Failsafe

4.1.2.2 Low Power Mode 1 (LP1: STANDBY)

LP1: STANDBY is core data retention mode and supports fast wakeup time (∼15us typical) while maintaining ultra-low power. Typically, the MAX32600 draws only

1.4uA in LP1: STANDBY without the RTC and only 1.8uA with the RTC enabled. All clocks are gated off, the core logic is in a static state, and the ARM is in deep sleep. SRAM and registers have full data retention. Many options for analog support circuitry are available in this mode and, to achieve the lowest possible power in LP1: STANDBY, it is recommended to turn off all unused analog circuitry. This includes the core 1.8V LDO because the Data Retention LDO is used to provide data retention.

To achieve the 15us fast resume from LP1: STANDBY, a power-up sequence has been implemented. Instead of waiting for the 1.8V LDO voltage to become stable, a gear shift mechanism is used that allows the core to run with a divided clock while the 1.8V LDO ramps and stabilizes; when the LDO is at a safe voltage, the system shifts gears to the normal operating frequency.

Optional improvements to wakeup time can be achieved at the expense of burning more power. This may be appropriate for short periods of time in low power modes. In this situation, continuous power consumption of run state is avoided, but extremely fast wake up times from a low power mode may be needed. To accelerate the resume time, the 1.8V LDO and/or Relaxation Oscillator can be enabled during LP1: STANDBY. Power consumption during LP1: STANDBY will be higher, but immediate resume times can be achieved under these conditions.

If the Relaxation Oscillator is not enabled during LP1: STANDBY, a 2us timeout is necessary due to waiting for the oscillator to stabilize prior to beginning code execution.

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4.1.2.3 Entering LP0: STOP or LP1: STANDBY

The following illustrates the procedure to change the MAX32600 operating state to either LP0: STOP or LP1: STANDBY. The examples used set up a GPIO wakeup on P0.0 that wakes up on an active high. Although P0.0 is used here, any available port.pin can be conﬁgured in this manner for a GPIO wakeup event.

Note The following steps to enter LP0: STOP and LP1: STANDBY should be used as guidelines; for best results, the user should always reference the

appropriate API.

Entering LP0: STOP

In order to change the MAX32600 operating state to LP0: STOP, the following steps should be followed:

• Conﬁgure P0.0 to be WUD Mode by setting PWRMAN_WUD_CTRL.pad_select

• Enable Active High WUD on P0.0 by setting PWRMAN_WUD_CTRL.pad_mode

• Activate WUD by setting bit 0 of PWRMAN_WUD_PULSE0

• Assert GPIO Freeze by setting PWRSEQ_REG1.pwr_gpio_freeze to 1

• Ensure pads are in the lowest power state by clearing the PWRMAN_PWR_RST_CTRL.io_active register

• Clear all ﬂags in PWRSEQ_FLAGS register

• Set Run/Sleep mode of peripherals in PWRSEQ_REG0

• Set LP0 mode in PWRSEQ_REG0

• CM3_PWRMAN bit 2 to 1; Arm Command WFE – ARM command puts MAX32600 in LP0 mode

Entering LP1: STANDBY

In order to change the MAX32600 operating state to LP1: STANDBY, the following steps should be followed:

• Conﬁgure the Power Sequencer for quick resume by setting desired clocks in PWRSEQ_REG3.pwr_rosel to 64

• Conﬁgure P0.0 to be WUD Mode by setting PWRMAN_WUD_CTRL.pad_select

• Enable Active High WUD on P0.0 by setting PWRMAN_WUD_CTRL.pad_mode

• Activate WUD by setting bit 0 of PWRMAN_WUD_PULSE0

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• Assert GPIO Freeze by setting PWRSEQ_REG1.pwr_gpio_freeze to 1

• Clear all ﬂags in PWRSEQ_FLAGS register

• Set Run/Sleep mode of peripherals in PWRSEQ_REG0

• Set LP1 mode in PWRSEQ_REG0

• CM3_PWRMAN bit 2 to 1; Arm Command WFE – ARM command puts MAX32600 in LP1 mode

Note CM3_PWRMAN bit 2 is is the ’Deep Sleep’ bit of the ARM Cortex-M3 System Control register. Setting this bit to 1 indicates to the system that the

Cortex-M3 clock can be stopped; the ’Deep Sleep’ port will be asserted when the processor can be stopped. Setting this bit to 0 prevents turning off the system clock.

4.1.2.4 Wakeup Events from LP0: STOP and LP1: STANDBY

The following events can wake up the MAX32600 from the Low Power states:

• RTC timer interrupt

– Timer has 244us resolution

• GPIO sensed high/low (All GPIO are wakeup capable as programmed by ﬁrmware)

• Analog input to a comparator

• USB plugin/remove

• Supply Voltage Monitor (SVM) low voltage condition sensed via periodic or continuous monitoring

Each of these events is conﬁgurable and must be enabled by the ﬁrmware.

Note Certain wakeup events can be masked out by writing to the PWRSEQ_MSK_FLAGS register.

After Wakeup Events

After the MAX32600 experiences a wakeup event from LP0: STOP or LP1: STANDBY, proceed with the following actions:

LP0 Wakeup

• Read PWRSEQ_FLAGS register to determine the source of the wakeup event

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• If the wakeup event was a GPIO event, do one of the following to clear the GPIO WUD:

1. If desired action is to clear all GPIO WUD latches:

• Clear all GPIO ﬂags by writing 1 to PWRMAN_WUD_CTRL.clear_all to clear all GPIO WUD setups

• Take all pads out of the low power state by setting the PWRMAN_PWR_RST_CTRL.io_active register to 1

• Deassert GPIO Freeze by setting PWRSEQ_REG1.pwr_gpio_freeze to 0

• Clear all ﬂags in PWRSEQ_FLAGS register

2. If desired action is to clear individual GPIO WUD latches that initiated the wakeup event:

• Set WUD Pad Select for the individual port in the PWRMAN_WUD_CTRL.pad_select register

• Set WUD Pad Signal Mode by writing 2 to PWRMAN_WUD_CTRL.pad_mode

• Set WUD Pulse 0 register, PWRMAN_WUD_PULSE0, to 1. This register self-clears.

• Take all pads out of the low power state by setting the PWRMAN_PWR_RST_CTRL.io_active register to 1

• Deassert GPIO Freeze by setting PWRSEQ_REG1.pwr_gpio_freeze to 0

• Clear all ﬂags in PWRSEQ_FLAGS register

LP1 Wakeup

• Read PWRSEQ_FLAGS register to determine the source of the wakeup event

• If the wakeup event was a GPIO event, it is recommended that GPIO ﬂags are cleared individually. Clearing of all GPIO WUD latches is not recommended when waking up from LP1.

– Set WUD Pad Select for the individual port in the PWRMAN_WUD_CTRL.pad_select register

– Set WUD Pad Signal Mode by writing 2 to PWRMAN_WUD_CTRL.pad_mode

– Set WUD Pulse 0 register, PWRMAN_WUD_PULSE0, to 1. This register self-clears.

– Take all pads out of the low power state by setting the PWRMAN_PWR_RST_CTRL.io_active register to 1

– Deassert GPIO Freeze by setting PWRSEQ_REG1.pwr_gpio_freeze to 0

– Clear all ﬂags in PWRSEQ_FLAGS register

4.1.3 Low Power Modes (LP2: PMU and LP3: RUN)

The Peripheral Management Unit (PMU) is in control of the system when using LP2: PMU. During LP3: RUN, the ARM core is in control of the system. A System Management unit controls entering and exiting both modes.

When operating in either mode, ﬁrmware is in control of the power used by the system. Firmware controls clock gating, peripheral enables, and the Analog Front End (AFE).

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4.1.3.1 Low Power Mode 2 (LP2: Peripheral Management Unit)

The Peripheral Management Unit (PMU) is a DMA engine for the MAX32600. It enables the lowest noise ﬂoor for analog measurements and reduced operating power for peripherals. The PMU acts like an internal state machine that can orchestrate events via programmable op codes for:

• Peripheral to Memory

• Memory to Peripheral

• Analog to Memory

• Memory to Analog

– Synchronization of analog measurements

– Control and synchronization of pulse train signals and events

During this state, the ARM Cortex-M3 has relinquished control to the PMU. The ARM Cortex-M3 is in sleep mode, resulting in power reduction and noise minimization. To further reduce power consumption and noise, only the required clocks and data buses are active during LP2: PMU. Typically, the MAX32600 draws 1.2mA of current (24MHz clock) with a single channel of the PMU active. Each additional channel draws approximately 100uA of current.

4.1.3.2 Low Power Mode 3 (LP3: RUN)

LP3: RUN mode is under full ﬁrmware control using the ARM core. During this state, the ARM Cortex-M3 and the digital core are fully powered and awake. The clocks to each peripheral are gated dynamically and only clock the circuitry in use. Firmware executes from the internal ﬂash memory based on the instruction cache. Typical power of 175uA/MHz is achieved in LP3: RUN. This is the default power up state.

Reference First Boot Power Up for detailed information regarding entering LP3: RUN from an initial boot up.

4.1.4 Power State Matrix Control Options

The Power State Diagram depicts the four major power states and how control is handled in the MAX32600.

The ﬁgure illustrates:

• Hardware controlled powering of circuit blocks

• Firmware controllable power options

• Firmware controllable clock gating

Note The chip hardware will power the minimal amount of circuitry necessary to achieve functionality of each mode. To achieve the lowest optimized

power solution, the user must fully analyze the usage case and choose the appropriate power and clock gating options.

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Figure 4.2: Power and Clock Gating Options

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4.1.5 Power Domains

The MAX32600 has multiple power domains that are controlled by the power management block. This includes the Power Sequencer, Power Manager, Trickle Charger, 1.8V LDO, 3.3V USB LDO, and Real Time Clock (RTC). The conﬁguration registers for the Power Manager are within the battery backed V

RTC

domain. The registers are conﬁgurable by ﬁrmware and dictate what analog and digital peripherals are enabled while in each of the Operating Modes, LP0: STOP; LP1: STANDBY; LP2: PMU; and LP3: RUN.

Figure 4.3: Power Domains

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Reference Power Pins below for a more detailed description of the power I/O.

4.1.6 Power Manager

The Power Manager monitors and distributes the three main voltage rail inputs (V V

DDA3DAC

, and V

DDA3REF

) are separate pins that allow the user to provide external isolation from each domain. The V

, VDD, and V

BUS

) on the MAX32600. The analog power domain inputs (V

RTC

analog power output can be shorted to

DDA3

DDA3ADC

any/all of the analog power domain inputs or optionally connected through ﬁltering networks for isolation. In addition to power distribution and management, the Power Manager monitors power levels using several Supply Voltage Monitors (SVMs) and Power-On Resets (PORs). SVM warning levels are programmable (see section Supply Voltage Monitoring During LP0: STOP and LP1: STANDBY for details). POR levels are not changeable and are set at the factory per the MAX32600 data sheet.

4.1.7 Power Sequencer

The Power Sequencer controls the MAX32600 during Low Power Modes (LP0: STOP and LP1: STANDBY). When LP0: STOP and LP1: STANDBY are exited, the Power Sequencer transfers control to the system manager and the part enters either LP2: PMU or LP3: RUN. One of the primary functions of the Power Sequencer is to ensure power, clocks, and resets are stable prior to transitioning the system to either LP2: PMU or LP3: RUN. During LP0: STOP and LP1: STANDBY, wakeup interrupts are continuously monitored while consuming very little power. Once an interrupt event occurs, the Power Sequencer automatically enables SVMs as well as active LP2: PMU and LP3: RUN peripherals, including the internal 1.8V regulator and the 24MHz Relaxation Oscillator.

When the Power Sequencer determines the power, clocks, and resets are valid, the clock gating circuitry is disabled and the MAX32600 is allowed to enter LP2: PMU or LP3: RUN.

4.1.7.1 Power Mode Transitioning to Low Power Modes

To take full advantage of the low power modes of operation in the MAX32600, application ﬁrmware will need to spend as much time as possible in either LP0: STOP and LP1: STANDBY modes. Prior to entering these modes, it is extremely important to set up the wakeup interrupts and supply voltage monitor conﬁguration. To enter LP0: STOP, reference section Entering LP0: STOP or LP1: STANDBY above.

4.1.7.2 Supply Voltage Monitoring During LP0: STOP and LP1: STANDBY

During LP0: STOP or LP1: STANDBY modes, the Power Sequencer can be set to monitor the Supply Voltage Monitors (SVM) periodically. Periodic monitoring enables the system to check to ensure power is adequate at a speciﬁc interval and reduces overall system power signiﬁcantly. To enable periodic monitoring, set the ﬁeld PWRSEQ_REG3.pwr_svmsel to a desired count value and enable one or more SVMs during LP0: STOP or LP1: STANDBY modes.

SVM Options for LP0 / LP1 Description Enable Field

3V Main Supply PWRSEQ_REG0.pwr_svm3en_slp

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SVM Options for LP0 / LP1 Description Enable Field

REG18

RTC

1.8V Regulated Output PWRSEQ_REG0.pwr_svm1en_slp

3V VRTC Supply PWRSEQ_REG0.pwr_svmrtcen_slp

4.1.7.3 SVM Periodic Monitoring

For periodic SVM during STOP or STANDBY modes, a clock source for the periodic timer should be enabled. The 8kHz oscillator or the RTC clock can be chosen as the timer source. For the 8kHz nano ring, set the PWRSEQ_REG0.pwr_nren_slp bit; to use the RTC, set the PWRSEQ_REG0.pwr_rtcen_slp bit.

8kHz Oscillator

The 8kHz Oscillator is a low-power internal oscillator with a nominal frequency of 8kHz that allows periodic supply voltage monitoring during Low Power Modes (LP0:

STOP and LP1: STANDBY).

4.1.7.4 First Boot Power Up

When initial power is applied, the PWRSEQ_FLAGS.pwr_ﬁrst_boot ﬂag will be set to indicate the MAX32600 is powering up from a ﬁrst boot condition. The pwr_−

ﬁrst_boot register must be set to 0 by ﬁrmware prior to attempting to enter either Low Power Modes (LP0: STOP and LP1: STANDBY). All power lost on the chip or

asserting RSTN will reset the pwr_ﬁrst_boot ﬂag.

First Boot Up (entering LP3: RUN)

• Ensure pads are in the lowest power state by clearing the PWRMAN_PWR_RST_CTRL.io_active register

• Clear I/O WUD on all pads by setting and clearing the PWRMAN_PWR_RST_CTRL.wud_clear register

• Take all pads out of low power state by setting PWRMAN_PWR_RST_CTRL.io_active to 1

• Deassert GPIO Freeze by setting PWRSEQ_REG1.pwr_gpio_freeze to 0

• Clear the ﬁrst boot signal, PWRSEQ_REG0.pwr_ﬁrst_boot

• Set the quick count bit in the the PWRSEQ_REG3.pwr_rosel_quick to 1

• The MAX32600 is in LP3: RUN

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After boot/resume for LP0: STOP or LP1: STANDBY, ﬁrmware should poll the PWRSEQ_FLAGS register to determine the source of the wakeup event. After determining the source, ﬁrmware should clear the speciﬁc PWRSEQ_FLAGS register prior to attempting to enter either LP0: STOP or LP1: STANDBY.

Reference Wakeup Events from LP0: STOP and LP1: STANDBY for a more detailed description of this process.

4.1.7.5 Brownout Detector

The Brownout Detector detects a failing power supply and sends a NMI to the ARM processor to shut down the MAX32600 before losing and/or corrupting core data. The Brownout Detection monitors the power supply for a ∼700mV drop and, if detected, sends the NMI to the ARM. The amount of time the supply must be below the detection level is conﬁgurable on the MAX32600 and can be set by ﬁrmware as shown in the following table. This setting indicates the minimum window of detection that the Brownout Detector will see as a brownout.

Brownout Detection Window PWRSEQ_FLAGS.pwr_brownout_det Setting

10uS 00b

50uS 01b

250uS 10b

750uS 11b (Default)

Note The brownout detect ﬂag, PWRSEQ_FLAGS.pwr_brownout_det, is disabled by default and does not need to be cleared by ﬁrmware on power up;

following any reset condition occurring while the brownout detect ﬂag was enabled, it should be checked to determine if a brownout was detected.

4.1.8 Trickle Charger

When a super capacitor is connected to the V supply (V

). Several charging options are available, including three different charging speeds as well as the optional addition of a series protection diode. Users

USB

can choose from 250 Ohm, 2K Ohm, or 4K Ohm series resistance between the power source voltage and V

rail, the Trickle Charger can be enabled to charge the super capacitor from the main supply (VDD) or from the USB

RTC

-connected super capacitor. In addition, a series

RTC

diode can be enabled between power rails.

4.1.8.1 Trickle Charger Conﬁguration

To enable and conﬁgure the trickle charger, series resistance, and protection diode, set the PWRSEQ_REG1.pwr_trikl_chrg ﬁeld as shown in the table below.

Trickle Charge Setting pwr_trikl_chrg Setting (8-bits)

No Diode, 250 Ohm series resistor 0xA5

No Diode, 2K Ohm series resistor 0xA6

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Trickle Charge Setting pwr_trikl_chrg Setting (8-bits)

No Diode, 4K Ohm series resistor 0xA7

Protection Diode, 250 Ohm series resistor 0xA9

Protection Diode, 2K Ohm series resistor 0xAA

Protection Diode, 4K Ohm series resistor 0xAB

If the Trickle Charger is enabled while USB power is available, the super capacitor will be charged using the USB power source. Otherwise, when enabled, the Trickle Charger will charge the super capacitor from the main VDDsupply.

Note When using a super capacitor, the MAX32600 cannot go into LP1 until the the super capacitor has been been sufﬁciently charged. Poll the V

RTC

Warning Level (user conﬁgurable) to set the appropriate level.

4.1.9 Low-Dropout Regulators (LDO)

4.1.9.1 1.8V LDO

The 1.8V LDO is the source of the V

rail and powers the digital core when in LP2: PMU and LP3: RUN. It can source power from either the USB supply or the

REG18

main VDDsupply. If the USB supply is available, the 1.8V regulator will automatically switch to USB as its source. The 1.8V regulator supports a 50mA maximum capacity (40mA maximum external capacity) over an input range of 2.2V to 3.6V and a 30mA maximum capacity (20mA maximum external capacity) over an input range of 2.0V to 2.2V. Once the LDO input voltage reaches 1.95V and below, the V

output voltage will attempt to equal the input voltage. V

REG18

can be supplied

REG18

to external components, but the maximum external current should not be violated.

Retention Regulator

The Retention Regulator sources power to the V

power rail when the MAX32600 is in LP1: STANDBY. Optionally, the Data Retention Regulator can be enabled

REG18

during LP2: PMU and LP3: RUN modes while the 1.8V LDO is enabled. No external loads should be placed on the Retention Regulator during LP1: STANDBY while the 1.8V LDO is disabled. The Retention Regulator is only capable of maintaining data, so any external load may cause a power fail event to occur.

4.1.9.2 3.3V USB LDO

The 3.3V USB LDO sources its power from the 5V USB power and outputs 3.3V via V

. By default, the MAX32600 will be powered from the USB supply when it

DDB

is available. To disable this, refer to PWRSEQ_REG4.pwr_usb_ldo_off and PWRSEQ_REG4.pwr_usb_frc_vdd register ﬁelds.

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4.1.10 Reset Pins

The MAX32600 contains two active low reset pins, RSTN and SRTSN. RSTN serves as the main chip reset input. Asserting the pin low will reset all registers on the chip except RTC related circuits and wakeup conﬁguration. This allows a restart of all chip functions (analog and digital) while still maintaining the Real Time Clock.

Note Asserting RSTN will turn off the 1.8V LDO but external capacitance will keep the V

A continued RSTN assertion will keep the 1.8V LDO off, eventually causing the V

rail and SRAM data intact during a momentary reset pulse.

REG18

rail to collapse and lose all SRAM data.

REG18

SRSTN is a bidirectional reset that will perform a reset to the digital core when asserted low and will subsequently drive a reset pulse to other components in the system.

To fully reset the entire chip including RTC related circuitry, all three main power inputs (V

BUS

, VDD, V

) must be powered down.

RTC

4.1.11 Power Pins

Pin Name Description

Main chip power input. Connect to 3V nominal power supply or battery. This pin must be connected to VSSthrough a 4.7uF capacitor.

BUS

USB power input. Connect a 5V nominal power supply, typically USB power. This pin must be connected to V

through a 4.7uF capacitor.

DDB

RTC

Output of USB 5V -> 3.3V LDO. This pin must be connected to VSSthrough a 4.7uF capacitor

Backup rail or “Last Man Standing” rail. Connect to super capacitor or 3V nominal power supply or battery. This pin must be connected to VSSthrough a 1.0uF capacitor if connected to a 3V nominal power supply or battery. Connect to VDDif backup rail is not used.

DDIO

3V nominal GPIO power. This pin (connected to Ports 6, 7) must be connected to VSSthrough a 4.7uF capacitor (if the 12mm x 12mm package is used). Up to 50mA may be sourced for external components. Note: On the 12mm

DDIO_SW1

x 12mm package, all GPIOs are powered by V

3V / 1.8V nominal GPIO power. Bank of GPIOs (connected to Ports 0, 1 on the 12mm x 12mm package and Port 1 on the 7mm x 7mm package) using V

DDIO

VDDIO

(3V nominal) or V

(1.8V nominal) as a power source. This pin

REG18

must be connected to VSSthrough a 1.0uF capacitor.

DDIO_SW2

3V / 1.8V nominal GPIO power. Bank of GPIOs (connected to Ports 2, 3, 4, 5 on the 12mm x 12mm package, Port 2 on the 7mm x 7mm package, and JTAG) using V

(3V nominal) or V

DDIO

(1.8V nominal) as a power source.

REG18

This pin must be connected to VSSthrough a 1.0uF capacitor.

DDA3

DDA3ADC

Analog power source (3V nominal). Option to connect ﬁlter network between V V

DDA3REF

ADC power input (3V nominal). Connect to V

. Short to V

pins if ﬁlter network not needed.

DDA3

directly or via a ﬁlter network.

DDA3

and V

DDA3ADC

/ V

DDA3DAC

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Pin Name Description

DDA3DAC

DDA3REF

REFADC

DAC / op amp power input (3V nominal). Connect to V

Reference power input (3V nominal). Connect to V

DDA3

directly or via a ﬁlter network.

DDA3

directly or via a ﬁlter network.

ADC reference voltage output. Buffered output can be set to 1.024V, 1.5V, 2.048V, and 2.5V. This pin must be connected to VSSthrough a 4.7uF capacitor.

REFDAC

DAC reference voltage output. Buffered output can be set to 1.024V, 1.5V, 2.048V, and 2.5V. This pin must be connected to VSSthrough a 4.7uF capacitor.

REFADJ

Precision reference input that may be optionally used be in place of internal reference by V

REFADC

and V

REFDAC

buffers. Ground if not used.

SSREF

SSADC

SSDAC

SSUB

Digital Ground. Tie all grounds together on circuit board.

Substrate Ground.

Reference Ground.

ADC Ground.

DAC Ground.

Note All grounds are assumed to be tied together at the circuit board level.

4.1.12 Registers (PWRMAN)

4.1.12.1 Module PWRMAN Registers

32b

Address Register

Word Len Description

0x40090800 PWRMAN_PWR_RST_CTRL 1 Power Reset Control and Status

0x40090804 PWRMAN_INTFL 1 Interrupt Flags

0x40090808 PWRMAN_INTEN 1 Interrupt Enable/Disable Controls

0x4009080C PWRMAN_SVM_EVENTS 1 SVM Event Status Flags (read-only)

0x40090810 PWRMAN_WUD_CTRL 1 Wake-Up Detect Control

0x40090814 PWRMAN_WUD_PULSE0 1 WUD Pulse To Mode Bit 0

0x40090818 PWRMAN_WUD_PULSE1 1 WUD Pulse To Mode Bit 1

0x40090830 PWRMAN_WUD_SEEN0 1 Wake-up Detect Status for P0/P1/P2/P3

0x40090834 PWRMAN_WUD_SEEN1 1 Wake-up Detect Status for P4/P5/P6/P7

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Address Register

0x40090838 PWRMAN_DIE_TYPE 1 Die Type ID Register

0x4009083C PWRMAN_BASE_PART_NUM 1 Base Part Number

0x40090840 PWRMAN_MASK_ID0 1 Mask ID Register 0

0x40090844 PWRMAN_MASK_ID1 1 Mask ID Register 1

0x40090848 PWRMAN_PERIPHERAL_RESET 1 Peripheral Reset Control Register

4.1.12.1.1 PWRMAN_PWR_RST_CTRL

PWRMAN_PWR_RST_CTRL.ﬂash_active

Field Bits Default Access Description

ﬂash_active 0 1 R/W Flash Active (Not Used)

No effect

PWRMAN_PWR_RST_CTRL.sram_active

Field Bits Default Access Description

sram_active 1 0 R/W SRAM Active (Not Used)

32b

Word Len Description

No effect

PWRMAN_PWR_RST_CTRL.afe_powered

Field Bits Default Access Description

afe_powered 2 0 R/W AFE Powered

• 0:Entire AFE is powered off

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• 1:AFE is powered on globally; individual AFE controls may be used to power sub-features of AFE on and off as needed.

PWRMAN_PWR_RST_CTRL.io_active

Field Bits Default Access Description

io_active 3 0 R/W I/O Active

• 0: Puts all I/O (GPIO-only) pins in the lowest power state.

• 1: All I/O pins are powered on normally.

PWRMAN_PWR_RST_CTRL.usb_powered

Field Bits Default Access Description

usb_powered 4 0 R/W USB Powered

1: Powers on the USB block.

PWRMAN_PWR_RST_CTRL.pullups_enabled

Field Bits Default Access Description

pullups_enabled 5 1 R/W Static Pullups Enabled

1: Enables static pullups on dedicated I/O pins.

PWRMAN_PWR_RST_CTRL.ﬁrmware_reset

Field Bits Default Access Description

ﬁrmware_reset 8 0 R/W Firmware Initiated Reset

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Initiates a system reset when set to 1. This bit is self-clearing.

PWRMAN_PWR_RST_CTRL.arm_lockup_reset

Field Bits Default Access Description

arm_lockup_reset 9 0 R/W ARM Lockup Reset

If this bit is set to 1, a system reset will be automatically triggered when the ARM core asserts its lockup state output signal.

PWRMAN_PWR_RST_CTRL.wud_clear

Field Bits Default Access Description

wud_clear 12 0 R/W I/O WUD Clear

When I/O Active (bit 3 of PWRMAN_RST_CNTL) is deasserted, setting this bit will clear the WUD latch in all I/O pads. This bit self clears.

PWRMAN_PWR_RST_CTRL.tamper_detect

Field Bits Default Access Description

tamper_detect 16 special R/O Reset Caused By - Tamper Detect

PWRMAN_PWR_RST_CTRL.fw_command_sysman

Field Bits Default Access Description

fw_command_sysman 17 special R/O Reset Caused By - Firmware Com-

manded Reset (SysMan)

PWRMAN_PWR_RST_CTRL.watchdog_timeout

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Field Bits Default Access Description

watchdog_timeout 18 special R/O Reset Caused By - Watchdog Reset

PWRMAN_PWR_RST_CTRL.fw_command_arm

Field Bits Default Access Description

fw_command_arm 19 special R/O Reset Caused By - Firmware Commanded

Reset (ARM Core)

PWRMAN_PWR_RST_CTRL.arm_lockup

Field Bits Default Access Description

arm_lockup 20 special R/O Reset Caused By - ARM Lockup

PWRMAN_PWR_RST_CTRL.srstn_assertion

Field Bits Default Access Description

srstn_assertion 21 special R/O Reset Caused By - External System Reset

PWRMAN_PWR_RST_CTRL.por

Field Bits Default Access Description

por 22 special R/O Reset Caused By - Power On Reset (POR)

PWRMAN_PWR_RST_CTRL.low_power_mode

Field Bits Default Access Description

low_power_mode 31 0 R/W Power Manager Dynamic Clock Gating En-

able

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1: Enables dynamic clock gating for pwrman functions.

4.1.12.1.2 PWRMAN_INTFL

PWRMAN_INTFL.v1_8_warning

Field Bits Default Access Description

v1_8_warning 0 0 W1C 1.8V Warning Monitor Int Flag

Write 1 to clear.

Set to 1 by hardware when the associated SVM event monitor detects the monitored condition.

PWRMAN_INTFL.v3_3_warning

Field Bits Default Access Description

v3_3_warning 1 0 W1C 3.3V Warning Monitor Int Flag

Write 1 to clear.

Set to 1 by hardware when the associated SVM event monitor detects the monitored condition.

PWRMAN_INTFL.rtc_warning

Field Bits Default Access Description

rtc_warning 2 0 W1C RTC Warning Monitor Int Flag

Write 1 to clear.

Set to 1 by hardware when the associated SVM event monitor detects the monitored condition.

PWRMAN_INTFL.v3_3_reset

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Field Bits Default Access Description

v3_3_reset 3 0 W1C 3.3V Reset Monitor Int Flag

Write 1 to clear.

Set to 1 by hardware when the associated SVM event monitor detects the monitored condition.

PWRMAN_INTFL.vdda_warning

Field Bits Default Access Description

vdda_warning 4 0 W1C VddA Warning Monitor Int Flag

Write 1 to clear.

Set to 1 by hardware when the associated SVM event monitor detects the monitored condition.

4.1.12.1.3 PWRMAN_INTEN

PWRMAN_INTEN.v1_8_warning

Field Bits Default Access Description

v1_8_warning 0 0 R/W 1.8V Warning Monitor Int Enable

0:Int disabled; 1:Interrupt enabled for the associated SVM monitor event.

PWRMAN_INTEN.v3_3_warning

Field Bits Default Access Description

v3_3_warning 1 0 R/W 3.3V Warning Monitor Int Enable

0:Int disabled; 1:Interrupt enabled for the associated SVM monitor event.

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PWRMAN_INTEN.rtc_warning

Field Bits Default Access Description

rtc_warning 2 0 R/W RTC Warning Monitor Int Enable

0:Int disabled; 1:Interrupt enabled for the associated SVM monitor event.

PWRMAN_INTEN.v3_3_reset

Field Bits Default Access Description

v3_3_reset 3 0 R/W 3.3V Reset Monitor Int Enable

0:Int disabled; 1:Interrupt enabled for the associated SVM monitor event.

PWRMAN_INTEN.vdda_warning

Field Bits Default Access Description

vdda_warning 4 0 R/W VddA Warning Monitor Int Enable

0:Int disabled; 1:Interrupt enabled for the associated SVM monitor event.

4.1.12.1.4 PWRMAN_SVM_EVENTS

PWRMAN_SVM_EVENTS.v1_8_warning

Field Bits Default Access Description

v1_8_warning 0 n/a R/O 1.8V Warning Monitor Event Input

Current state of the associated SVM event input.

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PWRMAN_SVM_EVENTS.v3_3_warning

Field Bits Default Access Description

v3_3_warning 1 n/a R/O 3.3V Warning Monitor Event Input

Current state of the associated SVM event input.

PWRMAN_SVM_EVENTS.rtc_warning

Field Bits Default Access Description

rtc_warning 2 n/a R/O RTC Warning Monitor Event Input

Current state of the associated SVM event input.

PWRMAN_SVM_EVENTS.v3_3_reset

Field Bits Default Access Description

v3_3_reset 3 n/a R/O 3.3V Reset Monitor Event Input

Current state of the associated SVM event input.

PWRMAN_SVM_EVENTS.vdda_warning

Field Bits Default Access Description

vdda_warning 4 n/a R/O VddA Warning Monitor Event Input

Current state of the associated SVM event input.

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4.1.12.1.5 PWRMAN_WUD_CTRL

PWRMAN_WUD_CTRL.pad_select

Field Bits Default Access Description

pad_select 5:0 000000b R/W Wake-Up Pad Select

Selects which pad to modify WUD/Weak latch states.

Pads are numbered from 0-63, where 0-7 corresponds to P0.0-P0.7, 8-15 corresponds to P1.0-P1.7, and so on.

PWRMAN_WUD_CTRL.pad_mode

Field Bits Default Access Description

pad_mode 9:8 00b R/W Wake-Up Pad Signal Mode

Deﬁnes WUD signal to be sent to selected pad.

• 0 = Clear/Activate WUD

• 1 = Set WUD Act Hi/Set WUD Act Lo

• 2 = Set Weak Hi/Set Weak Lo

• 3 = No pad state change

PWRMAN_WUD_CTRL.clear_all

Field Bits Default Access Description

clear_all 12 0 R/W Clear All WUD Pad States

When set forces all pads into Clr WUD/Weak state until cleared.

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4.1.12.1.6 PWRMAN_WUD_PULSE0

Default Access Description

n/a W/O WUD Pulse To Mode Bit 0

Writing to this register issues a pulse to the selected WUD pad mode[0] for one clock.

The effect on the pad behavior depends on the Wake-Up Pad Signal Mode as set in WUD_CTRL.

• 0 = Clr WUD/Weak

• 1 = Set WUD Act Hi

• 2 = Set Weak Hi

• 3 = No pad state change

4.1.12.1.7 PWRMAN_WUD_PULSE1

Default Access Description

n/a W/O WUD Pulse To Mode Bit 1

Writing to this register issues a pulse to the selected WUD pad mode[1] for one clock.

The effect on the pad behavior depends on the Wake-Up Pad Signal Mode as set in WUD_CTRL.

• 0 = WUD Activate

• 1 = Set WUD Act Lo

• 2 = Set Weak Lo

• 3 = No pad state change;

4.1.12.1.8 PWRMAN_WUD_SEEN0

PWRMAN_WUD_SEEN0.[gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7]

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Field Bits Default Access Description

gpio0 0 0 R/O Wake-Up Detect Status for P0.0

gpio1 1 0 R/O Wake-Up Detect Status for P0.1

gpio2 2 0 R/O Wake-Up Detect Status for P0.2

gpio3 3 0 R/O Wake-Up Detect Status for P0.3

gpio4 4 0 R/O Wake-Up Detect Status for P0.4

gpio5 5 0 R/O Wake-Up Detect Status for P0.5

gpio6 6 0 R/O Wake-Up Detect Status for P0.6

gpio7 7 0 R/O Wake-Up Detect Status for P0.7

Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

PWRMAN_WUD_SEEN0.[gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15]

Field Bits Default Access Description

gpio8 8 0 R/O Wake-Up Detect Status for P1.0

gpio9 9 0 R/O Wake-Up Detect Status for P1.1

gpio10 10 0 R/O Wake-Up Detect Status for P1.2

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Field Bits Default Access Description

gpio11 11 0 R/O Wake-Up Detect Status for P1.3

gpio12 12 0 R/O Wake-Up Detect Status for P1.4

gpio13 13 0 R/O Wake-Up Detect Status for P1.5

gpio14 14 0 R/O Wake-Up Detect Status for P1.6

gpio15 15 0 R/O Wake-Up Detect Status for P1.7

Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

PWRMAN_WUD_SEEN0.[gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23]

Field Bits Default Access Description

gpio16 16 0 R/O Wake-Up Detect Status for P2.0

gpio17 17 0 R/O Wake-Up Detect Status for P2.1

gpio18 18 0 R/O Wake-Up Detect Status for P2.2

gpio19 19 0 R/O Wake-Up Detect Status for P2.3

gpio20 20 0 R/O Wake-Up Detect Status for P2.4

gpio21 21 0 R/O Wake-Up Detect Status for P2.5

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Field Bits Default Access Description

gpio22 22 0 R/O Wake-Up Detect Status for P2.6

gpio23 23 0 R/O Wake-Up Detect Status for P2.7

Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

PWRMAN_WUD_SEEN0.[gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, gpio31]

Field Bits Default Access Description

gpio24 24 0 R/O Wake-Up Detect Status for P3.0

gpio25 25 0 R/O Wake-Up Detect Status for P3.1

gpio26 26 0 R/O Wake-Up Detect Status for P3.2

gpio27 27 0 R/O Wake-Up Detect Status for P3.3

gpio28 28 0 R/O Wake-Up Detect Status for P3.4

gpio29 29 0 R/O Wake-Up Detect Status for P3.5

gpio30 30 0 R/O Wake-Up Detect Status for P3.6

gpio31 31 0 R/O Wake-Up Detect Status for P3.7

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Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

4.1.12.1.9 PWRMAN_WUD_SEEN1

PWRMAN_WUD_SEEN1.[gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, gpio38, gpio39]

Field Bits Default Access Description

gpio32 0 0 R/O Wake-Up Detect Status for P4.0

gpio33 1 0 R/O Wake-Up Detect Status for P4.1

gpio34 2 0 R/O Wake-Up Detect Status for P4.2

gpio35 3 0 R/O Wake-Up Detect Status for P4.3

gpio36 4 0 R/O Wake-Up Detect Status for P4.4

gpio37 5 0 R/O Wake-Up Detect Status for P4.5

gpio38 6 0 R/O Wake-Up Detect Status for P4.6

gpio39 7 0 R/O Wake-Up Detect Status for P4.7

Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

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• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

PWRMAN_WUD_SEEN1.[gpio40, gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]

Field Bits Default Access Description

gpio40 8 0 R/O Wake-Up Detect Status for P5.0

gpio41 9 0 R/O Wake-Up Detect Status for P5.1

gpio42 10 0 R/O Wake-Up Detect Status for P5.2

gpio43 11 0 R/O Wake-Up Detect Status for P5.3

gpio44 12 0 R/O Wake-Up Detect Status for P5.4

gpio45 13 0 R/O Wake-Up Detect Status for P5.5

gpio46 14 0 R/O Wake-Up Detect Status for P5.6

gpio47 15 0 R/O Wake-Up Detect Status for P5.7

Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

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• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

PWRMAN_WUD_SEEN1.[gpio48, gpio49, gpio50, gpio51, gpio52, gpio53, gpio54, gpio55]

Field Bits Default Access Description

gpio48 16 0 R/O Wake-Up Detect Status for P6.0

gpio49 17 0 R/O Wake-Up Detect Status for P6.1

gpio50 18 0 R/O Wake-Up Detect Status for P6.2

gpio51 19 0 R/O Wake-Up Detect Status for P6.3

gpio52 20 0 R/O Wake-Up Detect Status for P6.4

gpio53 21 0 R/O Wake-Up Detect Status for P6.5

gpio54 22 0 R/O Wake-Up Detect Status for P6.6

gpio55 23 0 R/O Wake-Up Detect Status for P6.7

Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

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• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

PWRMAN_WUD_SEEN1.[gpio56, gpio57, gpio58, gpio59, gpio60, gpio61, gpio62, gpio63]

Field Bits Default Access Description

gpio56 24 0 R/O Wake-Up Detect Status for P7.0

gpio57 25 0 R/O Wake-Up Detect Status for P7.1

gpio58 26 0 R/O Wake-Up Detect Status for P7.2

gpio59 27 0 R/O Wake-Up Detect Status for P7.3

gpio60 28 0 R/O Wake-Up Detect Status for P7.4

gpio61 29 0 R/O Wake-Up Detect Status for P7.5

gpio62 30 0 R/O Wake-Up Detect Status for P7.6

gpio63 31 0 R/O Wake-Up Detect Status for P7.7

Displays wakeup detection status of the 8 listed GPIO pads,

• bit 0: Px.0

• bit 1: Px.1

• bit 2: Px.2

• bit 3: Px.3

• bit 4: Px.4

• bit 5: Px.5

• bit 6: Px.6

• bit 7: Px.7 where a ’1’ bit represents a wakeup condition detected.

Bits for any I/O pads that are not in Wakeup Detect Mode will always read 0.

4.1.12.1.10 PWRMAN_DIE_TYPE

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Default Access Description

n/a R/O Die Type ID Register

Read-only.

Always returns 4D513637h to identify as ’MQ67’.

4.1.12.1.11 PWRMAN_BASE_PART_NUM

PWRMAN_BASE_PART_NUM.base_part_number

Field Bits Default Access Description

base_part_number 15:0 n/a R/O Base Part Number

Always returns 3260h (base part number).

PWRMAN_BASE_PART_NUM.package_select

Field Bits Default Access Description

package_select 28 n/a R/O Package Select

Returns value of package select option setting.

4.1.12.1.12 PWRMAN_MASK_ID0

PWRMAN_MASK_ID0.revision_id

Field Bits Default Access Description

revision_id 3:0 n/a R/O Revision ID

Device revision information.

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PWRMAN_MASK_ID0.mask_id

Field Bits Default Access Description

mask_id 31:4 n/a R/O Mask ID[27:0]

Mask identiﬁcation information - low 28 bits.

4.1.12.1.13 PWRMAN_MASK_ID1

PWRMAN_MASK_ID1.mask_id

Field Bits Default Access Description

mask_id 30:0 n/a R/O Mask ID[58:28]

Mask identiﬁcation information - high 31 bits.

PWRMAN_MASK_ID1.mask_id_enable

Field Bits Default Access Description

mask_id_enable 31 0 R/W Enable Mask ID

Must set to 1 in order for the Mask ID ﬁelds to be readable.

4.1.12.1.14 PWRMAN_PERIPHERAL_RESET

PWRMAN_PERIPHERAL_RESET.uart0

Field Bits Default Access Description

uart0 0 0 R/W Reset UART0

• 0: Peripheral is released to run normally.

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• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.uart1

Field Bits Default Access Description

uart1 1 0 R/W Reset UART1

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.timer0

Field Bits Default Access Description

timer0 2 0 R/W Reset Timer0

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.timer1

Field Bits Default Access Description

timer1 3 0 R/W Reset Timer1

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

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PWRMAN_PERIPHERAL_RESET.timer2

Field Bits Default Access Description

timer2 4 0 R/W Reset Timer2

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.timer3

Field Bits Default Access Description

timer3 5 0 R/W Reset Timer3

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.watchdog0

Field Bits Default Access Description

watchdog0 6 0 R/W Reset Watchdog Timer 0

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.usb

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Field Bits Default Access Description

usb 7 0 R/W Reset USB

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.adc

Field Bits Default Access Description

adc 8 0 R/W Reset ADC

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.dac0

Field Bits Default Access Description

dac0 9 0 R/W Reset 12-Bit DAC 0

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.dac1

Field Bits Default Access Description

dac1 10 0 R/W Reset 12-Bit DAC 1

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• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.dac2

Field Bits Default Access Description

dac2 11 0 R/W Reset 8-Bit DAC 0

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.dac3

Field Bits Default Access Description

dac3 12 0 R/W Reset 8-Bit DAC 1

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.dma

Field Bits Default Access Description

dma 13 0 R/W Reset DMA/PMU

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

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PWRMAN_PERIPHERAL_RESET.lcd

Field Bits Default Access Description

lcd 14 0 R/W Reset LCD

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.gpio

Field Bits Default Access Description

gpio 15 0 R/W Reset GPIO Module

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.pulse_train

Field Bits Default Access Description

pulse_train 16 0 R/W Reset All Pulse Trains

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.spi0

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Field Bits Default Access Description

spi0 17 0 R/W Reset SPI 0

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.spi1

Field Bits Default Access Description

spi1 18 0 R/W Reset SPI 1

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.spi2

Field Bits Default Access Description

spi2 19 0 R/W Reset SPI 2

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.i2cm0

Field Bits Default Access Description

i2cm0 20 0 R/W Reset I2C Master 0

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• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.i2cm1

Field Bits Default Access Description

i2cm1 21 0 R/W Reset I2C Master 1

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.i2cs

Field Bits Default Access Description

i2cs 22 0 R/W Reset I2C Slave

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.crc

Field Bits Default Access Description

crc 23 0 R/W Reset CRC Engine

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

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PWRMAN_PERIPHERAL_RESET.tpu

Field Bits Default Access Description

tpu 24 0 R/W Reset TPU

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

PWRMAN_PERIPHERAL_RESET.ssb

Field Bits Default Access Description

ssb 25 0 R/W Reset RTC SSB

• 0: Peripheral is released to run normally.

• 1: Peripheral is held in a reset state.

4.1.13 Registers (PWRSEQ)

4.1.13.1 Module PWRSEQ Registers

Address Register

0x40090A30 PWRSEQ_REG0 1 Power Sequencer Control Register 0

0x40090A34 PWRSEQ_REG1 1 Power Sequencer Control Register 1

0x40090A38 PWRSEQ_REG2 1 Power Sequencer Control Register 2

0x40090A3C PWRSEQ_REG3 1 Power Sequencer Control Register 3

0x40090A40 PWRSEQ_REG4 1 Power Sequencer Control Register 4

0x40090A44 PWRSEQ_REG5 1 Power Sequencer Control Register 5 (Trim 0)

0x40090A48 PWRSEQ_REG6 1 Power Sequencer Control Register 6 (Trim 1)

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32b

Word Len Description

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Address Register

0x40090A50 PWRSEQ_FLAGS 1 Power Sequencer Flags

0x40090A54 PWRSEQ_MSK_FLAGS 1 Power Sequencer Flags Mask Register

4.1.13.1.1 PWRSEQ_REG0

PWRSEQ_REG0.pwr_lp1

Field Bits Default Access Description

pwr_lp1 0 0 (PwrSeq RSTN, see note) R/W Shutdown Power Mode Select

• 0: Shutdown to LP0 (default)

• 1: Shutdown to LP1

Note This ﬁeld is reset by any of the following conditions/ events:

• PwrSeq RSTN (power sequencer asynchronous reset)

• System Reboot event

• Whenever pwr_prv_pwr_fail_r == 1

32b

Word Len Description

PWRSEQ_REG0.pwr_ﬁrst_boot

Field Bits Default Access Description

pwr_ﬁrst_boot 1 1 R/W Wake on First Boot

Wakeup on ﬁrst power automatically. (default 1)

PWRSEQ_REG0.pwr_sys_reboot

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Field Bits Default Access Description

pwr_sys_reboot 2 0 W/O Firmware System Reboot Request

Writing a 1 to this bit triggers a system reboot.

PWRSEQ_REG0.pwr_ldoen_run

Field Bits Default Access Description

pwr_ldoen_run 3 1 (PwrSeq RSTN) R/W Enable Main 1.8V LDO Operation in

Run Mode

3V to 1.8V LDO enable during run (default 1)

PWRSEQ_REG0.pwr_ldoen_slp

Field Bits Default Access Description

pwr_ldoen_slp 4 0 (PwrSeq RSTN) R/W Enable Main 1.8V LDO Operation in

Sleep Mode

3V to 1.8V LDO enable during sleep (default 0)

PWRSEQ_REG0.pwr_chzyen_run

Field Bits Default Access Description

pwr_chzyen_run 5 0 (PwrSeq RSTN) R/W Enable Backup 1.8V LDO Opera-

tion in Run Mode

Chzy regulator enable during run (default 0)

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PWRSEQ_REG0.pwr_chzyen_slp

Field Bits Default Access Description

pwr_chzyen_slp 6 1 R/W Enable Backup 1.8V LDO Operation in Sleep

Mode

Chzy regulator enable during sleep (default 1)

PWRSEQ_REG0.pwr_roen_run

Field Bits Default Access Description

pwr_roen_run 7 1 R/W Enable System Relaxation Oscillator in Run

Mode

Relaxation osc enable during run (default 1)

PWRSEQ_REG0.pwr_roen_slp

Field Bits Default Access Description

pwr_roen_slp 8 0 (PwrSeq RSTN) R/W Enable System Relaxation Oscillator

in Sleep Mode

Relaxation osc enable during sleep (default 0)

PWRSEQ_REG0.pwr_nren_run

Field Bits Default Access Description

pwr_nren_run 9 0 (RTC POR) R/W Enable Nano Oscillator in Run Mode

Nano oscillator enable during run (default 0)

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PWRSEQ_REG0.pwr_nren_slp

Field Bits Default Access Description

pwr_nren_slp 10 0 (RTC POR) R/W Enable Nano Oscillator in Sleep Mode

Nano oscillator enable during sleep (default 0)

PWRSEQ_REG0.pwr_rtcen_run

Field Bits Default Access Description

pwr_rtcen_run 11 0 (RTC POR) R/W Enable Real Time Clock operation in Run

Mode

Real Time Clock enable during run (default 0)

PWRSEQ_REG0.pwr_rtcen_slp

Field Bits Default Access Description

pwr_rtcen_slp 12 0 (RTC POR) R/W Enable Real Time Clock operation in

Sleep Mode

Real Time Clock enable during sleep (default 0)

PWRSEQ_REG0.pwr_svm3en_run

Field Bits Default Access Description

pwr_svm3en_run 13 1 (PwrSeq RSTN) R/W Enable VDD3 SVM operation in

Run Mode

VDD3 SVM enable during run mode (default 1)

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PWRSEQ_REG0.pwr_svm3en_slp

Field Bits Default Access Description

pwr_svm3en_slp 14 1 (PwrSeq RSTN) R/W Enable VDD3 SVM operation in

Sleep Mode

VDD3 SVM enable during sleep mode (default 1)

PWRSEQ_REG0.pwr_svm1en_run

Field Bits Default Access Description

pwr_svm1en_run 15 1 (PwrSeq RSTN) R/W Enable VREG18 SVM operation

in Run Mode

VREG18 SVM enable during run mode (default 1)

PWRSEQ_REG0.pwr_svm1en_slp

Field Bits Default Access Description

pwr_svm1en_slp 16 1 (PwrSeq RSTN) R/W Enable VREG18 SVM operation in

Sleep Mode

VREG18 SVM enable during sleep mode (default 1)

PWRSEQ_REG0.pwr_svmrtcen_run

Field Bits Default Access Description

pwr_svmrtcen_run 17 0 (PwrSeq RSTN) R/W Enable VRTC SVM operation in

Run Mode

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VRTC SVM enable during run mode (default 0)

PWRSEQ_REG0.pwr_svmrtcen_slp

Field Bits Default Access Description

pwr_svmrtcen_slp 18 0 (PwrSeq RSTN) R/W Enable VRTC SVM operation in

Sleep Mode

VRTC SVM enable during sleep mode (default 0)

PWRSEQ_REG0.pwr_svmvdda3en

Field Bits Default Access Description

pwr_svmvdda3en 19 0 (PwrSeq RSTN) R/W Enable VDDA3 SVM operation (in

Run Mode only)

VDDA3 SVM enable (can only be enabled during RUN mode). default 0.

4.1.13.1.2 PWRSEQ_REG1

PWRSEQ_REG1.pwr_trikl_chrg

Field Bits Default Access Description

pwr_trikl_chrg 7:0 00h (PwrSeq RSTN) R/W Trickle Charge Control for VRTC

External Capacitor

Trickle charger (for VRTC external supercap). To enable the trickle charger, bits [7:4] must equal 1010b (Ah); all other settings for [7:4] result in the function staying disabled.

• A5h - no diode + 250ohm

• A6h - no diode + 2kohm

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• A7h - no diode + 4kohm

• A9h - diode + 250ohm

• AAh - diode + 2kohm

• ABh - diode + 4kohm

By default, the trickle charger is disabled.

PWRSEQ_REG1.pwr_pd_vdda3

Field Bits Default Access Description

pwr_pd_vdda3 8 0 (PwrSeq RSTN) R/W Power Down VDDA3 Supply Rail

• 0: VDDA3 supply rail is powered on (default).

• 1: VDDA3 supply rail is powered down.

PWRSEQ_REG1.pwr_temp_sensor_pd

Field Bits Default Access Description

pwr_temp_sensor_pd 9 1 (PwrSeq RSTN) R/W Power Down Internal Temper-

ature Sensor

• 0: Internal temp sensor is powered on and can be used.

• 1: Internal temp sensor is powered off (default).

PWRSEQ_REG1.pwr_pd_vddio

Field Bits Default Access Description

pwr_pd_vddio 10 0 (PwrSeq RSTN) R/W Power Down VDDIO Supply Rail

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• 0: VDDIO supply rail is powered on (default).

• 1: VDDIO supply rail is powered down.

PWRSEQ_REG1.pwr_man_vddio_sw

Field Bits Default Access Description

pwr_man_vddio_sw 11 0 (PwrSeq RSTN) R/W Manual Override Enable for V−

DDIO Switch 1/2

• 0: No effect (default).

• 1: Manual overrides are enabled for VDDIO_SW1 and VDDIO_SW2.

PWRSEQ_REG1.pwr_man_vddio_sw2

Field Bits Default Access Description

pwr_man_vddio_sw2 12 0 (PwrSeq RSTN) R/W Manual Override for VDDIO_−

SW2

This setting will only take effect when the Manual Override Enable for VDDIO Switch 1/2 has been set to 1.

• 0: VDDIO_SW2 is set to VREG18 mode (default).

• 1: VDDIO_SW2 is set to VDDIO mode.

PWRSEQ_REG1.pwr_man_vddio_sw1

Field Bits Default Access Description

pwr_man_vddio_sw1 13 0 (PwrSeq RSTN) R/W Manual Override for VDDIO_−

SW1

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This setting will only take effect when the Manual Override Enable for VDDIO Switch 1/2 has been set to 1.

• 0: VDDIO_SW1 is set to VREG18 mode (default).

• 1: VDDIO_SW1 is set to VDDIO mode.

PWRSEQ_REG1.pwr_gpio_freeze

Field Bits Default Access Description

pwr_gpio_freeze 14 0 (PwrSeq RSTN) R/W Freeze GPIO WUD and Keeper

Latches

• 0: GPIO WUD and keeper latches operate normally (default).

• 1: GPIO WUD and keeper latches are frozen.

4.1.13.1.3 PWRSEQ_REG2

PWRSEQ_REG2.pwr_rst3

Field Bits Default Access Description

pwr_rst3 4:0 4 (PwrSeq RSTN) R/W pwr_rst3_o - VDD3 Reset decode

approx 30-45mV step over applicable range.

PWRSEQ_REG2.pwr_w3

Field Bits Default Access Description

pwr_w3 9:5 16 (PwrSeq RSTN or VDD3 rail POR) R/W pwr_w3_o[4:0]

VDD3 Warning decode. approx 30-45mV step size over applicable range

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PWRSEQ_REG2.pwr_w1

Field Bits Default Access Description

pwr_w1 14:10 15 (PwrSeq RSTN or VDD3 rail POR) R/W pwr_w1_o[4:0]

VREG18 Warning decode. approx 30mV step size over applicable range.

PWRSEQ_REG2.pwr_w1_low

Field Bits Default Access Description

pwr_w1_low 19:15 4 (PwrSeq RSTN) R/W pwr_w1_low_o[4:0]

VREG18 Warning LOW decode. approx 25mV step size over applicable range.

PWRSEQ_REG2.pwr_wrtc

Field Bits Default Access Description

pwr_wrtc 24:20 16 (PwrSeq RSTN) R/W pwr_wrtc_o[4:0]

VRTC decode. 32 steps. approx 30-45mV step size over applicable range.

PWRSEQ_REG2.pwr_wvdda3

Field Bits Default Access Description

pwr_wvdda3 30:25 3Fh (PwrSeq RSTN) R/W pwr_wvdda3_o[5:0]

VDDA3 decode. 3.6V...1.59V total, 3.48V...1.59V in 64 steps. 30mV step size.

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4.1.13.1.4 PWRSEQ_REG3

PWRSEQ_REG3.pwr_rosel

Field Bits Default Access Description

pwr_rosel 2:0 101b (PwrSeq RSTN) R/W pwr_rosel_o[2:0]

Relaxation Oscillator Stable timeout setting (in RO clocks)

• 000b - Bypass

• 001b - 64 clocks

• 010b - 128 clocks

• 011b - 256 clocks

• 100b - 512 clocks

• 101b - 1024 clocks (default setting)

• 110b - 2048 clocks

• 111b - 262144 clocks

PWRSEQ_REG3.pwr_rosel_quick

Field Bits Default Access Description

pwr_rosel_quick 4:3 00b (PwrSeq RSTN, see notes∗) R/W pwr_rosel_quick_−

o[1:0]

Quick Relaxation Oscillator Stable timeout (in RO clocks)

• 00b: Bypass (default setting)

• 01b: 64 clocks

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• 10b: 128 clocks

• 11b: 256 clocks

Notes∗

• This ﬁeld is reset by any of the following conditions/events:

– PwrSeq RSTN (power sequencer asynchronous reset)

– System Reboot event

– Whenever pwr_prv_pwr_fail_r == 1

– Whenever pwr_prv_boot_fail_r == 1

PWRSEQ_REG3.pwr_svmsel

Field Bits Default Access Description

pwr_svmsel 7:5 000b (PwrSeq RSTN) R/W pwr_svmsel_o[2:0]

SVM timeout count. (SVM clks)

• 000 - Bypass (Default)

• 001 - 30 sec

• 010 - 1 min

• 011 - 2 min

• 100 - 4 min

• 101 - 8 min

• 110 - 16 min

• 111 - 32 min.

PWRSEQ_REG3.pwr_pwrﬂtrsvmselo

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Maxim Integrated MAX32600 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

MAX32600 User’s Guide Main Page

1.1 Legal Disclaimer

1.2 Revision Information

MAX32600 User’s Guide Introduction

2.1 Overview

2.3 Power Supplies and Modes

2.5 Memory

2.6 Analog Peripherals

2.7 Digital Peripherals

2.8 Security Features

MAX32600 User’s Guide Memory, Register Mapping, and Access

3.1 Memory, Register Mapping, and Access Overview

3.3 Device Memory Instances

3.4 AHB Bus Matrix and AHB Bus Interfaces

4.1 Power Ecosystem and Operating Modes