Maxim Integrated MAX1540, MAX1541 Schematic

General Description

The MAX1540/MAX1541 dual pulse-width modulation (PWM) controllers provide the high efficiency, excellent transient response, and high DC-output accuracy necessary for stepping down high-voltage batteries to generate low-voltage chipset and RAM power supplies in notebook computers.

The Maxim proprietary Quick-PWM™ controllers are free running, constant on-time with input feed forward. This configuration provides ultra-fast transient response, wide input-output (I/O) differential range, low supply current, and tight load-regulation characteristics. The controllers can accurately sense the inductor current across an external current-sense resistor in series with the output to ensure reliable overload and inductor saturation protection. Alternatively, the controllers can use the synchronous rectifier itself or lossless inductor current-sensing methods to provide overload protection with lower power dissipation.

For a single step-down PWM controller with inductorsaturation protection, external-reference input voltage, and dynamically selectable output voltages, refer to the MAX1992/MAX1993 data sheet.

Applications

Notebook Computers

Core/IO Supplies as Low as 0.7V

0.7V to 5.5V Supply Rails

CPU/Chipset/GPU with Dynamic Voltage Core Supplies (MAX1541)

DDR Memory Termination (MAX1541)

Active Termination Buses (MAX1541)

Features

♦ Inductor-Saturation Protection ♦ Accurate Differential Current-Sense Inputs ♦ Dual Ultra-High-Efficiency Quick-PWMs with

100ns Load-Step Response

♦ MAX1540

1.8V/1.2V Fixed or 0.7V to 5.5V Adjustable Output (OUT1)

2.5V/1.5V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Fixed 5V, 100mA Linear Regulator

♦ MAX1541

External Reference Input (REFIN1) Dynamically Selectable Output Voltage—0.7V to 5.5V (OUT1)

2.5V/1.8V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Optional Power-Good and Fault Blanking During Transitions Fixed 5V or Adjustable 100mA Linear Regulator

♦ 1% V

OUT

Accuracy over Line and Load

♦ 2V to 28V Battery Input Range ♦ 170kHz to 620kHz Selectable Switching

Frequency

♦ Overvoltage/Undervoltage-Protection Option ♦ 1.7ms Digital Soft-Start ♦ Drives Large Synchronous-Rectifier FETs ♦ 2V ±0.7% Reference Output ♦ Separate Power-Good Window Comparators

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

________________________________________________________________ Maxim Integrated Products 1

THIN QFN

TOP VIEW

32313029282726

ON1

ON2

CSP1

CSN1

FB1

OUT1

PGOOD1

25 DH1

1011121314

CSP2

CSN2

FB2

OUT2

PGOOD2

DH2

LX2

16BST2

GND

DL2

V+

LDOOUT

DL1

LDOON

BST1

REF

ILIM2

ILIM1

TON

LSAT

SKIP

MAX1540

1OVP/UVP

24 LX1

Pin Configurations

19-2861; Rev 2; 1/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Quick-PWM is a trademark of Maxim Integrated Products, Inc.

Ordering Information

PART

PIN-PACKAGE

MAX1540ETJ

32 Thin QFN 5mm x 5mm

MAX1541ETL

40 Thin QFN 6mm x 6mm

Pin Configurations continued at end of data sheet.

TEMP RANGE

-40°C to +85°C

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: For the MAX1540, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT),

and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+).

V+, LDOON to GND ...............................................-0.3V to +28V

LDOOUT to GND (MAX1540, Note 1) ......................-0.3V to +6V

LDOOUT to GND (MAX1541, Note 1) ....................-0.3V to +28V

to GND (MAX1541, Note 1) ..............................-0.3V to +6V

, ON_ to GND.....................................................-0.3V to +6V

SKIP, PGOOD_ to GND............................................-0.3V to +6V

FB_, CSP_, ILIM_ to GND.........................................-0.3V to +6V

TON, OVP/UVP, LSAT to GND ...................-0.3V to (V

+ 0.3V)

REF, OUT_ to GND.....................................-0.3V to (V

+ 0.3V)

LDOIN to GND (MAX1541).....................................-0.3V to +28V

REFIN1, GATE, OD, FBLDO to GND (MAX1541).....-0.3V to +6V

FBLANK, CC1 to GND (MAX1541).............-0.3V to (V

+ 0.3V)

DL_ to GND (Note 1) ..................................-0.3V to (V

+ 0.3V)

CSN_ to GND ............................................................-2V to +30V

DH_ to LX_..................................................-0.3V to (BST + 0.3V)

LX_ to GND................................................................-2V to +30V

BST_ to LX_ ..............................................................-0.3V to +6V

REF Short Circuit to GND ...........................................Continuous

Continuous Power Dissipation (T

= +70°C) 32-Pin 5mm x 5mm Thin QFN (derated 21.3mW/°C

above +70°C).............................................................1702mW

40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/°C

above +70°C).............................................................2105mW

Operating Temperature Range

MAX154_ET_ ...................................................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= 0°C to +85°C, unless otherwise noted. Typical values are at T

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

INPUT SUPPLIES (Note 1)

MAX1540: battery voltage, V+ > V

LDOOUT

5.5 28

MAX1541: battery voltage, V+ > V

LDOOUT

228

BIAS

CC, VDD

(MAX1541) 4.5 5.5Input Voltage Range

LDOIN

MAX1541: LDO input supply, V

LDOIN

> V

LDOOUT

4.5 28

FB1 and FB2 forced above the regulation point, LSAT = GND

0.7 1.5

Quiescent Supply Current (VCC)I

FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

, V

LSAT

> 0.5V

1.8

Quiescent Supply Current (V

, MAX1541 Only)

FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

<1 5 µA

MAX1540: FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

LDOON

= V+ = 28V

150

Quiescent Supply Current (V+) I

V+

MAX1541: ON1 or ON2 = VCC, V

LDOON

= V+ = 28V

25 40

µA

Quiescent Supply Current (LDOIN, MAX1541 Only)

LDOIN

FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

LDOON

= V+ = 28V

110 µA

Standby Supply Current (VCC) ON1 = ON2 = GND, V

LDOON

= V+ = 28V <1 5 µA

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= 0°C to +85°C, unless otherwise noted. Typical values are at T

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Standby Supply Current (V

, MAX1541 Only)

ON1 = ON2 = GND, V

LDOON

= V+ = 28V <1 5 µA

MAX1540: ON1 = ON2 = GND, LDOON = V+ = 28V, V

= 0 or 5V

105

Standby Supply Current (V+)

MAX1541: ON1 = ON2 = GND, LDOON = V+ = 28V, V

= VDD = 0 or 5V

<1 5

µA

Standby Supply Current (LDOIN, MAX1541 Only)

ON1 = ON2 = GND, V

LDOON

= V+ = 28V 100 µA

Shutdown Supply Current (VCC) ON1 = ON2 = LDOON = GND <1 5 µA

Shutdown Supply Current (V

, MAX1541 Only)

ON1 = ON2 = LDOON = GND <1 5 µA

MAX1540: ON1 = ON2 = LDOON = GND, V+ = 28V, V

= 0 or 5V

415

Shutdown Supply Current (V+)

MAX1541: ON1 = ON2 = LDOON = GND, V+ = 28V, V

= VDD = 0 or 5V

<1 5

µA

Shutdown Supply Current (LDOIN, MAX1541 Only)

LDOON = GND 4 10 µA

PWM CONTROLLERS

FB1 = GND

OUT1

Preset output, V+ = 5.5V to 28V, SKIP = V

FB1 = V

MAX1540 Main Output-Voltage Accuracy (OUT1) (Note 2)

FB1

Adjustable output, V+ = 5.5V to 28V, SKIP = V

FB2 = GND

OUT2

Preset output, V+ = 5.5V to 28V, SKIP = V

FB2 = V

MAX1540 Secondary OutputVoltage Accuracy (OUT2) (Note 2)

FB2

Adjustable output, V+ = 5.5V to 28V, SKIP = V

MAX1541 Main FeedbackVoltage Accuracy (FB1)

FB1

V+ = 4.5V to 28V, SKIP = V

FB2 = GND

OUT2

Preset output, V+ = 4.5V to 28V, SKIP = V

FB2 = V

MAX1541 Secondary OutputVoltage Accuracy (OUT2) (Note 2)

FB2

Adjustable output, V+ = 4.5V to 28V, SKIP = V

Load-Regulation Error I

LOAD

= 0 to 3A, SKIP = V

0.1 %

Line-Regulation Error VCC = 4.5V to 5.5V, V+ = 4.5V to 28V

FB_ Input Bias Current IFB_

µA

Output Adjust Range 0.7 5.5 V

REFIN1 = 0.35 x REF 0.693 0.70 0.707

1.782 1.80 1.818

1.188 1.20 1.212

0.693 0.70 0.707

2.475 2.50 2.525

1.485 1.50 1.515

0.693 0.70 0.707

2.475 2.50 2.525

1.782 1.80 1.818

0.693 0.70 0.707

-0.1 +0.1

0.25

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= 0°C to +85°C, unless otherwise noted. Typical values are at T

= +25°C.)

PARAMETER

CONDITIONS

UNITS

FB_ = GND 70

350

MAX1540

FB_ = V

adjustable

220

FB1 = OUT1

FB2 = GND 90

350

OUT_ Input Resistance R

OUT

MAX1541

FB2 = V

adjustable

270

kΩ

OUT_ Discharge Mode OnResistance

10 25 Ω

OUT_ Synchronous-Rectifier Discharge-Mode Turn-On Level

0.2 0.3 0.4 V

Soft-Start Ramp Time t

Rising edge on ON_ to full current limit 1.7 ms

TON = GN D ( 620kH z)

190

242

335

DH1 On-Time t

ON1

V+ = 15V, V

OUT1

= 1.5V

(Note 3)

491

256

331

453

DH2 On-Time t

ON2

V+ = 15V, V

OUT2

= 1.5V

(Note 3)

679

On-Time Tracking t

ON2

with respect to t

ON1

(Note 3)

150 %

Minimum Off-Time

)

(Note 3)

500 ns

LINEAR REGULATOR (LDO) (Note 1)

5.0

MAX1540 LDO Output-Voltage Accuracy

ON1 = ON2 = GND, V+ = 6V to 28V

5.0

MAX1541 LDO Output-Voltage Accuracy (Fixed V

LDOOUT

)

FBLDO = ON1 = ON2 = GND,

MAX1541 LDO Feedback

FBLDO = LDOOUT, ON1 = ON2 = GND, V

LDOIN

= 4.5V to

28V

MAX1541 LDO Output Adjust Range

24 V

LDOOUT Short-Circuit Current

FBLDO Input Bias Current I

FBLDO

µA

800

Dropout Voltage

MAX1541: V

LDOIN

- V

LDOOUT

= 50mA

800

Accuracy (Adjustable V

LDOOUT

)

SYMBOL

MIN TYP MAX

145

115

400 700 1500

170

130

D IS C H ARGE

TON = REF (485kHz) 191 216

149 169

TON = op en ( 345kH z) 274 304

TON = VCC (235kHz) 402 447

TON = GN D ( 460kH z) 201 228

TON = REF (355kHz) 260 296

TON = op en ( 255kH z) 371 412

TON = VCC (170kHz) 556 618

OFF(MIN

120 135

400

LDOOUT

LDOIN

FBLDO

= 6V to 28V

0 < I

LD OOU T

< 10mA 4.85

LDOOUT

< 100m A 4.70 5.10

< 10mA 4.85

LDOOUT

< 100m A 4.70 5.10

< 10mA 1.212 1.25 1.275

LDOOUT

< 100m A 1.175 1.275

1.175

130

-0.1 +0.1

MAX1540: V+ - V

LDOOUT

, I

LDOOUT

= 50mA 500

500

5.10

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= 0°C to +85°C, unless otherwise noted. Typical values are at T

= +25°C.)

PARAMETER

CONDITIONS

UNITS

REFERENCE (REF)

Reference Voltage V

REF

VCC = 4.5V to 5.5V, I

REF

= 0V

= 0° C to +85°C

Reference Load Regulation ∆V

REFIREF

= -10µA to +50µA

REF Lockout Voltage

)

Rising edge, hysteresis = 350mV

REFIN1 (MAX1541) Voltage Range

REFIN

0.7

REFIN1 (MAX1541) Input Bias Current

REFIN1

µA

FAULT DETECTION

Overvoltage Trip Threshold

With respect to error-comparator threshold, OVP/UVP = V

12 16 20 %

Overvoltage Fault-Propagation Delay

OVP

FB forced 2% above trip threshold 10 µs

Output Undervoltage-Protection Trip Threshold

With respect to error-comparator threshold, OVP/UVP = V

65 70 75 %

Output Undervoltage-Protection Blanking Time

BLANK

From rising edge of ON_ 10 35 ms

Output Undervoltage FaultPropagation Delay

UVP

10 µs

PGOOD_ Lower Trip Threshold

With respect to error-comparator threshold, hysteresis = 1%

-13 -10 -7 %

PGOOD_ Upper Trip Threshold

With respect to error-comparator threshold, hysteresis = 1%

PGOOD_ Propagation Delay

10 µs

PGOOD_ Output Low Voltage I

SINK

= 4mA 0.3 V

PGOOD_ Leakage Current

FB = REF (PGOOD high impedance), PGOOD forced to 5.5V

1µA

FBLANK = V

320

FBLANK = open 80

205

Fault-Blanking Time (MAX1541 Only)

FBLANK = REF 35 65 95

µs

LDOON = V

Thermal-Shutdown Threshold T

SHDN

Hysteresis = 10°C

LDOON = GND

°C

VCC Undervoltage-Lockout Threshold

)

Rising edge, PWM disabled below this level, hysteresis = 20mV

4.1

4.4 V

CURRENT LIMIT

ILIM_ Adjustment Range

CSP_ 0 2.7

Current-Limit Input Range

CSN_

CSP_/CSN_ Input Current 0.5 µA

SYMBOL

TA = + 25° C to + 85° C 1.986 2.00 2.014

REF(UVLO

PGOOD

FBLANK

UVLO(VCC

FB forced 2% beyond P GOOD _ trip threshold

MIN TYP MAX

1.983 2.00 2.017

-0.01 +0.01

1.95

0.01 0.05

+10 +13

120 220

0.25

-0.3 +28

140

+150

+160

4.25

REF

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

6 _______________________________________________________________________________________

Dual Mode is a trademark of Maxim Integrated Products, Inc.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Valley Current-Limit Threshold (Fixed)

)

CSP

_ - V

CSN

_, ILIM_ = V

45 50 55 mV

ILIM

_ = 250mV 15 25 35

Valley Current-Limit Threshold (Adjustable)

)

CSP

_ - V

CSN

ILIM

_ = 2.00V

230

Current-Limit Threshold (Negative)

NEG

CSP

_ - V

CSN

_, SKIP = ILIM_ = VCC,

= +25°C

-90 -65 -45 mV

Current-Limit Threshold (Zero Crossing)

With respect to valley current-limit threshold, V

CSP

_ - V

CSN

_, SKIP = GND,

ILIM_ = V

2.5 mV

LSAT = V

220

LSAT = open

193

Inductor-Saturation Current-Limit Threshold

With respect to valley currentlimit threshold, ILIM_ = V

LSAT = REF

165

ILIM_ Saturation Fault Sink Current

)

CSP

- V

CSN

> inductor saturation current

limit, 0.25V < V

ILIM

_ < 2.0V

468µA

ILIM_ Leakage Current

CSP

_ - V

CSN _

< inductor saturation current

limit

0.1 µA

GATE DRIVERS

DH_ Gate-Driver On-Resistance R

BST_-LX_ forced to 5V 1.5 5 Ω

DL_, high state 1.5 5

DL_ Gate-Driver On-Resistance R

DL_, low state 0.6 3

Ω

DH_ Gate-Driver Source/Sink Current

DL_ Gate-Driver Source Current

(

)

DL_ forced to 2.5V 1 A

DL_ Gate-Driver Sink Current

)

DL_ forced to 2.5V 3 A

DL_ rising 35

Dead Time t

DEAD

DH_ rising 26

INPUTS AND OUTPUTS

OD On-Resistance R

GATE = V

10 25 Ω

OD Leakage Current GATE = GND, OD forced to 5.5V 1 200 nA

Logic Input Threshold

ON1, ON2, SKIP, GATE rising edge, hysteresis = 225mV

1.2 1.7 2.2 V

LDOON Input Trip Level Rising edge, hysteresis = 250mV

Logic Input Current ON1, ON2, LDOON, SKIP, GATE -1 +1 µA

High 1.9 2.0 2.1

Dual Mode™ Threshold Voltage

MAX1541)

Low

0.1

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= 0°C to +85°C, unless otherwise noted. Typical values are at T

= +25°C.)

LIM_ (VAL

170 200

ILIM_ (LSAT

SOURCE

DL (SINK

DH_ forced to 2.5V, BST_-LX_ forced to 5V

FB1 (MAX1540), FB2 (MAX1540/

180 200

157 175

135 150

1.20 1.25 1.30

0.05

0.15

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= 0°C to +85°C, unless otherwise noted. Typical values are at T

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

High

Open

REF

Four-Level Input Logic Levels

TON, OVP/UVP, LSAT, SKIP, FBLANK

Low 0.5

Four-Level Logic Input Current

TON, OVP/UVP, LSAT, SKIP, FBLANK forced to GND or V

-3 +3 µA

ELECTRICAL CHARACTERISTICS

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)

PARAMETER

CONDITIONS

INPUT SUPPLIES (Note 1)

MAX1540: battery voltage, V+ > V

LDOOUT

5.5 28

MAX1541: battery voltage, V+ > V

LDOOUT

228

BIAS

CC, VDD

(MAX1541) 4.5 5.5Input Voltage Range

LDOIN

MAX1541: LDO input supply, V

LDOIN

> V

LDOOUT

4.5 28

FB1 and FB2 forced above the regulation point, LSAT = GND

1.5

Quiescent Supply Current (VCC)I

FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

, V

LSAT

> 0.5V

1.8

Quiescent Supply Current (V

, MAX1541 Only)

FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

5µA

MAX1540: FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

LDOON

= V+ = 28V

150

Quiescent Supply Current (V+) I

V+

MAX1541: ON1 or ON2 = VCC, V

LDOON

V+ = 28V

µA

Quiescent Supply Current (LDOIN, MAX1541 Only)

LDOIN

FB1 and FB2 forced above the regulation point, ON1 or ON2 = V

LDOON

= V+ = 28V

110 µA

Standby Supply Current (VDD) ON1 = ON2 = GND, V

LDOON

= V+ = 28V 5 µA

Standby Supply Current (V

, MAX1541 Only)

ON1 = ON2 = GND, V

LDOON

= V+ = 28V 5 µA

MAX1540: ON1 = ON2 = GND, LDOON = V+ = 28V, V

= 0 or 5V

105

Standby Supply Current (V+)

MAX1541: ON1 = ON2 = GND, LDOON = V+ = 28V, V

= VDD = 0 or 5V

µA

Standby Supply Current (LDOIN, MAX1541 Only)

ON1 = ON2 = GND, V

LDOON

= V+ = 28V 100 µA

SYMBOL

0.4V

3.15 3.85

1.65 2.35

MIN MAX UNITS

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

8 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)

PARAMETER

CONDITIONS

UNITS

Shutdown Supply Current (VCC) ON1 = ON2 = LDOON = GND 5 µA

Shutdown Supply Current (V

, MAX1541 Only)

ON1 = ON2 = LDOON = GND 5 µA

MAX1540: ON1 = ON2 = LDOON = GND, V+ = 28V, V

= 0 or 5V

Shutdown Supply Current (V+)

MAX1541: ON1 = ON2 = LDOON = GND, V+ = 28V, V

= VDD = 0 or 5V

µA

Shutdown Supply Current (LDOIN, MAX1541 Only)

LDOON = GND 10 µA

PWM CONTROLLERS

FB1 = GND

OUT1

Preset output, V+ = 5.5V to 28V, SKIP = V

FB1 = V

MAX1540 Main Output-Voltage Accuracy (OUT1) (Note 2)

FB1

Adjustable output, V+ = 5.5V to 28V, SKIP = V

FB2 = GND

OUT2

Preset output, V+ = 5.5V to 28V, SKIP = V

FB2 = V

MAX1540 Secondary OutputVoltage Accuracy (OUT2) (Note 2)

FB2

Adjustable output, V+ = 5.5V to 28V, SKIP = V

MAX1541 Main Feedback Voltage Accuracy (FB1)

FB1

V+ = 4.5V to 28V, SKIP = V

CC REFIN1 = REF

FB2 = GND

OUT2

Preset output, V+ = 4.5V to 28V, SKIP = V

FB2 = V

MAX1541 Secondary OutputVoltage Accuracy (OUT2) (Note 2)

FB2

Adjustable output, V+ = 4.5V to 28V, SKIP = V

190

242

335

DH1 On-Time (Note 3) t

ON1

V+ = 15V, V

OUT1

= 1.5V

491

256

331

453

DH2 On-Time (Note 3) t

ON2

V+ = 15V, V

OUT2

= 1.5V

679

On-Time Tracking t

ON2

with respect to t

ON1

(Note 3)

152 %

Minimum Off-Time

)

(Note 3) 500 ns

LINEAR REGULATOR (LDO) (Note 1)

MAX1540 LDO Output-Voltage Accuracy

ON1 = ON2 = GND, V+ = 6V to 28V

SYMBOL

MIN MAX

OFF(MIN

LDOOUT

1.773 1.827

1.182 1.218

0.689 0.711

2.462 2.538

1.477 1.523

0.689 0.711

REFIN1 = 0.35 x REF 0.689 0.711

1.97 2.03

2.462 2.538

1.773 1.827

0.689 0.711

TON = G N D ( 620kH z) 149

TON = RE F ( 485kH z) 191

TON = op en ( 345kH z) 274

TON = V CC ( 235kH z) 402

TON = G N D ( 460kH z) 201

TON = RE F ( 355kH z) 260

TON = op en ( 255kH z) 371

TON = V CC ( 170kH z) 556

0 < I

L D OOU T

< 10mA 4.85 5.10

LDOOUT

< 100m A 4.65 5.10

118

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

_______________________________________________________________________________________ 9

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)

PARAMETER

CONDITIONS

UNITS

MAX1541 LDO Output-Voltage Accuracy (Fixed V

LDOOUT

)

FBLDO = ON1 = ON2 = GND,

MAX1541 LDO Feedback

Accuracy (Adjustable V

LDOOUT

)

FBLDO = LDOOUT, ON1 = ON2 = GND, V

LDOIN

= 4.5V to

28V

800

Dropout Voltage

MAX1541: V

LDOIN

- V

LDOOUT

= 50mA

800

REFERENCE (REF)

Reference Voltage V

REF

VCC = 4.5V to 5.5V, I

REF

= 0

REFIN1 Input Bias Current I

REFIN1

µA

FAULT DETECTION

Overvoltage Trip Threshold

With respect to error-comparator threshold, OVP/UVP = V

10 21 %

Output Undervoltage-Protection Trip Threshold

With respect to error-comparator threshold, OVP/UVP = V

64 76 %

PGOOD_ Lower Trip Threshold

With respect to error-comparator threshold, hysteresis = 1%

-14 -5 %

PGOOD_ Upper Trip Threshold

With respect to error-comparator threshold, hysteresis = 1%

PGOOD_ Output Low Voltage I

SINK

= 4mA 0.3 V

VCC Undervoltage-Lockout Threshold

)

Rising edge, PWM disabled below this level, hysteresis = 20mV

4.1 4.4 V

CURRENT LIMIT

CSP_ 0 2.7

Current-Limit Input Range

CSN_

Valley Current-Limit Threshold (Fixed)

)

CSP

_ - V

CSN

_, ILIM_ = V

40 60 mV

Valley Current-Limit Threshold (Adjustable)

)

CSP

_ - V

CSN

_, V

ILIM

_ = 2.00V

240 mV

INPUTS AND OUTPUTS

Logic Input Threshold

ON1, ON2, SKIP, GATE, rising edge, hysteresis = 225mV

1.2 2.2 V

LDOON Input Trip Level Rising edge, hysteresis = 250mV 1.2 1.3 V

High 1.9 2.1

Dual Mode Threshold Voltage

FB1 (MAX1540), FB2 (MAX1540/MAX1541)

Low

SYMBOL

LDOOUT

FBLDO

= 6V to 28V

LDOIN

MAX1540: V+ - V

LDOOUT

0 < I

, I

LDOOUT

L D OOU T

LDOOUT

L D OOU T

LDOOUT

< 10mA 4.85 5.10

< 100m A 4.65 5.10

< 10mA 1.212 1.275

< 100m A 1.175 1.275

= 50mA

MIN MAX

1.98 2.02

UVLO(VCC

LIM_ (VAL

-0.3 +28.0

160

0.05 0.15

0.05

+14

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

10 ______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

High

Open

REF

Four-Level Input Logic Levels

TON, OVP/UVP, LSAT, SKIP, FBLANK

Low 0.5

Note 1: For the MAX1540, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT),

and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+).

Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-comparator

threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.

Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V,

and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.

Note 4: Specifications to -40°C are guaranteed by design, not production tested.

OUT2 EFFICIENCY vs. LOAD CURRENT

OUT2

= 2.5V)

MAX1540 toc01

LOAD CURRENT (A)

EFFICIENCY (%)

10.1

100

0.01 10

SKIP = GND SKIP = V

VIN = 7V

VIN = 12V

VIN = 20V

2.5V OUTPUT VOLTAGE (OUT2) vs. LOAD CURRENT

MAX1540 toc02

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

4321

2.49

2.50

2.51

2.52

2.53

2.54

2.55

2.48 05

SKIP = GND SKIP = V

OUT1 EFFICIENCY vs. LOAD CURRENT

OUT1

= 1.0V)

MAX1540 toc03

LOAD CURRENT (A)

EFFICIENCY (%)

10.1

100

0.01 10

SKIP = GND SKIP = V

VIN = 7V

VIN = 12V

VIN = 20V

Typical Operating Characteristics

(MAX1541 Circuit of Figure 12, V

= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)

0.4V

3.15 3.85

1.65 2.35

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 11

1.0V OUTPUT VOLTAGE (OUT1) vs. LOAD CURRENT

MAX1540 toc04

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

431 2

0.99

1.00

1.01

1.02

0.98 05

SKIP = GND SKIP = V

OUT2 SWITCHING FREQUENCY

vs. LOAD CURRENT

OUT2

= 2.5V)

MAX1540 toc05

LOAD CURRENT (A)

SWITCHING FREQUENCY (kHz)

4321

100

200

300

400

500

600

SKIP = GND SKIP = V

OUT1 SWITCHING FREQUENCY

vs. LOAD CURRENT

OUT1

= 1.0V)

MAX1540 toc06

LOAD CURRENT (A)

SWITCHING FREQUENCY (kHz)

4321

100

200

300

400

500

600

SKIP = GND

SKIP = V

SWITCHING FREQUENCY

vs. INPUT VOLTAGE

MAX1540 toc07

INPUT VOLTAGE (V)

SWITCHING FREQUENCY (kHz)

2420161284

250

300

350

400

450

200

028

4A LOAD

NO LOAD

2.5V OUTPUT SKIP = V

MAXIMUM OUTPUT CURRENT

vs. INPUT VOLTAGE

MAX1540 toc08

INPUT VOLTAGE (V)

MAXIMUM OUTPUT CURRENT (A)

242012 1684

4.2

4.4

4.6

4.8

5.0

5.2

5.4

5.6

5.8

6.0

4.0 028

2.5V OUTPUT

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

(FORCED-PWM OPERATION)

MAX1540 toc09

INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

2420161284

028

BIAS

SKIP = ON1 = ON2 = V

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

(PULSE-SKIPPING OPERATION)

MAX1540 toc10

INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

2420161284

0.2

0.4

0.6

0.8

1.0

1.2

1.4

028

SKIP = GND ON1 = ON2 = V

BIAS

2.0V REFERENCE LOAD REGULATION

MAX1540 toc11

REFERENCE LOAD CURRENT (µA)

REFERENCE VOLTAGE DEVIATION (mV)

100

-3

-2

-1

-4

-20

REFERENCE DISTRIBUTION

MAX1540 toc12

REFERENCE VOLTAGE (V)

SAMPLE PERCENTAGE (%)

2.0052.0001.995

1.990 2.010

SAMPLE SIZE = 50

Typical Operating Characteristics (continued)

(MAX1541 Circuit of Figure 12, V

= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

12 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(MAX1541 Circuit of Figure 12, V

= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)

LINEAR-REGULATOR OUTPUT (LDOOUT)

vs. LOAD CURRENT

MAX1540 toc13

LDO LOAD CURRENT (mA)

LDO OUTPUT VOLTAGE (V)

806020 40

3.22

3.24

3.26

3.28

3.30

3.32

3.34

3.36

3.20

0 100

LDOIN

= 5V

LDOIN

= 12V

STARTUP WAVEFORM

(HEAVY LOAD)

MAX1540 toc14

3.3V

2.5V

400µs/div

A. ON2, 5V/div B. INDUCTOR CURRENT, 2A/div

0.5Ω LOAD

C. OUT2, 2V/div D. PGOOD2, 5V/div

STARTUP WAVEFORM

(LIGHT LOAD)

MAX1540 toc15

3.3V

2.5V

200µs/div

A. ON2, 5V/div B. INDUCTOR CURRENT, 2A/div

100Ω LOAD

C. OUT2, 2V/div D. PGOOD2, 5V/div

SHUTDOWN WAVEFORM

(DISCHARGE MODE DISABLED)

MAX1540 toc16

3.3V

10ms/div

2.5V

A. ON2, 5V/div B. OUT2, 2V/div C. INDUCTOR CURRENT, 2A/div

100Ω LOAD, OVP/UVP = REF OR GND

D. DL2, 5V/div E. PGOOD2, 5V/div

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 13

Typical Operating Characteristics (continued)

(MAX1541 Circuit of Figure 12, V

= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)

SHUTDOWN WAVEFORM

(DISCHARGE MODE ENABLED)

MAX1540 toc17

3.3V

1ms/div

2.5V

A. ON2, 5V/div B. OUT2, 2V/div C. INDUCTOR CURRENT, 2A/div

100Ω LOAD, OVP/UVP = V

OR OPEN

D. DL2, 5V/div E. PGOOD2, 5V/div

2.5V OUTPUT LOAD TRANSIENT (FORCED PWM)

MAX1540 toc18

40µs/div

2.5V

2.4V

2.6V

A. I

OUT2

= 0 TO 4A, 5A/div

B. V

OUT2

= 2.5V, 100mV/div

SKIP = V

C. INDUCTOR CURRENT, 5A/div D. LX2, 10V/div

12V

2.5V OUTPUT LOAD TRANSIENT (PULSE SKIPPING)

MAX1540 toc19

40µs/div

2.5V

2.4V

2.6V

A. I

OUT2

= 0.1A TO 4A, 5A/div

B. V

OUT2

= 2.5V, 100mV/div

SKIP = GND

C. INDUCTOR CURRENT, 5A/div D. LX2, 10V/div

12V

LINEAR-REGULATOR

LOAD TRANSIENT

MAX1540 toc20

100mA

100µs/div

3.3V

3.2V

3.4V

A. I

LDOOUT

= 1mA TO 100mA, 50mA/div

B. V

LDOOUT

= 3.3V, 100mV/div

SKIP = GND

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

14 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(MAX1541 Circuit of Figure 12, V

= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)

LINEAR-REGULATOR

LINE TRANSIENT

MAX1540 toc21

20V

10V

20V

10V

3.8V

3.3V

2.8V

200µs/div

A. INPUT (V

), 10V/div

B. LDOIN (10V TO 20V), 10V/div

C. LDOOUT (3.3V), 500mV/div

20mA LOAD

OUTPUT OVERLOAD

(UVP DISABLED)

MAX1540 toc22

20A

2.5V

10A

40µs/div

A. LOAD (0 TO 150mΩ), 10A/div B. INDUCTOR CURRENT, 10A/div

OVP/UVP = OPEN OR GND

C. 2.5V OUTPUT, 2V/div D. PGOOD2, 5V/div

OUTPUT OVERLOAD

(UVP ENABLED)

MAX1540 toc23

20A

2.5V

10A

20µs/div

A. LOAD (0 TO 150mΩ), 10A/div B. INDUCTOR CURRENT, 10A/div C. DL2, 5V/div

OVP/UVP = V

OR REF

D. 2.5V OUTPUT, 2V/div E. PGOOD2, 5V/div

INDUCTOR-SATURATION PROTECTION

(LSAT DISABLED)

MAX1540 toc24

2.5V

20µs/div

7.5A

A. I

OUT2

= 0 TO 5A, 5A/div

B. 2.5V OUTPUT, 200mV/div

LSAT = GND, L = 3.3µH 3.5A

C. ILIM, 100mV/div D. INDUCTOR CURRENT, 5A/div

0.67V

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 15

Typical Operating Characteristics (continued)

(MAX1541 Circuit of Figure 12, V

= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)

INDUCTOR-SATURATION PROTECTION

(∆V

ILIM

= 200mV)

MAX1540 toc25

2.5V

20µs/div

7.5A

A. I

OUT2

= 0 TO 5A, 5A/div

B. 2.5V OUTPUT, 200mV/div

LSAT = REF, L = 3.3µH 3.5A

C. ILIM, 200mV/div D. INDUCTOR CURRENT, 5A/div

0.67V

0.47V

INDUCTOR-SATURATION PROTECTION

(∆V

ILIM

= 400mV)

MAX1540 toc26

2.5V

1.5V

20µs/div

A. I

OUT2

= 0 TO 5A, 5A/div B. 2.5V OUTPUT, 1V/div C. PGOOD, 5V/div

LSAT = REF, L = 3.3µH 3.5A

D. ILIM, 400mV/div E. INDUCTOR CURRENT, 5A/div

0.67V

0.27V

MAX1541

DYNAMIC OUTPUT-VOLTAGE TRANSITION

REFIN1

= 100pF)

MAX1540 toc27

-5A

1.5V B

40µs/div

A. GATE, 5V/div B. OUT1 (1.0V TO 1.5V), 0.5V/div C. REFIN1, 0.5V/div

200mA LOAD, SKIP = GND

D. PGOOD1, 5V/div E. INDUCTOR CURRENT, 5A/div

1.5V

MAX1541

DYNAMIC OUTPUT-VOLTAGE TRANSITION

REFIN1

= 1nF)

MAX1540 toc28

-5A

1.5V B

100µs/div

A. GATE, 5V/div B. OUT1 (1.0V TO 1.5V), 0.5V/div C. REFIN1, 0.5V/div

200mA LOAD, SKIP = GND

D. PGOOD1, 5V/div E. INDUCTOR CURRENT, 5A/div

1.5V

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

16 ______________________________________________________________________________________

MAX1540

NAME FUNCTION

1 1 OVP/UVP

Overvoltage/Undervoltage Protection and Discharge-Mode Control Input. This fourlevel logic input selects between various output fault-protection options (Table 7) by selectively enabling OVP protection and UVP protection. When enabled, the OVP limit defaults at 116% of the nominal output voltage, and the UVP limit defaults at 70% of the nominal output voltage. Discharge mode is enabled when OVP protection is also enabled. Connect OVP/UVP to the following pins for the desired function: V

= enable OVP and discharge mode, enable UVP. Open = enable OVP and discharge mode, disable UVP. REF = disable OVP and discharge mode, enable UVP. GND = disable OVP and discharge mode, disable UVP. See the Fault Protection and Shutdown and Output Discharge sections.

22SKIP

Pulse-Skipping Control Input. This four-level logic input enables or disables the lightload pulse-skipping operation of each output: V

= OUT1 and OUT2 in forced-PWM mode. Open = OUT1 in forced-PWM mode, OUT2 in pulse-skipping mode. REF = OUT1 in pulse-skipping mode, OUT2 in forced-PWM mode. GND = OUT1 and OUT2 in pulse-skipping mode.

3 3 LSAT

Inductor-Saturation Control Input. This four-level logic input sets the inductor-current saturation limit as a multiple of the valley current-limit threshold set by ILIM, or disables the function if not required. Connect LSAT to the following pins to set the saturation current limit: VCC = 2 x I

LIM(VAL)

Open = 1.75 x I

LIM(VAL)

REF = 1.5 x I

LIM(VAL)

GND = disable LSAT protection See the Inductor Saturation Limit and Setting the Current Limit sections.

44TON

On-Time Selection Control Input. This four-level logic input sets the K-factor value used to determine the DH_ on-time (see the On-Time One-Shot section). Connect to analog ground (GND), REF, or V

; or leave TON unconnected to select the following nominal switching frequencies: V

= 235kHz (OUT1) / 170kHz (OUT2) Open = 345kHz (OUT1) / 255kHz (OUT2) REF = 485kHz (OUT1) / 355kHz (OUT2) GND = 620kHz (OUT1) / 460kHz (OUT2)

55V

Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 20Ω resistor. Bypass V

to analog ground with a 1µF or greater ceramic

capacitor.

— 6 GATE

Buffered N-Channel MOSFET Gate Input. A logic low on GATE turns off the internal MOSFET so OD appears as high impedance. A logic high on GATE turns on the internal MOSFET, pulling OD to ground.

— 7 CC1

Integrator Capacitor Connection for Controller 1. Connect a 47pF to 470pF (47pF typ) capacitor from CC1 to analog ground (GND) to set the integration time constant for the main MAX1541 controller (OUT1).

Pin Description

MAX1541

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 17

MAX1540

NAME FUNCTION

6 8 ILIM1

Valley Current-Limit Threshold Adjustment for Controller 1. The valley current-limit threshold defaults to 50mV if ILIM1 is tied to V

. In adjustable mode, the valley current-limit threshold across CSP1 and CSN1 is precisely 1/10 the voltage seen at ILIM1 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV default value is approximately V

- 1V. When the inductor-saturation protection

threshold is exceeded, ILIM1 sinks 6µA. See the Current-Limit Protection section.

7 9 ILIM2

Valley Current-Limit Threshold Adjustment for Controller 2. The valley current-limit threshold defaults to 50mV if ILIM2 is tied to V

. In adjustable mode, the valley current-limit threshold across CSP2 and CSN2 is precisely 1/10th the voltage seen at ILIM2 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV default value is approximately V

- 1V. When the inductor-saturation protection

threshold is exceeded, ILIM2 sinks 6µA. See the Current-Limit Protection section.

8 10 REF

2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater ceramic capacitor. The reference can source up to 50µA for external loads. Loading REF degrades output voltage accuracy according to the REF load-regulation error. The reference is disabled when the MAX1540/MAX1541 are shut down.

— 11 REFIN1

External Reference Input for Controller 1. REFIN1 sets the main feedback regulation voltage (V

FB1

= V

REFIN1

) of the MAX1541.

— 12 OD Open-Drain Output. Controlled by GATE.

9 13 CSP2

Positive Current-Sense Input for Controller 2. Connect to the positive terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM2.

10 14 CSN2

Negative Current-Sense Input for Controller 2. Connect to the negative terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM2.

11 15 FB2

Feedback Input for Controller 2: M AX 1540: C onnect to V

C C

for a + 1.5V fi xed outp ut or to anal og g r ound ( G N D ) for a + 2.5V fi xed outp ut. For an ad j ustab l e outp ut ( 0.7V to 5.5V ) , connect FB2 to a r esi sti ve d i vi d er fr om OU T2. The FB2 r eg ul ati on l evel i s + 0.7V .

M AX 1541: C onnect to V

C C

for a + 1.8V fi xed outp ut or to anal og g r ound ( G N D ) for a + 2.5V fi xed outp ut. For an ad j ustab l e outp ut ( 0.7V to 5.5V ) , connect FB2 to a r esi sti ve d i vi d er fr om OU T2. The FB2 r eg ul ati on l evel i s + 0.7V .

12 16 OUT2

Output Voltage-Sense Connection for Controller 2. Connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (Figures 1 and 12). OUT2 senses the output voltage to determine the on-time for the high-side switching MOSFET. OUT2 also serves as the feedback input when using the preset internal output voltages as shown in Figure 10. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10Ω resistor connected between OUT2 and ground.

Pin Description (continued)

MAX1541

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

18 ______________________________________________________________________________________

MAX1540

NAME FUNCTION

13 17 PGOOD2

Open-Drain Power-Good Output. PGOOD2 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. After the soft-start circuit has terminated, PGOOD2 becomes high impedance if the output is in regulation.

14 18 DH2 High-Side Gate-Driver Output for Controller 2. DH2 swings from LX2 to BST2.

15 19 LX2

Inductor Connection for Controller 2. Connect to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver.

16 20 BST2

Boost Flying-Capacitor Connection for Controller 2. Connect to an external capacitor and diode as shown in Figure 8. An optional resistor in series with BST2 allows the DH2 pullup current to be adjusted.

17 21 GND Analog and Power Ground. Connect backside pad to GND.

18 22 DL2

Low-Side Gate-Driver Output for Controller 2. DL2 swings from GND to LDOOUT (MAX1540) or GND to V

(MAX1541).

19 23 V+

Battery Voltage Input. The controller uses V+ to set the on-time one-shot timing. The DH on-time is inversely proportional to input voltage over a range of 2V to 28V. For the MAX1540, V+ also serves as the linear-regulator input supply.

— 24 LDOIN

Internal Linear-Regulator Input Supply. Power LDOIN from a 4.5V to 28V voltage source. Bypass LDOIN to GND with a 4.7µF or greater capacitor. For the MAX1540, LDOIN is internally connected to V+.

—25V

MAX1541 Supply Voltage Input for the DL_ Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass V

to power ground with a 1µF or greater ceramic capacitor. For the MAX1540, LDOOUT supplies the DL_ gate drivers (V

= LDOOUT).

20 26 LDOOUT

Linear Regulator Output. Bypass LDOOUT with a 1µF or greater capacitor per 5mA of load (internal and external), with a minimum of 4.7µF. For the MAX1540, LDOOUT powers the DL_ gate drivers (V

internally connected to LDOOUT).

— 27 FBLDO

Feedback Input for the Linear Regulator. Connect to GND for a fixed 5V output. For an adjustable output (1.25V to V

LDOIN

- 0.6V), connect FBLDO to a resistive voltagedivider from LDOOUT to analog ground (GND). The FBLDO regulation voltage is +1.25V. For the MAX1540, FBLDO is internally connected to GND for a fixed 5V output.

21 28 DL1

Low-Side Gate-Driver Output for Controller 1. DL1 swings from GND to LDOOUT (MAX1540) or GND to V

(MAX1541).

22 29 LDOON

Linear-Regulator Enable Input. For automatic startup, connect to V+ or LDOIN (MAX1541). Connect to GND to shut down the linear regulator.

23 30 BST1

Boost Flying-Capacitor Connection for Controller 1. Connect to an external capacitor and diode as shown in Figure 8. An optional resistor in series with BST1 allows the DH1 pullup current to be adjusted.

Pin Description (continued)

MAX1541

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 19

MAX1540

NAME FUNCTION

24 31 LX1

Inductor Connection for Controller 1. Connect to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver.

25 32 DH1 High-Side Gate-Driver Output for Controller 1. DH1 swings from LX1 to BST1.

26 33 PGOOD1

Open-Drain Power-Good Output. PGOOD1 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the output is in regulation. For the MAX1541, PGOOD1 is blanked—forced high-impedance state—when FBLANK is enabled and the controller detects a transition on GATE.

27 34 OUT1

Output Voltage-Sense Connection for Controller 1. Connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (Figures 1 and 12). OUT1 senses the output voltage to determine the on-time for the high-side switching MOSFET. For the MAX1540, OUT1 also serves as the feedback input when using the preset internal output voltages as shown in Figure 10. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10Ω resistor connected between OUT1 and ground.

28 35 FB1

Feedback Input for Controller 1: M AX 1540: C onnect to V

C C

for a + 1.2V fi xed outp ut or to anal og g r ound ( G N D ) for a + 1.8V fi xed outp ut. For an ad j ustab l e outp ut ( 0.7V to 5.5V ) , connect FB1 to a r esi sti ve d i vi d er fr om OU T1. The FB1 r eg ul ati on l evel i s + 0.7V . M AX 1541: The FB1 r eg ul ati on l evel i s set b y the vol tag e at RE FIN 1.

29 36 CSN1

Negative Current-Sense Input for Controller 1. Connect to the negative terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM1.

30 37 CSP1

Positive Current-Sense Input for Controller 1. Connect to the positive terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM1.

— 38 FBLANK

Fault-Blanking Control Input. This four-level logic input enables or disables fault blanking, and sets the forced-PWM operation time (t

FBLANK

). When fault blanking is enabled, PGOOD1 and the OVP/UVP protection for controller 1 are blanked for the selected time period after the MAX1541 detects a transition on GATE. Additionally, controller 1 enters forced-PWM mode for the duration of t

FBLANK

anytime GATE changes states. Connect FBLANK as follows: V

= 220µs t

FBLANK

, fault blanking enabled.

Open = 140µs t

FBLANK

, fault blanking enabled.

REF = 65µs t

FBLANK

, fault blanking enabled.

GND = 140µs t

FBLANK

, fault blanking disabled.

See the Electrical Characteristics table for the t

FBLANK

limits.

Pin Description (continued)

MAX1541

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

20 ______________________________________________________________________________________

MAX1540

NAME FUNCTION

31 39 ON2

OUT2 Enable Input. Pull ON2 to GND to shut down controller 2 (OUT2). Connect to V

for normal operation. When discharge mode is enabled by OVP/UVP, the output

is discharged through a 10Ω resistor between OUT2 and GND, and DL2 is forced high after V

OUT2

drops below 0.3V. When discharge mode is disabled by OVP/UVP, OUT2 remains a high-impedance input and DL2 is forced low so LX2 also appears as a high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch.

32 40 ON1

OUT1 Enable Input. Pull ON1 to GND to shut down controller 1 (OUT1). Connect to V

for normal operation. When discharge mode is enabled by OVP/UVP, the output

is discharged through a 10Ω resistor between OUT1 and GND, and DL1 is forced high after V

OUT1

drops below 0.3V. When discharge mode is disabled by OVP/UVP, OUT1 remains a high-impedance input and DL1 is forced low so LX1 also appears as high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch.

Pin Description (continued)

Table 1. Component Selection for Standard Applications

MAX1540 MAX1541

COMPONENT

PWM1 PWM2 PWM1 PWM2

Input Voltage (VIN) 7V to 24V 7V to 24V 7V to 24V 7V to 24V

Output Voltage (V

OUT

1.8V 2.5V 1.0V/1.5V 2.5V

Load Current (I

OUT

4A 8A 4A 4A

S w i tchi ng Fr eq uency

( f

S W

TON = REF (485kHz) TON = REF (355kHz) TON = REF (485kHz) TON = REF (355kHz)

Input Capacitor (CIN)

(2) 10µF, 25V

Taiyo Yuden TMK432BJ106KM

(2) 4.7µF, 25V

Taiyo Yuden TMK325BJ475KM

Output Capacitor

OUT

220µF, 6.3V, 12mΩ

Sanyo POSCAP

6TPD220M

330µF, 4V, 12mΩ

Sanyo POSCAP

4TPD330M

470µF, 4V, 10mΩ

Sanyo POSCAP

4TPD470M

220µF, 6.3V, 12mΩ

Sanyo POSCAP

6TPD220M

High-Side MOSFET

35mΩ, 30V

20mΩ, 30V

Fairchild FDS6690

35mΩ, 30V

Fairchild 1/2 FDS6982S

Low-Side MOSFET

22mΩ, 30V

12.5mΩ, 30V

Fairchild FDS6670S

22mΩ, 30V

Fairchild 1/2 FDS6982S

Low-Side Schottky

(if needed)

1A, 30V Schottky

Nihon EP10QS03L

1A, 30V Schottky

Nihon EP10QS03L

1A, 30V Schottky

Nihon EP10QS03L

1A, 30V Schottky

Nihon EP10QS03L

Inductor (L_)

2.5µH, 6.2A, 15mΩ

Sumida

CDEP105(H)-2R5

2.2µH, 10A, 4.4mΩ

Sumida

CDEP105(L)-2R2

1.8µH, 9.0A, 6.2mΩ

Sumida

CDEP105(S)-1R8

4.3µH, 6.8A, 8.7mΩ

Sumida

CDEP105(L)-4R3

SENSE_

15mΩ ±1%, 0.5W

5mΩ ±1%, 0.5W

15mΩ ±1%, 0.5W

IRC LR2010-01-R015F

or Dale WSL-2010-R015F

MAX1541

Fairchild 1/2 FDS6982S

IRC LR2010-01-R015F

or Dale WSL-2010-R015F

IRC LR2010-01-R005F

or Dale WSL-2010-R005F

Fairchild 1/2 FDS6982S

IRC LR2010-01-R015F

or Dale WSL-2010-R015F

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 21

Figure 1. MAX1540 Standard Application Circuit

MAX1540

+5V BIAS

SUPPLY

OUTPUT 1

1.8V, 4A (MAX)

REF

(485kHz/355kHz)

POWER GROUND

ANALOG GROUND

POWER-GOOD

OFF

OPEN (I

LIM(VAL)

x 1.75)

OUTPUT 2

2.5V, 8A (MAX)

INPUT (V

7V TO 20V

LDOOUT

DH1

BST1

LX1

CSP1

DL1

CSN1

OUT1

FB1

SKIP

TON

REF

ILIM1

ILIM2

PGOOD2

PGOOD1

ON2

ON1

LDOON

LSAT

OVP/UVP

FB2

OUT2

CSN2

CSP2

GND

DL2

LX2

BST2

DH2

V+

R7 100kΩ

100kΩ

C2 1µF

20Ω

OUT2

330µF

CS2

5mΩ

2.2µH

CS1

15mΩ

OUT1

220µF

2.5µH

BST2

0.1µF

BST1

0.1µF

BST

22µF

REF

0.22µF

470pF

R2 100kΩ

49.9kΩ

200kΩ

49.9kΩ

SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.

*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.

+5V BIAS SUPPLY

(2) 10µF

MAX1540/MAX1541

Standard Application Circuits

The MAX1540 Standard Application Circuit (Figure 1) generates a 1.8V and 2.5V rail for general-purpose use in a notebook computer. The MAX1541 Standard Application Circuit (Figure 12) generates a dynamically adjustable output voltage (OUT1), typical of a graphicsprocessor core requirement, and a fixed 2.5V output (OUT2).

See Table 1 for component selections. Table 2 lists the component manufacturers.

Detailed Description

The MAX1540/MAX1541 provide three independent outputs with independent enable controls. They contain two Quick-PWM step-down controllers ideal for low-voltage power supplies for notebook computers, and a 100mA linear regulator. Maxim’s proprietary Quick-PWM pulsewidth modulators in the MAX1540/ MAX1541 are specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency currentmode PWMs, while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes.

The MAX1540 linear regulator draws power from the battery voltage and generates a preset 5V, which can be used to bootstrap the buck controllers for automatic startup. The MAX1541’s linear regulator can be connected to any input source from 4.5V to 28V to generate an adjustable output voltage as low as 1.25V, or as high as the input source with 800mV of dropout at 50mA load.

Single-stage buck conversion allows the MAX1540/ MAX1541 to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, twostage conversion (stepping down from another system supply rail instead of the battery at a higher switching frequency) allows the minimum possible physical size.

The MAX1540 generates chipset, dynamic randomaccess memory (DRAM), CPU I/O, or other low-voltage supplies down to 0.7V. The MAX1541 powers chipsets and graphics processor cores that require dynamically adjustable output voltages, or generates the active termination bus that must track the input reference. The MAX1540 is available in a 32-pin thin QFN package with optional inductor-saturation protection and overvoltage/undervoltage protection. The MAX1541 is available in a 40-pin thin QFN package with optional inductor-saturation protection and overvoltage/undervoltage protection.

+5V Bias Supply (VCCand VDD)

The MAX1540/MAX1541 require a 5V bias supply in addition to the battery. This 5V bias supply is either the MAX1540/MAX1541s’ internal linear regulator or the notebook’s 95%-efficient 5V system supply. Keeping the bias supply external to the IC can improve efficiency and allows the fixed 5V or adjustable linear regulator (MAX1541) to be used for other applications. For the MAX1540, the gate-driver input supply (VDD) is connect-

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

22 ______________________________________________________________________________________

Table 2. Component Suppliers

SUPPLIER PHONE WEBSITE

Central

Semiconductor

631-435-1110

(USA)

www.centralsemi.com

Coilcraft

800-322-2645

(USA)

www.coilcraft.com

Fairchild

Semiconductor

888-522-5372

(USA)

www.fairchildsemi.com

International Rectifier

310-322-3331

(USA)

www.irf.com

Kemet

408-986-0424

(USA)

www.kemet.com

Panasonic

65-6231-3226

408-749-9714

(USA)

www.panasonic.com

Sanyo

(USA)

www.sanyovideo.com

Siliconix (Vishay)

203-268-6261

(USA)

www.vishay.com

Sumida

408-982-9660

(USA)

www.sumida.com

Taiyo Yuden

03-3667-3408

(Japan),

408-573-4150

(USA)

www.t-yuden.com

TDK

847-803-6100

(USA),

81-3-5201-7241

(Japan)

www.component.tdk.com

TOKO

858-675-8013

(USA)

www.tokoam.com

(Singapore),

619-661-6835

ed internally to the fixed 5V linear-regulator output (LDOOUT).

The 5V bias supply must provide VCC(PWM controller) and VDD(gate-drive power), so the maximum current drawn is:

BIAS

= ICC+ fSW(Q

G(LOW)

+ Q

G(HIGH)

)

= 4mA to 50mA (typ)

where ICCis 1.1mA (typ), fSWis the switching frequency, and Q

G(LOW)

and Q

G(HIGH)

are the MOSFET data

sheet’s total gate-charge specification limits at VGS= 5V.

The V+ battery input and 5V bias inputs (VCCand VDD) can be connected together if the input source is a fixed

4.5V to 5.5V supply. If the 5V bias supply powers up prior to the battery supply, the enable signals (ON1 and ON2 going from low to high) must be delayed until the battery voltage is present in order to ensure startup.

Free-Running, Constant On-Time, PWM

Controller with Input Feed Forward

The Quick-PWM control architecture is a pseudofixedfrequency, constant on-time, current-mode regulator with voltage feed forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The Quick-PWM algorithm is simple: the high-side switch on-time relies solely on an adjustable one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a fixed minimum off-time (400ns typ). The controller triggers the on-time one-shot when the error comparator is low, the inductor current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out.

On-Time One-Shot (TON)

The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to the battery and output voltages. The highside switch on-time is inversely proportional to the battery voltage as measured by the V+ input (V

= V+), and proportional to the output voltage as measured by the OUT_ input:

where K (switching period) is set by the TON pin-strap connection (Table 3). This algorithm results in a nearly constant switching frequency despite the lack of a fixedfrequency clock generator. The benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band and 2) the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-time for the main controller (DH1) is set 15% higher than the nominal frequency setting (200kHz, 300kHz, 420kHz, or 540kHz), while the on-time for the secondary controller (DH2) is set 15% lower than the nominal setting. This prevents audio-frequency “beating” between the two asynchronous regulators.

The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics (approximately ±12.5% at 540kHz and 420kHz nominal settings, and ±10% with the 300kHz and 200kHz settings). On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wider range.

The constant on-time translates only roughly to a constant switching frequency. The on-times guaranteed in the Electrical Characteristics are influenced by resistive losses and by switching delays in the high-side MOSFET. Resistive losses—including the inductor, both MOSFETs, and PC board copper losses in the output and ground— tend to raise the switching frequency as the load increases. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times add to the effective on-time. It occurs only in PWM mode (SKIP = V

) and during dynamic output-voltage transitions when the inductor current reverses at light- or negative-load currents. With reversed inductor current, the inductor’s EMF causes LX_ to go high earlier than normal, extending the on-time by a period equal to the driver dead time.

For loads above the critical conduction point, where the dead-time effect no longer occurs, the actual switching frequency is:

where V

DROP1

is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; V

DROP2

the sum of the resistances in the charging path, includ-

OUT_ DROP1

ON IN DROP1 DROP2

V+V

tV+V -V

()

On- Time

OUT

⎛ ⎝

⎜

⎞ ⎠

⎟

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 23

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

24 ______________________________________________________________________________________

Figure 2. MAX1540/MAX1541 Functional Diagram

VALLEY

CURRENT

LIMIT

ZERO

CROSSING

SATURATION

LIMIT

VALLEY CURRENT LIMIT

ZERO CROSSING

SATURATION LIMIT

*V+

TON

SKIP

ILIM1

CSP1

CSN1

BST1

DH1

LX1

DL1

**CC1

GND

LSAT

ILIM2

CSP2

CSN2

BST2

DH2

LX2

DL2

GND

REF

13R

0.7V 7R

CURRENT

LIMIT 1

(FIGURE 5)

CURRENT

LIMIT 2

(FIGURE 5)

PWM

CONTROLLER 1

(FIGURE 3)

PWM

CONTROLLER 2

(FIGURE 3)

FB1 DECODE

(FIGURE 10)

POWER-GOOD AND

FAULT PROTECTION 1

(FIGURE 9)

FB2 DECODE

(FIGURE 10)

INTERNAL

MAX1540/MAX1541

OPTION

POWER-GOOD AND

FAULT PROTECTION 2

(FIGURE 9)

FB1

**REFIN1

OUT1

ON1

PGOOD1

FB2

OUT2

2.0V REF

ON2

PGOOD2

FAULT1

INT REF1

INT FB1

INT FB2

FAULT2

QUAD-LEVEL

DECODE

QUAD-LEVEL

DECODE AND

TIMER

**FBLANK

**OD

OVP/UVP

BLANK

ENABLE OVP ENABLE UVP

LINEAR REGULATOR

(FIGURE 13)

*LDOIN

*LDOOUT

**FBLDO

LDOON

**GATE

MAX1541

CONTROLLER 1

ONLY

MAX1540/MAX1541

INT REF2

*FOR THE MAX1540: LDOIN IS CONNECTED TO V+. LDOOUT IS CONNECTED TO V

**MAX1541 CONTROLLER ONLY.

ing the high-side switch, inductor, and PC board resistances; and tONis the on-time calculated by the MAX1540/MAX1541.

Light-Load Operation (

SSKKIIPP

)

The four-level SKIP input selects light-load, pulse-skipping operation by independently enabling or disabling the zero-crossing comparator for each controller (Table

4). When the zero-crossing comparator is enabled, the controller forces DL_ low when the current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. When the zero-crossing comparator is disabled, the controller maintains PWM operation under light-load conditions (see the Forced- PWM Mode section).

Automatic Pulse-Skipping Mode

In skip mode, an inherent automatic switchover to PFM takes place at light loads (Figure 3). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator differentially senses the inductor current across the current-sense inputs (CSP_ to CSN_). Once V

CSP_

- V

CSN_

drops below 5% of the current-limit threshold (2.5mV for the default 50mV current-limit threshold), the comparator forces DL_ low (Figure 3). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between con-

tinuous and discontinuous inductor-current operation (also known as the “critical-conduction” point). The load-current level at which PFM/PWM crossover occurs, I

LOAD(SKIP)

, is equal to half the peak-to-peak ripple current, which is a function of the inductor value (Figure 4). This threshold is relatively constant, with only a minor dependence on battery voltage:

where K is the on-time scale factor (Table 3). For example, in the MAX1541 Standard Application Circuit (Figure 12) (K = 3.0µs, V

OUT2

= 2.5V, VIN= 12V, and L

= 4.3µH), the pulse-skipping switchover occurs at:

The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).

DC-output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX1540/MAX1541 regulate the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction

2.5V 3 s 2 4.3 H

12V -2.5V

12V

⎛ ⎝

⎜

⎞ ⎠

⎟

⎛ ⎝

⎜

⎞ ⎠

⎟

=0069

LOAD(SKIP)

OUT IN OUT

VK2LV-V

≈

⎛ ⎝

⎜

⎞ ⎠

⎟

⎛ ⎝

⎜

⎞ ⎠

⎟

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 25

Table 3. Approximate K-Factor Errors

CONTROLLER 1 (OUT1) CONTROLLER 2 (OUT2)

NOMINAL TON SETTING (kHz)

K-FACTOR

TYPICAL

K-FACTOR

(µs)

OUT1

= 1.8V*

(V)

TYPICAL

K-FACTOR

(µs)

MINIMUM V

OUT2

= 2.5V*

(V)

200kHz (TON = VCC) ±10 4.5 (235kHz) 2.28 6.2 (170kHz) 2.96

300kHz (TON = open)

±10 3.0 (345kHz) 2.52 4.1 (255kHz) 3.18

420kHz (TON = REF) ±12.5 2.2 (485kHz) 2.91 3.0 (355kHz) 3.48

540kHz (TON = GND)

±12.5 1.7 (620kHz) 3.42 2.3 (460kHz) 3.87

*See the Step-Down Converter Dropout Performance section (h = 1.5 and worst-case K-factor value used).

Table 4. SKIP Configuration Table

SKIP OUT1 MODE OUT2 MODE

Forced PWM Forced PWM

Open Forced PWM Pulse skipping

REF Pulse skipping Forced PWM

GND Pulse skipping Pulse skipping

ERROR (%)

MINIMUM VIN AT

MAX1540/MAX1541

OUT

< I

LOAD(SKIP)

), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation.

Forced-PWM Mode

The low-noise forced-PWM mode disables the zerocrossing comparator, which controls the low-side switch on-time. This forces the low-side gate-drive waveform to be constantly the complement of the highside gate-drive waveform, so the inductor current

reverses at light loads while DH_ maintains a duty factor of V

OUT_

/ VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 4mA to 40mA, depending on the external MOSFETs and switching frequency.

Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response, and providing sink-current capability for dynamic output-voltage adjustment. The MAX1541 uses forcedPWM operation during all dynamic output-voltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. Since forced-PWM operation disables the zero-crossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. FBLANK determines how long the MAX1541 maintains forced-PWM operation—typically 220µs (FBLANK = VCC), 140µs (FBLANK = open or GND), or 65µs (FBLANK = REF).

Current-Limit Protection (ILIM_)

Valley Current Limit

The current-limit circuit employs a unique “valley” current-sensing algorithm that uses a current-sense resistor between CSP_ and CSN_ as the current-sensing ele-

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

26 ______________________________________________________________________________________

Figure 3. MAX1540/MAX1541 PWM-Controller Functional Diagram

VALLEY CURRENT

LIMIT

ON-TIME

COMPUTE

V+

TON

ERROR AMP

SATURATION

LIMIT

Q DH DRIVER

1-SHOT

TRIG

OFF(MIN)

1-SHOT

TRIG

OUT_

ZERO CROSSING

FAULT PROTECTION

DL DRIVER

INT REF_

INT FB_

SLOPE COMP

CC1

*MAIN MAX1541

CONTROLLER (OUT1) ONLY

CC1

= 80

A V

Figure 4. Pulse-Skipping/Discontinuous Crossover Point

INDUCTOR CURRENT

LOAD

= I

PEAK

ON-TIME0 TIME

PEAK

- V

OUT

∆I ∆t

ment (Figure 1). If the magnitude of the current-sense signal is above the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle (Figures 3 and 5). The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. Figure 6 shows the valley current-limit threshold point.

In forced-PWM mode, the MAX1540/MAX1541 also implement a negative current limit to prevent excessive reverse inductor currents when V

OUT

is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when ILIM is adjusted.

The current-limit threshold is adjusted with an external resistor-divider at ILIM_. A 2µA to 20µA divider current is recommended for accuracy and noise immunity. The current-limit threshold adjustment range is from 25mV to 200mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM_. The threshold defaults to 50mV when ILIM_ is

connected to VCC. The logic threshold for switchover to the 50mV default value is approximately VCC- 1V.

Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSP_ and CSN_. Place the IC close to the sense resistor with short, direct traces, making a Kelvin-sense connection to the current-sense resistor.

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 27

Figure 5. MAX1540/MAX1541 Current-Limit Functional Diagram

QUAD-LEVEL

DECODE

SATURATION

LIMIT

VALLEY CURRENT

LIMIT

ZERO

CROSSING

DH DRIVER

0.5V

CSP_

SKIP

CSN_

ILIM_

6µA

- 1.0V

LSAT

Figure 6. Valley Current-Limit Threshold Point

INDUCTOR CURRENT

LIMIT

LOAD

0 TIME

PEAK

LIM(VAL)

= I

LOAD(MAX)

LIR

()

MAX1540/MAX1541

Inductor-Saturation Limit

The LSAT connection selects an upper current-sense limit as the inductor-saturation threshold, or disables the inductor-saturation protection feature altogether (LSAT = GND). When enabled, the inductor-saturation threshold is a multiple of the positive valley current-limit threshold (Table 5) and tracks the valley current limit when ILIM is adjusted. The selected inductor-saturation threshold should give sufficient headroom above the peak inductor current so switching noise does not accidentally trip the saturation protection. Selecting an excessively high threshold may allow inductor saturation to go undetected. For an inductor with a low LIR (the ratio of the inductor ripple current to the designed maximum load current) near 20%, select the lowest saturation threshold of 1.5 x I

LIM(VAL)

(LSAT = REF). When using an inductor with a higher LIR, increase the inductor-saturation threshold accordingly.

When inductor-saturation protection is enabled, the MAX1540/MAX1541 continuously monitor the inductor current through the voltage across the current-sense resistor. When the inductor-saturation threshold is exceeded, the MAX1540/MAX1541 immediately turn off the high-side gate driver and enable a 6µA discharge current on ILIM_ (Figure 7) at the beginning of the next DH_ on-time. This reduces the voltage on ILIM_ by ∆V

ILIM

where:

where the ILIM saturation fault sink current (I

ILIM(LSAT)

) is typically 6µA (see the Electrical Characteristics table). When using the default 50mV valley current-limit threshold (ILIM_ = VCC), the ILIM_ saturation fault sink current does not lower the current-limit threshold (Figure 5).

If the inductor current remains below the saturation threshold during the next cycle, the controller disables the ILIM_ discharge current, allowing the ILIM_ voltage to return to its nominal set point. The inductor should not remain in saturation once the controller reduces the valley current limit. If the inductor remains saturated, the output voltage may drop low enough to trip the undervoltage fault protection (UVP enabled), causing the MAX1540/MAX1541 to set the fault latch and shut down both outputs. Adding a capacitor from ILIM_ to GND slows the ILIM_ voltage change by the time constant τ = (R

//RB) x C

ILIM

, where τ is between 5 to 10

switching periods. If the inductor saturation occurs only during a short load transient, the time constant allows the power supply to recover before the output voltage drops below the output undervoltage threshold.

Set ∆V

ILIM

to be at least 30% of the ILIM_ set voltage.

Calculate RAand RBusing the equations below:

Inductor-saturation sensing works best when using a current-sense resistor in series with the inductor. See the Setting the Current Limit section for various current-sense configurations (Figure 14) and LSAT recommendations.

R with set at

REF

ILIM(LSAT)

ILIM

ILIM(SET)

ILIM

ILIM(SET)

REF

ILIM(SET)

⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

∆∆

301%

∆VI

ILIM

ILIM(LSAT)

R+R

⎛ ⎝

⎜

⎞ ⎠

⎟

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

28 ______________________________________________________________________________________

MAX1540 MAX1541

REF

ILIM

6µA

REF

TO VALLEY

CURRENT-LIMIT

COMPARATOR

(FIGURE 2)

FROM LSAT

COMPARATOR

AND LOGIC

(FIGURE 2)

ILIM

Figure 7. Adjustable Current-Limit Threshold

Table 5. LSAT Configuration Table

LSAT INDUCTOR-SATURATION THRESHOLD

2.00 x I

LIM(VAL)

Open 1.75 x I

LIM(VAL)

REF 1.50 x I

LIM(VAL)

GND Disabled

MOSFET Gate Drivers (DH_, DL_)

The DH_ and DL_ drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications where a large VIN- V

OUT

differential exists. An adaptive dead-time circuit monitors the DL_ output and prevents the high-side MOSFET from turning on until DL_ is off. A similar adaptive deadtime circuit monitors the DH_ output, preventing the lowside MOSFET from turning on until DH_ is off. There must be a low-resistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX1540/MAX1541 interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver).

The internal pulldown transistor that drives DL_ low is robust, with a 0.6Ω (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX_) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require additional gateto-source capacitance to ensure fast-rising LX_ edges do not pull up the low-side MOSFETs gate, causing shoot-through currents. The capacitive coupling between LX_ and DL_ created by the MOSFET’s gate-todrain capacitance (C

RSS

), gate-to-source capacitance

ISS-CRSS

), and additional board parasitics should not

exceed the following minimum threshold:

Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Alternatively, adding a resistor less than 10Ω in series with BST_ can remedy the problem by increasing the turn-on time of the high-side MOSFET without degrading the turn-off time (Figure 8).

POR, UVLO, and Soft-Start

Power-on reset (POR) occurs when VCCrises above approximately 2V, resetting the fault latch and soft-start counter, powering-up the reference, and preparing the PWM for operation. Until VCCreaches 4.25V (typ), V

undervoltage lockout (UVLO) circuitry inhibits switching. The controller inhibits switching by pulling DH_ low, and holding DL_ low when OVP and shutdown discharge are disabled or forcing DL_ high when OVP and shutdown discharge are enabled (Table 7). When VCCrises above

4.25V and ON_ is driven high, the controller activates the PWM controller and initializes soft-start.

Soft-start allows a gradual increase of the internal currentlimit level during startup to reduce the input surge currents. The MAX1540/MAX1541 divide the soft-start period into five phases. During the first phase, the controller limits the current limit to only 20% of the full current limit. If the output does not reach regulation within 425µs, softstart enters the second phase, and the current limit is increased by another 20%. This process is repeated until the maximum current limit is reached after 1.7ms or when the output reaches the nominal regulation voltage, whichever occurs first (see the soft-start waveforms in the Typical Operating Characteristics).

Power-Good Output (PGOOD_)

PGOOD_ is the open-drain output for a window comparator that continuously monitors the output. PGOOD_ is actively held low in shutdown and during soft-start. After the digital soft-start terminates, PGOOD_ becomes high impedance as long as the respective output voltage is within ±10% of the nominal regulation voltage set by FB_. When the output voltage drops 10% below or rises 10% above the nominal regulation voltage, the MAX1540/MAX1541 pull the respective power-good output (PGOOD_) low by turning on the MOSFET (Figure

9). Any fault condition forces both PGOOD1 and PGOOD2 low until the fault latch is cleared by toggling

GS(TH) IN

RSS

ISS

⎛ ⎝

⎜

⎞ ⎠

⎟

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________________________ 29

Figure 8. Optional Gate-Driver Circuitry

MAX1540 MAX1541

BST

BYP

INPUT (VIN)

PGND

BST

)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (C

)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE

COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.

MAX1540/MAX1541

ON1 or ON2, or cycling VCCpower below 1V. For logiclevel output voltages, connect an external pullup resistor between PGOOD_ and V

. A 100kΩ resistor works

well in most applications.

Note that the power-good window detectors are completely independent of the overvoltage and undervoltage-protection fault detectors.

Fault Blanking (MAX1541 FBLANK)

The main MAX1541 controller (OUT1) automatically enters forced-PWM operation during all dynamic outputvoltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. FBLANK determines how long the main MAX1541 controller maintains forcedPWM operation (Table 6—typically 220µs (FBLANK = VCC), 140µs (FBLANK = open or GND), or 65µs (FBLANK = REF).

When fault blanking is enabled (FBLANK = VCC, open, or REF), the MAX1541 also disables the overvoltage and undervoltage fault protection for OUT1, and forces PGOOD1 to a high-impedance state during the transition period selected by FBLANK (Table 6). This prevents fault protection from latching off the MAX1541 and the PGOOD1 signal from going low when the output voltage change (∆V

OUT1

) cannot occur as fast as

the REFIN1 voltage change (∆V

REFIN1

Shutdown and Output Discharge (ON_)

When the output discharge mode is enabled (OVP/UVP connected to VCCor left open), and either ON_ is pulled low or an OVP fault or thermal fault sets the fault latch (Table 7), the controller discharges each output through an internal 10Ω switch connected between OUT_ and ground. While the output discharges, DL_ is forced low and the PWM controller is disabled. Once the output voltage drops below 0.3V, the low-side driver pulls DL_ high, effectively clamping the output and LX_ switching node to ground. The reference remains active until both output voltages are below 0.3V to provide an accurate 0.3V discharge threshold.

When OVP/UVP is connected to REF or GND, the controller does not actively discharge either output, and the DL_ driver remains low until the system reenables the controller. Under these conditions, the output discharge rate is determined by the load current and output capacitance.

The controller detects and latches the discharge-mode state set by OVP/UVP on startup.

Fault Protection

The MAX1540/MAX1541 provide over/undervoltage fault protection (Figure 9). Drive OVP/UVP to enable and disable fault protection as shown in Table 7. Once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions.

Overvoltage Protection (OVP)

When the output voltage rises above 116% of the nominal regulation voltage and OVP is enabled (OVP/UVP = V

or open), the OVP circuit sets the fault latch, shuts down both the Quick-PWM controllers, immediately pulls DH1 and DH2 low, and forces DL1 and DL2 high. This turns on the synchronous-rectifier MOSFETs with 100% duty, rapidly discharging the output capacitors and clamping both outputs to ground. Note that immediately latching DL_ high can cause the output voltages to go slightly negative due to energy stored in the output LC at the instant the OV fault occurs. If the load

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

30 ______________________________________________________________________________________

Figure 9. Power-Good and Fault Protection

20ms

TIMER

FAULT LATCH

POR

0.9 x

INT REF_

1.1 x

INT REF_

0.7 x

INT REF_

1.16 x

INT REF_

INT FB_

ENABLE OVP

ENABLE UVP

*BLANK

FAULT

POWERGOOD

*MAIN MAX1541 CONTROLLER (OUT1) ONLY

POWER-GOOD FAULT PROTECTION

Table 6. FBLANK Configuration Table

FBLANK

OUT1 FAULT

BLANKING

FORCED-PWM

DURATION (MIN/TYP)

(µs)

Enabled 120/220

Open Enabled 80/140

REF Enabled 35/65

GND Disabled 80/140

cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reversepolarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the input fuse blows. The MAX1541 ignores OVP faults on OUT1 when it detects a transition on GATE (FBLANK enabled). Toggle ON1 or ON2, or cycle V

power below 1V to clear the fault latch and restart the controller.

OVP is disabled when OVP/UVP is connected to REF or GND (Table 7).

Undervoltage Protection (UVP)

When the output voltage drops below 70% of the nominal regulation voltage and UVP is enabled (OVP/UVP = V

or REF), the controller sets the fault latch and activates the output discharge sequence (see the Shutdown and Output Discharge section) of both outputs. When the output voltage drops to 0.3V, the driver pulls DL high so the synchronous rectifier turns on, clamping the output to GND. UVP is ignored for at least 10ms (min) after startup (ON_ rising edge), and when transitions are detected on GATE (MAX1541 only, FBLANK enabled). Toggle ON1 or ON2, or cycle V

power below 1V to clear the fault latch and restart the controller.

UVP is disabled when OVP/UVP is left open or connected to GND (Table 7).

Thermal Fault Protection

The MAX1540/MAX1541 feature a thermal fault-protection circuit. When the linear regulator is disabled

(LDOON = GND), the controller sets the thermal limit at +160°C. When the linear regulator is enabled (LDOON = VCC), the controller sets the thermal limit at +150°C to protect the internal linear regulator from continuous short-circuit conditions. Once the junction temperature exceeds the thermal limit, the thermal-protection circuit activates the fault latch, pulls PGOOD1 and PGOOD2 low, disables the linear regulator, and activates the output discharge sequence of both outputs regardless of the OVP/UVP setting. Toggle ON1 or ON2, or cycle V

power below 1V to reactivate the controller after the junction temperature cools by 10°C.

Output Voltage

Preset Output Voltages

The MAX1540/MAX1541s’ Dual Mode operation allows the selection of common voltages without requiring external components (Figure 10). For the main controller (OUT1) of the MAX1540, connect FB1 to GND for a fixed 1.8V output, to VCCfor a fixed 1.2V output, or connect FB1 directly to OUT1 for a fixed 0.7V output. For the secondary controller (OUT2) of the MAX1540, connect FB2 to GND for a fixed 2.5V output, to VCCfor a fixed 1.5V output, or connect FB2 directly to OUT2 for a fixed 0.7V output. The main controller (OUT1) of the MAX1541 regulates to the voltage set at REFIN1 (V

FB1

= V

REFIN1

) and does not support Dual Mode operation. For the secondary controller (OUT2) of the MAX1541, connect FB2 to GND for a fixed 2.5V output, to VCCfor a fixed 1.8V output, or connect FB2 directly to OUT2 for a fixed 0.7V output. Table 8 shows the output voltage configuration.

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 31

Table 7. Fault Protection and Shutdown Setting Truth Table

OVP/UVP

ON_ DISCHARGE* UVP PROTECTION OVP PROTECTION THERMAL PROTECTION

Yes. Output discharged through a 10Ω resistor, and DL forced high when output drops below 0.3V.

Yes. UVP fault activates

Yes. DH pulled low and DL forced high immediately.

Yes. Thermal fault activates the discharge sequence.

Open

Yes. Output discharged through a 10Ω resistor, and DL forced high when output drops below 0.3V.

No. UVP disabled.

Yes. DH pulled low and DL forced high immediately.

Yes. Thermal fault activates the discharge sequence.

REF

No. DL forced low when shut down.

Yes. UVP fault activates

No. OVP disabled.

Yes. Thermal fault activates the discharge sequence.

GND

No. DL forced low when shut down.

No. UVP disabled. No. OVP disabled.

Yes. Thermal fault activates the discharge sequence.

*Discharge-mode state latched on power-up.

the discharge sequence.

MAX1540/MAX1541

Setting V

OUT

with a Resistive Voltage-Divider at FB_

The output voltage can be adjusted from 0.7V to 5.5V using a resistive voltage-divider (Figure 11). The MAX1540 regulates FB1 and FB2 to a fixed 0.7V reference voltage. The MAX1541 regulates FB1 to the voltage set at REFIN1 and regulates FB2 to a fixed 0.7V reference voltage. This makes the main MAX1541 controller (OUT1) ideal for memory applications where the termination supply must track the supply voltage. The adjusted output voltage is:

where V

FB_

= 0.7V for the MAX1540, and V

FB1

REFIN1

and V

FB2

= 0.7V for the MAX1541.

Dynamic Output Voltages (MAX1541 OUT1 Only)

The MAX1541 regulates FB1 to the voltage set at REFIN1. By changing the voltage at REFIN1, the MAX1541 can be used in applications that require dynamic output-voltage changes between two set points. Figure 12 shows a dynamically adjustable resistive voltage-divider network at REFIN1. Using the GATE signal and open-drain output (OD), a resistor can be switched in and out of the REFIN1 resistor-divider, changing the voltage at REFIN1. A logic high on GATE turns on the internal N-channel MOSFET, forcing OD to a low-impedance state. A logic low on GATE disables the N-channel MOSFET, so OD is high impedance. The two output voltages (FB1 = OUT1) are determined by the following equations:

The main MAX1541 controller (OUT1) automatically enters forced-PWM operation on the rising and falling edges of GATE, and remains in forced-PWM mode for a minimum time selected by FBLANK (Table 6). ForcedPWM operation is required to ensure fast, accurate negative voltage transitions when REFIN1 is lowered. Since forced-PWM operation disables the zero-crossing comparator, the inductor current may reverse under

OUT1(LOW) REF

OUT1(HIGH) REF

R8+ R9

(R9+ R10)

R8+ (R9+R10)

⎛ ⎝

⎜

⎞ ⎠

⎟

⎡ ⎣

⎢

⎤ ⎦

⎥

OUT_ FB_

R R

⎛ ⎝

⎜

⎞ ⎠

⎟

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

32 ______________________________________________________________________________________

Figure 10. MAX1540/MAX1541 Dual Mode Feedback Decoder

MAX1540 MAX1541

TO ERROR

AMPLIFIER

FB_

REF

(2.0V)

FIXED OUTPUT FB = GND

FIXED OUTPUT FB = V

OUT_

Table 8. Output Voltage Configuration

OUT1 OUT2

MAX1541

FB_ = V

Fixed

1.2V

Not

Fixed

1.5V

Fixed

1.8V

FB_ = GND

Fixed

1.8V

Not

Fixed

2.5V

Fixed

2.5V

FB_ = OUT_

or adjustable

0.7V

0.7V 0.7V

MAX1540 MAX1541 MAX1540

allowed

REFIN1

light loads, quickly discharging the output capacitors. If fault blanking is enabled, the MAX1541 also disables the main controller’s (OUT1) overvoltage and undervoltage fault protection, and forces PGOOD1 to a highimpedance state for the period selected by FBLANK (Table 6).

For a step-voltage change at REFIN1, the rate of change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. The inductor current ramp is limited by the voltage across the inductor and the inductance. The total output capacitance determines how much current is needed to change the output voltage. Additional load current slows down the output-voltage change during a positive REFIN1 voltage change, and speeds up the output-voltage change during a negative REFIN1 voltage change. For fast positive output-voltage transitions, the current limit must be greater than the load current plus the transition current:

Adding a capacitor across REFIN1 and GND filters noise and controls the rate of change of the REFIN1

voltage during dynamic transitions. With the additional capacitance, the REFIN1 voltage slews between the two set points with a time constant given by REQx C

REFIN1

, where REQis the equivalent parallel resistance seen by the slew capacitor. Looking at Figure 12, the time constant for a positive REFIN1 voltage transition is:

and the time constant for a negative REFIN1 voltage transition is:

Linear Regulator (LDO)

The maximum input voltage for the linear regulator is 28V, while the minimum input voltage is determined by the 800mV (max) dropout voltage (V

LDOIN(MIN)

LDOOUT

+ V

DROPOUT

) at 50mA load. Bypass the linear regulator’s output (LDOOUT) with a 4.7µF or greater capacitor, providing at least 1µF per 5mA of internal and external load on the linear regulator. The LDO can source up to 100mA for powering the controller or supplying a small external load.

For the MAX1540, the linear regulator provides the 5V bias supply that powers the gate drivers and analog controller (Figure 1), providing stand-alone capability. The linear regulator’s input is internally connected to the battery voltage input (LDOIN = V+), and the gatedriver input supply is internally connected to the linear regulator’s output (V

= LDOOUT). Figure 13 is the

internal linear-regulator functional diagram.

For the MAX1541, the linear regulator supports Dual Mode operation to allow the selection of a 5V output voltage without requiring external components (Figure

1). Connect FBLDO to GND for a fixed 5.0V output. The linear regulator’s output voltage can be adjusted from

1.25V to 5.5V using a resistive voltage-divider (Figure

12). The MAX1541 regulates FBLDO to a 1.25V feedback voltage. The adjusted output voltage is:

where V

FBLDO

= 1.25V. If unused, disable the MAX1541

linear regulator by connecting LDOON to GND.

R R

LDOOUT FBLDO

⎛ ⎝

⎜

⎞ ⎠

⎟

NEG REFIN1

R8 R9 R8+ R9

⎛ ⎝

⎜

⎞ ⎠

⎟

POS = REFIN1

R8 (R9+R10) R8+ (R9+R10)

⎡ ⎣

⎢

⎤ ⎦

⎥

IIC

OAD OUT

LIMIT L

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 33

Figure 11. Setting V

OUT

with a Resistive Voltage-Divider at FB_

MAX1540 MAX1541

DL_

GND

LX_

FB_

CSN_

CSP_

OUT

SENSE

OUT_

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

34 ______________________________________________________________________________________

Figure 12. MAX1541 Standard Application Circuit

MAX1541

+5V BIAS

SUPPLY

OUTPUT 1

OUT(HIGH)

= 1.5V

OUT(LOW)

= 1.0V

POWER GROUND

ANALOG GROUND

POWER-GOOD

OFF

OPEN (I

LIM(VAL)

x 1.75)

OUTPUT 2 V

OUT2

= 2.5V

INPUT (V

7V TO 20V

DH1

BST1

LX1

CSP1

DL1

CSN1

OUT1

FB1

CC1

SKIP

REF

ILIM1

ILIM2

PGOOD2

LDOIN

PGOOD1

ON2

ON1

LDOON

LSAT

REF (485kHz/355kHz)TON

OVP/UVP

FB2

OUT2

CSN2

CSP2

GND

DL2

LX2

BST2

DH2

V+

R7 100kΩ

100kΩ

C2 1µF

4.7µF

20Ω

OUT2

220µF

CS2

15mΩ

4.3µH

CS1

15mΩ

1.8µH

BST

0.1µF

BST1

0.1µF

BST

1µF

REF

0.22µF

OUT1

470µF

ILIM1

470pF

ILIM2

470pF

R2 100kΩ

49.9kΩ

100kΩ

49.9kΩ

SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.

*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.

CC1

47pF

OUT(LOW)

OUT(HIGH)

GATE

FBLANK

REFIN1

OPEN

(ENABLED, 140µs)

REF

75kΩ

R10

150kΩ

75kΩ

REFIN

470pF

R12 20kΩ

+5V BIAS SUPPLY

(2) 4.7µF

OUT(LOW)

= V

REF

OUT(HIGH)

= V

REF

R8 + R9

()

(R9 + R10)

R8 + (R9 + R10)

[]

LDOOUT

FBLDO

+5V BIAS SUPPLY

R13 10Ω

R11

32.4kΩ

C4 22µF

LDO OUTPUT V

LDOOUT

= 3.3V

()

Design Procedure

Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:

• Input voltage range: The maximum value (V

IN(MAX)

) must accommodate the worst-case, high AC-adapter voltage. The minimum value (V

IN(MIN)

) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency.

• Maximum load current: There are two values to consider. The peak load current (I

LOAD(MAX)

) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (I

LOAD

) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components.

• Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and V

IN2

. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical.

• Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs.

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 35

Figure 13. Internal Linear-Regulator Functional Diagram

VL REG

AND REF

GATE DRIVER

AND ERROR

AMP

LDOOUT

*MAX1541 ONLY.

*FBDLO

LDOON

*LDOIN

V+

0.2V

FIXED 5V

INTERNAL FBLDO

OPTION BETWEEN

THE MAX1540/MAX1541

INTERNAL LDOIN OPTION BETWEEN THE MAX1540/MAX1541

INTERNAL V

OPTION BETWEEN THE MAX1540/MAX1541

MAX1540/MAX1541

Inductor Selection

The switching frequency and inductor operating point determine the inductor value as follows:

For example: I

LOAD(MAX)

= 4A, VIN= 12V, V

OUT2

2.5V, fSW= 355kHz, 30% ripple current or LIR = 0.3:

Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I

PEAK

Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values.

Transient Response

The inductor ripple current also impacts transientresponse performance, especially at low VIN- V

OUT

differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time:

where t

OFF(MIN)

is the minimum off-time (see the

Electrical Characteristics) and K is from Table 3.

The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as:

Setting the Current Limit

The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at I

LOAD(MAX)

minus

half the ripple current; therefore:

where I

LIM(VAL)

equals the minimum valley current-limit threshold voltage divided by the current-sense resistance (R

SENSE

). For the 50mV default setting, the mini-

mum valley current-limit threshold is 40mV.

Connect ILIM_ to VCCfor a default 50mV valley currentlimit threshold. In adjustable mode, the valley currentlimit threshold is precisely 1/10th the voltage seen at ILIM_. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM_ connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10µA to prevent significant inaccuracy in the valley current-limit tolerance.

The current-sense method (Figure 14) and magnitude determine the achievable current-limit accuracy and power loss (Table 9). Typically, higher current-sense voltage limits provide tighter accuracy, but also dissipate more power. Most applications employ a valley current-sense voltage (V

LIM(VAL)

) of 50mV to 100mV,

so the sense resistor may be determined by:

SENSE

= V

LIM(VAL)

/ I

LIM(VAL)

For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 14a. This configuration constantly monitors the inductor current, allowing accurate valley current-limiting and inductor-saturation protection.

For low-output-voltage applications that require higher efficiency, the current-sense resistor can be connected between the source of the low-side MOSFET (NL_) and power ground (Figure 14b) with CSN_ connected to the drain of N

and CSP_ connected to power ground. In this configuration, the additional current-sense resistance only dissipates power when NL_is conducting current. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on.

VV V

VfL

OUT IN MIN OUT

IN MIN SW

LIM(VAL) LOAD(MAX)

⎛

⎝

⎜

⎞

⎠

⎟

()

SOAR

LOAD(MAX)

OUT OUT

≈

()

∆

V-V K

-t

SAG

LOAD(MAX)

OUT

OFF(MIN)

OUT OUT

IN OUT

OFF(MIN)

⎛ ⎝

⎜

⎞ ⎠

⎟

⎡

⎣

⎢ ⎢

⎤

⎦

⎥ ⎥

()

⎛

⎝

⎜

⎞

⎠

⎟

⎡

⎣

⎢ ⎢

⎤

⎦

⎥ ⎥

(∆I

CV2

LIR

PEAK LOAD(MAX)

⎛ ⎝

⎜

⎞ ⎠

⎟

kHz x A

××

2.5V (12V - 2.5V)

12V 3 4 0

4.65 H

55 3

VVV

V f x I LIR

()

××

OUT IN OUT

IN SW LOAD(MAX)

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

36 ______________________________________________________________________________________

For high-power applications that do not require highaccuracy current sensing or inductor-saturation protection, the MAX1540/MAX1541 can use the low-side MOSFET’s on-resistance as the current-sense element (R

SENSE

= R

DS(ON)

) by connecting CSN_ to the drain of NL_and CSP_ to the source of NL_(Figure 14c). Use the worst-case maximum value for R

DS(ON)

from the MOSFET data sheet, and add some margin for the rise in R

DS(ON)

with temperature. A good general rule is to

allow 0.5% additional resistance for each °C of temperature rise. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on.

Alternatively, high-power applications that require inductor saturation can constantly detect the inductor current by connecting a series RC circuit across the inductor (Figure 14d) with an equivalent time constant:

where RLis the inductor’s series DC resistance. In this configuration, the current-sense resistance is equivalent to the inductor’s DC resistance (R

SENSE

= RL). Use the worst-case inductance and RLvalues provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load.

In all cases, ensure an acceptable valley current-limit threshold voltage and inductor-saturation configurations despite inaccuracies in sense-resistance values.

Output Capacitor Selection

The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements.

For processor-core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:

In applications without large and fast load transients, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. Therefore, the maximum ESR required to meet ripple specifications is:

The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics).

When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V

SAG

and V

SOAR

from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the V

SAG

and V

SOAR

equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that may affect the overall stability (see the Output- Capacitor Stability Considerations section).

I LIR

ESR

RIPPLE

LOAD(MAX)

≤

×∆

ESR

STEP

LOAD(MAX)

≤

∆

=C R

EQ EQ

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 37

Table 9. Current-Sense Configurations

METHOD

CURRENT-SENSE

ACCURACY

INDUCTOR-SATURATION

PROTECTION

CURRENT-SENSE POWER LOSS

(EFFICIENCY)

a) Output current-sense resistor High

Allowed

(highest accuracy)

SENSE

x I

OUT

b) Low-side current-sense resistor High

Not allowed

(LSAT = GND)

c) Low-side MOSFET on-resistance Low

Not allowed

(LSAT = GND)

No additional loss

d) Equivalent inductor DC resistance Low Allowed No additional loss

⎛

OUT

⎜

⎝

⎞

××

SENSE OUT

⎟ ⎠

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

38 ______________________________________________________________________________________

Figure 14. Current-Sense Configurations

MAX1540 MAX1541

OUT

INDUCTOR

LSAT

d) LOSSLESS INDUCTOR SENSING

CSN

CSP

GND

DISABLE

LSAT

BIAS

= R

MAX1540 MAX1541

OUT

LSAT

c) LOW-SIDE MOSFET SENSING

CSP

GND

CSN

DISABLE

LSAT

MAX1540 MAX1541

OUT

SENSE

LSAT

b) LOW-SIDE SERIES RESISTOR SENSING

CSP

GND

CSN

CONNECT TO

PREFERRED

LSAT SETTING

MAX1540 MAX1541

OUT

LSAT

a) OUTPUT SERIES RESISTOR SENSING

GND

CONNECT TO

PREFERRED

LSAT SETTING

CSN

CSP

SENSE

Output-Capacitor Stability Considerations

For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:

For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mV

P-P

ripple is 25mV/1.2A = 20.8mΩ. One 220µF/4V Sanyo polymer (TPE) capacitor provides 15mΩ (max) ESR. This results in a zero at 48kHz, well within the bounds of stability.

Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor.

Unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits.

The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to monitor simultaneously the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.

Input-Capacitor Selection

The input capacitor must meet the ripple current requirement (I

RMS

) imposed by the switching currents:

For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX1540/MAX1541 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10°C temperature rise at the RMS input current for optimal reliability and lifetime.

Power MOSFET Selection

Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.

The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V

IN(MIN)

and V

IN(MAX)

. Ideally, the losses at V

IN(MIN)

should be roughly equal to the losses at V

IN(MAX)

, with

lower losses in between. If the losses at V

IN(MIN)

are

significantly higher, consider increasing the size of NH.

Conversely, if the losses at V

IN(MAX)

are significantly higher, consider reducing the size of NH. If VINdoes not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses.

Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (R

DS(ON)

), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1540/MAX1541 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology.

RMS

−+

−

() ( )

IVVV

OUT OUT IN OUT

where

2R C

ESR

ESR OUT

≤

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 39

MAX1540/MAX1541

Power-MOSFET Dissipation

Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage:

Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the R

DS(ON)

required to stay within package power-dissipation limits often restricts how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (R

DS(ON)

) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V.

Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:

where C

RSS

is the reverse transfer capacitance of NH,

and I

GATE

is the peak gate-drive source/sink current

(1A typ).

Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied due to the squared term in the switchingloss equation (C ✕V

fSW). If the high-side MOS-

FET chosen for adequate R

DS(ON)

at low-battery voltages becomes extraordinarily hot when subjected to V

IN(MAX)

, consider choosing another MOSFET with

lower parasitic capacitance.

For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage:

The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than I

LOAD(MAX)

but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate:

where I

VALLEY(MAX)

is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation.

Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical.

Applications Information

Step-Down Converter Dropout

Performance

The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the V

SAG

equation in the Design Procedure

section).

The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆I

DOWN

)

as much as it ramps up during the on-time (∆IUP). The ratio h = ∆IUP/∆I

DOWN

indicates the controller’s ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and V

SAG

greatly increases

unless additional output capacitance is used.

VV V

Vf L

OUT IN OUT

IN SW

LOAD VALLEY(MAX)

−

⎛ ⎝

⎜

⎞ ⎠

⎟

( )

PD (N Resistance) -

(I ) R

OUT

IN(MAX)

LOAD DS(ON)

⎛

⎝

⎜

⎞

⎠

⎟

⎡

⎣

⎢ ⎢

⎤

⎦

⎥ ⎥

×1

PD (N Switching)

IN(MAX) RSS SW LOAD

GATE

()

××VCfI

PD (N Resistance)

(I ) R

OUT

LOAD DS(ON)

⎛ ⎝

⎜

⎞ ⎠

⎟

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

40 ______________________________________________________________________________________

A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between V

SAG

, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as:

where V

DROP1

is the parasitic voltage drop in the charge path (see the On-Time One-Shot section), t

OFF(MIN)

is from the Electrical Characteristics, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1.

If the calculated V

IN(MIN)

is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable V

SAG

. If operation near dropout is anticipat-

ed, calculate V

SAG

to be sure of adequate transient

response.

Dropout Design Example

•V

OUT2

= 2.5V

•fSW= 355kHz

• K = 3.0µs, worst-case K

MIN

= 3.3µs

•t

OFF(MIN)

= 500ns

•V

DROP1

= 100mV

• h = 1.5

Calculating again with h = 1 and the typical K-factor value (K = 3.3µs) gives the absolute limit of dropout:

Therefore, VINmust be greater than 3.06V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V.

Multi-Output Voltage Settings

(MAX1541 OUT1 Only)

While the main MAX1541 controller (OUT1) is optimized to work with applications that require two dynamic out-

put voltages, it can produce three or more output voltages if required by using discrete logic or a DAC.

Figure 15 shows an application circuit providing four voltage levels using discrete logic. Switching resistors in and out of the resistor network changes the voltage at REFIN1. An edge-detection circuit is added to generate a 1µs pulse on GATE to trigger the fault blanking and forced-PWM operation. When using PWM mode (SKIP = V

or open) on the main controller, the edgedetection circuit is only required if fault blanking is enabled. Otherwise, leave OD unconnected.

Active Bus Termination

(MAX1541 OUT1 Only)

Active-bus-termination power supplies generate a voltage rail that tracks a set reference. They are required to source and sink current. DDR memory architecture requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the memory supply voltage. Configure the main MAX1541 controller (OUT1) to generate the termination voltage using a resistive voltage-divider at REFIN1. In such an application, the main MAX1541 controller (OUT1) must be kept in PWM mode (SKIP = VCCor open) in order for it to source and sink current. Figure 16 shows the main MAX1541 controller configured as a DDR termination regulator. Connect GATE and FBLANK to GND when unused.

IN(MIN)

⎛ ⎝

⎜

⎞ ⎠

⎟

25 01

1 500

306

IN(MIN)

⎛ ⎝

⎜

⎞ ⎠

⎟

25 01

1 5 500

347

IN(MIN)

OUT DROP1

OFF(MIN)

⎛ ⎝

⎜

⎞ ⎠

⎟

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 41

Figure 15. Multi-Output Voltage Settings

MAX1541

REF

REFIN1

GND

GATE

1000pF

1.5kΩ

1000pF

1.5kΩ

MAX1540/MAX1541

Voltage Positioning

In applications where fast load transients occur, the output voltage changes instantly by ESR

COUT

x ∆I

LOAD

. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the output voltage AC and DC tolerance window in tight-tolerance applications.

Figure 17 shows the connection of OUT_ and FB_ in voltage-positioned and nonvoltage-positioned circuits. In nonvoltage-positioned circuits, the MAX1540/ MAX1541 regulate at the output capacitor. In voltagepositioned circuits, the MAX1540/MAX1541 regulate on the inductor side of the current-sense resistor. V

OUT_

reduced to:

OUT(VPS)

= V

OUT(NO LOAD)

- R

SENSE

x I

LOAD

Figure 18 shows the voltage-positioning transient response.

PC Board Layout Guidelines

Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 19). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout:

• Keep the high-current paths short, especially at the

ground terminals. This practice is essential for stable, jitter-free operation.

• Keep the power traces and load connections short.

This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing

PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty.

• Minimize current-sensing errors by connecting CSP_ and CSN_ directly across the current-sense resistor (R

SENSE_

• When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.

• Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSP_, CSN_).

Layout Procedure

1) Place the power components first, with ground terminals adjacent (N

L _

source, CIN, C

OUT

_, and DL_ anode). If possible, make all these connections on the top layer with wide, copper-filled areas.

2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ in order to keep LX_, GND, DH_, and the DL_ gate-drive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing.

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

42 ______________________________________________________________________________________

Figure 16. Active Bus Termination

MAX1541

OUT

SKIP

REFIN1

GATE

10kΩ

FBLANK

DDQ

= DDR MEMORY SUPPLY VOLTAGE

= TERMINATION SUPPLY VOLTAGE

GND

DL1

10nF

DH1

LX1

CSN1

CSP1

SENSE

FB1

OUT1

DDQ

VTT =

DDQ

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 43

Figure 17. Voltage Positioning

MAX1540 MAX1541

VOLTAGE-POSITIONED OUTPUT (V

OUT(VPS)

)

OUT

INPUT (VIN)

+5V BIAS SUPPLY

BST

SENSE

OUT(VPS)

= V

OUT(NO LOAD)

- R

SENSEIOUT

CSN_

OUT_

CSP_

GND

DL_

DH_

BST_

V+

LX_

Figure 18. Voltage-Positioning Transient Response

50mV/div

1.4

A. CONVENTIONAL CONVERTER B. VOLTAGE-POSITIONED OUTPUT

VOLTAGE POSITIONING THE OUTPUT

OUT

ESR VOLTAGE STEP

STEP

x R

ESR

)

CAPACITIVE SOAR

(dV/dt = I

OUT/COUT

)

RECOVERY

CAPACITIVE SAG

(dV/dt = I

OUT/COUT

)

LOAD

MAX1540/MAX1541

3) Group the gate-drive components (BST_ diode and capacitor, VDDbypass capacitor) together near the controller IC.

4) Make the DC-DC controller ground connections as shown in Figures 1 and 12. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC.

5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical.

Chip Information

TRANSISTOR COUNT: 8612

PROCESS: BiCMOS

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

44 ______________________________________________________________________________________

Figure 19. PC Board Layout

INDUCTOR

OUT

OUTPUT

INPUT

GROUND

INPUT

OUTPUT

OUT

GROUND

INDUCTOR

HIGH-POWER LAYOUT LOW-POWER LAYOUT

MAX1540

BOTTOM LAYER

MAX1540

TOP LAYER

DUAL N-CHANNEL MOSFET

KELVIN-SENSE VIAS

UNDER THE SENSE RESISTOR

(REFER TO EVALUATION KIT)

SINGLE

N-CHANNEL

MOSFETS

VIA TO V

VIA TO REF PIN

VIA TO REF BYPASS CAPACITOR

VIA TO V

BYPASS CAPACITOR

VIA TO POWER GROUND

CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN

CONNECT THE

EXPOSED PAD TO

ANALOG GROUND

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 45

TOP VIEW

THIN QFN

40393837363534

ON1

ON2

FBLANK

CSP1

CSN1

FB1

OUT1

33 PGOOD1

11121314151617

REFIN1

CSP2

CSN2

FB2

OUT2

PGOOD2

V+

LDOIN

LDOOUT

FBLDO

DL1

LDOON

ILIM1

CC1

GATE

TON

LSAT

SKIP

MAX1541

1OVP/UVP

30 BST1

32 DH1

31 LX1

DH2

LX2

20BST2

2122GND

DL2

REF

ILIM2

Pin Configurations (continued)

QFN THIN.EPS

(ND-1) X e

PIN # 1 I.D.

(NE-1) X e

E/2

0.08 C

0.10 C

DETAIL A

E2/2

0.10 M C A B

PIN # 1 I.D.

0.35x45∞

D/2

D2/2

e e

DETAIL B

XXXXX

MARKING

21-0140

PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm

-DRAWING NOT TO SCALE-

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

46 ______________________________________________________________________________________

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

______________________________________________________________________________________ 47

COMMON DIMENSIONS

3.353.15

T2855-1 3.25 3.353.15 3.25

MAX.

3.20

EXPOSED PAD VARIATIONS

3.00T2055-2 3.10

NOM.MIN.

3.203.00 3.10

MIN.E2NOM. MAX.

PKG. CODES

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6.

NOTES:

SYMBOL

PKG.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

JEDEC

T1655-1

3.203.00 3.10 3.00 3.10 3.20

0.70 0.800.75

4.90

0.25

0.250--

WHHB

0.350.30

5.10

5.105.00

0.80 BSC.

5.00

0.05

0.20 REF.

0.02

MIN. MAX.NOM.

16L 5x5

3.10

T3255-2

3.00

3.20

3.00 3.10 3.20

2.70

T2855-2 2.60 2.602.80 2.70 2.80

0.30 0.500.40

---

WHHC

5.00

0.30

0.55

0.65 BSC.

0.45

0.25

4.90

0.25

0.65

5.10

0.35

20L 5x5

0.20 REF.

0.75

0.02

NOM.

0.70

MIN.

0.05

0.80

MAX.

---

WHHD-1

5.00

0.25

0.55

0.50 BSC.

0.45

0.25

4.90

0.20

0.65

5.10

0.30

28L 5x5

0.20 REF.

0.75

0.02

NOM.

0.70

MIN.

0.05

0.80

MAX.

---

WHHD-2

5.00

0.40

0.50 BSC.

0.30

0.25

4.90

0.50

5.10

32L 5x5

0.20 REF.

0.75

0.02

NOM.

0.70

MIN.

0.05

0.80

MAX.

0.20 0.25 0.30

DOWN BONDS

ALLOWED

YES3.103.00 3.203.103.00 3.20T2055-3

3.103.00 3.203.103.00 3.20T2055-4

T2855-3 3.15 3.25 3.35 3.15 3.25 3.35

T2855-6 3.15 3.25 3.35 3.15 3.25 3.35

T2855-4 2.60 2.70 2.80 2.60 2.70 2.80

T2855-5 2.60 2.70 2.80 2.60 2.70 2.80

T2855-7 2.60 2.70

2.80

2.60 2.70 2.80

3.203.00 3.10T3255-3 3.203.00 3.10

3.203.00 3.10T3255-4 3.203.00 3.10

NO NO

YES YES

YES

3.203.00T1655-2 3.10 3.00 3.10 3.20 YES NO3.203.103.003.10T1655N-1 3.00 3.20

3.353.15T2055-5 3.25 3.15 3.25 3.35

3.35

3.15T2855N-1 3.25 3.15 3.25 3.35

3.35

3.15T2855-8 3.25 3.15 3.25 3.35

3.203.10T3255N-1 3.00

3.203.103.00

0.40

** ** **

** ** ** **

** **

** ** **

SEE COMMON DIMENSIONS TABLE

±0.15

11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

21-0140

PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm

-DRAWING NOT TO SCALE-

12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator

48 ______________________________________________________________________________________

QFN THIN 6x6x0.8.EPS

e e

A1 A2

E/2

D/2

E2/2

(NE-1) X e

(ND-1) X e

D2/2

21-0141

PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

MAX1540/MAX1541

Dual Step-Down Controllers with Saturation

Protection, Dynamic Output, and Linear Regulator

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

3. N IS THE TOTAL NUMBER OF TERMINALS.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

NOTES:

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

21-0141

PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

Maxim Integrated MAX1540, MAX1541 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual