Maxim Integrated DS5001FP User Manual
A
www.maxim-ic.com
DS5001FP
128k Soft Microprocessor Chip
FEATURES
§ 8051-compatible microprocessor adapts to its
task
– Accesses up to 128kB of nonvolatile
SRAM
– In-system programming through on-chip
serial port
– Can modify its own program or data
memory
– Accesses memory on a separate byte-wide
bus
– Performs CRC-16 check of NV RAM
memory
– Decodes memory and peripheral chip
enables
§ High-reliability operation
– Maintains all nonvolatile resources for
over 10 years
– Power-fail reset
– Early warning power-fail interrupt
– Watchdog timer
– Lithium backs user SRAM for
program/data storage
– Precision bandgap reference for power
monitor
§ Fully 8051-compatible
– 128kB scratchpad RAM
– Two timer/counters
– On-chip serial port
– 32 parallel I/O port pins
§ Software security available with DS5002FP
secure microprocessor
PIN ASSIGNMENT (Top View)
BA2
PROG
BD7
RST
LE
BD6
BA1
P3.0/RXD
PSEN
BD5
BA0
P3.1/TXD
P2.7/A15
BD4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P3.2/INT0
P3.3/INT1
P0.4AD4
CE2
PE2
BA9
P0.3/AD3
BA8
P0.2/AD2
BA13
P0.1/AD1
R/W
P0.0/AD0
VCC0
VCC
MSEL
P1.0
BA14
P1.1
BA12
P1.2
BA7
P1.3
PE3
PE4
BA6
BA11
P0.5/AD5
PE1
P0.6/AD6
BA10
P0.7/AD7
CE1NCCE1N
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1.4
BA5
P1.5
BA4
DS5001FP
BA3
P1.6
P1.7
80-Pin MQFP
P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
BA15
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0
44-Pin MQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, click here: http://www.maxim-ic.com/errata.
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DS5001FP
DESCRIPTION
The DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAM
technology and designed for systems that need large quantities of nonvolatile memory. It provides full
compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM
instead of ROM, the user can program and then reprogram the microprocessor while in-system. The
application software can even change its own operation, which allows frequent software upgrades,
adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5001FP is ideal for
data logging applications. It also connects easily to a Dallas real-time clock.
The DS5001FP provides the benefits of NV RAM without using I/O resources. It uses a nonmultiplexed
byte-wide address and data bus for memory access. This bus performs all memory access and provides
decoded chip enables for SRAM, which leaves the 32 I/O port pins free for application use. The
DS5001FP uses ordinary SRAM and battery-backs the memory contents for over 10 years at room
temperature with a small external battery. A DS5001FP also provides high-reliability operation in harsh
environments. These features include the ability to save the operating state, power-fail reset, power-fail
interrupt, and watchdog timer.
A user programs the DS5001FP through its on-chip serial bootstrap loader. The bootstrap loader
supervises the loading of software into NV RAM, validates it, and then becomes transparent to the user.
Software can be stored in multiple 32kB or one 128kB CMOS SRAM(s). Using its internal partitioning,
the DS5001FP can divide a common RAM into user-selectable program and data segments. This partition
can be selected at program loading time, but can then be modified later at any time. The microprocessor
decodes memory access to the SRAM and addresses memory through its byte-wide bus. Memory portions
designated code or ROM are automatically write-protected by the microprocessor. Combining program
and data storage in one device saves board space and cost.
The DS5001FP offers several bank switches for access to even more memory. In addition to the primary
data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip
enables. This area can be used for memory-mapped peripherals or more data storage. The DS5001FP can
also use its expanded bus on ports 0 and 2 (like an 8051) to access an additional 64kB of data space.
Lastly, the DS5001FP provides one additional bank switch that changes up to 60kB of the NV RAM
program space into data memory. Thus, with a small amount of logic, the DS5001 accesses up to 252kB
of data memory.
The DS2251T is available (Refer to the data sheet at www.maxim-ic.com/microcontrollers.) for users
who want a preconstructed module using the DS5001FP, RAM, lithium cell, and a real-time clock. For
more details, refer to the Secure Microcontroller User’s Guide. For users desiring software security, the
DS5002FP is functionally identical to the DS5001FP but provides superior firmware security. The 44-pin
version of the device is functionally identical to the 80-pin version but sports a reduced pin count and
footprint.
Refer to the Secure Microcontroller User’s Guide for operating details. This data sheet provides ordering
information, pinout, and electrical specifications.
ORDERING INFORMATION
PART PIN-PACKAGE MAX. CLOCK SPEED (MHz) TEMP. RANGE (°C)
DS5001FP-16 80-MQFP 16 0 to +70
DS5001FP-16N 80-MQFP 16 -40 to +85
DS5001FP-12-44 44-MQFP 12 0 to +70
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Figure 1. BLOCK DIAGRAM
DS5001FP
3 of 26
PIN DESCRIPTION
DS5001FP
80-PIN
MQFP
11, 9, 7,
5, 1, 79,
77, 75
44-PIN
MQFP
31
(P0.5)
15, 17,
19, 21,
25, 27,
44
(P1.3)
29, 31
49, 50,
51, 56,
58, 60,
N/A
64, 66
36 8
38 10
39 N/A
40 11
41 N/A
44 12
45 13
46 N/A
68 25
34 6
70 27
47, 48 14, 15
52 16
SIGNAL DESCRIPTION
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires
P0.0–P0.7
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in
this mode, it does not require pullups.
P1.0–P1.7 General-Purpose I/O Port 1
P2.0–P2.7
P3.0 RXD
P3.1 TXD
P3.2
INT0
INT1
P3.3
P3.4 T0
P3.5 T1
P3.6
P3.7
General-Purpose I/O Port 2. Also serves as the MSB of the address in expanded memory
accesses, and as pins of the RPC mode when used.
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on board
UART. This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on board
UART. This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0.
General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1.
General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.
General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.
General-Purpose I/O Port Pin. Also serves as the write strobe for expanded bus
WR
operation.
General-Purpose I/O Port Pin. Also serves as the read strobe for expanded bus operation.
RD
Program Store Enable. This active-low signal is used to enable an external program
memory when using the expanded bus. It is normally an output and should be unconnected
PSEN
if not used.
down externally. This should only be done once the DS5001FP is already in a reset state.
PSEN also is used to invoke the bootstrap loader. At this time, PSEN is pulled
The device that pulls down should be open drain since it must not interfere with
under normal operation.
Active-High Reset Input. A logic 1 applied to this pin will activate a reset state. This pin
RST
is pulled down internally so this pin can be left unconnected if not used. An RC power-on
reset circuit is not needed and is not recommended.
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus
ALE
on port 0. This pin is normally connected to the clock input on a ’373 type transparent
latch.
XTAL2,
XTAL1
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
GND Logic Ground
PSEN
13 39
12 38
54 17
53, 16,
8, 18,
80, 76,
4, 6, 20,
24, 26,
28, 30,
41, 36,
42, 32,
30, 34,
35, 43,
1, 2, 3,
4, 5, 7,
VCC V
VCCO
VLI
BA14–0
- +5V
CC
V
- VCC Output. This is switched between VCC and VLI by internal circuits based on the
CCO
level of V
lithium cell remains isolated from a load. When V
V
source. V
LI
Lithium Voltage Input. Connect to a lithium cell greater than V
V
LImax
. When power is above the lithium input, power will be drawn from VCC. The
CC
should be connected to the VCC pin of an SRAM.
CCO
is below VLI, the V
CC
LIMIN
CCO
and no greater than
as shown in the electrical specifications. Nominal value is +3V.
switches to the
Byte-Wide Address-Bus Bits 14–0. This bus is combined with the nonmultiplexed data
bus (BD7–0) to access NV SRAM. Decoding is performed using
CE1 through CE4 .
Therefore, BA15 is not actually needed. Read/write access is controlled by R/ W . BA14–0
connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are
unconnected. If a 128k SRAM is used, the micro converts
CE2 and CE3 to serve as A16
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33, 35,
9 and A15 respectively.
37
71, 69,
67, 65,
61, 59,
57, 55
28, 26,
24, 23,
21, 20,
19, 18
10 37
74 29
72 N/A
233
63 22
62 N/A
78 N/A
3N/A
22 N/A
23 N/A
32 N/A
42 N/A
43 N/A
14 40
73
Byte-Wide Data-Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
BD7–0
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on
CE1 and CE2 . Read/write access is controlled by R/ W . BD7–0 connect directly to an
SRAM, and optionally to a real-time clock or other peripheral.
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It
R/
W
is controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.
Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-
CE1
wide bus. It connects to the chip enable input of one SRAM.
remains in a logic high inactive state when V
CE1N
Non-battery-backed version of chip enable 1. This can be used with a 32kB EPROM. It
should not be used with a battery-backed chip.
Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It
CE2
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts
into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic high when
falls below VLI.
V
CC
Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It
CE3
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts
into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at a logic high when
falls below VLI.
V
CC
Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It
CE4
connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused.
CE4 is lithium-backed and remains at a logic high when V
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when
the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock
PE1
such as the DS1283.
below V
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when
PE2
the PES bit is set to a logic 1.
falls below VLI. Connect PE2 to battery-backed functions only.
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when
PE3
the PES bit is set to a logic 1.
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
PE4
the PES bit is set to a logic 1.
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
Invokes the bootstrap loader on a falling edge. This signal should be debounced so that
PROG
only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.
This I/O pin (open drain with internal pullup) indicates that the power supply (VCC)
has fallen below the V
VRST
DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when V
low externally. This allows multiple parts to synchronize their power-down resets.
This output goes to a logic 0 to indicate that VCC < VLI and the micro has switched to
PF
lithium backup. Because the micro is lithium-backed, this signal is guaranteed even when
V
= 0V. The normal application of this signal is to control lithium powered current to
CC
isolate battery-backed functions from non-battery-backed functions.
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
MSEL
DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to
use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
NC No Connect.
falls below VLI.
CC
PE1 is lithium-backed and remains at a logic high when V
. Connect PE1 to battery-backed functions only.
LI
PE2 is lithium-backed and remains at a logic high when V
PE3 is not lithium-backed and can be connected to any type
CC
PE4 is not lithium-backed and can be connected to any type
CC
level and the micro is in a reset state. When this occurs, the
CCmin
= 0V. Because it is an I/O pin, it also forces a reset if pulled
CC
CE1 is lithium-backed. It
< VLI.
CC
< VLI.
< VLI.
DS5001FP
CE2
CE3
falls
CC
CC
5 of 26
DS5001FP
INSTRUCTION SET
The DS5001FP executes an instruction set that is object code-compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction
set and operation are provided in the Secure Microcontroller User’s Guide. Also note that the DS5001FP
is embodied in the DS2251T module. The DS2251T combines the DS5001FP with between 32k and 128k
of SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of
data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The
user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program
range and data range. Any area not mapped into the NV RAM is reached by the expanded bus on ports 0
and 2. An alternate configuration allows dynamic partitioning of a 64k space as shown in Figure 3.
Selecting PES=1 provides another 64k of potential data storage or memory-mapped peripheral space as
shown in Figure 4. These selections are made using special function registers. The memory map and its
controls are covered in detail in the Secure Microcontroller User’s Guide.
Figure 2. MEMORY MAP IN NONPARTITIONABLE MODE (PM = 1)
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Figure 3. MEMORY MAP IN PARTITIONABLE MODE (PM = 0)
DS5001FP
Note: Partitionable mode is not supported when MSEL pin = 0 (128kB mode).
7 of 26
Figure 4. MEMORY MAP WITH PES = 1
DS5001FP
8 of 26
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