Maxim Integrated DS5000-32-16, DS5000T-32-16, DS5000, DS5000T User Manual

A

A

www.maxim-ic.com

DS5000(T)

Soft Microcontroller Module

FEATURES

 8-Bit 8051-Compatible Microcontroller

Adapts to Task at Hand

8 or 32 kbytes of Nonvolatile RAM for

Program and/or Data Memory Storage

Initial Downloading of Software in End

System via On-Chip Serial Port

Capable of Modifying Its Own Program

and/or Data Memory in End Use

 Crashproof Operation

Maintains All Nonvolatile Resources for 10

Years in the Absence of VCC at Room

Temperature
Power-Fail Reset
Early Warning Power-Fail Interrupt
Watchdog Timer

 Software Security Feature

Executes Encrypted Software to Prevent

Unauthorized Disclosure

 On-Chip, Full-Duplex Serial I/O Ports
 Two On-Chip Timer/Event Counters
 32 Parallel I/O Lines
 Compatible with Industry Standard 8051

Instruction Set and Pinout

 Optional Permanently Powered Real-Time

Clock (DS5000T)

PIN ASSIGNMENT

40-Pin Encapsulated Package

1P1.0
2P1.1

DS5000(T)

3P1.2
4P1.3
5P1.4
6P1.5
7P1.6
8P1.7
9RST
10RXD P3.0
11TXD P3.1
12INT0 P3.2
13INT1 P3.3
14T0 P3.4
15T1 P3.5
16WR P3.6
17RD P3.7
18XTAL2
19XTAL1
20GND

40

31

V

CC

P0.0 AD039
P0.1 AD138
P0.2 AD237
P0.3 AD336
P0.4 AD435
P0.5 AD534
P0.6 AD633
P0.7 AD732
E

LE30
PSEN29
P2.7 A1528
P2.6 A1427
P2.5 A1326
P2.4 A1225
P2.3 A1124
P2.2 A1023
P2.1 A922
P2.0 A821

DESCRIPTION

The DS5000(T) Soft Microcontroller Module is a fully 8051-compatible 8-bit CMOS microcontroller that
offers “softness” in all aspects of its application. This is accomplished through the comprehensive use of
nonvolatile technology to preserve all information in the absence of system V

. The internal

CC

program/data memory space is implemented using either 8 or 32 kbytes of nonvolatile CMOS SRAM.
Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional real­time clock (RTC) gives permanently powered timekeeping. The clock keeps time to a hundredth of a
second using an on-board crystal.

Note: This data sheet provides ordering information, pinout, and electrical specifications. Refer to the

Secure Microcontroller User’s Guide

for operating information.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

1 of 19 REV: 070706

.

DS5000(T)

ORDERING INFORMATION

PART RAM SIZE (kB)

DS5000-32-16 32 16 No

DS5000-32-16+ 32 16 No

DS5000T-32-16 32 16 Yes

DS5000T-32-16+ 32 16 Yes

+ Denotes a lead-free package.

DS5000(T) BLOCK DIAGRAM Figure 1

MAX CRYSTAL

SPEED (MHz)

TIMEKEEPING?

2 of 19

PIN DESCRIPTION

PIN NAME FUNCTION

1–8 P1.0–P1.7 General-Purpose I/O Port 1

DS5000(T)

9 RST

10 P3.0/RXD

11 P3.1/TXD

Active-High Reset Input. A logic 1 applied to this pin will activate a reset state.
This pin is pulled down internally so this pin can be left unconnected if not used.

General-Purpose I/O Port Pin 3.0/Receive Signal for On-Board UART. This pin
should not be connected directly to a PC COM port.

General-Purpose I/O Port Pin 3.1/Transmit Signal for On-Board UART. This pin
should not be connected directly to a PC COM port.

12 P3.2/INT0 General-Purpose I/O Port Pin 3.2/Active-Low External Interrupt 0
13 P3.3/INT1 General-Purpose I/O Port Pin 3.3/Active-Low External Interrupt 1

14 P3.4/T0 General-Purpose I/O Port Pin 3.4/Timer 0 Input

15 P3.5/T1 General-Purpose I/O Port Pin 3.5/Timer 1 Input

16 P3.6/WR

17 P3.7/RD

18, 19

XTAL2,

XTAL1

General-Purpose I/O Port Pin 3.6/Active-Low Write Strobe for Expanded Bus
Operation

General-Purpose I/O Port Pin 3.7/Active-Low Read Strobe for Expanded Bus
Operation

Crystal Connection. Used to connect an external crystal to the internal oscillator.
XTAL1 is the input to an inverting amplifier and XTAL2 is the output.

20 GND Logic Ground

21–28

P2.0–P2.7/

A8–A15

General-Purpose I/O Port 2/MSB of the Expanded Address Bus

Active-Low Program Store Enable. Used to enable an external program memory
when using the expanded bus. It is normally an output and should be unconnected

29

PSEN

if not used. PSEN also is used to invoke the bootstrap loader. At this time, PSEN is
pulled down externally. This should only be done once the DS5000(T) is already in
a reset state. The device that pulls down should be open drain since it must not
interfere with PSEN under normal operation.

Address Latch Enable. Used to demultiplex the multiplexed expanded address/data

30 ALE

bus on Port 0. This pin is normally connected to the clock input on a ’373 type
transparent latch. When using a parallel programmer, this pin also assumes the
PROG function for programming pulses.

Active-Low External Access. This pin forces the DS5000(T) to behave like an

8031. No internal memory (or clock) is available when this pin is at a logic low.

31

EA

Since this pin is pulled down internally, it should be connected to +5V to use NV
RAM. In a parallel programmer, this pin also serves as V
pulses.

General-Purpose I/O Port 0/Multiplexed Expanded Address/Data Bus. This port is
open drain and cannot drive a logic 1. It requires external pullups. When used in
the multiplexed expanded address data/bus mode, this pin does not require pullups.

32-39

P0.7–P0.0/
AD7–AD0

40 VCC +5V Power Supply

for super voltage

PP

3 of 19

DS5000(T)

INSTRUCTION SET

The DS5000(T) executes an instruction set which is object code-compatible with the industry standard
8051 microcontroller. As a result, software development packages that have been written for the 8051,
including cross-assemblers, high-level language compilers, and debugging tools, are compatible with the
DS5000(T).

A complete description for the DS5000(T) instruction set is available in Secure Microcontroller User’s
Guide.

MEMORY ORGANIZATION

Figure 2 illustrates the address spaces, which are accessed by the DS5000(T). As illustrated in the figure,
separate address spaces exist for program and data memory. Since the basic addressing capability of the
machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be
accessed by the DS5000(T) CPU. The 8- or 32-kbyte RAM area inside of the DS5000(T) can be used to
contain both program and data memory.

The real-time clock (RTC) in the DS5000T is reached in the memory map by setting a SFR bit. The
MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2 = 1, all MOVXs will
be routed to this alternate memory map. The RTC is a serial device that resides in this area. A full
description of the RTC access and example software is given in the Secure Microcontroller User’s Guide.
If the ECE2 bit is set on a DS5000 without a timekeeper, the MOVXs will simply go to a nonexistent
memory. Software execution would not be affected otherwise.

4 of 19

DS5000(T) LOGICAL ADDRESS SPACES Figure 2

DS5000(T)

PROGRAM LOADING

The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization
may be performed in one of two ways:

1. Serial Program Loading that can perform Bootstrap Loading of the DS5000(T). This feature allows
the loading of the application program to be delayed until the DS5000(T) is installed in the end
system. Dallas Semiconductor strongly recommends the use of serial program loading because of its
versatility and ease of use.

2. Parallel Program Load cycles that perform the initial loading from parallel address/data information
presented on the I/O port pins. This mode is timing-set compatible with the 8751H microcontroller
programming mode.

The DS5000(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the
RST pin and forcing the
will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at
9600, 2400, 1200, or 300 bps over the serial port.

The hardware configurations used to select these modes of operation are illustrated in Figure 3.

PSEN line to a logic 0 level. Immediately following this action, the DS5000(T)

5 of 19

DS5000(T)

PROGRAM LOADING CONFIGURATIONS Figure 3

Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated
with these cycles is illustrated in the electrical specs.

SERIAL BOOTSTRAP LOADER

The Serial Program Load Mode is the easiest, fastest, most reliable, and most complete method of
initially loading application software into the DS5000(T) nonvolatile RAM. Communication can be
performed over a standard asynchronous serial communications port. A typical application would use a
simple RS232C serial interface to program the DS5000(T) as a final production procedure. The hardware
configuration required for the Serial Program Load mode is illustrated in Figure 3. Port pins 2.7 and 2.6
must be either open or pulled high to avoid placing the DS5000(T) in a parallel load cycle. Although an

11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud rates are

supported, shown in Table 2. The serial loader is designed to operate across a 3-wire interface from a
standard UART. The receive, transmit, and ground wires are all that are necessary to establish
communication with the DS5000(T).

The Serial Bootstrap Loader implements an easy-to-use command line interface that allows an application
program in an Intel hex representation to be loaded into and read back from the device. Intel hex is the
typical format which existing 8051 cross-assemblers output. The serial loader responds to single
character commands, which are summarized below:

6 of 19

COMMAND FUNCTION

C Return CRC-16 checksum of embedded RAM
D Dump Intel hex file
F Fill embedded RAM block with constant
K Load 40-bit encryption key
L Load Intel hex file
R Read MCON register
T Trace (echo) incoming Intel hex data
U Clear security lock
V Verify embedded RAM with incoming Intel hex
W Write MCON register
Z Set security lock
P Put a value to a port
G Get a value from a port

PARALLEL PROGRAM LOAD CYCLES Table 1

MODE RST

PSEN PROG EA

DS5000(T)

P2.7 P2.6 P2.5

Program 1 0 0 V

PP

1 0 X

Security Set 1 0 0 VPP 1 1 X

Verify 1 X X 1 0 0 X

Prog Expanded 1 0 0 VPP 0 1 0

Verify Expanded 1 0 1 1 0 1 0

Prog MCON or Key registers 1 0 0 VPP 0 1 1

Verify MCON registers 1 0 1 1 0 1 1

The Parallel Program Cycle is used to load a byte of data into a register or memory location within the
DS5000(T). The Verify Cycle is used to read this byte back for comparison with the originally loaded
value to verify proper loading. The Security Set Cycle may be used to enable and the Software Security
feature of the DS5000(T). One may also enter bytes for the MCON register or for the five encryption
registers using the Program MCON cycle. When using this cycle, the absolute register address must be
presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents
can likewise be verified using the Verify MCON cycle.

When the DS5000(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in
the Program Load Mode following a Power-On Reset, the internal hardware of the DS5000(T) is
initialized so that an existing 4-kbyte program can be programmed into a DS5000(T) with little or no
modification. This initialization automatically sets the Range Address for 8 kbytes and maps the lowest 4­kbyte bank of Embedded RAM as program memory. The next 4 kbytes of Embedded RAM are mapped
as Data Memory.

In order to program more than 4 kbytes of program code, the Program/Verify Expanded cycles can be
used. Up to 32 kbytes of program code can be entered and verified. Note that the expanded 32-kbyte
Program/ Verify cycles take much longer than the normal 4-kbyte Program/Verify cycles.

7 of 19

DS5000(T)

A typical parallel loading session would follow this procedure. First, set the contents of the MCON
register with the correct range and partition only if using expanded programming cycles. Next, the
encryption registers can be loaded to enable encryption of the program/data memory (not required). Then,
program the DS5000(T) using either normal or expanded program cycles and check the memory contents
using Verify cycles. The last operation would be to turn on the security lock feature by either a Security
Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1.

SERIAL LOADER BAUD RATES FOR
DIFFERENT CRYSTAL FREQUENCIES Table 2

CRYSTAL FREQ

(MHz)

14.7456 Y Y Y Y

11.0592 Y Y Y Y Y Y

9.21600 Y Y Y Y

7.37280 Y Y Y Y

5.52960 Y Y Y Y

1.84320 Y Y Y Y

300 1200 2400 9600 19200 57600

BAUD RATE

ADDITIONAL INFORMATION

Refer to the Secure Microcontroller User’s Guide for a complete description for all operational aspects of
the DS5000(T).

DEVELOPMENT SUPPORT

The DS89C450-K00 evaluation kit (www.maxim-ic.com/DS89C450evkit) can be used to develop and
test user code. It allows the user to download Intel hex-formatted code to the DS5000(T) from a PC.
Refer to the Secure Microcontroller User’s Guide for more information.

8 of 19

DS5000(T)

ABSOLUTE MAXIMUM RATINGS

Voltage on Any Pin Relative to Ground…………………………………………………….-0.3V to +7.0V
Operating Temperature…………………………………………………………………….….0°C to +70°C
Storage Temperature………………………………………………………………………...-40°C to +70°C
Soldering Temperature.…………………………………………See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.

DC CHARACTERISTICS (tA=0°C to 70°C; VCC=5V ± 5%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Low Voltage V

Input High Voltage V

Input High Voltage RST, XTAL1 V

Output Low Voltage

V

@ IOL=1.6 mA (Ports 1, 2, 3)

Output Low Voltage

V

@ IOL=3.2 mA (Ports 0, ALE, PSEN )

Output High Voltage

V

@ IOH=-80 µA (Ports 1, 2, 3)

Output High Voltage

V

@ IOH=-400 µA (Ports 0, ALE, PSEN )

Input Low Current V

= 0.45V

IN

(Ports 1, 2, 3)

Transition Current; 1 to 0
VIN=2.0V (Ports 1, 2, 3)

Input Leakage Current

0.45 < VIN < VCC (Port 0)

RST, EA Pulldown Resistor

R

IH1

IH2

OL1

OL2

OH1

OH2

I

IL

I

TL

I

IL

L

RE

-0.3 0.8 V 1

2.0 VCC+0.3 V 1

3.5 VCC+0.3 V 1

0.15 0.45 V

0.15 0.45 V 1

2.4 4.8 V 1

2.4 4.8 V 1

-50

-500

±10 µA

40 125

µA

µA

kΩ

Stop Mode Current I

Power-Fail Warning Voltage V

Minimum Operating Voltage V

Programming Supply Voltage
(Parallel Program Mode)

Program Supply Current I

Operating Current DS5000-8k @ 8MHz
DS5000-32k @ 12 MHz
DS5000(T)-32-16 @ 16 MHz

Idle Mode Current @ 12 MHz I

SM

PFW

CCmin

V

PP

PP

I

CC

CC

9 of 19

80

µA

4

4.15 4.6 4.75 V 1

4.05 4.5 4.65 V 1

12.5 13 V 1

15 20 mA

25.2

35.7

45.6

43
48
54

mA 2

4.5 6.2 mA 3

AC CHARACTERISTICS: EXPANDED

DS5000(T)

BUS MODE TIMING SPECIFICATIONS (t

=0°C to 70°C; VCC=5V ± 5%)

A

# PARAMETER SYMBOL MIN MAX UNITS

1 Oscillator Frequency 1/t

2 ALE Pulse Width t

3 Address Valid to ALE Low t

4 Address Hold After ALE Low t

5 ALE Low to Valid Instr. In @ 12 MHz

@ 16 MHz

6

ALE Low to PSEN Low

7

PSEN Pulse Width

8

PSEN Low to Valid Instr. In @ 12 MHz

t

@ 16 MHz

9

Input Instr. Hold after PSEN Going High

10

Input Instr. Float after PSEN Going High

11

Address Hold after PSEN Going High

12 Address Valid to Valid Instr. In @ 12 MHz

@ 16 MHz

13

PSEN Low to Address Float

CLK

ALPW

AVALL

AVAAV

t

ALLVI

ALLPSL

t

PSPW

t

PSLVI

t

PSIV

t

PSIX

t

PSAV

t

AVVI

t

PSLAZ

1.0 16 MHz

2t

-40 ns

CLK

t

-40 ns

CLK

t

-35 ns

CLK

4t

t

-25 ns

CLK

3t

-35 ns

CLK

3t

4t

3t

CLK

CLK

CLK

CLK

-150

-90

-150

-90

0 ns

t

t

-8 ns

CLK

5t

-20 ns

CLK

-150

CLK

5t

-90

CLK

0 ns

ns
ns

ns
ns

ns
ns

14

RD Pulse Width

15

WR Pulse Width

16

RD Low to Valid Data In @ 12 MHz

@ 16 MHz

17

Data Hold after RD High

18

Data Float after RD High

19 ALE Low to Valid Data In @ 12 MHz

@ 16 MHz

20 Valid Addr. to Valid Data In @ 12 MHz

@ 16 MHz

21

ALE Low to RD or WR Low

22

Address Valid to RD or WR Low

23

Data Valid to WR Going Low

24

Data Valid to WR High @ 12 MHz
@ 16 MHz

25

Data Valid after

26

RD Low to Address Float

WR High

t

RDPW

t

WRPW

t

RDLDV

t

RDHDV

t

RDHDZ

t

ALLVD

t

AVDV

t

ALLRDL

t

AVRDL

t

DVWRL

t

DVWRH

t

WRHDV

t

RDLAZ

6t

-100 ns

CLK

6t

-100 ns

CLK

5t

5t

CLK

CLK

-165

-105

ns
ns

0 ns

2t

8

9t

3t

-50 3t

CLK

4t

-130 ns

CLK

t

-60 ns

CLK

7t

-150

CLK

7t

-90

CLK

t

-50 ns

CLK

-70 ns

CLK

-150

CLK

8t

-90

CLK

-165

CLK

9t

-105

CLK

+50 ns

CLK

ns

ns
ns

ns
ns

ns

0 ns

27

RD or WR High to ALE High

10 of 19

t

RDHALH

t

-40 t

CLK

+50 ns

CLK

EXPANDED PROGRAM MEMORY READ CYCLE

DS5000(T)

EXPANDED DATA MEMORY READ CYCLE

11 of 19

EXPANDED DATA MEMORY WRITE CYCLE

DS5000(T)

EXTERNAL CLOCK TIMING

12 of 19

AC CHARACTERISTICS (cont'd)

DS5000(T)

EXTERNAL CLOCK DRIVE (t

=0°C to 70°C; VCC=5V ± 5%)

A

# PARAMETER SYMBOL MIN MAX UNITS

28 External Clock High Time @ 12 MHz

@ 16 MHz

29 External Clock Low Time @ 12 MHz

@ 16 MHz

30 External Clock Rise Time @ 12 MHz

@ 16 MHz

31 External Clock Fall Time @ 12 MHz

@ 16 MHz

t

CLKHPW

t

CLKLPW

t

CLKR

t

CLKF

20

ns

15

20

ns

15

20

15

20

15

AC CHARACTERISTICS (cont'd)
SERIAL PORT TIMING - MODE 0 (t

# PARAMETER SYMBOL MIN MAX UNITS

35 Serial Port Cycle Time t

36 Output Data Setup to Rising Clock Edge t

37 Output Data Hold after Rising Clock Edge t

38 Clock Rising Edge to Input Data Valid t

39 Input Data Hold after Rising Clock Edge t

SPCLK

DOCH

CHDO

CHDV

CHDIV

=0°C to 70°C; VCC=5V ± 5%)

A

12t

CLK

10t

-133 ns

CLK

2t

-117 ns

CLK

10t

-133 ns

CLK

0 ns

SERIAL PORT TIMING - MODE 0

ns

ns

ns
ns

ns
ns

µs

13 of 19

AC CHARACTERISTICS (cont'd)

DS5000(T)

POWER CYCLING TIMING (t

=0°C to 70°C; VCC=5V ± 5%)

A

# PARAMETER SYMBOL MIN MAX UNITS

32 Slew Rate from V

33 Crystal Start-up Time t

34 Power-on Reset Delay t

to 3.3V t

CCmin

F

CSU

POR

40

(note 5)

21504 t

POWER CYCLE TIMING

µs

CLK

14 of 19

AC CHARACTERISTICS (cont'd)

DS5000(T)

PARALLEL PROGRAM LOAD TIMING (t

=0°C to 70°C; VCC=5V ± 5%)

A

# PARAMETER SYMBOL MIN MAX UNITS

40 Oscillator Frequency 1/t

41

Address Setup to

42

Address Hold after PROG High

43

Data Setup to PROG Low

44

Data Hold after PROG High

45 P2.7, 2.6, 2.5 Setup to V

46

VPP Setup to PROG Low

47

V

Hold after PROG Low

PP

48

PROG Width Low

PROG Low

PP

49 Data Output from Address Valid t

t

AVPRL

t

PRHAV

t

DVPRL

t

PRHDV

t

P27HVP

t

VPHPRL

t

PRHVPL

t

AVDV

CLK

PRW

1.0 12.0 MHz

0

0

0

0

0

0

0

2400 t

48

1800*

50 Data Output from P2.7 Low t

DVP27L

48

1800*

51 Data Float after P2.7 High t

P27HDZ

0 48

1800*

CLK

t

CLK

t

CLK

t

CLK

52

Delay to Reset/ PSEN Active after Power On

53

Reset/ PSEN Active (or Verify Inactive) to

t

PORPV

t

RAVPH

21504 t

1200 t

VPP High

54 VPP Inactive (Between Program Cycles) t

55 Verify Active Time t

VPPPC

VFT

1200 t

48

2400*

* Second set of numbers refers to expanded memory programming up to 32k bytes.

CLK

CLK

CLK

t

CLK

15 of 19

PARALLEL PROGRAM LOAD TIMING

DS5000(T)

CAPACITANCE (test frequency=1MHz; t

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Output Capacitance C

Input Capacitance C

O

I

16 of 19

=25°C)

A

10 pF

10 pF

DS5000(T) TYPICAL ICC VS. FREQUENCY

DS5000(T)

Normal operation is measured using:

1) External crystals on XTAL1 and 2

2) All port pins disconnected

3) RST=0 volts and EA=V

CC

4) Part performing endless loop writing to internal memory

Idle mode operation is measured using:

1) External clock source at XTAL1; XTAL2 floating

2) All port pins disconnected

3) RST=0 volts and EA=V

CC

4) Part set in IDLE mode by software

17 of 19

DS5000(T)

NOTES:

1. All voltages are referenced to ground.

2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with t
t

= 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC.

CLKF

3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven with t
V

= 0.5V; XTAL2 disconnected; EA = PORT0 = VCC, RST = VSS.

IL

CLKR

, t

CLKF

= 10 ns,

4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = VCC; XTAL2 not
connected; RST = VSS.

5. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from
the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for the worst case spec on this time.

PACKAGE DRAWING

DIM

A IN. 2.080 2.100

B IN. 0.680 0.700

C IN. 0.290 0.325

D IN. 0.090 0.110

E IN. 0.030 0.060

F IN. 0.145 0.185

G IN. 0.016 0.020

H IN. 0.590 0.610

I IN. 0.009 0.015

INCHES

MIN MAX

CLKR

,

18 of 19

DS5000(T)

DATA SHEET REVISION SUMMARY

REVISION DESCRIPTION

072095 to

072496
112299 Converted from Interleaf to Word.

Corrected Figure 3 to show RST active high.
Added Data Sheet Revision Summary section.

Page 1: Features
Added “at Room Temperature” to “Maintains All Nonvolatile Resources Up to 10
Years in the Absence of VCC” bullet.

Page 2: Ordering Information
Removed 8kB parts from list; added 32kB and lead-free packages.

070706

Page 8: Development Support
Updated paragraph to reflect availability of DS89C450-K00 evaluation kit, not
DS5000TK.

Page 9: Absolute Maximum Ratings
Changed “260°C for 10 seconds” to “See IPC/JEDEC J-STD-020 Specification.”
Pages 1, 4, 8: Replaced references to “User’s Guide section of Secure
Microcontroller Data Book” with “Secure Microcontroller User’s Guide.”

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

19 of 19

© 2006 Maxim Integrated Products

Mouser Electronics

Authorized Distributor

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