DS4830
OpticalMicrocontroller
User’sGuide
Rev 0.3 8/2012
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves
the right to change the circuitry and specifications without notice at any time.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
DS4830 User’s Guide
Contents
SECTION 1 – OVERVIEW ...................................................................................................................................................... 9
SECTION 2 – ARCHITECTURE ........................................................................................................................................... 11
2.1 – Instruction Decoding ................................................................................................................................................. 11
2.2 – Register Space ......................................................................................................................................................... 12
2.3 – Memory Types .......................................................................................................................................................... 13
2.3.1 – Flash Memory .................................................................................................................................................... 13
2.3.2 – SRAM Memory ................................................................................................................................................... 13
2.3.3 – Utility ROM ......................................................................................................................................................... 13
2.3.4 – Stack Memory .................................................................................................................................................... 13
2.4 – Program and Data Memory Mapping and Access ................................................................................................... 14
2.4.1 – Program Memory Access .................................................................................................................................. 14
2.4.2 – Program Memory Mapping ................................................................................................................................ 15
2.4.3 – Data Memory Access ......................................................................................................................................... 15
2.4.4 – Data Memory Mapping ...................................................................................................................................... 16
2.5 – Data Alignment ......................................................................................................................................................... 20
2.6 – Reset Conditions ...................................................................................................................................................... 20
2.6.1 – Power-On/Brownout Reset ................................................................................................................................ 20
2.6.2 – Watchdog Timer Reset ...................................................................................................................................... 21
2.6.3 – External Reset ................................................................................................................................................... 21
2.6.4 – Internal System Resets ...................................................................................................................................... 22
2.7 – Clock Generation ...................................................................................................................................................... 22
SECTION 3 – SYSTEM REGISTER DESCRIPTIONS ......................................................................................................... 23
SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS ................................................................................................. 31
SECTION 5 – INTERRUPTS ................................................................................................................................................ 36
5.1 – Servicing Interrupts ................................................................................................................................................... 37
5.2 – Module Interrupt Identification Registers .................................................................................................................. 39
5.3 – Interrupt System Operation ...................................................................................................................................... 40
5.3.1 – Synchronous vs. Asynchronous Interrupt Sources ............................................................................................ 40
5.3.2 – Interrupt Prioritization by Software ..................................................................................................................... 40
5.3.3 – Interrupt Exception Window ............................................................................................................................... 40
SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC) ................................................................................................ 42
6.1 – Detailed Description ................................................................................................................................................. 42
6.1.1 – Reference Selection.......................................................................................................................................... 43
6.1.2 – Requirement for Enabled DACs ....................................................................................................................... 43
6.2 – DAC Register Descriptions ....................................................................................................................................... 43
6.3 –DAC Code Examples ................................................................................................................................................. 45
SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC) ................................................................................................ 46
7.1 – Detailed Description ................................................................................................................................................. 46
7.1.1 – ADC Controller ................................................................................................................................................... 46
7.1.2 – ADC Conversion Sequencing ............................................................................................................................ 47
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DS4830 User’s Guide
7.1.3 – Temperature Conversion ................................................................................................................................... 48
7.1.4 – Sample and Hold Conversion ............................................................................................................................ 48
7.1.5 – ADC Frame Sequence ....................................................................................................................................... 48
7.1.6 – ADC Conversion Time ....................................................................................................................................... 49
7.1.7 – Location Override............................................................................................................................................... 50
7.1.8 – ADC Data Reading ............................................................................................................................................ 50
7.1.9 – ADC Interrupts ................................................................................................................................................... 51
7.1.10 – ADC Internal Offset .......................................................................................................................................... 51
7.2 – ADC Register Descriptions ....................................................................................................................................... 52
7.3 –ADC Code Examples ................................................................................................................................................. 58
SECTION 8 – SAMPLE AND HOLD ..................................................................................................................................... 60
8.1 – Detailed Description ................................................................................................................................................. 60
8.1.1 – Operation ........................................................................................................................................................... 60
8.1.2 – Fast Mode Operation ......................................................................................................................................... 61
8.1.3 – Sampling Control ............................................................................................................................................... 61
8.1.4 – Pin Capacitance Discharge ............................................................................................................................... 63
8.1.5 – Sample and Hold Data Reading ........................................................................................................................ 64
8.1.6 – Sample and Hold Interrupts ............................................................................................................................... 64
8.2 – Sample and Hold Register Descriptions ................................................................................................................... 65
SECTION 9 – QUICK TRIP (FAST COMPARATOR) ........................................................................................................... 68
9.1 – Detailed Description ................................................................................................................................................. 68
9.1.1 – Quick Trip List Sequencing ................................................................................................................................ 69
9.1.2 – Operation ........................................................................................................................................................... 69
9.1.3 – Quick Trip Interrupts .......................................................................................................................................... 71
9.2 – Quick Trip Register Descriptions .............................................................................................................................. 72
SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE .................................................................................................. 76
10.1 – Detailed Description .............................................................................................................................................. 76
10.1.1 – Description of Master I2C Interface ................................................................................................................. 76
10.1.2 – Default Operation ............................................................................................................................................. 76
10.1.3 – I2C Clock Generation ...................................................................................................................................... 76
10.1.4 – Timeout ............................................................................................................................................................ 77
10.1.5 – Generating a START ....................................................................................................................................... 78
10.1.6 – Generating a STOP ......................................................................................................................................... 79
10.1.7 – Transmitting a Slave Address .......................................................................................................................... 80
10.1.8 – Transmitting Data............................................................................................................................................. 80
10.1.9 – Receiving Data................................................................................................................................................. 81
10.1.10 – I2C Master Clock Stretching .......................................................................................................................... 83
10.1.11 – Resetting the I2C Master Controller .............................................................................................................. 83
10.1.12 – Operation as a Slave ..................................................................................................................................... 84
10.1.13 – GPIO .............................................................................................................................................................. 84
10.2 – I2C Master Controller Register Description ........................................................................................................... 85
SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE ...................................................................................................... 89
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DS4830 User’s Guide
11.1 – Detailed Description .............................................................................................................................................. 90
11.1.1 – Default Operation ............................................................................................................................................. 90
11.1.2 – Slave Address .................................................................................................................................................. 90
11.1.3 – I2C Start Detection........................................................................................................................................... 90
11.1.4 – I2C Stop Detection ........................................................................................................................................... 90
11.1.5 – Slave Address Matching .................................................................................................................................. 90
11.1.6 – Transmitting Data............................................................................................................................................. 91
11.1.7 – Receiving Data................................................................................................................................................. 92
11.1.8 – Clock Stretching ............................................................................................................................................... 93
11.1.9 – SMBus Timeout ............................................................................................................................................... 93
11.1.10 – Resetting the I2C Slave Controller ................................................................................................................ 94
11.1.11 – Operation as a Master ................................................................................................................................... 94
11.2 – I2C Slave Controller Register Description .............................................................................................................. 95
SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI) .................................................................................................. 99
12.1 – Serial Peripheral Interface (SPI) Detailed Description ........................................................................................... 99
12.1.1 – SPI Transfer Formats .......................................................................................................................................... 99
12.1.2 – SPI Character Lengths ...................................................................................................................................... 101
12.2 – SPI System Errors ................................................................................................................................................ 101
12.2.1 – Mode Fault ......................................................................................................................................................... 101
12.2.2 – Receive Overrun ................................................................................................................................................ 101
12.2.3 – Write Collision While Busy ................................................................................................................................ 102
12.3 – SPI Interrupts ........................................................................................................................................................ 102
12.4 – SPI Master ............................................................................................................................................................ 103
12.4.1 – SPI Transfer Baud Rates .................................................................................................................................. 103
12.4.2 – SPI Master Operation ........................................................................................................................................ 103
12.4.3 – SPI Master Register Descriptions ..................................................................................................................... 105
12.5 – SPI Slave .............................................................................................................................................................. 107
12.5.1 – SPI Slave Select ................................................................................................................................................ 107
12.5.2 – SPI Transfer Baud Rates .................................................................................................................................. 107
12.5.3 – SPI Slave Operation .......................................................................................................................................... 107
12.5.4 – SPI Slave Register Descriptions ....................................................................................................................... 108
SECTION 13 – 3-WIRE ....................................................................................................................................................... 110
13.1 – Detailed Description ............................................................................................................................................. 110
13.1.1 – Operation ....................................................................................................................................................... 110
13.2 – 3-Wire Register Descriptions ................................................................................................................................ 112
SECTION 14 – PWM .......................................................................................................................................................... 113
14.1 – Detailed Description ............................................................................................................................................. 113
14.1.1 – PWMCN and PWMDATA SFRs .................................................................................................................... 113
14.1.2 – PWMSYNC SFR ............................................................................................................................................ 114
14.2 – Individual PWM Channel Operation ..................................................................................................................... 115
14.2.1 – Duty Cycle Register (DCYCn) ....................................................................................................................... 115
14.2.2 – PWM Configuration Register (PWMCFGn) ................................................................................................... 116
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DS4830 User’s Guide
14.2.3 – Pulse Spreading............................................................................................................................................. 116
14.2.4 – Alternate PWM Output ................................................................................................................................... 119
14.2.5 – PWM DELAY Register (PWMDLYn).............................................................................................................. 119
14.3 – PWM Output Register Descriptions ...................................................................................................................... 120
14.4 – PWM Output Code Examples .............................................................................................................................. 125
SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS ............................................................................. 126
15.1 – Overview ............................................................................................................................................................... 126
15.2 – GPIO Port 0 Register Descriptions ....................................................................................................................... 129
15.2.1 – GPIO Direction Register Port 0 (PD0) ........................................................................................................... 129
15.2.2 – GPIO Output Register Port 0 (PO0) .............................................................................................................. 129
15.2.3 – GPIO Input Register for Port 0 (PI0) .............................................................................................................. 129
15.2.4 – GPIO Port 0 External Interrupt Edge Select Register (EIES0) ..................................................................... 129
15.2.5 – GPIO Port 0 External Interrupt Flag Register (EIF0) ..................................................................................... 130
15.2.6 – GPIO Port 0 External Interrupt Enable Register (EIE0)................................................................................. 130
15.3 – GPIO Port 1 Register Descriptions ....................................................................................................................... 130
15.3.1 – GPIO Direction Register Port 1 (PD1) ........................................................................................................... 130
15.3.2 – GPIO Output Register Port 1 (PO1) .............................................................................................................. 130
15.3.3 – GPIO Input Register for Port 1 (PI1) .............................................................................................................. 131
15.3.4 – GPIO Port 1 External Interrupt Edge Select Register (EIES1) ..................................................................... 131
15.3.5 – GPIO Port 1 External Interrupt Flag Register (EIF1) ..................................................................................... 131
15.3.6 – GPIO Port 1 External Interrupt Enable Register (EIE1)................................................................................. 131
15.4 – GPIO Port 2 Register Descriptions ....................................................................................................................... 131
15.4.1 – GPIO Direction Register Port 2 (PD2) ........................................................................................................... 131
15.4.2 – GPIO Output Register Port 2 (PO2) .............................................................................................................. 132
15.4.3 – GPIO Input Register for Port 2 (PI2) .............................................................................................................. 132
15.4.4 – GPIO Port 2 External Interrupt Edge Select Register (EIES2) ..................................................................... 132
15.4.5 – GPIO Port 2 External Interrupt Flag Register (EIF2) ..................................................................................... 132
15.4.6 – GPIO Port 2 External Interrupt Enable Register (EIE2)................................................................................. 132
15.5 – GPIO Port 6 Register Descriptions ....................................................................................................................... 133
15.5.1 – GPIO Direction Register Port 6 (PD6) ........................................................................................................... 133
15.5.2 – GPIO Output Register Port 6 (PO6) .............................................................................................................. 133
15.5.3 – GPIO Input Register for Port 6 (PI6) .............................................................................................................. 133
15.5.4 – GPIO Port 6 External Interrupt Edge Select Register (EIES6) ..................................................................... 133
15.5.5 – GPIO Port 6 External Interrupt Flag Register (EIF6) ..................................................................................... 134
15.5.6 – GPIO Port 6 External Interrupt Enable Register (EIE6)................................................................................. 134
SECTION 16 – GENERAL-PURPOSE TIMERS ................................................................................................................ 135
16.1 – Detailed Description ............................................................................................................................................. 135
16.1.1 – Timer Modes .................................................................................................................................................. 135
16.1.2 – Clock Selection .............................................................................................................................................. 136
16.1.3 – Timer Clock Prescaler ................................................................................................................................... 136
16.2 – Timer Register Descriptions ................................................................................................................................. 137
SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM) ..................................................................................................... 139
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DS4830 User’s Guide
SECTION 18 – HARDWARE MULTIPLIER MODULE ....................................................................................................... 140
18.1 – Hardware Multiplier Organization ......................................................................................................................... 140
18.2 – Hardware Multiplier Controls ................................................................................................................................ 140
18.3 – Register Output Selection..................................................................................................................................... 141
18.3.1 – Signed-Unsigned Operand Selection ............................................................................................................ 141
18.3.2 – Operand Count Selection .............................................................................................................................. 141
18.4 – Hardware Multiplier Operations ............................................................................................................................ 141
18.4.1 – Accessing the Multiplier ................................................................................................................................. 141
18.5 – Hardware Multiplier Peripheral Registers ............................................................................................................. 142
18.6 – Hardware Multiplier Examples .............................................................................................................................. 145
SECTION 19 – WATCHDOG TIMER.................................................................................................................................. 146
19.1 - Overview ............................................................................................................................................................... 146
19.2 – Watchdog Timer Description ................................................................................................................................ 146
19.2.1 – Watchdog Timer Interrupt Operation ............................................................................................................. 147
19.2.2 – Watchdog Timer Reset Operation ................................................................................................................. 147
19.2.3 – Watchdog Timer Applications ........................................................................................................................ 147
SECTION 20 – TEST ACCESS PORT (TAP) ..................................................................................................................... 149
20.1 – TAP Controller ...................................................................................................................................................... 150
20.2 – TAP State Control ................................................................................................................................................. 151
20.2.1 – Test-Logic-Reset............................................................................................................................................ 151
20.2.2 – Run-Test-Idle ................................................................................................................................................. 151
20.2.3 – IR-Scan Sequence ......................................................................................................................................... 151
20.2.4 – DR-Scan Sequence ....................................................................................................................................... 152
20.3 – Communication via TAP ....................................................................................................................................... 152
20.3.1 - TAP Communication Examples – IR-Scan and DR-Scan .............................................................................. 153
SECTION 21 – IN-CIRCUIT DEBUG MODE ...................................................................................................................... 155
21.1 – Background Mode Operation ............................................................................................................................... 156
21.1.1 – Breakpoint Registers ..................................................................................................................................... 157
21.1.2 – Using Breakpoints .......................................................................................................................................... 159
21.2 – Debug Mode ......................................................................................................................................................... 160
21.2.1 – Debug Mode Commands ............................................................................................................................... 160
21.2.2 – Read Register Map Command Host-ROM Interaction .................................................................................. 162
21.2.3 – Single Step Operation (Trace) ....................................................................................................................... 163
21.2.4 – Return ............................................................................................................................................................ 164
21.2.5 – Debug Mode Special Considerations ............................................................................................................ 164
21.3 – In-Circuit Debug Peripheral Registers .................................................................................................................. 165
SECTION 22 – IN-SYSTEM PROGRAMMING .................................................................................................................. 169
22.1 – Detailed Description ............................................................................................................................................. 169
22.1.1 - Password Protection ....................................................................................................................................... 170
22.1.2 – Entering JTAG Bootloader ............................................................................................................................. 170
22.1.3 – Entering I2C Bootloader ................................................................................................................................ 171
22.2 – Bootloader Operation ........................................................................................................................................... 171
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DS4830 User’s Guide
22.2.1 – JTAG Bootloader Protocol ............................................................................................................................. 172
22.2.2 – I2C Bootloader Protocol ................................................................................................................................. 172
22.3 – Bootloader Commands ......................................................................................................................................... 173
22.3.1 - Command 00h – No Operation ....................................................................................................................... 173
22.3.2 - Command 01h – Exit Loader .......................................................................................................................... 173
22.3.3 - Command 02h – Master Erase ....................................................................................................................... 173
22.3.4 - Command 03h – Password Match ................................................................................................................. 174
22.3.5 - Command 04h – Get Status ........................................................................................................................... 174
22.3.6 - Command 05h – Get Supported Commands ................................................................................................. 175
22.3.7 - Command 06h – Get Code Size ..................................................................................................................... 175
22.3.8 - Command 07h – Get Data Size ...................................................................................................................... 175
22.3.9 - Command 08h – Get Loader Version ............................................................................................................. 175
22.3.10 - Command 09h – Get Utility ROM Version .................................................................................................... 175
22.3.11 - Command 10h – Load Code ........................................................................................................................ 176
22.3.12 - Command 11h – Load Data ......................................................................................................................... 176
22.3.13 - Command 20h – Dump Code ....................................................................................................................... 176
22.3.14 - Command 21h – Dump Data ........................................................................................................................ 177
22.3.15 - Command 30h – CRC Code ......................................................................................................................... 177
22.3.16 - Command 31h – CRC Data .......................................................................................................................... 177
22.3.17 - Command 40h – Verify Code ....................................................................................................................... 177
22.3.18 - Command 41h – Verify Data ........................................................................................................................ 177
22.3.19 - Command 50h – Load and Verify Code ....................................................................................................... 178
22.3.20 - Command 51h – Load and Verify Data ........................................................................................................ 178
22.3.21 - Command E0h – Code Page Erase ............................................................................................................. 178
SECTION 23 – PROGRAMMING ....................................................................................................................................... 179
23.1 – Addressing Modes ................................................................................................................................................ 179
23.2 – Prefixing Operations ............................................................................................................................................. 179
23.3 – Reading and Writing Registers ............................................................................................................................. 179
23.3.1 – Loading an 8-bit register with an immediate value ........................................................................................ 180
23.3.2 – Loading a 16-bit register with a 16-bit immediate value ................................................................................ 180
23.3.3 – Moving values between registers of the same size ....................................................................................... 180
23.3.4 – Moving values between registers of different sizes ....................................................................................... 180
23.4 – Reading and Writing Register Bits ....................................................................................................................... 181
23.5 – Using the Arithmetic and Logic Unit ..................................................................................................................... 182
23.5.1 – Selecting the active accumulator ................................................................................................................... 182
23.5.2 – Enabling auto-increment and auto-decrement .............................................................................................. 182
23.5.3 – ALU operations using the active accumulator and a source ......................................................................... 184
23.5.4 – ALU operations using only the active accumulator........................................................................................ 184
23.5.5 – ALU bit operations using only the active accumulator ................................................................................... 184
23.5.6 – Example: Adding two four-byte numbers using auto-increment .................................................................... 184
23.6 - Processor Status Flag Operations ........................................................................................................................ 184
23.6.1 - Sign Flag ......................................................................................................................................................... 184
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DS4830 User’s Guide
23.6.2 - Zero Flag ........................................................................................................................................................ 185
23.6.3 - Equals Flag ..................................................................................................................................................... 185
23.6.4 - Carry Flag ....................................................................................................................................................... 185
23.6.5 - Overflow Flag .................................................................................................................................................. 186
23.7 - Controlling Program Flow ...................................................................................................................................... 186
23.7.1 - Obtaining the next execution address ............................................................................................................ 186
23.7.2 - Unconditional jumps ....................................................................................................................................... 186
23.7.3 - Conditional jumps ........................................................................................................................................... 187
23.7.4 - Calling subroutines ......................................................................................................................................... 187
23.7.5 - Looping operations ......................................................................................................................................... 187
23.7.6 - Conditional returns.......................................................................................................................................... 188
23.8 - Handling Interrupts ................................................................................................................................................ 188
23.8.1 - Conditional return from interrupt ..................................................................................................................... 189
23.9 - Accessing the Stack .............................................................................................................................................. 189
23.10 - Accessing Data Memory ..................................................................................................................................... 190
SECTION 24 – INSTRUCTION SET................................................................................................................................... 192
SECTION 25 – UTILITY ROM ............................................................................................................................................ 220
25.1 – Overview ............................................................................................................................................................... 220
25.2 – In-Application Programming Functions ................................................................................................................ 221
25.2.1 – UROM_flashWrite .......................................................................................................................................... 221
25.2.2 – UROM_flashErasePage ................................................................................................................................ 221
25.3 – Data Transfer Functions ....................................................................................................................................... 222
25.3.1 – UROM_moveDP0 .......................................................................................................................................... 223
25.3.2 – UROM_moveDP0inc ..................................................................................................................................... 223
25.3.3 – UROM_moveDP0dec .................................................................................................................................... 223
25.3.4 – UROM_moveDP1 .......................................................................................................................................... 224
25.3.5 – UROM_moveDP1inc ..................................................................................................................................... 224
25.3.6 – UROM_moveDP1dec .................................................................................................................................... 224
25.3.7 – UROM_moveBP ............................................................................................................................................ 225
25.3.8 – UROM_moveBPinc ........................................................................................................................................ 225
25.3.9 – UROM_moveBPdec ...................................................................................................................................... 225
25.3.10 – UROM_copyBuffer ....................................................................................................................................... 226
25.4 – Utility ROM Examples ........................................................................................................................................... 227
25.4.1 – Reading Constant Word Data from Flash ...................................................................................................... 227
25.4.2 – Reading Constant Byte Data from Flash (Indirect Function Call) .................................................................. 227
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DS4830 User’s Guide
SECTION 1 – OVERVIEW
The DS4830 System Management Microcontroller provides a complete optical control, calibration, and monitor solution.
The IC is based on the high-performance 16-bit family of MAXQ
microcontrollers, and provides generous amounts of flash program memory and SRAM data memory.
Some of the resources and features that the DS4830 provides for monitoring and controlling an optical sy stem include the
following:
16-Bit MAXQ20 Low-Power Microcontroller
13-Bit ADC with a 26 Input Mux
Single and Differential Mode
4 User-Selectable Gains for Individual Channel
V
, Internal Reference and DAC External Reference Measurement
DD
40ksps with Fastest ADC Clock
10 PWM Channels
Normal and Pulse Spreading Operation Modes
PWM Output Synchronization
User-Selectable 7- to 12-Bit Resolution
1MHz Switching Using 133MHz External Clock
8-bit Fast Comparator with 16 Input Mux
Single and Differential Mode
Low and High Threshold Configurations
3.2s Conversion Time per Channel
Two Independent Sample and Hold
Single, Fast and Dual Mode Operation
Internal and External Trigger Option
Pin Discharge
Temperature Sensors
Internal Die Temperature Measurement
Remote Temperature Measurement of Two Diode Connected Transistors
8 Voltage DAC Channels having 12-Bit Resolution with Selectable Internal or External Reference Option
SPI or 400kHz I
SPI, 400kHz I
2
C-Compatible Slave Communication Interface
2
C-Compatible, or Maxim Integrated 3-Wire Laser Driver Master Communication Interface
Two 16-bit Timers with Synchronous and Compare modes
Watchdog Timer
Maskable Interrupt Sources
Hardware Multiplier Unit
Supply Voltage Monitoring
32KWords of Flash and 1KWords of SRAM Memory
Included ROM Routines that allow Bootloading and In-Application Programming of Flash Memory
In-System Debugging
®
reduced instruction set computing (RISC)
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
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DS4830 User’s Guide
Figure 1-1 DS4830 Block Diagram
This document is provided as a supplement to the DS4830 IC data sheet. This user’s guide provides the information
necessary to develop applications using the DS4830. All electrical and timing specifications, pin descriptions, package
information, and ordering information can be found in the DS4830 IC data sheet.
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DS4830 User’s Guide
FORMAT DESTINATION SOURCE
s sd
f s s
s s s sd d d d
d d
SECTION 2 – ARCHITECTURE
The DS4830 contains a MAXQ20 low-cost, high-performance, CMOS, fully static microcontroller with flash memory. It is
structured on a highly advanced, 16-accumulator-based, 16-bit RISC architecture. Fetch and execution operations are
completed in one cycle without pipelining, since the instruction contains both the op code and data. The highly efficient
core is supported by 16 accumulators and a 16-level hardware stack, enabling fast subroutine calling and task switching.
Data can be quickly and efficiently manipulated with three internal data pointers. Two of these data pointers, DP0 and
DP1, are stand-alone 16-bit pointers. The third data pointer, Frame Pointer, is composed of a 16-bit base pointer (BP) and
an 8-bit offset register (OFFS). All three pointers support post-increment/decrement functionality for read operations and
pre-increment/decrement for write operations. For the Frame Pointer (FP=BP[OFFS]), the increment/decrement operation
is executed on the OFFS register and does not affect the base pointer. Multiple data pointers allow more than one
function to access data memory without having to save and restore data pointers each time.
Stack functionality is provided by dedicated memory with a 16-bit width and a depth of 16. An on-chip memory
management unit (MMU) allows logical remapping of the program and data spaces, and thus facilitates in-system
programming and fast access to data tables, arrays, and constants located in flash memory.
This section provides details on the following topics.
1. Instruction decoding
2. Register space
3. Memory types
4. Program and data memory mapping and access
5. Data alignment
6. Reset conditions
7. Clock generation
8. Power modes
2.1 – Instruction Decoding
The DS4830 uses the standard 16-bit MAXQ20 core instruction set, which is described in the Instruction Set section.
Every instruction is encoded as a single 16-bit word. The instruction word format is shown in Figure 2-1.
Figure 2-1: Instruction Word Format
Bit 15 (f) indicates the format for the source field of the instruction as follows:
o If f equals 0, the instruction is an immediate source instruction. The source field represents an immediate
8-bit value.
o If f equals 1, the instruction is a register source instruction. The source field represents the register that
the source value will be read from.
Bits 14 to 8 (ddddddd) represent the destination for the transfer. This value always represents a destination
register. The lower four bits contain the module specifier and the upper three bits contain the register index in
that module.
Bits 7 to 0 (ssssssss) represent the source for the transfer. Depending on the value of the format field, this can
either be an immediate value or a source register. If this field represents a register, the lower four bits contain the
module specifier and the upper four bits contain the register index in that module.
This instruction word format presents the following limitations.
1. There are 32 registers per register module, but only four bits are allocated to designate the source register and
only three bits are allocated to designate the destination register.
2. The source field only provides 8 bits of data for an immediate value; however a 16-bit immediate value may be
required.
The DS4830 uses a prefix register (PFX) to address these limitations. The prefix register provides the additional bits
required to access all 32 register within a module. The prefix register also provides the additional 8 bits of data required
to make a 16-bit immediate data source. The data that is written to the prefix register survives for only one clock cycle.
This means the write to the prefix register must occur immediately prior to the instruction requiring the prefix register. The
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DS4830 User’s Guide
prefix register is cleared to zero after one cycle so it will not affect any other instructions. The write to the prefix register is
done automatically by the assembler and requires one additional execution cycle. So, while most instructions execute in
a single cycle, two cycles are needed for instructions that require the prefix register.
The architecture of the DS4830 is transport-triggered. This means that writing to or reading from certain register locations
will also cause side effects to occur. These side effects form the basis of the DS4830’s higher level op codes, such as
ADDC, OR, and JUMP. While these op codes are actually implemented as MOVE instructions between certain register
locations, the encoding is handled by the assembler and need not be a concern to the programmer. The unused "empty"
locations in the System Register Modules are used for these higher level op codes.
The instruction set is designed to be highly orthogonal. All arithmetic and logical operations that use two registers can use
any register along with the accumulator. Data can be transferred between any two registers in a single instruction.
2.2 – Register Space
The DS4830 provides a total of 13 register modules broken up into two different groups. These groupings are descriptive
only, as there is no difference between accessing the two register groups from a programming perspective. The two
groups are:
1. Peripheral Registers: These are the lower six modules (Modules 0h through 5h). The Peripheral Registers in the
DS4830 are used for functionalities such as ADC, PWM Outputs, Sample and Hold, 3Wire, I2C Master and Slave,
SPI Master and Slave, GPIO, etc. The Peripheral Registers are not used to implement op codes.
2. System Registers: These are modules 8h, 9h, and Bh through Fh. The System Registers in the DS4830 are used
to implement higher level op codes as well as the following common system features.
16-bit ALU and associated status flags (zero, equals, carry, sign, overflow)
16 working accumulator registers, each 16-bit, along with associated control registers
Instruction pointer
Registers for interrupt control, handling, and identification
Auto-decrementing Loop Counters for fast, compact looping
Two Data Pointer registers and a Frame Pointer for data memory access
Each System Register module has 16 registers, while each Peripheral Register module has 32 registers. The number of
cycles required to access a particular register depends upon the register’s index within the module. The access times
based upon the register index are grouped as follows:
The first eight registers (index 0h to 7h) in each module may be read from or written to in a single cycle
The second eight registers (index 8h to 0Fh) may be read from in a single cycle and written to in two cycles (by
using the prefix register PFX).
The last sixteen registers (10h to 1Fh) in Peripheral Register modules may be read or written in two cycles
(always requiring use of the prefix register PFX).
Registers may be 8 or 16 bits in length. Some registers may contain reserved bits. The user should not write to any
reserved bits. Data transfers between registers of different sizes are handled as shown in Table 2-1.
If the source and destination registers are both 8 bits wide, data is copied bit to bit.
If the source register is 8 bits wide and the destination register is 16 bits wide, the data from the source register is
transferred into the lower 8 bits of the destination register. The upper 8 bits of the destination register are set to
the current value of the prefix register; this value is normally zero, but it can be set to a different value by the
previous instruction if needed. The prefix register reverts back to zero after one cycle, so this must be done by the
instruction immediately before the one that will be using the value.
If the source register is 16 bits wide and the destination register is 8 bits wide, the lower 8 bits of the source are
transferred to the destination register.
If both registers are 16 bits wide, data is copied bit to bit.
The above rules apply to all data movements between defined registers. Data transfer to/from undefined register locations
has the following behavior:
If the destination is an undefined register, the MOVE is a dummy operation but may trigger an underlying
operation according to the source register (e.g., @DPn--).
If the destination is a defined register and the source is undefined, the source data for the transfer will depend
upon the source module width. If the source is from a module containing 8-bit or 8-bit and 16-bit source registers,
the source data will be equal to the prefix data as the upper 8 bits and 00h as the lower 8 bits. If the source is
from a module containing only 16-bit source registers, 0000h source data is used for the transfer.
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DS4830 User’s Guide
SOURCE REGISTER
SIZE (BITS)
DESTINATION REGISTER
SIZE (BITS)
PREFIX
SET?
DESTINATION SET TO VALUE
HIGH 8 BITS
LOW 8 BITS
8
8
X — Source [7:0] 8 16
No
00h
Source [7:0] 8 16
Yes
PFX [7:0]
Source [7:0]
16
8
X — Source [7:0]
16
16
X
Source [15:8]
Source [7:0]
Table 2-1. Register-to-Register Transfer Operations
2.3 – Memory Types
In addition to the internal register space, the DS4830 incorporates the following memory types:
32KWords of flash memory
4KWords of utility ROM contain a debugger and program loader
1KWords of SRAM
16-level stack memory for storage of program return addresses
The memory on the DS4830 is organized according to a Harvard architecture. This means that there are separate busses
for both program and data memory. Stack memory is also separate and is accessed through a dedicated register set.
2.3.1 – Flash Memory The DS4830 contains 32KWords (32K x 16) of flash memory. The flash memory begins at address 0000h and is contiguous through word address 7FFFh. The flash memory can also be used for storing lookup tables and other nonvolatile data.
The incorporation of flash memory allows the contents of the flash memory to be upgraded in the field, either by the
application or by one of the bootloaders (JTAG or I2C). Writing to flash memory must be done indirectly by using routines
that are provided by the utility ROM. See the Utility ROM and In-System Programming sections for more details.
2.3.2 – SRAM Memory
The DS4830 contains 1KWords (1K x 16) of SRAM memory. The SRAM memory address begins at address 0000h and
is contiguous through word address 03FFh. The contents of the SRAM are indeterminate after power-on reset, but are
maintained during non-POR resets.
When using the in-circuit debugging features, the highest 19 bytes of the SRAM must be reserved for saved state storage
and working space for the debugging routines. If in-circuit debug is not used, the entire 1KWords of SRAM is available for
application use.
2.3.3 – Utility ROM
The utility ROM is a 4kWord segment of memory. The utility ROM memory address begins at word address 8000h and is
contiguous through word address 8FFFh. The utility ROM is programmed at the factory and cannot be modified. The
utility ROM provides the following system utility functions:
Reset vector (not user code reset vector)
In-system programming (bootstrap loader) over JTAG or I2C-compatible interfaces
In-circuit debug routines
Routines for in-application flash programming
Following any reset, the DS4830 automatically starts execution at the Reset Vector which is address 8000h in the utility
ROM. The ROM code determines whether the program execution should immediately jump to the start of application code
(flash address 0000h), or to one of the special routines mentioned. Routines within the utility ROM are firmwareaccessible and can be called as subroutines by the application software. See the Utility ROM, In-System Programming,
and In-Circuit Debug sections for more information on the routines provided by the utility ROM.
2.3.4 – Stack Memory
A 16-bit, 16-level on-chip stack provides storage for program return addresses and temporary storage of system registers.
The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed, and when an
interrupt is serviced. The stack can also be used explicitly to store and retrieve data by using the @SP- - source, @++SP
destination, or the PUSH, POP, and POPI instructions. The POPI instruction acts identically to the POP instruction except
that it additionally clears the INS bit.
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DS4830 User’s Guide
The width of the stack is 16 bits to accommodate the instruction pointer size. On reset, the stack pointer SP initializes to
the top of the stack (0Fh). The CALL, PUSH, and interrupt vectoring operations first increment SP and then store a value
at @SP. The RET, RETI, POP, and POPI operations first retrieve the value at @SP and then decrement SP.
The stack memory is initialized to indeterminate values upon reset or power-up. Stack memory is dedicated for stack
operations only and cannot be accessed by the DS4830 program or data busses.
When using the in-circuit debugging features, one word of the stack must be reserved for the debugging routines. If incircuit debug is not used, the entire stack is available for application use.
2.4 – Program and Data Memory Mapping and Access
The memory on the DS4830 is implemented using a Harvard architecture, with separate busses for program and data
memory. The Memory Management Unit (MMU) allows the DS4830 to also support a pseudo-Von Neumann memory
map. The pseudo Von Neumann memory map allows each of the memory segments (flash, SRAM, and utility ROM) to
be logically mapped into a single contiguous memory map. This allows all of the memory segments to be accessed as
both program and memory data. The advantages the pseudo-Von Neumann memory map provides are:
Program execution can occur from the flash, SRAM, or utility ROM memory segments
The SRAM and flash memory segments can both be used for data memory.
Using the pseudo-Von Neumann memory map does have one restriction. This restriction is that a particular memory
segment cannot be simultaneously accessed as both program and data memory.
2.4.1 – Program Memory Access
The instructions that the DS4830 is executing reside in what is defined as the program memory. The MMU fetches the
instructions using the program bus. The Instruction Pointer (IP) register designates the program memory address of the
next instruction to fetch. The Instruction Pointer is read/write accessible by the user software. A write to the Instruction
Pointer will force program flow to the new address on the next cycle following the write. The content of the Instruction
Pointer will be incremented by 1 automatically after each fetch operation. From an implementation perspective, system
interrupts and branching instructions simply change the contents of the Instruction Pointer and force the op code to fetch
from a new program location.
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DS4830 User’s Guide
2.4.2 – Program Memory Mapping
The DS4830’s mapping of the three memory segments (flash, SRAM, and utility ROM) as program memory is shown in
Figure 2-2. The mapping of memory segments into program space is always the same. When referring to memory as
program memory, all addresses are given as word addresses. The 32KWord flash memory segment is located at
memory location 0000h through 7FFFh and is logically divided into two pages, each containing 16KWords. The utility
ROM is located from location 8000h through 8FFFh, followed by the SRAM memory segment at location A000h through
A3FFh. The user code reset vector, which is the first instruction of user program code that is executed, is located at flash
memory address 0000h. User program code should always begin at this address.
Figure 2-2: Program Memory Mapping
2.4.3 – Data Memory Access
Data memory mapping and access control are handled by the memory management unit (MMU). Read/write access to
data memory can be in word or in byte mode. The DS4830 provides three pointers that can be used for indirect
accessing of data memory. The DS4830 has two data pointers (@DPn) and one frame pointer (@BP[OFFS]). These
pointers are implemented as registers that can be directly accessed by user software. A data memory access requires
only one system clock period.
2.4.3.1 – Data Pointers
To access data memory, the data pointers are used as one of the operands in a MOVE instruction. If the data pointer is
used as a source, the core performs a load operation that reads data from the memory location addressed by the data
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DS4830 User’s Guide
CDA0
Selected Page in Byte Mode
Selected Page in Word Mode
0
P0
P0 and P1
1
P1
P0 and P1
pointer. If the data pointer is used as destination, the core performs a store operation that writes data to the memory
location addressed by the data pointer. Following are some examples of setting and using a data pointer.
move DP[0], #0100h ; set pointer DP[0] to address 100h
move Acc, @DP[0] ; read data from location 100h
move @DP[0], Acc ; write to location 100h
The address pointed to by the data pointers can be automatically incremented or decremented. If the data pointer is used
as a source, the pointer can be incremented or decremented after the data access. If the data pointer is used as a
destination, the increment or decrement can occur prior to the data access. Following are examples of using the data
pointers increment/decrement features.
move Acc, @DP[0]++ ; increment DP[0] after read
move Acc, @DP[1]-- ; decrement DP[1] after read
move @++DP[0], Acc ; increment DP[0] before write
move @--DP[1], Acc ; decrement DP[0] before write
2.4.3.2 – Frame Pointer
The frame pointer (BP[OFFS]) is formed by the 16-bit unsigned addition of the 16-bit Frame Pointer Base Register (BP)
and the 8-bit Frame Pointer Offset Register (OFFS). The method the DS4830 uses to access data using the frame
pointer is similar to the data pointers. When increments or decrements are used, only the value of OFFS is incremented
or decremented. The base pointer (BP) will remain unaffected by increments or decrements of the OFFS register,
including when the OFFS register rolls over from FFh to 00h or from 00h to FFh. Following are examples of how to use
the frame pointer.
move BP, #0100h ; set base pointer to address 100h
move OFFS, #10h ; set the offset to 10h,
move Acc, @BP[OFFS] ; read data from location 0110h
move @BP[OFFS], Acc ; write data to location 0110h
move Acc, @BP[OFFS++] ; increment OFFS after read
move Acc, @BP[OFFS++] ; decrement OFFS after read
move @BP[++OFFS], Acc ; increment OFFS before write
move @BP[--OFFS], Acc ; decrement OFFS before write
2.4.4 – Data Memory Mapping
The DS4830’s pseudo-Von Neumann memory map allows the MMU to read data from each of the three memory
segments (flash, SRAM, utility ROM). The MMU can also write data directly to the SRAM memory segment. Data
memory can be written to the flash memory segment, but because writing to flash requires the use of the utility ROM
routines, this is not a direct access. The logical mapping of the three memory segments as data memory varies
depending upon:
which memory segment instructions are currently being executed from
if data memory is being accessed in word or byte mode
In all cases, whichever memory segment is currently being used as program memory cannot be accessed as data
memory.
When the program is currently executing instructions from either the SRAM or utility ROM memory segments, the flash
memory will be mapped to half of the data memory space. If word access mode is selected, both pages (32KWords) can
be logically mapped to data memory space. If byte access mode is selected, only one page (32KBytes) can be logically
mapped to half of the data memory space. When operating in byte access mode, the selection of which flash page is
mapped into data memory space is determined by the Code Data Access bit (CDA0):
The next three sections detail the mapping of the different memory segments as data memory depending upon which
memory segment instructions are currently being executed from.
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DS4830 User’s Guide
2.4.4.1 – Memory Map When Executing from Flash Memory
When executing from the flash memory:
Read and write operations of SRAM memory are executed normally.
The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written.
Figure 2-3 illustrates the mapping of the SRAM and utility ROM memory segments into data memory space when code is
executing from the flash memory segment.
Figure 2-3: Memory Map When Executing from Flash Memory
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DS4830 User’s Guide
2.4.4.2 – Memory Map When Executing from Utility ROM
When executing from the utility ROM:
Read and write operations of SRAM memory are executed normally.
Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM
routines.
One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data
with an offset of 8000h as determined by the CDA0 bit.
Figure 2-4 illustrates the mapping of the SRAM and flash memory segments into data memory space when code is
executing from the utility ROM memory segment.
Figure 2-4: Memory Map When Executing from Utility ROM
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DS4830 User’s Guide
2.4.4.3 – Memory Map When Executing from SRAM
When executing from the SRAM:
The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written.
Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM
routines.
One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data
with an offset of 0000h. For byte access mode, the page of flash accessed is determined by the CDA0 bit.
Figure 2-5 illustrates the mapping of the flash and utility ROM memory segments into data memory space when code is
executing from the SRAM memory segment.
Figure 2-5: Memory Map When Executing from SRAM
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DS4830 User’s Guide
2.5 – Data Alignment
To support merged program and data memory operation while maintaining efficient memory space usage, the data
memory must be able to support both byte and word mode accessing. Data is aligned in data memory as words, but the
effective data address is resolved to bytes. This data alignment allows program instruction fetching in words while
maintaining data accessibility at the byte level. It is important to realize that this accessibility requires strict word
alignment. All executable or data words must align to an even address in byte mode. Care must be taken when updating
a code segment as misalignment of words will likely result in loss of program execution control.
Memory will always be read as a complete word, whether for program fetch or data access. The program decoder always
uses a full 16-bit word. The data access can utilize a word or an individual byte. Data memory is organized as two bytewide memory banks with common word address decode but two 8-bit data buses. In byte mode, data pointer hardware
reads out the full word containing the selected byte using the effective data word address pointer (the least significant bit
of the byte data pointer is not initially used). Then, the least significant data pointer bit functions as the byte select that is
used to place the correct byte on the data bus. For write access, data pointer hardware addresses a particular word using
the effective data word address while the least significant bit selects the corresponding data bank for write. The contents
of the other byte are left unaffected.
2.6 – Reset Conditions
The DS4830 has several possible sources of reset.
Power-On/Brownout Reset
Watchdog Timer Reset
External Reset
Internal System Reset
Once a reset condition has completed or been removed, code execution begins at the beginning of utility ROM, which is
address 8000h. The utility ROM code interrogates the I2C_SPE, JTAG_SPE, and PWL bits to determine if bootloading is
necessary. If bootloading is not required, execution will jump to the user code reset vector, which is at flash memory
address 0000h.
The /RST\ pin is an output as well as an input. If a reset condition is generated by one of the DS4830’s internal reset
sources (brownout, watchdog timer, or internal reset), an output reset pulse is generated on the /RST\ pin while the
DS4830 remains in reset.
2.6.1 – Power-On/Brownout Reset
The DS4830 provides a power-on reset (POR) circuit to ensure proper initialization of internal device states and analog
circuits. The POR voltage threshold range is between approximately 1.1V and 1.7V. When VDD is below the POR level,
the state of all the DS4830 pins, including /RST\, is weak pull up.
The DS4830 also includes brownout detection capability. This is an on-chip precision reference and comparator that
monitors the supply voltage, VDD, to ensure that it is within acceptable limits. If VDD is below the brownout level (VBO), the
power monitor generates a reset. This can occur when:
The DS4830 is being powered up and VDD is above the POR level but still less than VBO.
VDD drops from an acceptable level to less than VBO.
Once VDD exceeds VBO, the DS4830 exits the reset condition and the internal oscillator starts up. After approximately 1ms
(t
The transition between POR, Brownout, and normal operation is detailed in Figure 2-6: DS4830 State Diagram.
Note: If VDD is below VBO, there is a chance that the SRAM was corrupted. If the POR flag in WDCN is set, all data in
SRAM should be re-initialized.
) the DS4830 performs the following tasks.
SU:MOSC
All registers and circuits enter their reset state
The POR flag in the Watchdog Control Register is set to indicate the source of the reset
The DS4830 begins normal operation (CPU State)
Code execution begins at utility ROM location 8000h
20
BROWNOUT STATE
CPU DISABLED
ANALOG ACTIVE
SYSTEM CLOCK
STARTUP DELAY
CPU MODE
DIGITAL CORE ON
ANALOG ON
CODE EXECUTION
VDD > V
BO
VDD < VBO
POR
VDD < VBO
DS4830 User’s Guide
Figure 2-6: DS4830 State Diagram
2.6.2 – Watchdog Timer Reset
The watchdog timer is a programmable hardware timer that can be used to reset the processor in case a software lockup
or other unrecoverable error occurs. Once the watchdog is enabled, software must reset the watchdog timer periodically.
If the processor does not reset the watchdog timer before it elapses, the watchdog can initiate a reset.
If the watchdog resets the processor, the DS4830 will remain in reset and hold the /RST\ pin low for 12 clock cycles.
When a reset occurs due to a watchdog timeout, the Watchdog Timer Reset Flag (WTRF) in the WDCN register is set to
indicate the source of the reset.
2.6.3 – External Reset
During normal operation, the DS4830 is placed into external reset when the /RST\ pin is held at logic 0 for at least four
clock cycles. Once the DS4830 enters reset mode, it remains in reset as long as the /RST\ pin is held at logic 0. After the
/RST\ pin returns to logic 1, the processor exits reset within 12 clock cycles.
An external reset pulse on the /RST\ pin will reset the DS4830 and return to normal CPU mode operation within 10 clock
cycles.
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DS4830 User’s Guide
2.6.4 – Internal System Resets
There are two possible sources of internal system resets. An internal reset will hold the DS4830 in reset mode for 12
clock cycles.
1. When data BBh is written to the special I2C slave address 34h.
2. When in-system programming is complete and the ROD bit is set to 1.
2.7 – Clock Generation
The DS4830 generates its 20MHz peripheral clock using an internal oscillator and generates 10MHz instruction clock by
divide 2.This oscillator will startup when VDD exceeds the brownout voltage level, VBO. There is a delay of approximately
1msec between when the oscillator starts and when clocking of the DS4830 begins. This delay ensures that the clock is
stable prior to beginning normal operation.
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DS4830 User’s Guide
REGISTER
INDEX
REGISTER MODULE
AP (8h)
A (9h)
PFX (Bh)
IP (Ch)
SP (Dh)
DPC (Eh)
DP (Fh)
00h
AP
A[0]
PFX[0]
IP 01h
APC
A[1]
PFX[1]
SP
02h A[2]
PFX[2]
IV
03h A[3]
PFX[3]
OFFS
DP[0]
04h
PSF
A[4]
PFX[4]
DPC
05h
IC
A[5]
PFX[5]
GR
06h
IMR
A[6]
PFX[6]
LC[0]
GRL
07h
A[7]
PFX[7]
LC[1]
BP
DP[1]
08h
SC
A[8] GRS
09h
A[9] GRH
0Ah
A[10] GRXL
0Bh
IIR
A[11] FP
0Ch
A[12] 0Dh
A[13] 0Eh
A[14] 0Fh
WDCN
A[15]
SECTION 3 – SYSTEM REGISTER DESCRIPTIONS
Most functions of the DS4830 are controlled by sets of registers. These registers provide a working space for memory
operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major
types: system registers and peripheral registers. The common register set, also known as the system registers, includes
ALU access and control registers, accumulator registers, data pointers, interrupt vectors and control, and stack pointer.
The peripheral registers define additional functionality and the functionality is broken up into discrete modules.
This section describes the DS4830’s system registers. Table 3-1 shows the DS4830 system register map. Table 3-2
explains system register bit functions. This is followed by a detailed bit description.
Table 3-1. System Register Map
23
REGISTER
REGISTER BIT NUMBER
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
AP
— — — —
AP (4 bits)
APC
CLR
IDS
— — —
MOD2
MOD1
MOD0
PSF
Z S — GPF1
GPF0
OV C E
IC
—
— — — — —
INS
IGE
IMR
IMS — IM5
IM4
IM3
IM2
IM1
IM0
SC
TAP
—
—
CDA0
—
ROD
PWL
—
IIR
IIS — II5
II4
II3
II2
II1
II0
WDCN
POR
EWDI
WD1
WD0
WDIF
WTRF
EWT
RWT
A[n] (n=15:0)
A[n] (16 bits)
PFX[n] (n=7:0)
PFX[n] (16 bits)
IP
IP (16 bits)
SP
— — — — — — — — — — — — SP (4 bits)
IV
IV (16 bits)
LC[0]
LC[0] (16 bits)
LC[1]
LC[1] (16 bits)
OFFS
OFFS (8 bits)
DPC
— — — — — — — — — — —
WBS2
WBS1
WBS0
SDPS1
SDPS0
GR
GR (16 bits)
GRL
GRL (8 bits)
BP
BP (16 bits)
GRS
GRS (16 bits) = (GRL : GRH)
GRH
GRH (8 bits)
GRXL
GRXL (16 bits) = (GRL.7, 8 bits) : (GRL, 8 bits)
FP
FP = BP[OFFS] (16 bits)
DP[0]
DP[0] (16 bits)
DP[1]
DP[1] (16 bits)
Table 3-2. System Register Bit Functions
DS4830 User’s Guide
24
Bit
Name
Function
7:4
Reserved
Reserved. All reads return 0.
3:0
AP[3:0]
Active Accumulator Select. These bits select which of the 16 accumulator registers are used for arithmetic and logical
operations. If the APC register has been set to perform automatic increment/decrement of the active accumulator, this setting
will be automatically changed after each arithmetic or logical operation. If a ‘MOVE AP, Acc’ instruction is executed, any enabled
AP inc/dec/modulo control will take precedence over the transfer of Acc data into AP.
Bit
Name
Function
7
CLR
AP Clear. Writing this bit to 1 clears the accumulator pointer AP to 0. Once set, this bit will automatically be reset to 0 by
hardware. If a ‘MOVE APC, Acc’ instruction is executed requesting that AP be set to 0 (i.e., CLR = 1), the AP clear function
overrides any enabled inc/dec/modulo control. All reads from this bit return 0.
6
IDS
Increment/Decrement Select. If this bit is set to 0, the accumulator pointer AP is incremented following each arithmetic or logical
operation according to MOD[2:0]. If this bit is set to 1, the accumulator pointer AP is decremented following each arithmetic or
logical operation according to MOD[2:0]. If MOD[2:0] is set to 000, the setting of this bit is ignored.
5:3
Reserved
Reserved. All reads return 0.
2:0
MOD[2:0]
Accumulator Pointer Auto Increment/Decrement Modulus. If these bits are set to a nonzero value, the accumulator pointer
(AP[3:0]) will be automatically incremented or decremented following each arithmetic or logical operation. The mode for the
auto-increment/ decrement is determined as follows:
MOD[2:0]
AUTO INCREMENT/DECREMENT MODE
000
No auto-increment/decrement (default)
001
Increment/decrement AP[0] modulo 2
010
Increment/decrement AP[1:0] modulo 4
011
Increment/decrement AP[2:0] modulo 8
100
Increment/decrement AP modulo 16
101 to 111
Reserved (modulo 16 when set)
Bit
Name
Function
7
Z
Zero Flag. The value of this bit flag equals 1 whenever the active accumulator is equal to zero. This bit equals 0 if the active
accumulator is not equal to 0.
6 S Sign Flag. This bit flag mirrors the current value of the high bit of the active accumulator (Acc.15).
5
Reserved
Reserved. All reads return 0.
4:3
GPF[1:0]
General-Purpose Flags. These general-purpose flag bits are provided for user software control.
2
OV
Overflow Flag. This flag is set to 1 if there is a carry out of bit 14 but not out of bit 15, or a carry out of bit 15 but not out of bit 14
from the last arithmetic operation, otherwise, the OV flag remains as 0. OV indicates a negative number resulted as the sum of
two positive operands, or a positive sum resulted from two negative operands.
1
C
Carry Flag. This bit flag is set to 1 whenever an add or subtract operation (ADD, ADDC, SUB, SUBB) returns a carry or borrow.
This bit flag is cleared to 0 whenever an add or subtract operation does not return a carry or borrow. Many other instructions
potentially affect the carry bit. Reference the instruction set documentation for details.
0
E
Equals Flag. This bit flag is set to 1 whenever a compare operation (CMP) returns an equal result. If a CMP operation returns not
equal, this bit is cleared.
Bit
Name
Function
7:2
Reserved
Reserved. All reads return 0.
1
INS
Interrupt In Service. The INS is set by hardware automatically when an interrupt is acknowledged. No further interrupts occur as
long as the INS remains set. The interrupt service routine can clear the INS bit to allow interrupt nesting. Otherwise, the INS bit is
cleared by hardware upon execution of an RETI or POPI instruction.
0
IGE
Interrupt Global Enable. If this bit is set to 1, interrupts are globally enabled, but still must be locally enabled to occur. If this bit is
set to 0, all interrupts are disabled.
3.1 Accumulator Pointer Register (AP, 8h[0h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.2 Accumulator Pointer Control Register (APC, 8h[1h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.3 Processor Status Flags Register (PSF, 8h[4h])
Initialization: This register is cleared to 80h on all forms of reset.
Access: Bit 7 (Z), bit 6 (S), and bit 2 (OV) are read only. Bits [4:3] (GPF[1:0]), bit 1 (C), and bit 0 (E) are unrestricted
read/write.
3.4 Interrupt and Control Register (IC, 8h[5h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
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DS4830 User’s Guide
Bit
Name
Function
7
IMS
Interrupt Mask for System Modules
6
Reserved
Reserved. All reads return 0.
5
IM5
Interrupt Mask for Register Module 5
4
IM4
Interrupt Mask for Register Module 4
3
IM3
Interrupt Mask for Register Module 3
2
IM2
Interrupt Mask for Register Module 2
1
IM1
Interrupt Mask for Register Module 1
0
IM0
Interrupt Mask for Register Module 0
Bit
Name
Function
7
TAP
Test Access Port (JTAG) Enable. This bit controls whether the Test Access Port special-function pins are enabled. The TAP
defaults to being enabled. Clearing this bit to 0 disables the TAP special function pins.
6:5
Reserved
Reserved. All reads return 0.
4
CDA0
Code Data Access Bit 0.
The CDA0 bit is used to logically map the flash memory pages to the data space for read/write access. The logical data memory
addresses of the flash depend on whether execution is from Utility ROM or SRAM. The CDA0 bit is not needed if data memory is
accessed in word mode.
CDA0
Byte Mode Active Page
Word Mode Active Page
0
P0
P0 and P1
1
P1
P0 and P1
3
Reserved
Reserved. All reads return 0.
2
ROD
ROM Operation Done. This bit is used to signify completion of a ROM operation sequence to the control units. This allows the
Debug engine to determine the status of a ROM sequence. Setting this bit to logic 1 causes an internal system reset if the JTAG
SPE bit is also set. Setting the ROD bit will clear the JTAG SPE and I2C_SPE bits if set. The ROD bit will be automatically
cleared by hardware once the control unit acknowledges the done indication.
1
PWL
Password Lock. This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte password to be matched with
the password in the program space before allowing access to the password protected in-circuit debug or bootstrap loader ROM
routines. Clearing this bit to 0 disables the password protection for these ROM routines.
0
Reserved
Reserved. All reads return 0.
Bit
Name
Function
7
IIS
Interrupt Identifier Flag for System Modules
6
Reserved
Reserved. All reads return 0.
5
II5
Interrupt Identifier Flag for Register Module 5
4
II4
Interrupt Identifier Flag for Register Module 4
3
II3
Interrupt Identifier Flag for Register Module 3
2
II2
Interrupt Identifier Flag for Register Module 2
1
II1
Interrupt Identifier Flag for Register Module 1
0
II0
Interrupt Identifier Flag for Register Module 0
3.5 Interrupt Mask Register (IMR, 8h[6h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted read/write access.
The first six bits in this register are interrupt mask bits for modules 0 to 5, one bit per module. The eighth bit, IMS, serves
as a mask for any system module interrupt sources. Setting a mask bit allows the enabled interrupt sources for the
associated module or system (for the case of IMS) to generate interrupt requests. Clearing the mask bit effectively
disables all interrupt sources associated with that specific module or all system interrupt sources (for the case of IMS).
The interrupt mask register is intended to facilitate user-definable interrupt prioritization.
3.6 System Control Register (SC, 8h[8h])
Initialization: This register is reset to 1000 00s0b on all reset. Bit 1 (PWL) is set to 1 on a power-on reset only.
Access: Unrestricted read/write access.
3.7 Interrupt Identification Register (IIR, 8h[Bh])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Read only.
The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module. The eighth bit, IIS,
indicates a pending system interrupt, such as from the watchdog timer. The interrupt pending flags will be set only for
enabled interrupt sources waiting for service. The interrupt pending flag will be cleared when the pending interrupt
sources within that module are disabled or when the interrupt flags are cleared by software
26
DS4830 User’s Guide
BIT
NAME
DESCRIPTION
7
POR
Power-On Reset Flag: This bit is set to 1 whenever a power-on/brownout reset occurs. It is unaffected by other forms of reset.
This bit can be checked by software following a reset to determine if a power-on/brownout reset occurred. It should always be
cleared by software following a reset to ensure that the sources of following resets can be determined correctly.
6
EWDI
Enable Watchdog Timer Interrupt: If this bit is set to 1, an interrupt request can be generated when the WDIF bit is set to 1 by any
means. If this bit is cleared to 0, no interrupt will occur when WDIF is set to 1, however, it does not stop the watchdog timer or
prevent watchdog resets from occurring if EWT = 1. If EWT = 0 and EWDI = 0, the watchdog timer will be stopped. If the
watchdog timer is stopped (EWT = 0 and EWDI = 0), setting the EWDI bit will reset the watchdog interval and reset counter, and
enable the watchdog timer. This bit is cleared to 0 by power-on reset and is unaffected by other forms of reset.
5:4
WD[1:0]
Watchdog Timer Interval Control Bits: These bits determine the watchdog timeout interval. The timeout interval is set in terms of
system clocks. Modifying the watchdog interval will automatically reset the watchdog timer unless the 512 system clock reset
counter is already in progress, in which case, changing the WD[1:0] bits will not affect the watchdog timer or reset counter.
WD1
WD0
CLOCKS UNTIL INTERRUPT
CLOCKS UNTIL RESET
0
0
212
212 + 512
0
1
215
215 + 512
1
0
218
218 + 512
1
1
221
221 + 512
3
WDIF
Watchdog Interrupt Flag: This bit will be set to 1 when the watchdog timer interval has elapsed or can be set to 1 by user
software. When WDIF = 1, an interrupt request will occur if the watchdog interrupt has been enabled (EWDI = 1) and not
otherwise masked or prevented by an interrupt already in service (i.e., IGE = 1, IMS = 1, and INS = 0 must be true for the
interrupt to occur). This bit should be cleared by software before exiting the interrupt service routine to avoid repeated interrupts.
Furthermore, if the watchdog reset has been enabled (EWT = 1), a reset is scheduled to occur 512 system clock cycles following
setting of the WDIF bit.
2
WTRF
Watchdog Timer Reset Flag: This bit is set to 1 when the watchdog resets the processor. Software can check this bit following a
reset to determine if the watchdog was the source of the reset. Setting this bit to 1 in software will not cause a watchdog reset.
This bit is cleared by power-on reset only and is unaffected by other forms of reset. It should also be cleared by software
following any reset so that the source of the next reset can be correctly determined by software. This bit is only set to 1 when a
watchdog reset actually occurs. If EWT is cleared to 0 when the watchdog timer elapses, this bit will not be set.
1
EWT
Enable Watchdog Timer Reset: If this bit is set to 1 when the watchdog timer elapses, the watchdog resets the DS4830 512
system clock cycles later unless action is taken to disable the reset event. Clearing this bit to 0 prevents a watchdog reset from
occurring but does not stop the watchdog timer or prevent watchdog interrupts from occurring if EWDI = 1. If EWT = 0 and EWDI
= 0, the watchdog timer will be stopped. If the watchdog timer is stopped (EWT = 0 and EWDI = 0), setting the EWT bit will reset
the watchdog interval and reset counter, and enable the watchdog timer. This bit is cleared on power-on reset and is unaffected
by other forms of reset.
0
RWT
Reset Watchdog Timer: Setting this bit to 1 resets the watchdog timer count. If watchdog interrupt and/or reset modes are
enabled, the software must set this bit to 1 before the watchdog timer elapses to prevent an interrupt or reset from occurring.
This bit always returns 0 when read.
BIT
DESCRIPTION
A[n][15:0]
These registers (n=0 to 15) act as the accumulator for all ALU arithmetic and logical operations when selected by the
accumulator pointer (AP). They can also be used as a general-purpose working register.
3.8 Watchdog Control Register (WDCN, 8h[Fh])
Initialization: Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions.
Access: Unrestricted direct read/write access.
3.9 Accumulator n Register (A[n], 9h[nh])
Initialization: These registers are cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
27
BIT
NAME
DESCRIPTION
15:0
PFX[n][15:0]
The Prefix register provides a means of supplying an additional 8 bits of high-order data for use by the succeeding instruction
as well as providing additional indexing capabilities. This register will only hold any data written to it for one execution cycle,
after which it will revert to 0000h. Although this is a 16-bit register, only the lower 8 bits are actually used for prefixing purposes
by the next instruction. Writing to or reading from any index in the Prefix module will select the same 16-bit register. However,
when the Prefix register is written, the index n used for the PFX[n] write also determines the high-order bits for the register
source and destination specified in the following instruction.
The index selection reverts to 0 (default mode allowing selection of registers 0h to 7h for destinations) after one cycle in the
same manner as the contents of the Prefix register.
WRITE TO
SOURCE REGISTER
RANGE
DESTINATION REGISTER
RANGE
PFX[0]
0h to Fh
0h to 7h
PFX[1]
10h to 1Fh
0h to 7h
PFX[2]
0h to Fh
8h to Fh
PFX[3]
10h to 1Fh
8h to Fh
PFX[4]
0h to Fh
10h to 17h
PFX[5]
10h to 1Fh
10h to 17h
PFX[6]
0h to Fh
18h to 1Fh
PFX[7]
10h to 1Fh
18h to 1Fh
BIT
DESCRIPTION
15:0
This register contains the address of the next instruction to be executed and is automatically incremented by 1 after each
program fetch. Writing an address value to this register will cause program flow to jump to that address. Reading from this
register will not affect program flow.
BIT
DESCRIPTION
15:4
Reserved; all reads return 0.
3:0
These four bits indicate the current top of the hardware stack, from 0h to Fh. This pointer is incremented after a value is
pushed on the stack and decremented before a value is popped from the stack.
BIT
DESCRIPTION
15:0
This register contains the address of the interrupt service routine. The interrupt handler will generate a CALL to this address
whenever an interrupt is acknowledged.
BIT
DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[0], src operation. This operation decrements LC[0] by one and
then jumps to the address specified in the instruction by src if LC[0] = 0.
BIT
DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[1], src operation. This operation decrements LC[1] by one and
then jumps to the address specified in the instruction by src if LC[1] = 0.
3.10 Prefix Register (PFX[n], Bh[n])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.11 Instruction Pointer Register (IP, Ch[0h])
Initialization: This register is cleared to 8000h on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.12 Stack Pointer Register (SP, Dh[1h])
Initialization: This register is cleared to 000Fh on all forms of reset.
Access: Unrestricted direct read/write access.
3.13 Interrupt Vector Register (IV, Dh[2h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.14 Loop Counter 0 Register (LC[0], Dh[6h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.15 Loop Counter 1 Register (LC[1], Dh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
28
BIT
DESCRIPTION
7:0
This 8-bit register provides the Frame Pointer (FP) offset from the base pointer (BP). The Frame Pointer is formed by
unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset Register (Offs). The contents of this
register can be post-incremented or post-decremented when using the Frame Pointer for read operations and may be
pre-incremented or pre-decremented when using the Frame Pointer for write operations. A carry out or borrow resulting
from an increment/decrement operation has no effect on the Frame Pointer Base Register (BP).
BIT
NAME
DESCRIPTION
15:5
RESERVED
Reserved. All reads return 0.
4
WBS2
Word/Byte Select 2. This bit selects access mode for BP[Offs]. When WBS2 is set to logic 1, the BP[Offs] is operated in word
mode for data memory access; when WBS2 is cleared to logic 0, BP[Offs] is operated in byte mode for data memory access.
3
WBS1
Word/Byte Select 1. This bit selects access mode for DP[1]. When WBS1 is set to logic 1, the DP[1] is operated in word mode
for data memory access; when WBS1 is cleared to logic 0, DP[1] is operated in byte mode for data memory access.
2
WBS0
Word/Byte Select 0. This bit selects access mode for DP[0]. When WBS0 is set to logic 1, the DP[0] is operated in word mode
for data memory access; when WBS0 is cleared to logic 0, DP[0] is operated in byte mode for data memory access.
1:0
SDPS[1:0]
Source Data Pointer Select Bits[1:0]. These bits select one of the three data pointers as the active source pointer for the load
operation. A new data pointer must be selected before being used to read data memory:
SDPS1
SDPS0
SOURCE POINTER SELECTION
0
0
DP[0]
0
1
DP[1]
1
0
FP (BP[Offs])
1 1 Reserved (select FP if set)
These bits default to 00b but do not activate DP[0] as an active source pointer until the SDPS bits are explicitly cleared to 00b or
the DP[0] register is written by an instruction. Also, modifying the register contents of a data/frame pointer register (DP[0],
DP[1], BP or Offs) will change the setting of the SDPS bits to reflect the active source pointer selection.
BIT
DESCRIPTION
15:0
This register is intended primarily for supporting byte operations on 16-bit data. The 16-bit register is byte-readable, bytewriteable through the corresponding GRL and GRH 8-bit registers and byte-swappable through the GRS 16-bit register.
BIT
DESCRIPTION
7:0
This register reflects the low byte of the GR register and is intended primarily for supporting byte operations on 16-bit data.
Any data written to the GRL register will also be stored in the low byte of the GR register.
BIT
DESCRIPTION
15:0
This register serves as the base pointer for the Frame Pointer (FP). The Frame Pointer is formed by unsigned addition of
Frame Pointer Base Register (BP) and Frame Pointer Offset Register (Offs). The content of this base pointer register is not
affected by increment/decrement operations performed on the offset (OFFS) register.
BIT
DESCRIPTION
15:0
This register is intended primarily for supporting byte operations on 16-bit data. This 16-bit read only register returns the
byte-swapped value for the data contained in the GR register.
3.16 Frame Pointer Offset Register (OFFS, Eh[3h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.17 Data Pointer Control Register (DPC, Eh[4h])
Initialization: This register is cleared to 001Ch on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.18 General Register (GR, Eh[5h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.19 General Register Low Byte (GRL, Eh[6h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.20 Frame Pointer Base Register (BP, Eh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.21 General Register Byte-Swapped (GRS, Eh[8h])
Initialization: This register is cleared to 0000h on all forms of reset
Access: Unrestricted read-only access.
29
BIT
DESCRIPTION
7:0
This register reflects the high byte of the GR register and is intended primarily for supporting byte operations on 16-bit data.
Any data written to the GRH register will also be stored in the high byte of the GR register.
BIT
DESCRIPTION
15:0
This register provides the sign extended low byte of GR as a 16-bit source.
BIT
DESCRIPTION
15:0
This register provides the current value of the frame pointer (BP[Offs]).
BIT
DESCRIPTION
15:0
This register is used as a pointer to access data memory. DP[0] can be automatically incremented or decremented
following each read operation or can be automatically incremented or decremented before each write operation.
BIT
DESCRIPTION
15:0
This register is used as a pointer to access data memory. DP[1] can be automatically incremented or decremented
following each read operation or can be automatically incremented or decremented before each write operation.
3.22 General Register High Byte (GRH, Eh[9h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.23 General Register Sign Extended Low Byte (GRXL, Eh[Ah])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read-only access.
3.24 Frame Pointer Register (FP, Eh[Bh])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read-only access.
3.25 Data Pointer 0 Register (DP[0], Fh[3h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.26 Data Pointer 1 Register (DP[1], Fh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
30
Reg
M0
M1
M2
M3
M4
M5
0
PO2
I2CBUF-M
I2CBUF-S
MCNT
DACD0
QTDATA
1
PO1
I2CST-M
I2CST-S
MA
DACD1
QTCN
2
PO0
I2CIE-M
I2CIE-S
MB
DACD2
LTIF
3
EIF2
PO6
ADCN
MC2
DACD3
HTIF
4
EIF1
SPIB_S
DADDR
MC1
DACD4
SPIB_M
5
EIF0
MIIR1
SENR
MC0
DACD5
PWMDATA
6
GTV1
EIF6
ADST
GTV2
DACD6
PWMCN
7
GTCN1
EIE6
ADADDR
GTCN2
DACD7
PWMSYNC
8
PI2
PI6
MIIR2
MC1R
DACCFG
LTIE
9
PI1
SVM
ADDATA
MC0R HTIE
10
PI0 TWR
GTC2 QTLST
11
GTC1
TEMPCN
12 I2CCN-M
I2CCN-S
13
EIE2
I2CCK-M
I2CCK-S
14
EIE1
I2CTO-M
I2CTO-S
15
EIE0
I2CSLA-M
I2CSLA-S
16
PD2
EIES6
SHCN
17
PD1
PD6
18
PD0
SPICN_S
PINSEL
SPICN_M
19
EIES2
SPICF_S
SPICF_M
20
EIES1
SPICK_S
SPICK_M
21
EIES0
I2C_SPB
22 ETS
23 ADCG1
24 ADCG2
ICDT0
25 ADVOFF
ICDT1
26 TOEX
ICDC
27 ADCG3
ICDF 28 ADCG4
ICDB
29 CHIPREV
ICDA
30
ICDD
31
SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS
DS4830 User’s Guide
31
MODULE 0
Register
index
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
PO2
00h
PO2[7:0]
PO1
01h
PO1[7:0]
PO0
02h
PO0[7:0]
EIF2
03h
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
EIF1
04h
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
EIF0
05h
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
GTV1
06h
GTV1[15:0]
GTCN1
07h - - - GTR
MODE
CLK_SEL[1:0]
GTIE - - - GTIF - GTPS[2:0]
PI2
08h
PI2[7:0]
PI1
09h
PI1[7:0]
PI0
0Ah
PI0[7:0]
GTC1
0Bh
GTC1[15:0]
EIE2
0Dh
EX7
EX6
EX5
EX4
EX3
EX2
EX1
EX0
EIE1
0Eh
EX7
EX6
EX5
EX4
EX3
EX2
EX1
EX0
EIE0
0Fh
EX7
EX6
EX5
EX4
EX3
EX2
EX1
EX0
PD2
10h
PD2[7:0]
PD1
11h
PD1[7:0]
PD0
12h
PD0[7:0]
EIES2
13h
IT7
IT6
IT5
IT4
IT3
IT2
IT1
IT0
EIES1
14h
IT7
IT6
IT5
IT4
IT3
IT2
IT1
IT0
EIES0
15h
IT7
IT6
IT5
IT4
IT3
IT2
IT1
IT0
DS4830 User’s Guide
32
MODULE 1
Register
index
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
I2CBUF_M
00h
-
D[7:0]
I2CST_M
01h
I2CBUS
I2CBUSY - -
I2CSPI
I2CSCL
I2CROI
I2CGCI
I2CNACKI
-
I2CAMI
I2CTOI
I2CSTRI
I2CRXI
I2CTXI
I2CSRI
I2CIE_M
02h - - - -
I2CSPIE
-
I2CROIE
I2CGCIE
I2CNACKIE
-
I2CAMIE
I2CTOIE
I2CSTRIE
I2CRXIE
I2CTXIE
I2CSRIE
PO6
03h
-
PO6[6:0]
SPIB_S
04h
SPIB[15:0]
MIIR1
05h - - - - - SPI_S - I2CM
SVM
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
EIF6
06h - IE6
IE5
IE4
IE3
IE2
IE1
IE0
EIE6
07h - EX6
EX5
EX4
EX3
EX2
EX1
EX0
PI6
08h
-
PI6[6:0]
SVM
09h - - - -
SVMTH[3:0]
- - - - SVMI
SVMIE
SVMRDY
SVMEN
I2CCN_M
0Ch - - - - - SMB_MOD
I2CSTREN
I2CGCEN
I2CSTOP
I2CSTART
I2CACK
I2CSTRS - -
I2CMST
I2CEN
I2CCK_M
0Dh
I2CCKH[7:0]
I2CCKL[7:0]
I2CTO_M
0Eh
I2CTO[7:0]
I2CSLA_M
0Fh
-
SLAVE_ADDRESS[7:1]
I2CMODE
EIES6
10h - IT6
IT5
IT4
IT3
IT2
IT1
IT0
PD6
11h
-
PD6[6:0]
SPICN_S
12h
STBY
SPIC
ROVR
WCOL
MODF
MODFE
MSTM
SPIEN
SPICF_S
13h
ESPII
SAS - - - CHR
CKPHA
CKPOL
SPICK_S
14h
SPICK[7:0]
ETS
16h
-
EXTERNAL TEMP SLOPE [7:0]
ADCG1
17h
ADC VOLTAGE SCALE TRIM FOR GAIN1[13:0]
- - ADCG2
18h
ADC VOLTAGE SCALE TRIM FOR GAIN2[13:0]
-
-
ADVOFF
19h
ADC VOLTAGE OFFSET [15:0]
TOEX
1Ah
EXTERNAL TEMP OFFSET [15:0]
ADCG3
1Bh
ADC VOLTAGE SCALE TRIM FOR GAIN3[13:0]
- - ADCG4
1Ch
ADC VOLTAGE SCALE TRIM FOR GAIN4[13:0]
-
-
CHIPREV
1Dh
CHIPREV[15:0]
DS4830 User’s Guide
33
MODULE 2
Register
index
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
I2CBUF_S
00h
-
D[7:0]
I2CST_S
01h
I2CBUS
I2CBUSY - -
I2CSPI
I2CSCL
I2CROI
I2CGCI
I2CNACKI
-
I2CAMI
I2CTOI
I2CSTRI
I2CRXI
I2CTXI
I2CSRI
I2CIE_S
02h - - - -
I2CSPIE
-
I2CROIE
I2CGCIE
I2CNACKIE
-
I2CAMIE
I2CTOIE
I2CSTRIE
I2CRXIE
I2CTXIE
I2CSRIE
ADCN
03h
ADCCLK[2:0]
NUM_SMP[4:0]
ADDAINV
ADCONT
ADDAIE
LOC_OVR
ADACQ[3:0]
DADDR
04h
ADDR[6:0]
RWN
DATA[7:0]
SENR
05h - -
-
INT_TRIG_EN1
INT_TRIG1
-
-
INT_TRIG_EN0
INT_TRIG0
ADST
06h - - - SH1DAI
SH0DAI
EX1DAI
EX0DAI
INTDAI
ADDAI
ADCONV
ADCFG
ADIDX[4:0]
ADADDR
07h - -
-
ADSTART[4:0]
- - -
ADEND[4:0]
MIIR2
08h - - - - - -
I2CS
ADC
TW
ADDATA
09h
ADDATA[15:0], SEE ADC SECTION FOR DETAILS
TWR
0Ah
TWEN
TWCP[2:0]
TWIE
TWCSDIS
TWI
BUSY
TEMPCN
0Bh - - - - INT_IEN
EX0_IEN
EX1_IEN
-
EX1_ALIGN
EX0_ALIGN
INT_ALIGN
-
EX1_TEMP
EX0_TEMP
INT_TEMP
I2CCN_S
0Ch - - - - - SMB_MOD
I2CSTREN
I2CGCEN
I2CSTOP
I2CSTART
I2CACK
I2CSTRS - -
I2CMST
I2CEN
I2CCK_S
0Dh
I2CCKH[7:0]
I2CCKL[7:0]
I2CTO_S
0Eh
I2CTO[7:0]
I2CSLA_S
0Fh
-
SLAVE_ADDRESS[7:1]
I2CMODE
SHCN
10h
SSC[3:0]
FAST_MODE
PIN_DIS1
PIN_DIS0
SH_DUAL
-
SH1_ALGN
SHDAI1_EN
SMP_HLD1
CLK_SEL
SH0_ALGN
SHDAI0_EN
SMP_HLD0
PINSEL
12h
PINSEL[15:0]
I2C_SPB
15h - - - - - - - I2C_SPE
ICDT0
18h
ICDT0[15:0]
ICDT1
19h
ICDT1[15:0]
ICDC
1Ah
DME - REGE
-
CMD[3:0]
ICDF
1Bh - - - -
PSS1
PSS0
JTAG_SPE
TXC
ICDB
1Ch
ICDB[7:0]
ICDA
1Dh
ICDA[15:0]
ICDD
1Eh
ICDD[15:0]
DS4830 User’s Guide
34
MODULE 3
Register
index
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
MCNT
00h
OF
MCW
CLD
SQU
OPCS
MSUB
MMAC
SUS
MA
01h
MA[15:0]
MB
02h
MB[15:0]
MC2
03h
MC2[15:0]
MC1
04h
MC1[15:0]
MC0
05h
MC0[15:0]
GTV2
06h
GTV2[15:0]
GTCN2
07h - - - GTR
MODE
CLK_SEL[1:0]
GTIE - - - GTIF - GTPS[2:0]
MC1R
08h
MC1R[15:0]
MC0R
09h
MC0R[15:0]
GTC2
0Ah
GTC2[15:0]
MODULE 4
Register
index
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
DACD0
00h - - - -
DACD0[11:0]
DACD1
01h - - - -
DACD1[11:0]
DACD2
02h - - - -
DACD2[11:0]
DACD3
03h - - - -
DACD3[11:0]
DACD4
04h - - - -
DACD4[11:0]
DACD5
05h - - - -
DACD5[11:0]
DACD6
06h - - - -
DACD6[11:0]
DACD7
07h - - - -
DACD7[11:0]
DACCFG
08h
DACCFG7[1:0]
DACCFG6[1:0]
DACCFG5[1:0]
DACCFG4[1:0]
DACCFG3[1:0]
DACCFG2[1:0]
DACCFG1[1:0]
DACCFG0[1:0]
MODULE 5
Register
index
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
QTDATA
00h
QTDATA[15:0] SEE QUICK TRIP FOR DETAILS
QTCN
01h - - - QTEN - - - -
RW_LST - -
LTHT
QTIDX[3:0]
LTIF
02h
IF[15:0]
HTIF
03h
IF[15:0]
SPIB_M
04h
SPIB[15:0]
PWMDATA
05h
PWMDATA[15:0] SEE PWM SECTION FOR DETAILS
PWMCN
06h - - - M_EN - - - UPDATE
PWM_SEL[3:0]
- - REG_SEL[1:0]
PWMSYNC
07h - - - - - -
PWMSYNC[9:0]
LTIE
08h
IE[15:0]
HTIE
09h
IE[15:0]
QTLIST
0Ah - - - - - - - -
QTSTART[3:0]
QTEND[3:0]
SPICN_M
12h
STBY
SPIC
ROVR
WCOL
MODF
MODFE
MSTM
SPIEN
SPICF_M
13h
ESPII
SAS - - - CHR
CKPHA
CKPOL
SPICK_M
14h
SPICK[7:0]
DS4830 User’s Guide
35
DS4830 User’s Guide
System Module
WATCHDOG INTERRUPT
WDCN.WDIF
WDCN.EWDI
(local enable)
IMR.IMS
Module Enable
Module 0
GPIO INTERRUPTS
External Interrupt Pn.: EIFn.IEm
Local Enable EIEn.EXm
n can be 0,1 or 2 and m can be 0 to 7
TIMER1 INTERRUPT
Timer1 Flag GTIF
Timer Local Enable GTIE
IMR.IM0
Module0 Enable
IIR.IIS
IIR.II0
Module 3
IMR.IM3
Module3 Enable
IIR.II3
TIMER2 INTERRUPT
Timer Local Enable GTIE
External Interrupt P2.0: EIF2.IE0
Local Enable EIE2.EX0
Timer2 Flag GTIF
Module 1
External Interrupt P6.m: EIF6.IEm
Local Enable EIE6.EXm
m can be 0 to 6
PORT6 GPIO INTERRUPTS
Master I2C START Interrupt
I2CST_M.I2CSRI
Local Enable I2CIE_M.I2CSRIE
Any I2C Interrupt I2CST_M.x
Local Enable I2CIE_M.x
SVM Interrupt SVM.SVMI
Local Enable SVM.SVMIE
MASTER I2C INTERRUPTS
SVM INTERRUPT
Slave Interrupt SPICN_S.SPIC
Local Enable SPICF_S.ESPII
SPI Slave INTERRUPT
Module1 Enable
IIR.III1
JUMP TO
INTERRUPT
VECTOR
IC.INS
Interrupt is NOT
in Service
IC.IGE
Global Enable
IMR.IM1
SECTION 5 – INTERRUPTS
The DS4830 provides a single, programmable interrupt vector (IV) that can be used to handle internal and external
interrupts. Interrupts can be generated from system level sources (e.g., watchdog timer) or by sources associated with the
peripheral modules. Only one interrupt can be handled at a time, and all interrupts naturally have the same priority. A
programmable interrupt mask register allows software-controlled prioritization and nesting of high-priority interrupts.
Figure 5-1 shows a diagram of the interrupt hierarchy.
Figure 5-1: Interrupt Hierarchy
36
DS4830 User’s Guide
INTERRUPT
INTERRUPT FLAG
LOCAL ENABLE BIT
MODULE
INTERRUPT
IDENTIFICATIO
N BIT
INTERRUPT
IDENTIFICATION
BIT
MODULE
ENABLE
BIT
External Interrupt P2.0
EIF2.IE0
EIE2.EX0
-
IIR.II0
IMR.IM0
External Interrupt P2.1
EIF2.IE1
EIE2.EX1
-
External Interrupt P2.2
EIF2.IE2
EIE2.EX2
-
External Interrupt P2.3
EIF2.IE3
EIE2.EX3
-
External Interrupt P2.4
EIF2.IE4
EIE2.EX4
-
External Interrupt P2.5
EIF2.IE5
EIE2.EX5
-
External Interrupt P2.6
EIF2.IE6
EIE2.EX6
-
External Interrupt P2.7
EIF2.IE7
EIE2.EX7
-
External Interrupt P1.0
EIF1.IE0
EIE1.EX0
-
External Interrupt P1.1
EIF1.IE1
EIE1.EX1
-
External Interrupt P1.2
EIF1.IE2
EIE1.EX2
-
External Interrupt P1.3
EIF1.IE3
EIE1.EX3
-
External Interrupt P1.4
EIF1.IE4
EIE1.EX4
-
External Interrupt P1.5
EIF1.IE5
EIE1.EX5
-
External Interrupt P1.6
EIF1.IE6
EIE1.EX6
-
External Interrupt P1.7
EIF1.IE7
EIE1.EX7
-
External Interrupt P0.0
EIF0.IE0
EIE0.EX0
-
External Interrupt P0.1
EIF0.IE1
EIE0.EX1
-
External Interrupt P0.2
EIF0.IE2
EIE0.EX2
-
External Interrupt P0.3
EIF0.IE3
EIE0.EX3
-
External Interrupt P0.4
EIF0.IE4
EIE0.EX4
-
External Interrupt P0.5
EIF0.IE5
EIE0.EX5
-
External Interrupt P0.6
EIF0.IE6
EIE0.EX6
-
External Interrupt P0.7
EIF0.IE7
EIE0.EX7
-
Timer1 Interrupt
GTCN1.GTIF
GTCN1.GTIE
-
External Interrupt P6.0
EIF6.IE0
EIE6.EX0
MIIR1.P6_0
IIR.II1
IMR.IM1
External Interrupt P6.1
EIF6.IE1
EIE6.EX1
MIIR1.P6_1
External Interrupt P6.2
EIF6.IE2
EIE6.EX2
MIIR1.P6_2
External Interrupt P6.3
EIF6.IE3
EIE6.EX3
MIIR1.P6_3
External Interrupt P6.4
EIF6.IE4
EIE6.EX4
MIIR1.P6_4
External Interrupt P6.5
EIF6.IE5
EIE6.EX5
MIIR1.P6_5
External Interrupt P6.6
EIF6.IE6
EIE6.EX6
MIIR1.P6_6
Supply Voltage Monitor Interrupt
SVM.SVMI
SVM.SVMIE
MIIR1.SVM
I2C Master Start Interrupt
I2CST_M.I2CSRI
I2CIE_M.I2CSRIE
MIIR1.I2CM
I2C Master Transmit Complete Interrupt
I2CST_M.I2CTXI
I2CIE_M.I2CTXIE
I2C Master Receive Ready Interrupt
I2CST_M. I2CRXI
I2CIE_M.I2CRXIE
I2C Master Clock Stretch Interrupt
I2CST_M.I2CSTRI
I2CIE_M.I2CSTRIE
I2C Master Timeout Interrupt
I2CST_M.I2CTOI
I2CIE_M.I2CTOIE
I2C Master NACK Interrupt
I2CST_M.I2CNACKI
I2CIE_M.I2CNACKIE
I2C Master Receiver Overrun Interrupt
I2CST_M.I2CROI
I2CIE_M.I2CROIE
I2C Master Stop Interrupt
I2CST_M.I2CSPI
I2CIE_M.I2CSPIE
SPI Slave Transfer Complete
SPICN_S.SPIC
SPICF_S.ESPII
MIIR1.SPI_S
SPI Slave Write Collision
SPICN_S.WCOL
SPI Slave Receive Overrun
SPICN_S.ROVR
I2C Slave Stop Interrupt
I2CST_S.I2CSRI
I2CIE_S.I2CSRIE
MIIR2.I2CS
IIR.II2
IMR.IM2
Note: Some of the DS4830 module and peripheral interrupts sources are shown in the Figure 5-1 interrupt hierarchy
diagram. Please refer the corresponding sections of this user’s guide for more detailed information about all of the
possible interrupts.
5.1 – Servicing Interrupts
For the DS4830 to service an interrupt, interrupts must be enabled globally, modularly, and locally. The Interrupt Global
Enable (IGE) bit is located in the Interrupt Control (IC) register acts as a global interrupt mask. This bit defaults to 0, and it
must be set to 1 before any interrupt takes place.
The local interrupt-enable bit for a particular source is in one of the peripheral registers associated with that peripheral
module, or in a system register for any system interrupt source. Between the global and local enables are intermediate
per-module and system interrupt mask bits. These mask bits reside in the Interrupt Mask system register. By
implementing intermediate per-module masking capability in a single register, interrupt sources spanning multiple
modules can be selectively enabled/disabled in a single instruction. This promotes a simple, fast, and user-definable
interrupt prioritization scheme. The interrupt source-enable hierarchy is illustrated in Figure 5-1 as well as Table 5-1.
Table 5-1. Interrupt Sources and Control Bits
37
I2C Slave Transmit Complete Interrupt
I2CST_S.I2CTXI
I2CIE_S.I2CTXIE
I2C Slave Receive Ready Interrupt
I2CST_S. I2CRXI
I2CIE_S.I2CRXIE
I2C Slave Clock Stretch Interrupt
I2CST_S.I2CSTRI
I2CIE_S.I2CSTRIE
I2C Slave Timeout Interrupt
I2CST_S.I2CTOI
I2CIE_S.I2CTOIE
I2C Slave Address Match Interrupt
I2CST_S.I2CAMI
I2CIE_S.I2CAMIE
I2C Slave NACK Interrupt
I2CST_S.I2CNACKI
I2CIE_S.I2CNACKIE
I2C Slave General Call Interrupt
I2ST_S.I2CGCI
I2CIE_S.I2CGCIE
I2C Slave Receiver Overrun Interrupt
I2CST_S.I2CROI
I2CIE_S.I2CROIE
I2C Slave Stop Interrupt
I2CST_S.I2CSPI
I2CIE_S.I2CSPIE
ADC Data Available Interrupt
ADST.ADDAI
ADCN.ADDAIE
MIIR2.ADC
Internal Temperature Interrupt
ADST.INTADI
TEMPCN.INT_IEN
External Temperature 0 Interrupt
ADST.EX0ADI
TEMPCN.EX0_IEN
External Temperature 1 Interrupt
ADST.EX1ADI
TEMPCN.EX1_IEN
Sample and Hold 0 Interrupt
ADST.ADDAI
SHCN.SHDAI0_EN
Sample and Hold 1 Interrupt
ADST.ADDAI
SHCN.SHDAI1_EN
3 Wire Interrupt
TWR.TWI
TWR.TWIE
MIIR2.TW
Timer2 Interrupt
GTCN1.GTIF
GTCN1.GTIE
-
IIR.II3
IMR.IM3
LT 0 Interrupt
LTI.IF0
LTIE.IE0
-
IIR.II5
IMR.IM5
LT 1 Interrupt
LTI.IF1
LTIE.IE1
-
LT 2 Interrupt
LTI.IF2
LTIE.IE2
-
LT 3 Interrupt
LTI.IF3
LTIE.IE3
-
LT 4 Interrupt
LTI.IF4
LTIE.IE4
-
LT 5 Interrupt
LTI.IF5
LTIE.IE5
-
LT 6 Interrupt
LTI.IF6
LTIE.IE6
-
LT 7 Interrupt
LTI.IF7
LTIE.IE7
-
LT 8 Interrupt
LTI.IF8
LTIE.IE8
-
LT 9 Interrupt
LTI.IF9
LTIE.IE9
-
LT 10 Interrupt
LTI.IF10
LTIE.IE10
-
LT 11 Interrupt
LTI.IF11
LTIE.IE11
-
LT 12 Interrupt
LTI.IF12
LTIE.IE12
-
LT 13 Interrupt
LTI.IF13
LTIE.IE13
-
LT 14 Interrupt
LTI.IF14
LTIE.IE14
-
LT 15 Interrupt
LTI.IF15
LTIE.IE15
-
HT 0 Interrupt
HTI.IF0
HTIE.IE0
-
HT 1 Interrupt
HTI.IF1
HTIE.IE1
-
HT 2 Interrupt
HTI.IF2
HTIE.IE2
-
HT 3 Interrupt
HTI.IF3
HTIE.IE3
-
HT 4 Interrupt
HTI.IF4
HTIE.IE4
-
HT 5 Interrupt
HTI.IF5
HTIE.IE5
-
HT 6 Interrupt
HTI.IF6
HTIE.IE6
-
HT 7 Interrupt
HTI.IF7
HTIE.IE7
-
HT 8 Interrupt
HTI.IF8
HTIE.IE8
-
HT 9 Interrupt
HTI.IF9
HTIE.IE9
-
HT 10 Interrupt
HTI.IF10
HTIE.IE10
-
HT 11 Interrupt
HTI.IF11
HTIE.IE11
-
HT 12 Interrupt
HTI.IF12
HTIE.IE12
-
HT 13 Interrupt
HTI.IF13
HTIE.IE13
-
HT 14 Interrupt
HTI.IF14
HTIE.IE14
-
HT 15 Interrupt
HTI.IF15
HTIE.IE15
-
SPI Master Transfer Complete
SPICN_M.SPIC
SPICF_M.ESPII
-
SPI Master Write Collision
SPICN_M.WCOL
-
SPI Master Receive Overrun
SPICN_M.ROVR
-
SPI Master Mode Fault
SPICN_M.MODF
SPICN_M.MODFE
-
Watchdog Interrupt
WDCN.WDIF
WDCN.EWDI
N/A
IIR.IIS
IMR.IMS
DS4830 User’s Guide
When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or
global level. Interrupt flags must be cleared within the user interrupt routine to avoid repeated interrupts from the same
source.
Since all interrupts vector to the address contained in the Interrupt Vector (IV) register, the Interrupt Identification Register
(IIR) may be used by the interrupt service routine to determine the module source of an interrupt. The IIR contains a bit
flag for each peripheral module and one flag associated with all system interrupts; if the bit for a module is set, then an
interrupt is pending that was initiated by that module.
In the DS4830 MIIR registers are defined for module 1 and 2. In these modules the DS4830 provides two ways to
determine which block inside a module (for module 1 and 2 only) caused an interrupt to occur. Module 0 and 1 has
Module Interrupt Identification Registers (MIIR1 and MIIR2) that indicate which of the module’s interrupt sources has a
38
DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
SPI_S
Reserved
I2CM
SVM
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r r r r r r r r
r
BIT
NAME
DESCRIPTION
15:11
Reserved
Reserved. A read returns 0.
10
SPI_S
This bit is set when there is an interrupt at SPI Slave.
9
Reserved
Reserved. A read returns 0.
8
I2CM
This bit is set when there is an interrupt from the I2C master block. The I2C interrupt is a
combination of all interrupts defined in the I2CST_M register for the I2C master block. The
Master I2C section has more detail on the individual interrupts.
7
SVM
This bit is set when there is an interrupt from Supply Voltage Monitor (SVM).
6
P6_6
This bit is set when there is an External GPIO Interrupt at P6.6.
5
P6_5
This bit is set when there is an External Interrupt at P6_5.
4
P6_4
This bit is set when there is an External Interrupt at P6.4.
3
P6_3
This bit is set when there is an External Interrupt at P6.3.
2
P6_2
This bit is set when there is an External Interrupt at P6.2.
1
P6_1
This bit is set when there is an External Interrupt at P6.1.
0
P6_0
This bit is set when there is an External Interrupt at P6.0.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CS
ADC
TW
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r r r r r r r r
r
BIT
NAME
DESCRIPTION
15:3
Reserved
Reserved. A read returns 0.
2
I2CS
This bit is set when there is an interrupt from the I2C slave block. The I2C interrupt is a
combination of all interrupts defined in the I2CST_S register for the I2C slave block. The
Slave I2C section has more detail on the individual interrupts.
1
ADC
This bit is set when there is an Interrupt from the ADC.
0
TW
This bit is set when there is an interrupt from the 3Wire Block.
pending interrupt. The peripheral register bits inside the module also provide a way to differentiate among interrupt
sources. Section 5.2 has more detail on the Module Interrupt Identification Registers.
The Interrupt Vector (IV) register provides the location of the interrupt service routine. It may be set to any location within
program memory. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the
user program must determine whether a jump to 0000h came from a reset or interrupt source.
5.2 – Module Interrupt Identification Registers
The MIIR registers are implemented to indicate which particular function within a peripheral module has caused the
interrupt. The DS4830 has 6 peripheral modules, M0 through M5. MIIR registers are implemented in peripheral module 1
and 2. The MIIR registers are 16-bit read-only registers and all of them default to 0000h on system reset.
Each defined bit in an MIIR register is the final interrupt from a specific function, i.e., the interrupt enable bit(s) AND-ed
with the interrupt flag(s). A function can have multiple flags but they all are AND-ed with corresponding enable bits and
combined to create a single interrupt identification bit for that specific function. For example, the I2C master has several
interrupt sources; however, they all are combined to form a single identification bit, MIIR1.I2CM. The individual register bit
functions are defined as follows.
Peripheral Module 1 Interrupt Identification Register (MIIR1, M1[04h])
Peripheral Module 2 Interrupt Identification Register (MIIR2, M2[03h])
39
DS4830 User’s Guide
5.3 – Interrupt System Operation
The interrupt handler hardware responds to any interrupt event when it is enabled. An interrupt event occurs when an
interrupt flag is set. All interrupt requests are sampled at the rising edge of the clock and can be serviced by the processor
one clock cycle later, assuming the request does not hit the interrupt exception window. The one-cycle stall between
detection and acknowledgement/servicing is due to the fact that the current instruction may also be accessing the stack.
For this reason, the CPU must allow the current instruction to complete before pushing the stack and vectoring to IV. If an
interrupt exception window is generated by the currently executing instruction, the following instruction must be executed,
so the interrupt service routine will be delayed an additional cycle.
Interrupt operation in the DS4830 CPU is essentially a state machine generated long CALL instruction. When the interrupt
handler services an interrupt, it temporarily takes control of the CPU to perform the following sequence of actions:
1. The next instruction fetch from program memory is cancelled.
2. The return address is pushed on to the stack.
3. The INS bit is set to 1 to prevent recursive interrupt calls.
4. The instruction pointer is set to the location of the interrupt service routine (contained in the Interrupt Vector
register).
5. The CPU begins executing the interrupt service routine.
Once the interrupt service routine completes, it should use the RETI instruction to return to the main program. Execution
of RETI involves the following sequence of actions:
1. The return address is popped off the stack.
2. The INS bit is cleared to 0 to re-enable interrupt handling.
3. The instruction pointer is set to the return address that was popped off the stack.
4. The CPU continues execution of the main program.
Pending interrupt requests will not interrupt an RETI instruction; a new interrupt will be serviced after first being
acknowledged in the execution cycle which follows the RETI instruction and then after the standard one stall cycle of
interrupt latency. This means there will be at least two cycles between back-to-back interrupts.
5.3.1 – Synchronous vs. Asynchronous Interrupt Sources
Interrupt sources can be classified as either asynchronous or synchronous. All internal interrupts are synchronous
interrupts. An internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle. All external
interrupts are asynchronous interrupts by nature. When the device is not in stop mode, asynchronous interrupt sources
are passed through a 3-clock sampling/glitch filter circuit before being routed to the interrupt handler. The sampling/glitch
filter circuit is running on the system clock. An interrupt request with a pulse width less than three system clock cycles is
not recognized. Note that the granularity of interrupt source is at module level. Synchronous interrupts and sampled
asynchronous interrupts assigned to the same module produce a single interrupt to the interrupt handler.
5.3.2 – Interrupt Prioritization by Software
All interrupt sources of the DS4830 naturally have the same priority. However, when CPU operation vectors to the
programmed Interrupt Vector address, the order in which potential interrupt sources are interrogated is left entirely up to
the user, as this often depends upon the system design and application requirements. The Interrupt Mask system register
provides the ability to knowingly block interrupts from modules considered to be of lesser priority and manually re-enable
the interrupt servicing by the CPU (by setting INS = 0). Using this procedure, a given interrupt service routine can continue
executing, only to be interrupted by higher priority interrupts. An example demonstrating this software prioritization is
provided in the Handling Interrupts section of Section 19: Programming.
5.3.3 – Interrupt Exception Window
An interrupt exception window is a non interruptable execution cycle. During this cycle, the interrupt handler does not
respond to any interrupt requests. All interrupts that would normally be serviced during an interrupt exception window are
delayed until the next execution cycle.
Interrupt exception windows are used when two or more instructions must be executed consecutively without any delays
in between. Currently, there is a single condition in the DS4830 that causes an interrupt exception window: activation of
the prefix (PFX) register.
40
DS4830 User’s Guide
When the prefix register is activated by writing a value to it, it retains that value only for the next clock cycle. For the prefix
value to be used properly by the next instruction, the instruction that sets the prefix value and the instruction that uses it
must always be executed back to back. Therefore, writing to the PFX register causes an interrupt exception window on
the next cycle. If an interrupt occurs during an interrupt exception window, an additional latency of one cycle in the
interrupt handling will be caused as the interrupt will not be serviced until the next cycle.
41
DS4830 User’s Guide
12-Bit
Decoder
Data Bus
To DAC Switches
R
R
R
R
R
DAC Output
Internal
Reference
External
Reference
Ref Selection
4095
1
0
4094
4093
MUX
10b
01b
Output
Buffer
SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC)
The DS4830 contains eight 12-bit digital-to-analog converters (DACs). Each DAC has a voltage output buffer. Each DAC
can independently select between a 2.5V internal reference and external reference at REFINA pin for DAC0 to DAC3 and
at REFINB pin for DAC4 to DAC7.
Figure 6-1: DAC Functional Block Diagram
6.1 – Detailed Description
The DS4830 DAC architecture consists of a resistor string with switches and decoder followed by a voltage buffer. The
DS4830 has eight independent DACs, each having the same architecture. As shown in Figure 6-1, each DAC’s reference
is software selectable. Each DAC is independently configurable using the DAC configuration and DAC data registers. The
DAC configuration register (DACCFG) provides the facility to enable or disable DACs independently and select the
reference. Each DAC can be configured for either an internal (2.5V) or an external reference.
42
DS4830 User’s Guide
The DAC Data register programs the DAC for a particular voltage output depending on the value of this register and the
reference setting. The DAC outputs are voltage buffered and have the capability to sink or source current. Each DAC
output has an output impedance which limits the DAC operating range if configured to sink current (refer to the DS4830 IC
data sheet). The DAC output voltage is maintained during any type of reset except POR. All DACs, REFINA and REFINB
pins default to GPIO on reset.
6.1.1 – Reference Selection
Each DAC can be independently enabled with 2.5V internal reference or external reference. Each DAC has two bits in the
DAC configuration register (DACCFG) which are used to enable or disable the DAC with either an internal or an external
reference.
Any DAC can be enabled for using the internal reference by writing 10b at the corresponding location in the DACCFG
register. The internal reference automatically powers-down when none of the 8 DACs use it as a reference source.
The external reference at REFINA (Port2.6) is selected by writing 01b at the corresponding location in the DACCFG for
DAC0-3. The REFINA automatically becomes GPIO when none of the lower 4 DACs (DAC0 to DAC3) use REFINA as its
reference. The external reference at REFINB (Port1.4) is selected by writing 01b at the corresponding location in the
DACCFG register for DAC4-7. The REFINB pin automatically becomes GPIO when none of the upper 4 DACs (DAC4 to
DAC7) use REFINB as its reference.
6.1.2 – Requirement for Enabled DACs
If a DAC output will be used during the lifetime of the DS4830, the DAC must always be enabled to guarantee meeting the
INL and offset specifications in the DS4830 IC data sheet Electrical Characteristics table. This requirement can be met by
setting the DAC’s configuration bits (DACCFGx) to 01b or 10b at device power on. To disable a DAC that is being used,
the DAC must be set to either the reference voltage (DACDx = 0FFFh) or to 0V (DACDx = 0000h). If a pin will be used for
a DAC, it should be used only for the DAC function. The pin’s function should not be switched between DAC and PWM or
switched between DAC and GPIO.
6.2 – DAC Register Descriptions
The DAC module has total 9 SFR registers. These are DAC Configuration Register DACCFG and 8 DAC Data registers
DACDx (DACD0 to DACD7). The DACCFG configures all DACs and the data register DACDx (DACD0-DACD7) controls
the corresponding DAC output voltage. These SFR’s are located in module 4.
43
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
DACCFG7[1:0]
DACCFG6[1:0]
DACCFG5[1:0]
DACCFG4[1:0]
DACCFG3[1:0]
DACCFG2[1:0]
DACCFG1[1:0]
DACCFG0[1:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:8
DACCFG7[1:0]
DACCFG6[1:0]
DACCFG5[1:0]
DACCFG4[1:0]
DAC Configuration: These bits configure DAC7-4 and select the DAC reference for
DAC7-4 when the corresponding DAC is enabled.
DACCFGx[1:0]
DACx Control/Reference Select
00
DACx is Disabled and is in power down mode.
01
DACx is enabled and REFINB is selected as the external reference
10
DACx is enabled and the 2.5V Internal Reference is selected as the
DAC reference
11
Reserved. (User should not write this value+)
PIN 39 is REFINB (Port1.4).
7:0
DACCFG3[1:0]
DACCFG2[1:0]
DACCFG1[1:0]
DACCFG0[1:0]
DAC Configuration: These bits configure DAC3-0 and select the DAC reference for
DAC3-0 when DAC enabled.
DACCFGx[1:0]
DACx Control/Reference Select
00
DACx is Disabled and is in power down mode.
01
DACx is enabled and REFINA is selected as the external reference
10
DACx is enabled and the 2.5V Internal Reference is selected as the
DAC reference
11
Reserved. (User should not write this value+)
PIN 31 is REFINA (Port2.6).
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - -
-
DACDx[11:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:12
-
Reserved. The user should write zero to these bits.
11:0
DACDx*[11:0]
DACDx: These bits set the DACx output voltage according to reference selection and
reference value.
DACx Output voltage (in Volts) = (DAC Count / 4095) * Reference Voltage (in Volts)
6.2.1 – DAC Configuration Register (DACCFG)
Register Address: M4 [08h]
DS4830 User’s Guide
6.2.2 – DAC Data Registers (DACD0-DACD7)
DACD0 Register Address: M4 [00]
DACD1 Register Address: M4 [01]
DACD2 Register Address: M4 [02]
DACD3 Register Address: M4 [03]
DACD4 Register Address: M4 [04]
DACD5 Register Address: M4 [05]
DACD6 Register Address: M4 [06]
DACD7 Register Address: M4 [07]
* ‘x’ = 0 to 7
44
DS4830 User’s Guide
6.3 – DAC Code Examples
6.3.1 – DAC0 enabled with internal reference and output voltage is configured for 50% (1.25V) of internal
reference.
DACCFG = 0x0002; //Only DAC0 enabled and internal reference is selected
DACD0 = 0x0800; //DACD0 is set for 50%
6.3.2 – DAC2 enabled with external reference and output voltage is configured for 25% of external reference at
REFINA pin.
DACCFG = 0x0010; //Only DAC2 enabled and external reference is selected
DACD2 = 0x0400; //DACD2 is set for 25%
6.3.3 – DAC6 enabled with external reference and output voltage is configured for 25% of external reference at
REFINB pin.
DACCFG = 0x1000; //Only DAC6 enabled and external reference is selected
DACD6 = 0x0400; //DACD6 is set for 25%
45
DS4830 User’s Guide
13-BIT ADC CORE
ADC-S0
ADC-S1
ADC-S14
ADC-S15
A
N
A
L
O
G
M
U
X
VOLTAGE OFFSET
(ADVOFF)
TEMPERATURE
OFFSET (TOEX)
INTERNAL DIE TEMPERATURE
Current Source
For Temperature
Measurement
TEMPERATURE
SCALE (ETS)
ADC SEQUENCER
ADSTART
ADEND
ADCONV
ADCONT
ADCG1
ADCG4
ADGAIN
INTERNAL
REFERENCE
CONFIGURATION[0]
CONFIGURATION[19]
CONFIGURATION[1]
DATA BUFFER[0]
DATA BUFFER[24]
DATA BUFFER[1]
ADCFG=1
ADIDX[4:0]
ADCFG=0
ADIDX[4:0]
ADDATA
ADCG3
ADCG2
REFINA
REFINB
DAC INT REF
VDD
EXT1 DIODE
EXT0 DIODE
SH0
SH1
Internal Offset
NUM_SMP
CONFIGURATION[23]
Data buffer
Configuration / Data Buffer Selection
0-15
External Channels (0-15 in Single Ended or 0-7 in Differential)
16
REFINA
17
REFINB
18
VDD (Supply Voltage)
19
DAC Internal Reference
20
External Diode Temperature 1
21
External Diode Temperature 0
22
Internal Die Temperature
23
Sample and Hold 0
24
Sample and Hold 1
0-24 (Any)
ADC Internal Offset (with Location Override)
SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC)
The DS4830 provides a 13-bit analog-to-digital converter (ADC) with 26-input MUX. As shown in Figure 7-1, the MUX
selects the ADC input from 16 external channels, DAC external references at REFINA and REFINB, VDD, DAC Internal
Reference, Internal Die Temperature, External Remote Diode temperatures at GP8-GP9 and GP10-GP11, Sample and
Hold at GP2-GP3 and GP12-GP13 and ADC Internal Offset. The ADC external channels can operate in differential
voltage mode or in single-ended voltage mode. GP8-GP9 and GP10-GP11 channels can be configured to measure the
temperature of an external diode. An internal channel is used exclusively to measure the die temperature.
Figure 7-1: ADC Functional Block Diagram
7.1 – Detailed Description
7.1.1 – ADC Controller
The ADC controller is the digital interface block between CPU and the ADC. It provides all necessary controls to the ADC
and the CPU interface. The ADC controller provides 25 buffers (0-24) for various configurations and data buffers. By
default, the ADC conversion result is placed at the location shown in Table 7-1. The user can override the default buffers
and define alternate locations in the ADC Data and Configuration register (ADDATA) during configuration by settling the
LOC_OVR bit to ‘1’ in the ADC Control register (ADCN). The internal and remote diode temperature sensors and Sample
and Hold (S/H) use fixed data buffer locations. The ADC internal offset does not have any data buffer and its
measurement is performed with location override enable. Table 7-1 has the default configuration and data buffer
locations.
Table 7-1. ADC Configuration and Data buffers
46
DS4830 User’s Guide
ADCFG = 0
Data Buffer[0]
Data Buffer[23]
Data Buffer[1]
Data Buffer[24]
DATA BUFFERS
CONFIGURATION[0]
CONFIGURATION[22]
CONFIGURATION[1]
CONFIGURATION[23]
ADC CONFIGURATIONS
ADIDX[4:0]
ADCFG = 1 ADIDX[4:0]
By default, the external channels GP0-15 are general-purpose input. The DS4830 has the Pin Select Register (PINSEL).
The PINSEL register is used to configure the external channels as an analog pin for ADC or/and Quick Trip use. Each bit
location in this register corresponds to the ADC/Quick Trip input pin.
The ADC controller uses a set of Special Function Registers (SFRs) to configure the ADC for the desired mode of
operation. The DS4830 ADC can operate in the three modes mentioned below.
1. ADC Sequence Mode Conversions
2. Temperature Mode Conversions
3. Sample and Hold Mode Conversions
7.1.2 – ADC Conversion Sequencing
The ADC controller provides 24 ADC configuration registers. The DS4830 ADC controller performs a user defined
sequence for up to 16 single ended or 8 differential external voltage channels. Additionally, the ADC controller allows the
user to add the DAC external references (REFINA and REFINB), the DAC internal reference, and VDD to the sequence.
The configuration registers are accessed by writing to the ADDATA register when ADST.ADCFG = 1. Each conversion in
a sequence is setup using one of the ADC configuration registers. The results from the ADC converter are located in the
25 data buffers. These are accessed by reading from the ADDATA register when ADST.ADCFG = 0. See Figure 7-2 for
ADC configurations and data buffers.
Figure 7-2: ADC Configurations and Data Buffers
Note: With location override enabled, a single channel can be added multiple times as demonstrated in Example 7.3.2.
The configuration register pointed to by ADDATA is selected using the ADIDX bits in the ADST register when ADCFG = 1.
The individual configuration registers allows each of the conversions in a sequence to select from the following options.
ADC channel selection
Differential or single ended conversion
Full scale range
Extended acquisition enable
ADC conversion data alignment (left or right)
Alternate location
For more information, see the Configuration Register description for the ADDATA register.
A sequence is setup in the ADC Address register (ADADDR) by defining the starting conversion configuration address
(ADSTART) and an ending conversion configuration address (ADEND). The configuration start address designates the
configuration register to be used for the first conversion in a sequence. The configuration end address designates the
configuration register used for the last conversion in a sequence. A single channel conversion can be viewed as a special
47
DS4830 User’s Guide
case for sequence conversion, where the starting and ending configuration address is the same. The configuration
registers can be viewed as a circular register array where ADSTART does not have to be less than ADEND. For example,
if ADSTART = 1 and ADEND = 5, then the sequence of conversions would be configurations 1, 2, 3, 4, 5. If ADSTART =
5 and ADEND = 1, then the sequence of conversions would be configurations 5, 6, 7,…… 23 , 0, 1.
The ADC has two conversion sequence modes, single and continuous which are set by the ADCONT bit. When the start
conversion bit (ADCONV) is set to ‘1’, the ADC controller starts the ADC conversion sequence. In single sequence mode
(ADCONT=0), the ADCONV bit will remain set until the ADC has finished the conversion of the last channel in the
sequence. In continuous mode (ADCONT=1), the ADCONV bit remains set until the continuous mode is stopped. Writing
a ‘0’ to the ADCONV bit stops the ADC operation at the completion of the current ADC conversion. Writing a ‘1’ to the
ADCONV bit when ADCONV bit is already set to ‘1’ will be ignored by the ADC controller. The ADC should be used in the
continuous mode if temperature conversion or/and sample and hold are used with the ADC conversion sequence.
7.1.3 – Temperature Conversion
The DS4830 allows monitoring of internal die temperature and two external remote temperature measurements. These
temperature channels can be independently enabled by writing a ‘1’ to the corresponding bit location in the Temperature
Control register (TEMPCN). Each temperature sensor has a separate temperature conversion complete flag located in the
ADST register. Data buffer 22, 21 and 20 are reserved for the results of the internal die temperature sensor, external
remote temperature 0 and external remote temperature 1 respectively. The TEMPCN register has separate bits for
interrupt enable and data alignment bit for each temperature sensors.
A DS4830 temperature conversion provides 0.0625 °C of resolution. If temperature conversions are enabled
simultaneously with voltage conversions, the temperature conversions get time slots in between voltage conversions in a
sequence. See Figure 7-3, ADC Frame Sequence for more details. The result of a temperature conversion will always be
copied to their respective data buffers.
Each temperature conversion time is nominally 4.1msec at the lowest ADC Clock. The time required for the ADC to make
a temperature measurement is greater than the time required for a voltage measurement. When a temperature
conversion is performed, the ADC’s internal current source forces current into the diode connected to the channel. As the
current is being sourced, the ADC integrates the voltage across the diode. This is known as the integration time (t_int).
The integration time lasts approximately 2 ms. This integration time is a constant and does not scale when the ADC clock
speed is changed. When the integration time is complete, the ADC performs a voltage conversion of the integrated
voltage. The voltage conversion is a normal voltage conversion and will take 30 ADC clock cycles. A temperature
conversion requires that this integration and conversion process be performed twice. The extended acquisition time
function does not apply when in temperature sensing mode. The time required for a complete temperature conversion
can be calculated to be:
2 X (t_int + 30 ADC clocks)
The temperature integration time will be performed concurrently in the background if the ADC is running a sequence of
voltage conversions. The voltage sequence will only be interrupted when the integration time is complete and a
conversion of the integration needs to occur. By performing the integration in the background, the interruption to a voltage
sequence is minimized.
7.1.4 – Sample and Hold Conversion
The DS4830 has two Sample and Hold (S/H) inputs at pins GP2-GP3 and GP12-GP13. These can be independently
enabled or disabled by writing to their corresponding bit locations in the Sample and Hold Control register (SHCN). See
the Sample and Hold description in Section 8. The Sample and Hold uses data buffer 23 and 24 for S/H0 and S/H1
respectively. The Sample and Hold conversion complete flags are located in the ADST register. When enabled with
voltage conversions, the sample and hold conversions get time slots in between voltage conversions. See Figure 7-3,
ADC Frame Sequence for more details. The result of a sample and hold conversion will always be copied to their
respective data buffers.
7.1.5 – ADC Frame Sequence
When all modes (voltage, temperature, and sample and hold) are used simultaneously, the ADC controller uses time
slicing. The ADC controller uses the ADC sequence of voltage conversions as “primary channels” and other channels
(temperature sensors and sample and hold) as secondary channels. The time slicing rules are
1. The primary channels (ADC voltage channels) have priority over the secondary channels (Temperature sensors
or S/Hs).
2. Among secondary channels, temperature conversion has priority over the Sample and Hold.
48
DS4830 User’s Guide
CH0
Temp
Sample
1
CH4 S/H0 CH5 S/H1 CH6 S/H0 CH0 S/H1 CH4 ……..……..
One of the temperature
sensors & both S/H are ready
for conversion. Temperature
sensor gets priority as it
occurs after approx. 2ms.
Every alternate
channel is primary
channel
Both S/H0 & S/H1 are
ready. S/H0 gets
priority over S/H1
S/H1 gets chance
here even if S/H0
is ready.
Sequence
keeps
repeating
Temp
Sample
2
……..
SH0 or 1 if
triggered by
internal or
SHEN0/1l
Temperature Sample 1 and 2 conversions are ~2msec apart
3. S/H0 has priority over S/H1 if both S/Hs are ready for conversion. However, in next slot for S/H, the S/H1 will get
slot even if S/H0 is also ready.
For example, if the ADC sequence mode conversion is enabled for channel 0, 4, 5, 6 and all secondary channels are
enabled and ready for conversion then the sequence of conversion is performed as shown in figure 7-3
Figure 7-3: ADC Frame Sequence
1. Temperature channels can’t occur simultaneously in sequence as they share the same resources on chip.
2. Both Sample and Hold channels can occur simultaneously as they have dedicated resources.
7.1.6 – ADC Conversion Time
The ADC clock is derived from the system clock with divide ratio defined by the ADC Clock Divider Bits ADCCLK [2:0] in
the ADC Control register (ADCN). Each sample takes 15 ADC clock cycles to complete. Two of the 15 ADC clock cycles
are used for sample acquisition, and the remaining 13 clocks are used for data conversion. The ADC automatically reads
each measurement twice and outputs the average of the two readings. This makes the resulting time for one complete
conversion 30 ADC clock cycles. Additionally, 4 core clocks are used in data processing for each of the two readings.
Knowing this, it is possible to calculate the fastest ADC sample rate. The fastest ADC clock is:
ADC Clock = Core Clock / 8 = 10 MHz / 8 = 1250 kHz
One conversion requires 30 ADC Clocks + 8 Core Clocks
Conversion Time = (30 ADC Clocks Time+ 8 Core Clocks Time)
= 30 * 0.8 + 0.8s
Sample Rate = 40.3 ksps
= 24.8s per ADC Conversion
The ADC has an internal power management system that automatically shuts down the ADC when conversions are
complete by clearing ADCONV to 0. After being shut down, the ADC begins conversions again when the ADCONV bit is
set to 1 again. After ADCONV is set to 1, the ADC requires 20 ADCCLK cycles to setup and power up prior to beginning
the first conversion of the sequence. So the first ADC conversion time is ~40s at the fastest ADC Clock. If the quick trip
is also enabled and if the ADC controller and the quick trip are sampling the same channel, the ADC sampling is delayed
by two quick trip conversions (3.2s) to prevent collision.
In applications where extending the acquisition time is desired, the user can make use of the ADC Acquisition Extension
Bits (ADACQ[3:0] in the ADCN register). When the ADC Acquisition Extension is enabled (ADACQEN=1), the sample will
be acquired over a prolonged period during the sample acquisition. The extended acquisition time will be determined by
49
DS4830 User’s Guide
ADACQ[3:0]
# of Core
Clocks
Time (in s)
ADACQ[3:0]
# of Core
Clocks
Time (in s)
0 2 0.2 8 1032
103.2 1 6
0.6 9 2056
205.6 2 14
1.4
10
4104
410.4 3 30
3.0
11
8190
819.0 4 62
6.2
12
16382
1638.2
5
126
12.6
13
32766
3276.6
6
254
25.4
14
65534
6553.4
7
520
52.0
15
131070
13107
10 111 2 3 4 5 6 7 8 9 181615141312 28 2919 20 21 22 23 24 25 26 2717 30
...
1 19 20
ADACQ
SAMPLE 1 HOLD AND CONVERT SAMPLE 1 SAMPLE 2 HOLD AND CONVERT SAMPLE 2
ADC
STARTUP
ADC DATA
VALID
ADCCLK
ADCONV
ADDATA
Core Clock
delays
(ADACQ[3:0])
ADACQ[3:0]. Table 7-2 shows the extended acquisition time in terms of core clocks at different ADACQ[3:0] The total
acquisition time, ACQ, is two ADC clocks plus the Extended Acquisition Time (ADACQ, as listed in Table 7-2). Figure 7-4
shows the clocking required for one conversion.
Table 7-2. Extended Acquisition Time in Terms of Core Clock and Time (s)
Figure 7-4: Extended Acquisition Time
7.1.7 – Location Override
By default, the ADC controller stores ADC conversion results in the ADC buffer location corresponding to the channel
number (as defined in Table 7.1). The ADC controller allows the user to override the default data buffer location and store
the ADC result at any of the buffer location (0-24). The location override is enabled by setting the LOC_OVR bit to ‘1’ in
the ADCN register. The user has to define the alternate location for storing the ADC conversion result during ADC
configuration (when ADST.ADCFG = 1). The alternate location is defined by ADDATA[12:8] (ALT_LOC). Location override
is demonstrated in Example 7.3.2,
Note: If the location override is used with fixed addresses (as mentioned in 7.1.1), the corresponding peripheral should be
disabled. Example, if the buffer location 20 is used in the ADC sequence with the location override option, the external
remote temperature 1 should be disabled.
7.1.8 – ADC Data Reading
The ADC has a circular data buffer that can hold the results from 25 conversions. When the location override (LOC_OVR
= 0) is disabled, the ADC controller writes the ADC conversion result at the data buffer location corresponding to ADC
channel number, see Table 7-1. When location override is enabled, the ADC controller writes the result to the data buffer
50
DS4830 User’s Guide
ADDAINV
Set ADDAI after
0
End of Every Sequence (ADSTART to ADEND)
1
After End of Every Sequence (ADSTART to ADEND) and After
(NUM_SMP + 1) ADC Conversions
SAMPLE1 SAMPLE2 SAMPLE3 SAMPLE4 SAMPLE5 SAMPLE6 SAMPLE7 SAMPLE8 ……...
ADDAI Set
After
(NUM_SMP + 1)
ADC Samples
ADDAI Set
After END of
Sequence
4 ADC Samples 4 ADC Samples
ADDAI Set
After
(NUM_SMP + 1)
ADC Samples
ADC
SAMPLES
ADDAI
Flag
location configured in the ALT_LOC[4:0] bits in the ADDATA during ADC configuration (ADST.ADCFG = 1). This buffer is
accessed by reading the ADDATA register when ADCFG is set to 0. The data buffer pointed to by ADST.ADIDX [4:0] will
be the buffer returned when ADDATA is read. The ADIDX is automatically incremented following a read of ADDATA.
This allows repeated reads of ADDATA to return the results from multiple conversions. The ADC will continue writing to
the data buffer until the end of the buffer. Once the end of the data buffer is reached, the ADC index will rollover and write
to data buffer 0.
7.1.9 – ADC Interrupts
The ADC Data Available Ready ADDAI in the ADST register will be set when conversions are complete. This flag will
generate an interrupt if enabled by setting the ADCN.ADDAIE interrupt enable bit. The condition that causes the ADDAI
flag to be set can be selected using the ADCN.ADDAINV bit.
Table 7-3. ADC Interrupt Intervals
For example, if ADSTART = 0, ADEND = 6 and NUM_SMP = 3 with ADDAINV = 1, then ADDAI will be set to ‘1’ after
every (NUM_SMP + 1) ADC conversions and every End of Sequence. In the given example, ADDAI will be set after
4,7,8,12,14… ADC Samples. Interrupts after 4, 8 and 12 ADC Samples are because of (NUM_SMP+1) configurations and
interrupts after 7 and 14 are because of “End of Sequence”. Figure 7-5 demonstrates above ADC example sequence.
Figure 7-5: ADC Interrupt Intervals with NUM_SMP
The ADDAI flag is cleared by software by writing a ‘0’, or it will be automatically cleared when a new conversion sequence
is started by setting the ADCONV bit to a ‘1’.
Note: The ADC controller processes ADC, remote diode sensors and sample and holds conversions according to the
ADC frame sequence and sets the corresponding interrupt flags in the ADST register. The user should process and clear
the interrupt flag when it is set before another flag in the ADST is set by the ADC controller. Clearing interrupts in the
upper byte of the ADST register requires multiple clock cycles. While these interrupts are being cleared, it is possible that
there is a period of up to 3 clock cycles during which an interrupt can be missed due to the time required to clear these
interrupts.
.
7.1.10 – ADC Internal Offset
The DS4830 ADC controller allows the ADC internal offset measurement. The ADC controller does not have a dedicated
buffer for the internal offset so it can only be accessed with location override enabled. For measurement of ADC internal
offset, the ADC controller connects internal ground to the ADC input and starts conversion on the ADC. Using this feature,
software can calibrate the ADC internal offset.
Refer to Application Note 5321: Calibrating the ADC Internal Offset of the DS4830 Optical Microcontroller
51
DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 5 3 2 1 0
Name
ADCCLK[2:0]
NUM_SMP[4:0]
ADDAINV
ADCONT
ADDAIE
LOC_OVR
ADACQ[3:0]
Reset
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
BIT
NAME
DESCRIPTION
15:13
ADCCLK[2:0]
ADC Clock Divider. These bits select the ADC conversion clock in relationship to the
Core Clock.
ADCCLK[2:0]
ADC Clock
000
System Clock/8
001
System Clock/10
010
System Clock/12
011
System Clock/14
100
System Clock/16
101
System Clock/18
110
System Clock/20
111
System Clock/40
12:8
NUM_SMP[4:0]
Interrupt After Number of Sample. These bits define interrupt after Number of ADC
Samples and are used with ADDAINV. If ADDINV is set to ‘1’, then ADC Interrupt will
occur after (NUM_SMP + 1) ADC samples and End of Sequence.
7
ADDAINV
ADC Data Available Interrupt Interval. This bit selects the condition for setting data
available interrupt flag (ADDAI).
When ADDAINV = 0, ADDAI is set after End of Sequence.
When ADDAINV = 1, ADDAI is set after End of Sequence and after ADC Samples =
(NUM_SMP + 1).
6
ADCONT
ADC Continuous Sequence Mode. Setting this bit to ‘1’ will enable the continuous
sequence mode. Clearing this bit to ‘0’ will disable the continuous sequence mode. In
single sequence mode, the ADC conversion will stop after the end of the sequence. The
user should set this bit to ‘1’, when temperature and sample and hold are also enabled.
5
ADDAIE
ADC Data Available Interrupt Enable. Setting the ADDAIE bit to ‘1’ will enable an
interrupt to be generated when the ADDAI=1. Clearing this bit to ‘0’ will disable an interrupt
from generating when ADDAI=1.
4
LOC_OVR
Location override bit. Setting this bit to ‘1’ will enable the user to select an alternate
location for storing ADC conversion results. The alternate location is defined by
ADDATA[12:8] (ALT_LOC). By default, the ADC conversion results are stored in ADC
buffer location corresponding to channel number. Refer Table 7-1.
3:0
ADACQ[3:0]
ADC Acquisition Extension Bits [3:0]. These bits are used to extend sample acquisition
time if the corresponding ADC Acquisition Extension is enabled (ADDATA.ADACQEN =1
when ADST.ADCFG is set to ‘1’). See ADC Conversion Time Section for details. The ADC
acquisition extension should not be used when the fast comparator is used for the same
channel.
7.2 – ADC Register Descriptions
The ADC is controlled by ADC SFR registers. The PINSEL register is used to configure pins as analog pin for ADC use.
Four of the registers, ADST, ADADDR, ADCN, and ADDATA are used for setup, control, and reading from the ADC.
There are few other registers, ETS, ADCG1-4, ADVOFF, and TOEX, which are used to adjust the gains and offsets
applied to ADC results. To avoid undesired operations, the user should not write to bits labeled as “Reserved”.
7.2.1 – ADC Control Register (ADCN)
Register Address: M2[03h]
* Unrestricted read, but can only be written to when ADCONV = 0.
52
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - -
SH1DAI
SH0DAI
EX1DAI
EX0DAI
INTDAI
ADDAI
ADCONV
ADCFG
ADIDX[4:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:13
-
Reserved. The user should write 0 to these bits.
12
SH1DAI
Sample and Hold 1 Data Available Interrupt Flag. This bit is set to ‘1’ when Sample and
Hold is completed on GP12-GP13 in dual mode and data is ready at buffer location 24.
This flag will cause an interrupt if the SH1DAI_EN (SHCN.5) is set to ‘1’. This bit is cleared
by software writing a ‘0’.
11
SH0DAI
Sample and Hold 0 Data Available Interrupt Flag. This bit is set to ‘1’ when Sample and
Hold is completed on GP2-GP3 if only S/H0 is used or after completion of S/H1 conversion
on GP12-GP13 when both are used in single mode. The S/H0 and S/H1 data is ready at
buffer location 23 and 24 respectively. This flag will cause an interrupt if the SH0DAI_EN
(SHCN.1) is set to ‘1’. This bit is cleared by software writing a ‘0’.
10
EX1DAI
External Temperature 1 Data Available Interrupt Flag. This bit is set to ‘1’ when an
external temperature conversion on GP10-GP11 is complete and data is ready in buffer
location 20. This flag will cause an interrupt if the EX1_IEN (TEMPCN.8) is enabled. This
bit is cleared by software writing a ‘0’.
9
EX0DAI
External Temperature 0 Data Available Interrupt Flag. This bit is set to ‘1’ when an
external temperature conversion on GP8-GP9 is complete and data is ready in buffer
location 21. This flag will cause an interrupt if the EX0_IEN (TEMPCN.9) is enabled. This
bit is cleared by software writing a ‘0’.
8
INTDAI
Internal Temperature Data Available Interrupt Flag. This bit is set to ‘1’ when an internal
temperature conversion is complete and data is ready in buffer location 22. This flag will
cause an interrupt if the INT_IEN (TEMPCN.10) is enabled. This bit is cleared by software
writing a ‘0’.
7
ADDAI
ADC Data Available Interrupt Flag. This bit is set to ‘1’ when the condition matching
ADDAINV bit is met. This flag will cause an interrupt if the ADDAIE bit is set. This bit is
cleared by software writing a ‘0’ or when software changes ADCONV bit from '0' to ‘1’.
6
ADCONV
ADC Start Conversion. Setting this bit to ‘1’ starts the ADC conversion process. This bit
will remain set until the ADC conversion process is finished. In single sequence mode, this
bit will be cleared to ‘0’ when the ADC conversion sequence is finished. In continuous
sequence mode, this bit will remain set until the ADC conversion is stopped. To stop ADC
conversion at any time, write ‘0’ to this bit. The ADC will stop acquiring data after the
current conversion is finished or if the ADC is waiting during extended acquisition time, the
ADC will stop immediately.
5
ADCFG
ADC Conversion Configuration Register Select.
ADCFG = 0: The ADDATA register points to the data buffers. The ADIDX[4:0] bits
determine which data buffer is currently being accessed. When ADCFG=0, ADDATA is
read only.
ADCFG = 1: The ADDATA register points to the ADC sequence configuration registers.
The ADIDX[4:0] bits determine which configuration register is currently being accessed.
When ADCFG=1, ADDATA has read/write access.
4:0
ADIDX[4:0]
ADC Register Index Bits [4:0]. These bits together with ADCFG select the source /
destination for ADDATA access. When ADCFG=1, ADIDX [4:0] are used to address one of
24 configuration registers. When ADCFG=0, ADIDX [4:0] are used to select one of 25 data
buffers. This register value will be auto-incremented on successive access (read/write) of
ADDATA register.
7.2.2 – ADC Status Register (ADST)
Register Address: M2[06h]
DS4830 User’s Guide
53
DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
PINSEL.15
PINSEL.14
PINSEL.13
PINSEL.12
PINSEL.11
PINSEL.10
PINSEL.9
PINSEL.8
PINSEL.7
PINSEL.6
PINSEL.5
PINSEL.4
PINSEL.3
PINSEL.2
PINSEL.1
PINSEL.0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - -
ADSTART[4:0]
- - -
ADEND[4:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r
rw*
rw*
rw*
rw*
rw* r r r rw*
rw*
rw*
rw*
rw*
BIT
NAME
DESCRIPTION
15:13
-
Reserved. The user should write 0 to these bits.
12:8
ADSTART[4:0]
ADC Conversion Configuration Start Address Bits [4:0]. These bits select the first
conversion configuration register.
7:5
-
Reserved. The user should write 0 to these bits.
4:0
ADEND[4:0]
ADC Conversion Configuration Ending Address Bits [4:0]. These bits select the last
conversion configuration register. This register is inclusive when defining the sequence.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
-
ADGAIN[1:0]
ALT_LOC[4:0]
ADACQEN
ADALIGN
ADDIFF
ADCH[4:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
BIT
NAME
DESCRIPTION
15
-
Reserved. The user should write 0 to this bit.
14:13
ADGAIN[1:0]
ADC Gain Select. This bit selects the ADC scale factor.
ADGAIN[1:0]
ADC SCALE
Full Scale (typ)
00
ADCG1
1.2V
01
ADCG2
0.6V
10
ADCG3
2.4V
11
ADCG4
4.8*
* When the ADCG4 select, the ADC input should not be above 3.6V. It is limited by VDD
operating range.
12:8
ALT_LOC[4:0]
Alternate location for conversion result. These bits specify the alternate location for storing
the ADC conversion result when LOC_OVR bit in the ADCN register is set to ‘1’.
7
ADACQEN
ADC Acquisition Extension Enable. Setting this bit to ‘1’ will enable additional acquisition
time to be inserted prior to this conversion. Clearing this bit to ‘0’ will disable the extended
acquisition time.
7.2.3 – PIN Select Register (PINSEL)
Register Address: M2 [12h]
s = special, initial value is dependent on trim settings
Each bit location in this register corresponds to the ADC input pin. When these bits are set the corresponding pins are
dedicated for ADC use. On POR, the pin selection register is 0000h which corresponds to GP0 to GP15 being GPIO, or
PWMs. For using these pins as ADC input, Sample and Hold or External Remote Diode temperature input or Quick Trip
input the corresponding PINSEL bit should be set to ‘1’.
7.2.4 – ADC Address Register (ADADDR)
Register Address: M2 [07h]
* Unrestricted read, but can only be written to when ADCONV = 0.
7.2.5 – ADC Data and Configuration Register (ADDATA)
Register Address: M2 [09h]
The ADDATA register is used to setup the ADC sequence configurations and also to read the results of the ADC
conversions. If the ADST.ADCFG bit is set to a 1, writing to ADDATA will write to one of the configuration registers. If
ADST.ADCFG is set to 0, reading from ADDATA will read one of the conversion results.
7.2.5.1 – ADC Configuration Register (ADDATA when ADCFG = 1)
When ADCFG = 1, writing to the ADDATA register will write to one of the configuration registers. The configuration
register written to is selected by the ADIDX[4:0] bits. The ADIDX[4:0] bits will automatically increment after a write to
ADDATA. This allows consecutive writes of ADDATA to setup consecutive configuration registers. The configuration
registers will be reset to ‘0’ on all forms of reset.
* When ADCFG = 1, unrestricted read, but can only be written to when ADCONV = 0.
54
6
ADALIGN
ADC Data Alignment Select. This bit selects the ADC data alignment mode. Setting this bit to
‘1’ returns ADC data left aligned in ADDATA [15:2] with ADDATA[1:0] zero padded. Clearing
this bit to ‘0’ returns ADC data in right aligned format in ADDATA[13:0] with ADDATA[15:14]
sign-extended by ADDATA[13].
5
ADDIFF
ADC Differential Mode Select. This bit selects the ADC conversion mode. When this bit is set
to ‘1’, the ADC conversion is in differential mode. When this bit is cleared to ‘0’, the ADC
conversion is performed in single-ended mode. During single ended mode, the sample is
measured between ADC Channel and ground.
4:0
ADCH[4:0]
ADC Channel Select. These bits select the input channel source for configuration of ADC
conversion.
ADCH [4:0]
ADDIFF = 0
ADDIFF=1
00000
ADC-S0
ADC-D0P- ADC-D0N
00001
ADC-S1
ADC-D1P- ADC-D1N
00010
ADC-S2
ADC-D2P- ADC-D2N
00011
ADC-S3
ADC-D3P- ADC-D3N
00100
ADC-S4
ADC-D4P- ADC-D4N
00101
ADC-S5
ADC-D5P- ADC-D5N
00110
ADC-S6
ADC-D6P- ADC-D6N
00111
ADC-S7
ADC-D7P- ADC-D7N
01000
ADC-S8
NOT VALID
01001
ADC-S9
NOT VALID
01010
ADC-S10
NOT VALID
01011
ADC-S11
NOT VALID
01100
ADC-S12
NOT VALID
01101
ADC-S13
NOT VALID
01110
ADC-S14
NOT VALID
01111
ADC-S15
NOT VALID
10000
ADC-REFINA
ADC-REFINA
10001
ADC-REFINB
ADC-REFINB
10010
VDD
VDD
10011
DAC_INT_REF
DAC_INT_REF
10100- 11000
NOT VALID
NOT VALID
11001
ADC OFFSET
ADC OFFSET
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Temperature Right Aligned
S S S
28
27
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
Temperature Left Aligned
S
28
27
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4 0 0
Voltage Right Aligned
S S S
212
211
210
29
28
27
26
25
24
23
22
21
20
Voltage Left Aligned
S
212
211
210
29
28
27
26
25
24
23
22
21
20 0 0
DS4830 User’s Guide
7.2.5.2 – ADC Data Buffer (ADDATA when ADCFG = 0)
When ADCFG = 0, reading from the ADDATA register will read the ADC results stored in one of the 25 data buffers. The
ADIDX[4:0] bits point to the data buffer to be read. Reading ADDATA register returns the 14-bits (13-bits plus a sign bit) of
ADC conversion data from the selected data buffer memory. The ADIDX[4:0] bits will automatically increment after a read
of ADDATA. This allows multiple reads of ADDATA to access consecutive data buffer locations without needing to change
the ADIDX[4:0] bits. The data buffers will be reset to 0 on all forms of reset and are not writable by the user.
The data that is read from the ADC Buffer may be from either a temperature or voltage conversion. Also, the data may be
right or left aligned. Table 7-4 shows the returned bit weighting for each type of conversion.
Table 7-4. Voltage Data (ADC and Sample and Hold) and Temperature Bit weighting with alignment option
The ADC controller produces temperature, sample and hold and ADC data reading in the 2’s complement format.
55
DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - -
INT_IEN
EX0_iEN
EX1_iEN
-
EX1_ALIGN
EX0_ALIGN
INT_ALIGN
-
EX1_TEMP
EX0_TEMP
INT_TEMP
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:11
-
Reserved. The user should write 0 to these bits.
10
INT_IEN
Internal Temperature Interrupt Enable: Setting this bit to ‘1’ will enable an interrupt generation
on completion of an internal temperature conversion.
9
EX0_IEN
External Diode 0 Temperature Interrupt Enable: Setting this bit to ‘1’ will enable an interrupt
generation on completion of an external diode 0 temperature conversion.
8
EX1_IEN
External Diode 1 Temperature Interrupt Enable: Setting this bit to ‘1’ will enable an interrupt
generation on completion of an external diode 1 temperature conversion.
7
-
Reserved. The user should write 0 to this bit.
6
EX1_ALIGN
External Diode 1 Temperature Data Align. Setting this bit to ‘1’ configures external diode 1
temperature conversion data in left aligned mode. Setting this bit to ‘0’ configures external diode
1 temperature conversion data in right aligned mode.
5
EX0_ALIGN
External Diode 0 Temperature Data Align. Setting this bit to ‘1’ configures external diode 0
temperature conversion data in left aligned mode. Setting this bit to ‘0’ configures external diode
0 temperature conversion data in right aligned mode.
4
INT_ALIGN
Internal Temperature Data Align. Setting this bit to ‘1’ configures internal temperature
conversion data in left aligned mode. Setting this bit to ‘0’ configures internal temperature
conversion data in right aligned mode.
3
-
Reserved. The user should write 0 to this bit.
2
EX1_TEMP
External Diode 1 Temperature Enable. Setting this bit to ‘1’ initiates external diode 1
temperature conversion. The external diode 1 temperature typical conversion time is 4.1msec.
After external diode 1 temperature conversion result is available in data buffer 20.
1
EX0_TEMP
External Diode 0 Temperature Enable. Setting this bit to ‘1’ initiates external diode 0
temperature conversion. The external diode 0 temperature typical conversion time is 4.1msec.
After external diode 0 temperature conversion result is available in data buffer 21.
0
INT_TEMP
Internal Temperature Enable. Setting this bit to ‘1’ initiates internal temperature conversion.
The internal temperature typical conversion time is 4.1msec. After internal temperature
conversion result is available in data buffer 22.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name - - - - - - - -
ETS.7
ETS.6
ETS.5
ETS.4
ETS.3
ETS.2
ETS.1
ETS.0
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Access r r r r r r r r
rw
rw
rw
rw
rw
rw
rw
rw
7.2.6 – Temperature Control Register (TEMPCN)
Register Address: M2 [0Bh]
The Temperature Control register TEMPCN configures and enables internal die temperature and two external remote
diodes temperatures. Internal Temperature, external diode 0 and external diode 1 temperatures have dedicated data
buffers 22, 21 and 20 respectively. The DS4830 ADC Controller forces current in the diode and integrates voltage across
diode. After integration the ADC Controller measured voltage on ADC and convert measured voltage in temperature.
7.2.7 – External Temperature Slope Control Register (ETS)
Register Address: M1 [16h]
The ETS register sets changes the slope of external temperature measurements to compensate for changes in diode
ideality factor. The DS4830 is factory calibrated to work with a diode connected 2N3904 NPN transistor.
56
DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
S S S S 28
27
26
25
24
23
22
21
20
2-1
2-2
2-3
Reset
s s s s s s s s s s s S s s s
s
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name S S S 212
211
210
29
28
27
26
25
24
23
22
21
20
Reset s s s s s s s s s s s s s s s s
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
ADCG.15
ADCG.14
ADCG.13
ADCG.12
ADCG.11
ADCG.10
ADCG.9
ADCG.8
ADCG.7
ADCG.6
ADCG.5
ADCG.4
ADCG.3
ADCG.2
ADCG.1
ADCG.0
Reset s s S s s s s s s s S s s s s s
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
7.2.8 – ADC External Temperature Offset Register (TOEX)
Register Address: M1 [1Ah]
s = special, initial value is dependent on trim settings
This register contains the temperature offset for the external temperature measurements. The default value of this
register is -273 (Kelvin to Celsius) plus any offset that was calibrated out at the factory. This offset is applied to the raw
data from the ADC prior to the value being stored into the data buffer. The final result stored in the data buffer will be
raw_adc + TOEX, where raw_adc is the converted temperature in Kelvin.
7.2.9 – ADC Voltage Offset Register (ADVOFF)
Register Address: M1 [19h]
s = special, initial value is dependent on trim settings
This register contains the ADC voltage offset for the voltage mode. This is calibrated for ADCG1 at the factory to cancel
out any offset that may be present in the ADC. The user can add or subtract any offset that they desire by altering this
register. This offset is applied to the raw data from the ADC prior to the value being stored into the data buffer. The value
stored in the data buffer will be raw_adc + ADVOFF, where raw_adc is the converted voltage without any offset
compensation.
7.2.10 – ADC Voltage Scale Trim Registers (ADCG1, ADCG2, ADCG3 and ADCG4)
ADCG1 Register Address: M1 [17h]
ADCG2 Register Address: M1 [18h]
ADCG3 Register Address: M1 [1Bh]
ADCG4 Register Address: M1 [1Ch]
s = special, initial value is dependent on trim settings
These registers are used to adjust the ADC full scale by changing the gain applied to the ADC reference (internal). These
registers are set at the factory to work with the internal reference. The internal reference voltage is set to 1.2V and cannot
be changed by the user.
These gain registers are provided so the ADC full scale can be adjusted to meet the needs of the targeted application.
Only bits ADCG[15:2] are used to adjust the full scale level. Some approximate settings are:
ADCGx = 32A8h: The full scale is ~1X the reference level
ADCGx = 1960h: The full scale is ~2X the reference level
ADCGx = 0B90h: The full scale is ~4X the reference level
ADCGx = 0328h: The full scale is ~6X the reference level
It is not recommended that a gain other than 1X, 2X, 4X or 6X be used. This is because the weightings of the ADCGx
[15:0] bits are non-linear. An application specific program needs to be developed that tests the ADC full scale for each
possible code setting until the proper full scale is achieved. It is recommended that the user not change ADCG1. The ADC
controller uses ADCG1 (not user selectable) for Sample and Hold.
57
DS4830 User’s Guide
7.3 – ADC Code Examples
7.3.1 – One Sequence of 4 Voltage Conversions for Ch0 (Diff), Ch1 (Diff), Ch14 (Single) and Ch15 (Single)
PINSEL = 0xC00F; //Configure Pin as ADC Ch0 (Diff), Ch1 (Diff), Ch14 (Single) and Ch15(Single)
ADCN_bit.ADCONT = 0; //run a single conversion sequence
ADST_bit.ADCFG = 1; //set ADDATA for configuration (ADCFG)
ADST_bit.ADIDX = 0; //ADIDX = 0, set to ADCFG [0]
ADDATA = 0x0020; //ADCFG [0]: Differential voltage, CH0, 1.2V FS, Right Aligned
ADDATA = 0x2021; //ADCFG [1]: Differential voltage, CH1, 0.6V FS, Right Aligned
ADDATA = 0x400E; //ADCFG [2]: Single voltage, CH14, 2.4V FS, Right Aligned
ADDATA = 0x600F; //ADCFG [3]: Single voltage, CH15, 4.8V FS, Right Aligned
ADST_bit.ADCFG = 0; //set ADDATA to data buffer
ADADDR_bit.ADSTART = 0; //start sequence with ADCFG [0]
ADADDR_bit.ADEND = 3; //end sequence with ADCFG [3]
ADST_bit.ADCONV = 1; //start the conversions
while (!ADST_bit.ADDAI); //wait for conversions to complete
ADST_bit.ADDAI = 0; //Clear ADDAI flag
ADST_bit.ADIDX = 0; //set ADDATA to data buffer [0]
ch0_volt = ADDATA; //read and store ch0 voltage to variable
ch1_volt = ADDATA; //read and store ch1 voltage to variable
ADST_bit.ADIDX = 14; //set ADDATA to data buffer [14] (according to channel number)
ch14_volt = ADDATA; //read and store ch14 voltage to variable
ch15_volt = ADDATA; //read and store ch15 voltage to variable
7.3.2 – Continuous Conversion of 16 Samples of Ch0 with location override
PINSEL = 0x0003; //Configure Pins as ADC Ch0 (Diff)
ADCN_bit.ADCONT = 1; //run a continuous conversion sequence
ADCN_bit.LOC_OVR = 1; //location override enable
ADST_bit.ADCFG = 1; //set ADDATA as configuration (ADCFG)
ADST_bit.ADIDX = 0; //ADIDX = 0, set to ADCFG [0]
ADDATA = 0x0020; //ADCFG [0]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 0
ADDATA = 0x0120; //ADCFG [1]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 1
ADDATA = 0x0220; //ADCFG [2]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 2
ADDATA = 0x0320; //ADCFG [3]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 3
ADDATA = 0x0420; //ADCFG [4]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 4
ADDATA = 0x0520; //ADCFG [5]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 5
ADDATA = 0x0620; //ADCFG [6]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 6
ADDATA = 0x0720; //ADCFG [7]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 7
ADDATA = 0x0820; //ADCFG [8]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 8
ADDATA = 0x0920; //ADCFG [9]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 9
ADDATA = 0x0A20; //ADCFG [10]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 10
ADDATA = 0x0B20; //ADCFG [11]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 11
ADDATA = 0x0C20; //ADCFG [12]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 12
ADDATA = 0x0D20; //ADCFG [13]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 13
ADDATA = 0x0E20; //ADCFG [14]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 14
ADDATA = 0x0F20; //ADCFG [15]: Differential voltage, CH0, 1.2 V FS, Right Aligned and Location override 15
ADST_bit.ADCFG = 0; //set ADDATA to data buffer
ADADDR_bit.ADSTART = 0; //start sequence with ADCFG [0]
ADADDR_bit.ADEND = 15; //end sequence with ADCFG [15]
ADST_bit.ADCONV = 1; //start the conversions
58
while (1)
{
while (!ADST_bit.ADDAI); //wait for conversions to complete
ADST_bit.ADDAI = 0;
ADST_bit.ADIDX = 0; //set ADDATA to data buffer [0]
for (iCount = 0; iCount < 16; iCount++)
ch0 [iCount]= ADDATA; //read and store ch0 voltage to variable
}
DS4830 User’s Guide
59
DS4830 User’s Guide
Sampling
Control
ANALOG
MUX
Input
Discharge
Control
S/H Circuit
Current
Source
SHEN*
ADC
External
Clock
Peripheral
Clock
Cs
Cs
*SHEN can be internal or external (SHEN0 or SHEN1)
SHP
SHN
Cp
Cp
SECTION 8 – SAMPLE AND HOLD
The DS4830 has two independent, but identical, Sample and Hold differential channels. Sample and Hold 0 (S/H0) is on
GP2-GP3 and Sample and Hold 1 (S/H1) is on GP12-GP13. The sample and hold function can be configured for internal
or external triggering. Each sample and hold has a dedicated pin for external trigger.
Figure 8-1: Sample and Hold Functional Block Diagram
8.1 – Detailed Description
As shown in figure 8-1, each Sample and Hold consists of fully differential sampling capacitors (Cs), control logic and a
differential output buffer. The sample and hold also contains a charge injection nulling circuit. Additionally, it has a
discharge circuit to discharge parasitic capacitance on the input node and the sample capacitor before it starts sampling.
The input voltage is sampled using 5pF capacitor on the positive input and another 5pF capacitor on the negative input.
The negative input pin is used to reduce ground offset and noise. The capacitors are connected to the input when sample
trigger signal SHEN (either internal or external) is high. During high period of sample pulse, the sample and hold performs
sampling which ends at negative edge of the sample pulse SHEN. In addition to the sampling capacitors, the input pins
also have parasitic capacitance. When the sample and hold is configured for internal triggering, the sample pulse is
internally generated by the sample and hold hardware.
8.1.1 – Operation
When the SHEN signal goes high, the sample and hold capacitors are connected to the sample and hold input pins (GPx)
for sampling of the input signal. The minimum sample time for should be 300nSec for proper sampling. When the SHEN
signal goes low, the sampling is stopped and voltage stored at sampling capacitors are converted by the ADC controller.
See Figure 8-2 for Sample and Hold Timings. Each Sample and Hold can be independently enabled by setting their
respective enable bit in the Sample and Hold Control Register (SHCN). The sample and hold has two modes of operation
“Single Mode” and “Dual Mode”.
60
Sample Time
(min 300nSec)
Conversion Time
Depends upon ADC
Sequencing
Sample and Hold Sample and Conversion Timings
Sample Pulse
Internal or External
Min 125uSec in Fast Mode or 250uSec in Normal Mode
Pin Discharge, if
Enabled
SH Sample &
Conversion Timings
DS4830 User’s Guide
Figure 8-2 – Sample and Hold Conversion Timings
8.1.1.1 – Single Mode Operation
During the single mode operation, the SHEN signal (either internal trigger or external trigger at SHEN0) acts as a sample
pulse for both sample and hold 0 and 1. The SH0DAI bit in the ADST register is set to ‘1’, after conversion of both sample
and holds by the ADC and an interrupt is generated if enabled. The results are available at data buffer locations 23 and 24
respectively for both sample and holds after the ADC conversion is complete.
In the single mode operation the SH0DAI bit is set to ‘1’
a. At the completion of both sample and hold channels ADC conversion, if both sample and holds are enabled.
b. At the completion of only enabled sample and hold channel if any one sample and hold enabled.
The sample and hold interrupt for both sample and hold circuits can be enabled by the setting the SHDAI0_EN bit in the
SHCN register. In single mode operation, the SENR[1:0] register bits control the SHEN source for both of the sample and
holds.
8.1.1.2 – Dual Mode Operation
Dual mode operation is selected when SH_DUAL bit in the SHCN register is set to ‘1’. In this mode of operation, both the
sample and hold circuits work independently. Each sample and hold can have separate internal or external triggers. The
SHEN0 and SHEN1 provide sample pulses to Sample and Hold 0 and Sample and Hold 1 respectively for external trigger.
The Sample and Hold Internal Trigger Enable Register (SENR) has bits to enable the internal trigger for both sample and
hold circuits individually. In the dual mode operation each sample and hold generates its own Sample and Hold Data
Available Interrupt Flag (SH0DAI and SH1DAI) in the ADST register. Each of these flags can generate an interrupt if
enabled. The results are available in ADC data buffer (ADDATA, refer ADC SFR description for detail) 23 and 24
respectively.
8.1.2 – Fast Mode Operation
The DS4830 Sample and Hold provides a special “Fast Mode” feature which gives priority to a sample and hold
conversion over an ADC voltage conversion. The “Fast Mode” is enabled by setting the FAST_MODE bit to ‘1’ in the
SHCN register. This mode is useful when only Sample and Hold 0 is used. In fast mode operation the Sample and Hold 0
is guaranteed to get a conversion slot in the ADC conversion sequence every 125s. In this mode, the user is allowed to
issue SHEN pulses (either internal of external pulse) at every 125s interval. This bit should be used with care, as it
creates priority for the Sample and Hold0 over other sequence mode channels and hence their ADC conversion will be
delayed. When the FAST_MODE bit is set to ‘0’, the user can issue SHEN pulse every 250s time interval.
8.1.3 – Sampling Control
The sample and hold circuitry provides the option to select the internal peripheral clock or the external clock. When the
clock select bit CLK_SEL (located in the SHCN register) is set to ‘0’, the peripheral clock is used for the sample and hold
61
DS4830 User’s Guide
Sample
Pulse
External
Trigger
Internal
Trigger
0
1
Mux
INTTRIG_EN
0
NonZero
Mux
SSC
SHEN OUT
{
SHEN OUT when SSC=0
Sampling Pulse depends
upon SSC Value
Falling edge (Sample stop) depends
upon SSC[3:0]
SHEN0/1
or
INT_REIG0/1
Sample
Pulse
Sample Pulse Width with peripheral clock
300ns
min
SSC[3:0] = 0
circuit. When the clock select bit CLK_SEL is set to ‘1’, the external clock (CLKIN on the DACPW2 pin) is used for the
sample and hold circuit.
Figure 8-3: Sample Pulse
The end of the sample and hold sample time is controlled by the Sampling Stop Control bits SSC[3:0] in the SHCN
register. These bits are used along with the CLK_SEL bit to determine the length of the sample pulse. When the SSC[3:0]
bits have non-zero values and the CLK_SEL bit is set to ‘1’, the stop sampling will depend upon of the number of external
clock cycles. When the SSC[3:0] bits have non-zero values and the CLK_SEL bit is ‘0’, the stop sampling will depend
upon the time from the rising edge of SHEN0/1 (See Figure 8-3 for Sample Pulse). See SSC[3:0] bit description for stop
sampling timings.
Figure 8-4: Sample Pulse Width with the Peripheral Clock
As shown in Figure 8-4, the sample pulse width time depends upon the SSC bits value when the peripheral clock is
selected (CLK_SEL = 0).
62
SHEN0/1
or
INT_REIG0/1
Sample Pulse
Sample Pulse Width with external clock
CLKIN ….
Falling edge (Sample stop) depends
upon SSC[3:0]
300ns
min
….
….
SSC[3:0] = 0
Sample Time
(min 300nSec)
Conversion Time
Pin discharge function
Pin Discharge
Pulse
Min 125uSec in Fast Mode or 250uSec in Normal Mode
Pin Discharge
SHEN0/1
or
INT_TRIG0/1
Pulse
DS4830 User’s Guide
Figure 8-5: Sample Pulse Width with the External Clock
As shown in Figure 8-5, the sample pulse width time depends upon the SSC bits value when the external clock is selected
(CLK_SEL = 1).
8.1.4 – Pin Capacitance Discharge
Before the sample and hold circuitry start sampling, the DS4830 has an option to discharge pin capacitance. The SHCN
register has PIN_DIS0 and PIN_DIS1 bits to enable the pin discharge function before sampling begins. This is an
optional feature, which generates a discharge pulse that discharges the pin or PCB capacitance for the sample and hold
channels. The discharge pulse is active after the corresponding sample and hold channel’s conversion is complete and
goes inactive on the rising edge of SHEN0 or SHEN1 pulse. See pin discharge timing is shown below in Figure 8-6.
Figure 8-6 – Pin Discharge operation
63
DS4830 User’s Guide
8.1.5 – Sample and Hold Data Reading
Each sample and hold has defined data buffer locations where the ADC controller writes sample and hold results after the
ADC conversion. The data buffer location 23 and 24 are reserved for Sample and Hold 0 and 1 respectively. The ADC
controller uses ADCG1 (1.2V full scale) for ADC conversion of the sampled signal of both sample and holds.
8.1.6 – Sample and Hold Interrupts
The DS4830 sample and hold has two interrupt flags SH0DAI and SH1DAI in the ADST register. The SH1DAI bit is used
only when both Sample and Hold are enabled in the dual mode operation. In single mode operation, SH0ADI is set only
when:
1. Both sample and holds are enabled, then after the ADC conversion of both samples.
2. If only one sample and hold is enabled, then after the ADC conversion of the enabled sample and hold.
64
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
SSC[3:0]
FAST_MODE
PIN_DIS1
PIN_DIS0
SH_DUAL
-
SH1_ALIGN
SHDAI1_EN
SMP_HLD1
CLK_SEL
SH0_ALIGN
SHDAI0_EN
SMP_HLD0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw r rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:12
SSC[3:0]
STOP Sample Control. These bits control the end of the sample and hold sampling
relative to the SHEN0 and SHEN1 pulse.
CLK_SEL = 0
SSC[3:0]
STOP Sampling
0000
Falling Edge of SHEN0/SHEN1
0001
Reserved
0010
Reserved
0011
Reserved
0100
300ns after rising edge of SHEN0/SHEN1
0101
350ns after rising edge of SHEN0/SHEN1
0110
450ns after rising edge of SHEN0/SHEN1
0111
550ns after rising edge of SHEN0/SHEN1
1000
750ns after rising edge of SHEN0/SHEN1
1001
1us after rising edge of SHEN0/SHEN1
1010
1.5us after rising edge of SHEN0/SHEN1
1011
1.75us after rising edge of SHEN0/SHEN1
1100
2us after rising edge of SHEN0/SHEN1
1101
2.5us after rising edge of SHEN0/SHEN1
1110
4us after rising edge of SHEN0/SHEN1
1111
5us after rising edge of SHEN0/SHEN1
CLK_SEL = 1
SSC[3:0]
STOP Sampling
0000
Falling Edge of SHEN0/SHEN1
0001
21 ext-clock after rising edge of SHEN0/SHEN1
0010
22 ext-clock after rising edge of SHEN0/SHEN1
0011
23 ext-clock after rising edge of SHEN0/SHEN1
0100
24 ext-clock after rising edge of SHEN0/SHEN1
0101
25 ext-clock after rising edge of SHEN0/SHEN1
0110
26 ext-clock after rising edge of SHEN0/SHEN1
0111
27 ext-clock after rising edge of SHEN0/SHEN1
1000
28 ext-clock after rising edge of SHEN0/SHEN1
1001
29 ext-clock after rising edge of SHEN0/SHEN1
1010
30 ext-clock after rising edge of SHEN0/SHEN1
1011
31 ext-clock after rising edge of SHEN0/SHEN1
1100
32 ext-clock after rising edge of SHEN0/SHEN1
1101
33 ext-clock after rising edge of SHEN0/SHEN1
1110
34 ext-clock after rising edge of SHEN0/SHEN1
1111
35 ext-clock after rising edge of SHEN0/SHEN1
Note: A minimum sample time of 300nSec must be used when external clock is used
to guarantee accurate results.
11
FAST_MODE
Fast Mode Enable. Setting this bit to ‘1’ enables the fast operation for Sample and Hold 0.
In this mode, the Sample and Hold 0 is guaranteed to get a conversion slot in the ADC
conversion sequence every 125s and the user can issue sample pulses at an interval of
8.2 – Sample and Hold Register Descriptions
The sample and hold has two SFRs. These are Sample and Hold Control Register (SHCN) and Sample and Hold Internal
Trigger Enable register (SENR). The SHCN register controls both sample and holds. The SENR controls the internal
sample pulse for both sample and holds. The sample and hold SFRs are located in module 2.
8.2.1 – Sample and Hold Control Register (SHCN)
SHCN Register Address: M2[10h]
DS4830 User’s Guide
65
125s. During fast mode, the sample and hold conversion priority is increased over voltage
channels in the sequence and the voltage conversions will be delayed. When this bit is ‘0’,
Sample and Hold 0 acts in the normal mode in which Sample and Hold 0 will get a
conversion slot in the ADC sequence every 250s.
10
PIN_DIS1
Pin Discharge Enable 1. Setting this bit to ‘1’ will enable the pin discharge function for
Sample and Hold 1. The discharge function will discharge pin capacitances (GP12-GP13)
after the Sample and Hold 1 ADC conversion.
9
PIN_DIS0
Pin Discharge Enable 0. Setting this bit to ‘1’ will enable pin discharge function at Sample
and Hold 0. The discharge function will discharge pin capacitances (GP2-GP3) after the
Sample and Hold 0 ADC conversion.
8
SH_DUAL
Sample and Hold Dual Mode. Setting this bit to ‘1’ will configure Sample and Hold in
“Dual Mode” operation. In dual mode, both sample and holds will act independently and will
use different sample trigger input signals. The SHEN0 (pin 23) acts as the sample trigger
input signal for Sample and Hold 0. The SHEN1 (pin 21) acts as the sample trigger input
signal for Sample and Hold 1. In single mode operation both sample and hold circuits are
triggered by the SHEN0 signal.
7
-
Reserved. The user should write 0 to this bit.
6
SH1_ALGN
Sample and Hold 1 Data Alignment Select. This bit selects the Sample and Hold 1 data
alignment mode. Setting this bit to ‘1’ returns data left aligned in ADDATA[15:2] with
ADDATA[1:0] zero padded. Clearing this bit to ‘0’ returns data in right aligned format in
ADDATA[13:0] with ADDATA[15:14] sign-extended by ADDATA[13].
5
SHDAI1_EN
Sample and Hold 1 Interrupt Enable. Setting this bit to ‘1’ will enable interrupt generation
on the completion of Sample and Hold 1 ADC conversion in the dual mode.
4
SMP_HLD1
Sample and Hold 1 Enable. Setting this bit to ‘1’ enables Sample and Hold 1 operation on
GP12-GP13 input pins. The conversion results are available in ADC data buffer location
24.
3
CLK_SEL
Clock Select for Sample and Holds Trigger delayed rising edge control. This bit
selects the clock used to stop sampling when operating in SSC mode. During this mode
SSC[3:0] bits controls the delay from the start to stop of sampling..
When this bit is set to ‘0’, the peripheral clock is used for generating the SHEN pulse.
When this bit is set to ‘1’, the External Clock (CLKIN pin) is used for generating the SHEN
pulse.
See the SSC[3:0] bit description to see the effect of CLK_SEL on the SHEN0/SHEN1 pulse
generation.
2
SH0_ALGN
Sample and Hold 0 Data Alignment Select. This bit selects the Sample and Hold 0 data
alignment mode. Setting this bit to ‘1’ returns data left aligned in ADDATA[15:2] with
ADDATA[1:0] zero padded. Clearing this bit to ‘0’ returns data in right aligned format in
ADDATA[13:0] with ADDATA[15:14] sign-extended by ADDATA[13].
1
SHDAI0_EN
Sample and Hold 0 Interrupt Enable. Setting this bit to ‘1’ will enable interrupt generation
on the completion of Sample and Hold 0 ADC conversion when operating in dual mode
operation. In the single mode operation, this bit is set at the completion of both sample
and hold conversions.
0
SMP_HLD0
Sample and Hold 0 Enable. Setting this bit to ‘1’ enables Sample and Hold 0 operation on
GP2-GP3 input pins. The conversion results are available in ADC data buffer location 23.
DS4830 User’s Guide
66
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
INT_TRIG_EN1
INT_TRIG1 - -
INT_TRIG_EN0
INT_TRIG0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r r r rw
rw r r
rw
rw
BIT
NAME
DESCRIPTION
15:6
-
Reserved. The user should write 0 to these bits.
5
INT_TRIG_EN1
Sample and Hold 1 Internal Trigger Enable. Setting this bit to ‘1’ will enable internal
trigger mode for Sample and Hold 1. When this bit is set to ‘1’, writing a ‘1’ to INT_TRIG1
will start an internal sample pulse for Sample and Hold 1. When this bit is ‘1’, sample
pulses on SHEN1 are rejected.
Setting this bit to ‘0’ will configure Sample and Hold 1 for external sample pulse.
This bit is used in the dual mode operation only.
4
INT_TRIG1
Sample and Hold 1 Internal Trigger. This bit is used when the INT_TRIG_EN1 is set to
‘1’. Setting this bit to ‘1’ will start internal sample pulse for Sample and Hold 1. Depending
upon the SSC[3:0] bit setting, the sample pulse will stop when this bit is set to ‘0’. This bit
is used in the dual mode operation only.
3:2
-
Reserved. The user should write 0 to these bits.
1
INT_TRIG_EN0
Sample and Hold Internal Trigger Enable. Setting this bit to ‘1’ will enable internal
trigger mode for Sample and Hold 0. When this bit is set to ‘1’, writing a ‘1’ to INT_TRIG0
will start an internal sample pulse for Sample and Hold 0. When this bit is ‘1’, sample
pulses on SHEN0 are rejected.
Setting this bit to ‘0’ will configure Sample and Hold 0 for external sample pulse.
In the single mode operation, this bit is used for both sample and holds.
0
INT_TRIG0
Sample and Hold0 Internal Trigger. This bit is used when the INT_TRIG_EN0 is set to
‘1’. Setting this bit to ‘1’ will start internal sample pulse for Sample and Hold 0. Depending
upon the SSC[3:0] bit setting, the sample pulse will stop when this bit is set to ‘0’.
In the single mode operation, this bit is used for both sample and holds.
8.2.2 – Sample and Hold Internal Trigger Enable Register (SENR)
SENR Register Address: M2[05h]
DS4830 User’s Guide
8.2.3 – Sample and Hold Interrupt flag
See ADST description for Sample and Hold interrupts flags SH0DAI and SH1DAI descriptions.
67
DS4830 User’s Guide
QT CONFIGURATIONS
ADC-S0
ADC-S1
ADC-S14
ADC-S15
A
N
A
L
O
G
M
U
X
QT SEQUENCER
QTSTART
QTEND
QTEN
QT HIGH
THRESHOLD
QT LOW
THRESHOLD
CHSEL[3:0]DIFF
Digital MUX
8-Bit
Internal
DAC
HT Register[0]
HT Register[14]
HT Register[1]
HT Register[15]
16 High Threshold
Registers
LT Register[0]
LT Register[14]
LT Register[1]
LT Register[15]
16 Low Threshold
Registers
LIST REGISTER[0]
LIST REGISTER[14]
LIST REGISTER[1]
LIST REGISTER[15]
16 List Configurations
5 bit Each
LTI / HTI
LTIE / HTIE
Interrupt
QT CLOCK
QTDATA[15:0]
Comparator
QT- 2.42V
Internal
Reference
.
.
.
RW_LST = 0
LTHT = 0
RW_LST = 1
.
.
.
.
.
.
RW_LST = 0
LTHT = 1
SECTION 9 – QUICK TRIP (FAST COMPARATOR)
The DS4830 has 16 8-bit quick trips with 16-input Analog MUX (Figure 9-1). The MUX selects the quick trip analog input
from 16 external channels. The quick trip external channels can be configured to operate as eight fully differential inputs
or sixteen single-ended inputs. The quick trip monitors all configured quick trip channels in a round robin sequence.
Figure 9-1: Quick Trip Functional Block Diagram
9.1 – Detailed Description
As shown in Figure 9-1, the DS4830 Quick Trip (QT) controller has a 16-input analog MUX and Quick Trip Sequencer.
The QT sequencer creates a list of configurations and sets user defined low and high threshold for external channels. The
quick trip controller has 16 low trip threshold and 16 high trip threshold internal registers.
The Quick Trip Control Register (QTCN) has two bits RW_LST and LTHT which are used to configure thresholds and list
creation. The QTIDX[3:0] bits (located in the QTCN register) together with LTHT and RW_LST bits select the source or
destination address for the QTDATA register access. Figure 9-1 illustrates the threshold configuration and list creation.
68
DS4830 User’s Guide
RW_LST
LTHT
QTIDX
Register Selected
0 0 N(0 to 15)
Low threshold configuration for the channel defined in list N
0 1 N(0 to 15)
High threshold configuration for the channel defined in list N
1 X N(0 to 15)
Nth register of list configuration
By default, the external channels GP0-15 are general-purpose input. The DS4830 has the Pin Select Register (PINSEL).
The PINSEL register is used to configure the external channels as an analog pin for ADC or/and Quick Trip use. Each bit
location in this register corresponds to the ADC/Quick Trip input pin.
Table 9-1. Low and High Thresholds Configuration and List Creation
Thresholds Configuration
Each configuration has two threshold registers to configure low and high threshold. Each threshold register is addressed
by the QTIDX[3:0] bits. These bits are auto incremented on any read or write operation to the QTDATA register. The low
trip thresholds are configured by writing to the QTDATA register when the RW_LST and LTHT bits are set to ‘0’. The high
trip thresholds are configured by writing to the QTDATA register when the RW_LST bit is set to ‘0’ and LTHT bit is set to
‘1’.
List Creation
As shown in Figure 9-1, the quick trip controller has 16 list registers. These are configured by writing to the QTDATA
register when the RW_LST bit is set to ‘1’. The list address is addressed by the QTIDX[3:0] bits. Each list register uses
only lower 5 bits. The first 4 lower bits CHSEL [3:0] specifies the quick trip input channel. The DIFF bit selects between
single-ended mode (when DIFF bit is set to ‘0’) and differential mode (when DIFF bit is set to ‘1’) quick trip comparison.
The start and stop addresses of the list are provided by the Quick Trip List Register (QTLST). Any channel can be used
multiple times at any location in the list.
Refer 9.2 - Quick Trip Register Descriptions for details.
As shown in Figure 9-1, the quick trip sequencer selects a channel from 16 external channels. The quick trip controller
has an internal 8-bit DAC which generates voltage for low and high threshold comparisons with the external channel input.
The quick trip is also called “Fast Comparator” as it compares the input with threshold using the fast comparator. The
conversion time is 1.6s for each threshold; so each channel’s thresholds are compared in 3.2s (1.6s for low trip
threshold + 1.6s for high trip threshold).
9.1.1 – Quick Trip List Sequencing
The DS4830 quick trip controller performs the user defined sequence of up to 16 Single ended or 8 Differential external
channels conversions.
A sequence is setup in the QTLST register by defining the starting conversion configuration address (QTSTART) and an
ending conversion configuration address (QTEND). The configuration start address designates the configuration register
to be used for the first conversion in a sequence. The configuration end address designates the configuration register
used for the last conversion in a sequence. A single channel conversion can be viewed as a special case for sequence
conversion, where the starting and ending configuration address is the same. The configuration registers can be viewed
as a circular register array where QTSTART does not have to be less than QT END. For example, if QTSTART = 1 and
QTEND = 5, then the sequence of conversions would be configurations 1, 2, 3, 4, 5. . If QTSTART = 5 and QT END = 1,
then the sequence of conversions would be configurations 5, 6, 7 … 15, 0, 1.
9.1.2 – Operation
The quick trip is enabled by setting the Quick Trip Enable (QTEN) bit to ‘1’ in the QTCN register. The Quick Trip Controller
takes ~120 core clocks to wake up after enable and then starts scanning through the list of channels specified in the
channel list register QTLST continuously in the round robin sequence. The quick trip sequence reads the list, selects the
input channel and reads the low trip threshold and performs 8-bit comparison, then reads the high trip threshold and again
performs 8-bit comparison. The quick trip has separate interrupt flag registers for the low and high trip threshold. The low
trip interrupt flag is set when the input voltage is less than the configured low threshold. Similarly, the high trip interrupt
flag is set when the input voltage is greater than the configured high threshold. The interrupt can be generated if enabled.
The channel list can be filled up using the QTDATA register by setting the RW_LST bit to ‘1’ in the QTCN register. For
example to scan channels S5, S6 and S14-15 having configurations for channels 5 & 6 in the single-ended mode, channel
7 (S14-S15) in the differential mode and channel 6 again (any channel can be configured multiple times in the QT list).
The quick trip list can be filled sequentially with data 05h (channel 5 + single-ended), 06h (channel 6 + single-ended), 17h
69
DS4830 User’s Guide
QT List Number
QTDATA
Description
List Registers Used for comparison
0
05h
Channel 5 (S5) in single-ended mode
LT0 and HT0
1
06h
Channel 6 (S6) in single-ended mode
LT1 and HT1
2
17h
Channel 7(S14-S15) in differential mode
LT2 and HT2
3
06h
Channel 6 (S6) in single-ended mode
LT3 and HT3
QT List Number
Low Threshold Value (as Example)
QTDATA
0
0.6V
0x0100
1
0.8V
0x0154
2
1.0V
0x01AC
3
1.1V
0x01D4
QT List Number
High Threshold Value (as Example)
QTDATA
0
2.2V
0x03AC
1
2.0V
0x0354
2
1.8V
0x0300
3
1.6V
0x02AC
(channel 7 + differential mode) and 06h (channel 6 + single-ended). See below Table 9-2 for the quick trip list
configurations.
To scan (See Figure 9-2) these list registers, the QTSTART bits are set to 0 (0000b) and the QTSTOP bits is set to 3
(0011b). Each channel is scanned twice (See Figure 9-2). First the low trip threshold (LT) is scanned and then the high
trip threshold (HT).
Table 9-2. Quick Trip List Configuration
Quick Trip Start address (QTSTART) = 0
Quick Trip Stop address (QTEND) = 3
The quick trip threshold can be calculated by using the following formula.
Below table demonstrates Quick Trip low and high threshold configuration.
Table 9-3. Quick Trip Low Threshold Configuration
QTCN = 0x0000; //Low Threshold Configuration Register, Index = 0
QTDATA = 0x0100; //0.6V Low Threshold Configuration for List0 Configuration
QTDATA = 0x0154; //0.8V Low Threshold Configuration for List1 Configuration
QTDATA = 0x01AC; //1.0V Low Threshold Configuration for List2 Configuration
QTDATA = 0x01D4; //1.1V Low Threshold Configuration for List3 Configuration
Table 9-4. Quick Trip High Threshold Configuration
QTCN = 0x0010; //High Threshold Configuration Register, Index = 0
QTDATA = 0x03AC; //2.2V High Threshold Configuration for List0 Configuration
QTDATA = 0x0354; //2.0V High Threshold Configuration for List1 Configuration
QTDATA = 0x0300; //1.8V High Threshold Configuration for List2 Configuration
QTDATA = 0x02AC; //1.6V High Threshold Configuration for List3 Configuration
70
Channel 5
LT HT
Channel 6
LT HT
Channel 7
LT HT
……….
Channel 5
LT HT
Channel 6
LT HT
Channel 7
LT HT
……….
Channel 6*
LT HT
Channel 6*
LT HT
* Note: Channels can be defined multiple times in the list.
DS4830 User’s Guide
Figure 9-2: Quick Trip Operation
9.1.3 – Quick Trip Interrupts
The DS4830 quick trip has two interrupt flag registers the Low Trip Interrupt Flag Register (LTI) and High Trip interrupt
Flag Register (HTI). Each flag bit refers to the corresponding list sequence number defined in the QTLST. The
corresponding bit is set in the interrupt flag register if the corresponding sequence list number for the channel is tripped.
71
DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - -
QTEN - - - -
RW_LST - -
LTHT
QTIDX[3:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r
rw r r r r
rw r r
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:13
-
Reserved. The user should write 0 to these bits.
12
QTEN
Quick Trip Enable. When this bit is set to ‘1’, it enables the quick trip operation. After
setting the QTEN bit to ‘1’, there is an initial delay for 120 core clock to wake up the quick
trip circuitry. When this bit is set to ‘0’, it disables the quick trip operation.
11:8
-
Reserved. The user should write 0 to these bits.
7
RW_LST
Read List Register: When this bit is set to ‘1’, it selects one of the sixteen list register
(addressed by QTIDX[3:0], refer below) in the list configuration. When this bit is set to ‘0’,
the low or high threshold register (depends upon the LTHT bit) are configured.
6:5
-
Reserved. The user should write 0 to these bits.
4
LTHT
Low or High Threshold Select: This bit is used only when RW_LST is set to ‘0’. This bit is
used to select low or high threshold read or write. When the LTHT bit is set to ‘0’, it points
to the low threshold configuration register list. When this bit is set to ‘1’, it points to the high
threshold configuration register list. The address of low or high threshold configuration is
addressed by QTIDX[3:0] bits.
3:0
QTIDX[3:0]
Quick Trip Index Select. These bits together with LTHT and RW_LST bits select the
source or destination address for the QTDATA register access.
When the RW_LST and LTHT bits are set to ‘0’, the QTIDX[3:0] bits address to one of the
sixteen low threshold register for read or write. When RW_LST = 0 and LTHT = 1, the
QTIDX[3:0] bits address one of the sixteen high threshold register for read or write.
When RW_LST = 1 (irrespective of LTHT bit), the QTDATA register selects the list register
addressed by QTIDX[3:0] bits for read and write operation. A read or write operation on the
QTDATA register will read or write to the list register addressed by QTIDX[3:0].
These bits are auto incremented on any read or write operation to the QTDATA register.
9.2 – Quick Trip Register Descriptions
The quick trip has 7 SFRs. These are the Quick Trip Control Register (QTCN), Quick Trip List Register (QTLST), Quick
Trip Data Register (QTDATA), Low Trip Interrupt Flag Register (LTI), High Trip Interrupt Flag Register (HTI), Low Trip
Interrupt Enable Register (LTIE) and High Trip Interrupt Enable Register (HTIE). The QTCN register controls the quick trip
operation. The QTLIST register defines the list for the quick trip controller. The QTDATA register is used to read and write
list and threshold (high and low threshold) registers. The LTI and HTI are interrupt flag registers for high and low
threshold. The LTIE and HTIE are the interrupt enable registers. The Quick Trip SFRs are located in module 5.
9.2.1 – Quick Trip Control Register (QTCN)
QTCN Register Address: M5 [01h]
9.2.2 – Quick Trip Data Register (QTDATA)
QTDATA Register Address: M5 [00h]
The Quick Trip Data register is used with LTHT, RW_LST and QTIDX[3:0] bits to configure thresholds and list
configurations. The QTDATA register selects the list register and threshold registers addressed by QTIDX[3:0] bits for
read and write operation.
Threshold registers are selected when the bit RW_LST is set to ‘0’. List registers are selected when the bit RW_LST is set
to ‘1’. Refer below tables for RW_LST = 0 and RW_LST = 1.
72
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
-
LOW or HIGH THRESHOLD
-
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:10
-
Reserved. The user should write these bits to ‘0’.
9:2
QTDATA[9:2]
a. Low Threshold Configuration (When the LTHT bit in the QTCN register is set to ‘0’)
The QTDATA register selects low threshold register addressed by QTIDX[3:0] bits in the
QTCN register for read and write operation. The low threshold registers are 10-bit wide
but only bits QTDATA [9:2] are used in comparison and the upper QTDATA [15:10] bits
are ignored and return 0. The user should write 0 at the QTDATA [1:0] bits.
b. High Threshold Configuration (When the LTHT bit in the QTCN register is set to ‘1’)
The QTDATA selects high threshold register addressed by QTIDX[3:0] bits in the QTCN
register for read and write operation. The high threshold registers are 10-bit wide but only
bits QTDATA [9:2] are used in comparison and upper QTDATA [15:10] bits are ignored
and return 0. The user should write 0 at the QTDATA [1:0] bits.
1:0
-
Reserved. The user should write 00b to these bits.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - - - - - - - -
DIFF
CHSEL[3:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r r r r
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:5
-
Reserved. The user should write 0 to these bits.
4
DIFF
Mode Selection (DIFF): This bit selects the Quick trip input channel source either as
single ended or differential mode. When this bit is set to ‘0’, quick trip channel (addressed
by CHSEL[3:0] is select as “Single Ended” input. When this bit is set to ‘1’, quick trip
channel (addressed by CHSEL[3:0] is select as “Differential Mode” input. Refer below
table for various quick trip input channel configuration in Single Ended as well as
differential mode.
3:0
CHSEL [3:0]
QT Channel Select (CHSEL [3:0]): These bits select the Quick trip input channel source
for the quick trip list configuration.
CHSEL[3:0]
DIFF = 0
Channel Selected
Single Ended
DIFF = 1
Channel Selected
Differential Mode
0000
ADC-S0
ADC-D0P – ADC-D0N
0001
ADC-S1
ADC-D1P – ADC-D1N
0010
ADC-S2
ADC-D2P – ADC-D2N
0011
ADC-S3
ADC-D3P – ADC-D3N
0100
ADC-S4
ADC-D4P – ADC-D4N
0101
ADC-S5
ADC-D5P – ADC-D5N
0110
ADC-S6
ADC-D6P – ADC-D6N
0111
ADC-S7
ADC-D7P – ADC-D7N
1000
ADC-S8
NOT VALID
1001
ADC-S9
NOT VALID
1010
ADC-S10
NOT VALID
1011
ADC-S11
NOT VALID
1100
ADC-S12
NOT VALID
1101
ADC-S13
NOT VALID
1110
ADC-S14
NOT VALID
1111
ADC-S15
NOT VALID
QTDATA Register map when RW_LST = 0 (in the QTCN Register)
QTDATA Register map when RW_LST = 1 (in the QTCN Register)
DS4830 User’s Guide
73
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
IF[15:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:0
IF[15:0]
Low Trip Interrupt Flag. The corresponding bit of the Low Trip Interrupt register is set
when a low threshold trip is occurred on a channel list register. In other words, when
voltage across channel is less than the low threshold configuration for the channel.
For Example, if a low trip occurs on the list register 0 then LTI will be set to 0x0001. If the
corresponding bit in the LTIE register is also ‘1’, and then this will generate an interrupt.
Software should clear the Low Trip Interrupt Flag once it is set by hardware. Setting this
bit to ‘1’ by software will generate an interrupt if enabled.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
IF[15:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:0
IF[15:0]
High Trip Interrupt Flag. The corresponding bit of the High Trip Interrupt register is set
when a high threshold trip is occurred on a channel list register. In other words, when
voltage across channel is greater than the high threshold configuration for the channel.
For Example, if a high trip occurs on the list register 0 then HTI will be set to 0x0001. If
the corresponding bit in the HTIE register is also ‘1’, and then this will generate an
interrupt. Software should clear the High Trip Interrupt Flag once it is set by hardware.
Setting this bit to ‘1’ by software will generate an interrupt if enabled.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
IE[15:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:0
IE[15:0]
Low Trip Interrupt Enable. This register is used to enable/mask the corresponding LTI
register interrupts. For Example, if LTIE = 0x0001 then Quick Trip list 0 can generate an
interrupt when LTI LSB is set to ‘1’ and all other interrupts from LTI are ignored. Similarly,
if LTIE = 0xFFFF, then all interrupts from LTI will generate interrupts.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
IE[15:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:0
IE[15:0]
High Trip Interrupt Enable. This register is used to enable/mask the corresponding HTI
register interrupts. For Example, if HTIE = 0x0001 then Quick Trip list 0 can generate an
interrupt when HTI LSB is set to ‘1’ and all other interrupts from HTI are ignored. Similarly,
if HTIE = 0xFFFF, then all interrupts from HTI will generate interrupts.
9.2.3 – Low Trip Interrupt Register (LTI)
LTI Register Address: M5 [02h]
9.2.4 – High Trip Interrupt Register (HTI)
HTI Register Address: M5 [03h]
DS4830 User’s Guide
9.2.5 – Low Trip Interrupt Enable Register (LTIE)
LTIE Register Address: M5 [08h]
9.2.6 – High Trip Interrupt Enable Register (HTIE)
HTIE Register Address: M5 [09h]
74
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - - - -
-
QTSTART3:0]
QTEND[3:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:8
-
Reserved. The user should write these bits to ‘0’.
7:4
QTSTART[3:0]
Quick Trip Configuration Start Address Bits [3:0]. These bits select the start address of
quick trip channel list.
3:0
QTEND[3:0]
Quick Trip Configuration Ending Address Bits [3:0]. These bits select the stop address
of quick trip channel list.
9.2.7 – Quick Trip List Register (QTLST)
QTLIST Register Address: M5 [0Ah]
DS4830 User’s Guide
75
DS4830 User’s Guide
SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE
The DS4830 provides an I2C-compatible master controller that allows the DS4830 to communicate with a slave device.
The I2C master interface can be setup to provide system interrupts after each I2C event.
10.1 – Detailed Description
10.1.1 – Description of Master I2C Interface
The master I2C interface uses the MSDA and MSCL pins. These pins are the master I2C controller’s connection to the
SDA and SCL pins of an I2C bus. In addition to driving these pins, the I2C master port also senses the state of both
MSDA and MSCL. This allows the I2C master port to offer bus error detection and allows a slave device to clock stretch.
Unless explicitly stated, all references to SDA and SCL in this section refer to the SDA and SCL lines of the I2C bus, not
the DS4830’s I
10.1.2 – Default Operation
The I2C master controller is disabled by default. The I2C master controller is enabled by setting the I2CEN and I2CMST
bits in the I2CCN_M register to a 1. Prior to the I2C master controller being used for communication, some software setup
is required. This setup includes setting the clock rate, timeout period, and which I2C events should generate interrupts.
The DS4830 master I2C controller is not intended to be used on an I2C bus that has multiple masters connected to the
bus.
10.1.3 – I2C Clock Generation
In an I2C system, the master is responsible for generating the SCL signal. The DS4830 I2C Master Controller provides
complete control over the clock rate and duty cycle. The I2C Master Controller generates SCL from the system clock.
The bit rate is controlled by the I2C Clock Control Register (I2CCK_M).
The high period of SCL clock is defined by the high byte of the I2C Clock Control register (I2CCKH) whereas the low
period of SCL is defined by the low byte (I2CCKL). The minimum clock high period is three system clocks while the
minimum low period has to be at least five system clock periods. The I2C clock characteristics can be defined by the
following equations:
SCL Low Time = System Clock Period x (I2CCKL[7:0] + 1)
SCL High Time = System Clock Period x (I2CCKH[7:0] + 1)
I2C Clock Rate = System Clock Frequency/(I2CCLK[7:0] + I2CCKH[7:0] + 2 )
One feature of the master I2C controller is that is also monitors SCL while the clock is being output. This allows the
controller to ensure that the SCL level is at the desired level prior to beginning the count for SCL Low or High Time.
Figure 10-1 illustrates the SCL sampling performed by the master I2C controller. When SCL is released by the master
I2C controller, there will be a rise time that is determined by the capacitive loading and pull-up resistance on the SCL line.
When the controller senses the SCL line has reached a high logic level, the count for SCL High Time will begin. The
same is true for a falling edge. The SCL Low Time will only begin after the controller senses the SCL line at a low logic
level.
Figure 10-1 also illustrates that the calculated I2C clock period will not be exactly accurate because the rise and fall time
of SCL is not taken into consideration. The actual clock period will be the period set by the I2CCK_M register plus any
rise and fall time.
2
C slave interface SDA and SCL pins.
76
DS4830 User’s Guide
Figure 10-1: I2C Clock Generation
The master I
stretch. A slave device may clock stretch, or hold SCL low, while it is busy or processing data. The master I2C controller
will always release SCL after holding it low for the SCL Low Time duration. By monitoring the state of SCL, the master I2C
controller realizes that SCL has not been released and does not begin the SCL High Time count. Only after the master
controller detects a high state on SCL will it begin the I2CCKH count. This is illustrated in Figure 10-2.
2
C controller’s ability to monitor the state of SCL allows the master to operate with slave devices that clock
Figure 10-2: Master I2C Clock Generation during Slave Clock Stretching
10.1.4 – Timeout
The Master I2C Controller has a programmable timeout function that allows the controller to recover from a bus error.
The timeout period is determined by the setting of the I2C Master Timeout Register (I2CTO_M) using the following
equation
Timeout Period = I2C Bit Rate x (I2CTO[7:0]+1)
where I2C Bit Rate is determined by the setting of the I2CCK_M register. The timeout can be disabled by clearing the
I2CTO_M register to 0. The I2C timeout timer starts counting:
When the I2CSTART bit is set to 1. The I2C controller will monitor the bus status until it can generate a
START condition. The I2C bus is considered busy if another master has generated a START condition and
no corresponding STOP has been detected (the I2CBUS bit is set to 1) or the SCL line is low. If the bus
remains busy for a period longer than specified in the timeout register, the I2C controller concludes that there is
a bus error and will set the I2CTOI flag.
If the I2C Controller has started a transfer (after the 1st bit rising edge), it will wait for the current byte transfer
to finish (after the 9th bit (acknowledge) has been transmit) before generating the START condition. In this
case, the timeout timer will start counting after the end of the 9th bit low time.
After the master I2C controller attempts to generate a STOP condition. If a STOP is not detected (I2CSPI = 1)
during the timeout period, the I2CTOI flag will be set.
If the I2C Controller has started a transfer (after the 1st bit rising edge), it will wait for the current byte transfer to finish
(after the 9th bit (acknowledge) has been transmit) before generating the STOP condition. In this case, the timeout
timer will start counting after the end of the 9th bit low time.
77
DS4830 User’s Guide
Whenever SCL goes low. If the SCL line is low for a period longer than specified in the timeout register, the I2C
controller concludes that there is a bus error and will set the I2CTOI flag.
For all of these cases, when the I2C timeout period is reached, the I2CTOI flag will be set. The setting of I2CTOI can
generate an interrupt if enabled. If the master I2C controller is in the process of transferring data when the timeout occurs, the
controller will abort the current transfer and clear the I2CBUSY flag. The I2CBUS flag will continue to be set until a STOP
condition is detected or I2CEN is set to 0.
10.1.5 – Generating a START
To initiate a data transfer, the I2C master controller must first issue a START command. The master I2C controller’s flow
when attempting to issue a START command is shown in Figure 10-3. A START command is generated by setting the
I2CSTART bit to 1. The I2C controller will then determine the state of the I2C bus. If the bus is busy (I2CBUS = 1), the
controller will not generate a START until the bus is available. The I2C bus is considered busy if another master has
generated a START condition and no corresponding STOP has been detected (the I2CBUS bit is set to 1) or SCL is
being held low.
If the bus is not busy, the I2C master controller will attempt to generate a START. Because the SDA line is feedback
into the device, when the master generates a START, it can also detect the START condition. When a start condition is
detected, the I2C START interrupt flag (I2CSRI) will be set and an interrupt will be generated if enabled. The
I2CBUS bit will be set to indicate that the I2C bus is now in use and the I2CSTART bit will be cleared.
When the I2CSTART bit is set to a 1, the I2C controller will start its timeout timer if enabled (I2CTO_M ≠ 0). If the
timer expires before the START can be generated, the I2C timeout interrupt flag (I2CTOI) will be set and an interrupt
generated if enabled. If a timeout occurs, the I2C master controller will reset to an idle state and the I2CSTART bit will
be cleared.
If the I2CSTART bit is set when the I2C Controller is in the middle of a byte transfer (after the 1st bit rising edge), the
controller will wait for the current byte transfer to finish (after the 9th bit) before generating the START condition. In this
case, the timeout timer will not start counting until after the end of the 9th bit low time.
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DS4830 User’s Guide
Figure 10-3: Master I2C Generated START and STOP
10.1.6 – Generating a STOP
To end an I2C transfer, a STOP must be transmitted. A STOP is generated by setting the I2CSTOP bit. The master
I2C controller’s flow when attempting to issue a STOP command is shown in Figure 10-3.
If the I2CSTOP bit is set when the I2C Controller is in the middle of a byte transfer (after the 1st bit rising edge), it will wait for
the current byte transfer to finish (after the 9th bit) before generating the STOP condition.
Because the SDA line is feedback into the device, when the master generates a STOP, it will also detect the STOP
condition. When a STOP condition is detected, the I2C STOP interrupt flag (I2CSPI) will be set and an interrupt will be
generated enabled. The I2CBUS bit will be cleared to indicate that the I2C bus is now idle and the I2CSTOP bit will be
cleared.
When the master I2C controller attempts to generate the STOP condition, it will also start the timeout timer if this feature is
enabled. If a timeout is generated before the STOP condition is detected, a timeout will occur. When a timeout occurs,
the I2CTOI bit will be set, which can generate an interrupt if enabled, and the I2CSTOP bit will also be cleared to 0.
79
DS4830 User’s Guide
10.1.7 – Transmitting a Slave Address
The first byte after an I2C start or restart condition is the slave address byte. This byte, which is transmitted by the master,
contains seven bits of slave address followed by the R/W bit. The transmission of the slave address begins with writing
7bit slave address + the R/W bit to I2CBUF_M.
Figure 10-4 shows the format for slave address 36h in write mode. The address bits A[6:0], which is the slave address
the R/W bit is written to I2CBUF_M[6:0]. 0th bit of I2CBUF_M is copied to 0th bit I2CMODE of I2CSLA_M register. When the
0th bit is ‘1’, the I2C master is operating in receiver mode (data read from slave). When the 0th bit is ‘0’, the I2C master is
operating in transmitter mode (data write to slave).
Figure 10-4: Slave Address Format
After the slave address has been written to I2CBUF_M, the I2C master controller will set the I2CBUSY bit to indicate the
controller is actively participating in a transaction. The eight bits in I2CBUF_M[7:0] will be transmit on SDA. The data for
the 8th bit transmit, which is the R/W bit, is copied in the I2CMODE bit of the I2CSLA_M register. The I2C master then
issues the 9th clock, which is for the acknowledge bit, and reads SDA for an acknowledgment from a slave device. The
I2C master controller then performs the following steps. This is illustrated in Figure 10-5.
Set the I2CNACKI bit with the value of the received acknowledgement.
The I2CTXI bit will then be set to indicate a byte was transmit.
Clear the I2CBUSY flag.
Upon transmitting the slave data byte (7 bits of slave address + R/W bit + acknowledge), the I2C master controller will enter
one of the three states.
Data Transmit: The I2CMODE (R/W) bit was set to a 0, indicating that the master will be writing data to a slave
device. The DS4830 will retain control of the SDA line.
Data Receive: The I2CMODE (R/W) bit was set to a 1, indicating that the master will be receiving data from a
slave. The DS4830 releases control of SDA to allow a slave device to output data. The DS4830 Master I2C
controller automatically begins clocking bytes of data from the slave.
The slave address was NACK’d. The master I2C controller will retain control of SDA and is able to transmit data.
10.1.8 – Transmitting Data
The DS4830 I2C Master Controller enters into data transmission mode after transmitting a slave address with the R/W bit
(I2CMODE) set to a 0. The steps of data transmission are shown in Figure 10-5. Data transmission is started by software
loading a byte of data into the I2CBUF_M register. Loading I2CBUF_M causes the I2CBUSY bit to be set. Once set,
writes to I2CBUF_M will be ignored. The first bit of data (most significant bit) will be shifted to SDA when SCL is low.
Each of the next seven bits will then be shifted following high to low transitions of SCL.
Following the 8th bit of data (least significant bit) being shifted to SDA, the SDA line will be released by the DS4830 master
controller. This allows the slave to signal an ACK or NACK during the 9th clock cycle. The DS4830 I2C master controller
samples the acknowledge bit following the 9th SCL rising edge. After the acknowledge bit is sampled, the DS4830 I2C
master controller will perform the following tasks:
Set or clear the I2CNACKI flag to reflect the received acknowledge bit. The setting of I2CNACKI can generate an
interrupt if enabled.
Set the I2CTXI flag to indicate that the I2C master controller transmit a complete byte. This can generate an
interrupt if enabled.
Clear the I2CBUSY flag to indicate that the I2C master controller is not actively participating in the transfer of data.
80
I2CNACKI =
ACKNOWLEDGE
Transmit I2CBUF_M[7:0]
I2CBUF_M[0] I2CMODE
I2CBUSY=1
I2CTXI=1
I2CBUSY=0
Write to
I2CBUF_M
RECEIVE
ACKNOWLEDGE
Transmitting
Byte
Receiving
Byte
I2CNACKI =
ACKNOWLEDGE
Transmit Shift
Register Byte,
MSB First
N
Y
I2CBUSY=1
8 Bits
Transmit?
I2CTXI=1
I2CBUSY=0
Write to
I2CBUF_M
Receive a Bit into
Shift Register
MSB first
N
Y
I2CBUSY=1
8 Bits
Received?
Load Shift
Register into
I2CBUF_M
I2CRXI=1
Send
I2CACK
Y
N
I2CROI=1
Receiver
Full
?
First SCL
Rising Edge
Generated
I2CBUSY=0
RECEIVE
ACKNOWLEDGE
Transmitting
Slave Address
DS4830 User’s Guide
Figure 10-5: Master I2C Data Flow
10.1.9 – Receiving Data
The DS4830 I2C Master Controller enters data reception mode after transmitting a slave address with the R/W bit
(I2CMODE) set to a 1. The steps of data reception are shown in Figure 10-5. After transmitting the slave address, the
master controller will switch to receiver mode and automatically begin outputting SCL clock pulses and shifting in data
from SDA.
When receiving data, the DS4830 I2C master controller uses a double buffer consisting of the I2CBUF_M register and the
shift register. This allows the I2C module to continue receiving data while the previous data byte is being processed.
When a full byte of data (8 bits) has been received by the I2C master controller, the master must send an
acknowledgement to the slave. This occurs during the 9th clock cycle when the value in I2CACK is transmitted to the
slave.
After a complete byte (8 bits) of data is received, the I2C master controller will attempt to copy the received data from the
shift register to I2CBUF_M. There are two possible results from the I2C master controller’s attempt to copy the shift
register to I2CBUF_M.
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DS4830 User’s Guide
1. If I2CBUF_M is empty, the I2C master controller will copy the data from the shift register into I2CBUF_M. The
I2CRXI flag will be set to indicate a received byte is ready to be read. The setting of I2CRXI can generate an
interrupt if enabled.
2. If I2CBUF_M is full, the data in the shift register cannot be copied into I2CBUF_M. This causes a receive overrun
condition. The receive overrun flag, I2CROI, will be set which can generate an interrupt if enabled. I2CBUF_M
will be full if it was not read by software following the reception of a previous byte.
After receiving a byte of data and the I2CRXI flag being set, it is up to software to read I2CBUF_M prior to a second byte
being received. Reading the I2CBUF_M register returns the received data and also clears I2CBUF_M. As long as the
previous byte of data is read from I2CBUF_M before the next byte has completed, receive overrun will not occur.
When receive overrun is detected and I2CROI bit is set, the DS4830 master I2C controller will stop outputting SCL clocks
and not clock the acknowledge bit until the receive overrun condition is cleared. The receive overrun condition and the
I2CROI flag can only be cleared by software reading the first byte received from I2CBUF_M. When the receive overrun
condition is cleared, the I2C master controller will copy the second byte that was received into I2CBUF_M, and again set
I2CRXI to indicate a byte of data was received. The I2C master controller will resume clocking SCL after satisfying SCL
low time requirements.
The master I2C controller will continue to automatically clock bytes of data until any of the following conditions occur.
1) A receive overrun condition occurs.
2) A STOP command is issued (I2CSTOP=1) prior to the master I2C controller beginning to clock a new byte.
3) The master I2C controller has clock stretching enabled and the clock is currently being held low by the master.
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DS4830 User’s Guide
10.1.10 – I2C Master Clock Stretching
The Master I2C Controller is capable of clock stretching at the end of each transfer cycle. Clock stretching is when SCL is
held low. If the I2C Clock Stretch Enable bit (I2CSTREN) is set to a 1, the I2C controller will hold SCL low after the clock
pulse defined by the I2C Clock Stretch Select bit (I2CSTRS). If I2CSTRS=0, the I2C controller will hold SCL low after the
falling edge of the 9th clock pulse. If I2CSTRS=1, the I2C controller will hold SCL low after the falling edge of the 8th clock
pulse. When the I2C controller is holding SCL low, the I2C Clock Stretch Interrupt flag (I2CSTRI) will be set, which can
generate an interrupt if enabled. The I2C slave controller will hold SCL low until I2CSTRI is cleared to 0 by software.
If clock stretching is enabled after the 8
I2CACK bit until clock stretching is released by clearing I2CSTRI. This allows software time to examine the data that was
received prior to sending an ACK or NACK to the slave. The continuous output of I2CACK will occur even if the master
I2C controller is transmitting data. In this mode, the slave should be sending the acknowledgement. To allow the slave to
send the proper acknowledgement, the I2CACK bit should be set to a 1, which prompts the master I2C controller to
release SDA.
The Master I2C Controller may need to use clock stretching when receiving data from a slave. When receiving data, the
master I2C controller automatically generates clock pulses. Without using clock stretching, this automatic clock generation
is only halted when a STOP command is issued or a receive overrun occurs. If clock stretching is enabled, software can
control when each byte of data is clocked from the slave device.
10.1.11 – Resetting the I2C Master Controller
The I2C master controller can be reset by disabling the I2C master controller by writing ‘0’ at I2CEN = 0 in the I2CCN
I2CCN_M register. A reset will force the master I2C controller to release both MSDA and MSCL if they are being held low
by the I2C master controller. A reset may reset few or all bits of I2CCN, I2CST and I2CBUF I2C registers, and reset the
2
I
C master controller’s internal state machine. Following a reset, the I
can be used again.
After a reset, the master I2C controller will be in a known state but the slave devices may be in an unknown state. It is
recommended that the master I2C controller attempts to reset the slave devices prior to beginning communication. A
reset of slave devices can be performed by outputting at least 9 clock pulses on the MSCL line while MSDA is high. This
easiest way to achieve this is to use MSDA and MSCL as GPIO pins (see the GPIO section) while the master I2C
controller is disabled (I2CEN=0). After the 9 clock pulses, a STOP command should be generated. This can be done
either using GPIO, or by enabling the master I2C controller and generating a STOP.
th
clock pulse, the master I2C controller will continue outputting the value of the
2
C master controller must be re-initialized before it
83
DS4830 User’s Guide
10.1.12 – Operation as a Slave
The DS4830 contains two I2C interfaces, the master (MSDA and MSCL) and slave (DS4830 SDA and SCL pins). These
are two totally separate blocks within the DS4830. However, both of the blocks are identical. Because of this, it is
possible to operate the master as a slave and also operate the slave as a master.
To operate the master (MSDA and MSCL) as a slave I2C interface, the I2CMST bit in I2CCN_M needs to be set to a 0.
When the master is operating as a slave, it will use the same registers (I2CCN_M, I2CST_M, etc) that it uses for master
operation. However, the bits in these registers will have different functionality, as described in the I2C Slave Interface
Section. The I2CCN_M.SMB_MOD bit only affects the interface when it is operating as a slave. See the I2C Slave
Interface section for details on initializing and using a slave I2C interface.
10.1.13 – GPIO
When the I2C master controller is disabled (I2CEN=0), the MSDA and MSCL pins can be used as GPIO pins. The MSDA
pin is mapped to GPIO port P1.0 and MSCL is mapped to GPIO port P1.1. When used as GPIO outputs, the MSDA and
MSCL pins are push pull outputs. See the General-Purpose I/O Section for more information on using MSDA and MSCL
as GPIO pins.
84
DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - -
SMB_MOD
I2CSTREN
I2CGCEN
I2CSTOP
I2CSTART
I2CACK
I2CSTRS - -
I2CMST
I2CEN
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0
Access
r r r r r r rw
rw
rw
rw
rw
rw r r
rw*
rw*
BIT
NAME
DESCRIPTION
15:11
Reserved
Reserved. The user should write 0 to these bits.
10
SMB_MOD
SMBus Mode Enable. This bit enables the SMBUS timeout feature only when
the master I2C interface (MSDA and MSCL) is enabled to be a slave interface.
See the Operation as a Slave section for more details.
9
I2CSTREN
I2C Master Clock Stretch Enable. Setting this bit to ‘1’ will stretch the clock (hold
SCL low) at the end of the clock cycle specified by I2CSTRS. Clearing this bit
disables clock stretching.
8
I2CGCEN
I2C General Call Enable. This bit has no function when operating in master
mode.
7
I2CSTOP
I2C STOP Enable. Setting this bit to ‘1’ generates a STOP condition. This bit is
automatically cleared to ‘0’ after the STOP condition has been generated.
The setting of I2CSTOP will start the timeout timer if enabled. If the timeout timer
expires before the STOP condition is generated, the I2CTOI flag is set, which can
generate an interrupt if enabled. A timeout will also clear the I2CSTOP bit.
6
I2CSTART
I2C START Enable. Setting this bit to ‘1’ generates a START or repeated
START condition. This bit is automatically cleared to ‘0’ after the START
condition has been generated.
The setting of I2CSTART will start the timeout timer if enabled. If the timeout
timer expires before the START condition is generated, the I2CTOI flag is set,
which can generate an interrupt if enabled. A timeout will also clear the
I2CSTART bit.
5
I2CACK
I2C Master Data Acknowledge Bit. This bit selects the acknowledge bit returned
by the master I2C controller while acting as a receiver. Setting this bit to ‘1’ will
generate a NACK (leaving SDA high). Clearing the I2CACK bit to ‘0’ will generate
an ACK (pulling SDA LOW) during the acknowledgement cycle. This bit will retain
its value unless changed by software or hardware.
4
I2CSTRS
I2C Master Clock Stretch Select. Setting this bit to ‘1’ will enable clock
stretching after the falling edge of the 8th clock cycle. Clearing this bit to ‘0’ will
enable clock stretching after the falling edge of the 9th clock cycle. This bit has no
effect when clock stretching is disabled (I2CSTREN=0).
3:2
Reserved
Reserved. The user should write 0 to these bits.
1
I2CMST
I2C Master Mode Enable. Setting this bit to ‘1’ will enable I2C master functionality
on the MSDA and MSCL pins. Setting this bit to ‘0’ enables I2C slave
functionality. See the I2C Slave Interface section for more details.
0
I2CEN
I2C Enable. This bit enables the I2C Master interface. When set to ‘1’, the I2C
Master Interface is enabled. When cleared to ‘0’, the I2C function is disabled.
10.2 – I2C Master Controller Register Description
Following are the registers that are used to control the I2C Master Interface, which is the MSDA and MSCL pins. These
registers are used to control the I2C master interface if it is operating as either a master or slave. The bit descriptions
below detail how to use these registers when operating in master mode. When operating in slave mode, some of the bits
and registers have different functionality. See the I2C Slave Interface for more information on how to control the I2C
Master Interface when it is operating as a slave.
10.2.1 – I2C Master Control Register (I2CCN_M)
Address: M1[0Ch]
* Unrestricted Read. Unrestricted write access when I2CBUSY=0. Writes to I2CEN are disabled when I2CBUSY=1.
Notes: The I2CSTART and I2CSTOP are mutually exclusive. If both bits are set at the same time, it is considered an
invalid operation and the I2C controller ignores the request and resets both bits to 0. Setting the I2CSTART bit to 1 while
I2CSTOP = 1 is an invalid operation and is ignored, leaving the I2CSTART bit cleared to 0.
85
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
I2CBUS
I2CBUSY - -
I2CSPI
I2CSCL
I2CROI
I2CGCI
I2CNACKI
-
I2CAMI
I2CTOI
I2CSTRI
I2CRXI
I2CTXI
I2CSRI
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r*
r* r r
rw
r*
rw
rw
rw* r rw
rw
rw*
rw*
rw
rw
BIT
NAME
DESCRIPTION
15
I2CBUS
I2C Master Bus Busy. This bit is set to ‘1’ when a START/repeated START
condition is detected and cleared to 0 when the STOP condition is detected. This bit
is reset to ‘0’ when I2CEN=0. This bit is controlled by hardware and is read only.
14
I2CBUSY
I2C Master Busy. This bit is used to indicate the current status of the I2C controller.
The I2CBUSY is set to ‘1’ when the I2C controller is actively participating in a
transaction. This bit is controlled by hardware and is read only.
13:12
Reserved
Reserved. The user should write 0 to these bits.
11
I2CSPI
I2C Master STOP Interrupt Flag. This bit is set to ‘1’ when a STOP condition is
detected. This bit must be cleared to ‘0’ by software once set. Setting this bit to ‘1’
by software will cause an interrupt if enabled.
10
I2CSCL
I2C Master SCL Status. This bit reflects the logic state of the SCL signal. This bit is
set to ‘1’ when SCL is at a high logic level and cleared to ‘0’ when SCL is at a low
logic level. This bit is controlled by hardware and is read only.
9
I2CROI
I2C Master Receiver Overrun Flag. This bit indicates a receive overrun when set to
‘1’. This bit is set to ‘1’ if the receiver has received two bytes since the last software
reading of I2CBUF_M. This bit can only be cleared to ‘0’ by software reading
I2CBUF_M. Setting this bit to ‘1’ by software will cause an interrupt if enabled.
8
I2CGCI
I2C General Call Interrupt Flag. This bit has no function when operating in master
mode.
7
I2CNACKI
I2C Master NACK Interrupt Flag. This bit is set by hardware to ‘1’ if a NACK was
received from a slave or a 0 if an ACK was received from a slave. The setting of
this bit to ‘1’ will cause an interrupt if enabled. This bit can be cleared to ‘0’ by
software once set. This bit is set by hardware only.
6
Reserved
Reserved. The user should write 0 to this bit.
5
I2CAMI
I2C Address Match Interrupt Flag. This bit has no function when operating in
master mode.
4
I2CTOI
I2C Master Timeout Interrupt Flag. This bit is set to ‘1’ if the I2C controller cannot
generate a START or STOP condition or the SCL low time is greater than the
timeout value specified in the I2CTO_M register. This bit must be cleared to ‘0’ by
software once set. Setting this bit to ‘1’ by software causes an interrupt if enabled.
3
I2CSTRI
I2C Master Clock Stretch Interrupt Flag. This bit is set to ‘1’ to indicate that the I2C
master controller is operating with clock stretching enabled and is currently holding
the SCL clock signal low. The I2C controller will release SCL after this bit has been
cleared to ‘0’. This bit must be cleared to ‘0’ by software once set. This bit is set by
hardware only.
2
I2CRXI
I2C Master Receive Ready Interrupt Flag. This bit is set to ‘1’ to indicate that a
data byte has been received in I2CBUF_M. This bit must be cleared to ‘0’ by
software once set. This bit is set by hardware only.
1
I2CTXI
I2C Master Transmit Complete Interrupt Flag. This bit is set to ‘1’ to indicate that
an address or a data byte has been successfully shifted out and the I2C controller
has received an acknowledgment from the receiver (ACK or NACK). This bit must
be cleared to ‘0’ by software once set. Setting this bit to ‘1’ by software will cause an
interrupt if enabled.
0
I2CSRI
I2C Master START Interrupt Flag. This bit is set to ‘1’ when a START condition (or
restart) is detected. This bit must be cleared to ‘0’ by software once set. Setting this
bit to ‘1’ by software will cause an interrupt if enabled.
10.2.2 – I2C Master Status Register (I2CST_M)
Address: M1[01h]
* Set by hardware only.
DS4830 User’s Guide
86
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - I2CSPIE
-
I2CROIE
I2CGCIE
I2CNACKIE
-
I2CAMIE
I2CTOIE
I2CSTRIE
I2CRXIE
I2CTXIE
I2CSRIE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r rw r rw
rw
rw r rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:12
Reserved
Reserved. The user should write 0 to these bits.
11
I2CSPIE
I2C Master STOP Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt
when a STOP condition is detected (I2CSPI=1). Clearing this bit to ‘0’ will disable
the STOP detection interrupt.
10
Reserved
Reserved. The user should not write to this bit.
9
I2CROIE
I2C Master Receiver Overrun Interrupt Enable. Setting this bit to ‘1’ will enable
an interrupt when a receiver overrun condition is detected (I2ROI=1). Clearing this
bit to ‘0’ will disable the receiver overrun detection interrupt.
8
I2CGCIE
I2C General Call Interrupt Enable. This bit has no function when operating in
master mode.
7
I2CNACKIE
I2C Master NACK Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt
when a NACK is detected (I2CNACKI=1). Clearing this bit to ‘0’ will disable the
NACK detection interrupt.
6
Reserved
Reserved. The user should write 0 to this bit.
5
I2CAMIE
I2C Address Match Interrupt Enable. This bit has no function when operating in
master mode.
4
I2CTOIE
I2C Master Timeout Interrupt Enable. Setting this bit to ‘1’ will enable an
interrupt when a timeout condition is detected (I2CTOI=1). Clearing this bit to ‘0’
will disable the timeout interrupt.
3
I2CSTRIE
I2C Master Clock Stretch Interrupt Enable. Setting this bit to ‘1’ will enable an
interrupt when the clock stretch interrupt flag is set (I2CSTRI=1). Clearing this bit
will disable the clock stretch interrupt.
2
I2CRXIE
I2C Master Receive Ready Interrupt Enable. Setting this bit to ‘1’ will enable an
interrupt when receive ready interrupt flag is set (I2CRXI=1). Clearing this bit to ‘0’
will disable the receive ready interrupt.
1
I2CTXIE
I2C Master Transmit Complete Interrupt Enable. Setting this bit to ‘1’ will enable
an interrupt when transmit complete interrupt flag is set (I2CTXI=1). Clearing this
bit to ‘0’ disables transmit complete interrupt.
0
I2CSRIE
I2C Master START Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt
when a START condition is detected (I2CSRI=1). Clearing this bit to ‘0’ will
disable the START detection interrupt.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - - - - - D7
D6
D5
D4
D3
D2
D1
D0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
BIT
NAME
DESCRIPTION
15:8
Reserved
Reserved. The user should write 0 to these bits.
7:0
D[7:0]
Data for I2C transfer is read from or written to this location. The I2C transmit and receive buffers are
separate but both are addressed at this location.
10.2.3 – I2C Master Interrupt Enable Register (I2CIE_M)
Address: M1[02h]
DS4830 User’s Guide
10.2.4 – I2C Master Data Buffer Register (I2CBUF_M)
Address: M1[00h]
* Unrestricted read access. This register can be written to only when I2CBUSY = 0.
87
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
I2CCKH7
I2CCKH6
I2CCKH5
I2CCKH4
I2CCKH3
I2CCKH2
I2CCKH1
I2CCKH0
I2CCKL7
I2CCKL6
I2CCKL5
I2CCKL4
I2CCKL3
I2CCKL2
I2CCKL1
I2CCKL0
Reset
0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:8
I2CCKH[7:0]
I2C Clock High Period. These bits define the high period of the I
2
C clock. This period
is defined by the number of system clocks. The high time duration is calculated using the
following equation:
I2C High Time Period = System Clock Period x (I2CCKH[7:0] + 1)
I2CCKH[7:0] must be set to a minimum value of 2 to ensure proper operation. Any value
less than 2 will be set to 2.
7:0
I2CCKL[7:0]
I2C Clock Low Period. These bits define the low period of the I
2
C clock. This period is
defined by the number of system clocks. The low time duration is calculated using the
following equation:
I2C Low Time Period = System Clock Period x (I2CCKL[7:0] + 1)
I2CCKL[7:0] must be set to a minimum value of 4 to ensure proper operation. Any value
less than 4 will be set to 4.
Bit 7 6 5 4 3 2 1 0
Name
I2CTO7
I2CTO6
I2CTO5
I2CTO4
I2CTO3
I2CTO2
I2CTO1
I2CTO0
Reset
0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - - - - - A6
A5
A4
A3
A2
A1
A0
I2CMODE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r rw
rw
rw
rw
rw
rw
rw
rw
10.2.5 – I2C Master Clock Control Register (I2CCK_M)
Address: M1[0Dh]
10.2.6 – I2C Master Timeout Register (I2CTO_M)
Address: M1[0Eh]
DS4830 User’s Guide
The I2CTO_M register determines the length of the timeout interval. The timeout interval is defined by the number of I2C bit periods
(SCL high + SCL low). When cleared to 00h, the timeout function is disabled. When set to any other value, the I2C controller waits until
the timeout expires and sets the I2CTOI flag. The timeout period is:
I2C Timeout = I2C Bit Rate x (I2CTO[7:0] + 1)
The timeout timer resets to 0 and starts to count after each of the following events.
The I2CSTART bit is set.
The I2CSTOP bit is set.
Any time that SCL goes low.
10.2.7 – I2C Master Address Register (I2CSLA_M)
Address: M1[0Fh]
This register has no function when operating in master mode.
88
DS4830 User’s Guide
Detect STOP
I2CSPI=1
I2CBUS=0
1
Y
I2CNACKI
Receive
Slave
Address
Transmit
Data
Detect START
I2CSRI=1
I2CBUS=1
I2CBUSY=1
I2CAMI=1
?
Y
N
STOP ?
0
N
R/W Bit
I2CMODE
Receive
Data
Y
STOP ?
N
0
1
SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE
The DS4830 provides an I2C-compatible slave controller that allows the DS4830 to communicate with a host device. This
controller can also operate as an SMBUS slave. Also designed into the I2C slave controller is the ability to bootload the
DS4830 with new user Flash memory. The I2C slave interface can be setup to provide system interrupts after each I2C
event. Figure 11-1 shows the basic operation flow of the I2C slave controller. The blocks in Figure 11-1 that are shaded
are shown in more detail in Figure 11-2.
Figure 11-1: Slave I2C Flow
89
DS4830 User’s Guide
11.1 – Detailed Description
11.1.1 – Default Operation
The I2C slave controller is enabled (I2CCN_S.I2CEN=1) by default. As long as the I2C slave controller is enabled, the
DS4830 I2C bootloader can operate. This allows bootloading of blank devices without any setup of the I2C slave
controller. Prior to the I2C slave controller being used for normal data communication, some software setup will be
required. This setup will include setting an I2C slave address and telling the slave controller which I2C events should
generate interrupts.
11.1.2 – Slave Address
Prior to communication, an I2C slave address may need to be selected. The I2C slave controller normally responds to two
slave addresses. The I2C bootloader uses address 34h. This bootloader address cannot be changed and should not be
used as the device slave address for normal communication. The second slave address is the address used for
communication with the host. This slave address is set using the I2CSLA_S register. The address contained in the
I2CSLA_S register is the address with the R/W bit. If an address other than 36h is desired, the I2CSLA_S register can be
programmed with this new address. The I2C slave controller can also be programmed to respond to a third address, the
General Call Address, which is 00h. This feature can be enabled by setting the I2CCN_S.I2CGCEN bit to a 1.
11.1.3 – I2C Start Detection
The I2C Slave Controller always monitors the I2C bus for an I2C start, which is a high to low transition on SDA while SCL is
held high. If an I2C start (or restart) condition is detected, the I2C slave will set the I2CSRI bit in the I2CST_S register,
which can cause an interrupt if enabled. The detection of a start brings the I2C controller out of its idle state. Following a
start, the I2C controller begins to monitor data on the I2C bus and the I2CBUSY bit will be set to a 1. The I2CBUS bit will
also be set to a one to indicate that the I2C bus is currently busy.
11.1.4 – I2C Stop Detection
The I2C Slave Controller also always monitors the I2C bus for an I2C stop, which is a low to high transition on SDA while
SCL is held high. If an I2C stop condition is detected, the I2C slave controller will set the I2CSPI bit in the I2CST_S
register, which can cause an interrupt if enabled. The I2CBUS bit will be cleared to 0 following a stop to indicate that the
I2C bus is no longer busy.
11.1.5 – Slave Address Matching
Following an I2C start or restart, the I2C slave controller knows that the next byte of data transmit by the host should be
the slave address. The I2C slave automatically monitors for the slave address without any software interaction required.
The I2C slave controller compares the first 7 bits received to the slave address programmed into I2CSLA_S.
After receiving the first 8 bits of data following a start, the I2C controller compares the first 7 bits to the value programmed
into the I2CSLA_S register. If the received slave address matches I2CSLA_S, the I2C slave controller does the following
steps. This is illustrated in Figure 11-2.
Transmit an ACK or NACK on the 9th clock based upon the setting of the I2CCN_S.I2CACK bit.
Set the I I2CSLA _S_I2CMODE bit with the value of the received R/W bit. This bit can be used by software to
determine if the I2C slave controller will be asked to receive or transmit data.
Set the I2CST_S.I2CAMI bit to indicate that a slave address match was made. The setting of this bit can
generate an interrupt if enabled.
Clears the I2CBUSY flag.
Upon completion of the slave data byte (7 bits of slave address + R/W bit + ACK/NACK), the I2C slave controller will enter
one of three states.
Data Transmit: The slave address matched and the R/W bit was a 1. The host is now expecting to clock data from
the DS4830. The DS4830 retains control of the SDA line so data can be transmitted to the host.
Data Receive: The slave address matched and the R/W bit was a 0. The host wants to write data to the DS4830.
After the ACK/NACK bit, the DS4830 releases SDA and prepares to receive a byte of data.
Wait for Start/Stop: The received slave address did not match I2CSLA_S. The controller enters idle state and
waits for the next start condition or stop condition.
90
Transmitting
Byte
Receiving
Byte
Y
Receive
Addr[6:0] + R/W
Match
I2CSLA_S[7:1]
?
Transmit
I2CACK
I2CBUSY=0
N
I2CAMI=1
Set
I2CMODE
According to R/W
Detect START
I2CSRI=1
I2CBUS=1
I2CBUSY=1
I2CNACKI =
ACKNOWLEDGE
Transmit Shift
Register Byte,
MSB First
N
Y
I2CBUSY=1
8 Bits
Transmit
?
I2CTXI=1
I2CBUSY=0
Write to
I2CBUF_S
Receive a Bit into
Shift Register
,
MSB first
N
Y
I2CBUSY=1
8 Bits
Received
?
Load Shift
Register into
I2CBUF_S
I2CRXI=1
Send
I2CACK
Y
N
I2CROI=1
Receiver
Full
?
Detect 1
st
SCL
Rising Edge
I2CBUSY=0
Receiving Slave
Address
RECEIVE
ACKNOWLEDGE
DS4830 User’s Guide
Figure 11-2: Slave I2C Data Flow
11.1.6 – Transmitting Data
The DS4830 I2C Slave Controller enters into data transmission mode after receiving a matching slave address with the
R/W bit set to a 1. The steps of data transmission are shown in Figure 11-2. Data transmission is started by software
loading a byte of data into the I2CBUF_S register. Loading I2CBUF_S causes the I2CBUSY bit in I2CST_S to be set.
Once set, a write to I2CBUF_S will be ignored. The first bit of data (most significant bit) will be shifted to SDA when SCL
is low. Each of the next seven bits will then be shifted following high to low transitions of SCL.
91
DS4830 User’s Guide
Following the 8th data (least significant bit) being shifted to SDA, the SDA line will be released by the DS4830 slave
controller. This allows the host to signal an ACK or NACK during the 9th clock cycle. The DS4830 I2C slave controller
samples the acknowledge bit following the rising 9th SCL rising edge. After the acknowledge bit is sampled, the DS4830
I2C slave controller will perform the following tasks:
Set the I2CST_S.I2CTXI flag to indicate that the I2C slave controller transmit a complete byte. This can generate
an interrupt if enabled.
Set or clear the I2CST_S.I2CNACKI flag to reflect the received acknowledge bit. The setting of I2CNACKI can
generate and interrupt if enabled.
Clear the I2CST_S.I2CBUSY flag to indicate that the I2C slave controller is not actively participating in the transfer
of data.
The detection of an ACK by the DS4830 I2C slave controller indicates that the host wants to receive another byte of data.
The I2C slave controller will maintain control of SDA following the ACK. The next byte to transmit needs to be loaded into
I2CBUF_S prior to the host starting to clock this next byte. However, data cannot be loaded into I2CBUF_S prior to
I2CBUSY being cleared, which indicates that all the bits in I2CBUF_S have been shifted onto SDA.
The detection of a NACK indicates that the host does not want to receive any additional data. The DS4830 I2C slave
controller will release control of SDA following the reception of the NACK bit. After the NACK, the slave controller enters
idle state and monitors the I2C bus for a start or stop condition.
11.1.7 – Receiving Data
The DS4830 I2C Slave Controller enters data reception mode after receiving a matching slave address with the R/W bit set
to a 0. The steps of data reception are shown in Figure 11-2. The reception process begins when the I2C slave controller
detects the first rising edge of SCL. This first rising edge will set I2CBUSY and also clock the first bit (MSB) of data from
SDA into the data shift register.
When receiving data, the DS4830 I2C slave controller uses a double buffer consisting of the I2CBUF_S register and the
shift register. This allows the I2C module to continue receiving data while the previous data byte is being processed.
After a complete byte (8 bits) of data is received, the I2C slave controller will attempt to copy the received data from the
shift register to I2CBUF_S. There are two possible results from the I2C slave controllers attempt to copy the shift register
to I2CBUF_S.
1. If I2CBUF_S is empty, the I2C slave controller will copy the data from the shift register into I2CBUF_S. The
I2CRXI flag will be set to indicate a received byte is ready to be read. The setting of I2CRXI can generate an
interrupt if enabled.
2. If I2CBUF_S is full, the data in the shift register cannot be copied into I2CBUF_S. This causes a receive overrun
condition. The receive overrun flag, I2CROI, will be set which can generate an interrupt if enabled. I2CBUF_S
will be full if it was not read by software following the reception of a previous byte.
After receiving a byte of data and the I2CRXI flag being set, it is up to software to read I2CBUF_S prior to a second byte
being received. Reading the I2CBUF_S register returns the received data and also clears I2CBUF_S. As long as the
previous byte of data is read from I2CBUF_S before the next byte has completed, receive overrun will not occur.
When in receive overrun and the I2CROI bit is set, any new incoming data will not be shifted into the I2C slave controller.
The controller will respond to any bytes received with a NACK regardless of the setting of the I2CACK bit. The receive
overrun condition and the I2CROI flag can only be cleared by software reading the first byte received from I2CBUF_S.
When the receive overrun condition is cleared, the I2C slave controller will copy the second byte that was received into
I2CBUF, and again set I2CRXI to indicate a byte of data was received. The I2C slave controller will resume its normal
operation in the next SCL clock cycle after I2CROI is cleared. To avoid losing any data, I2CROI must to be cleared prior
to the 1st SCL clock rising edge of the next byte.
After the 9th bit of any byte has been received, the I2CBUSY bit will be cleared to indicate that the controller is no longer
participating in a data transaction. The value in I2CACK will be transmitted to the host on the 9th SCL clock cycle,
assuming the I2C slave controller is not operating in receive overrun.
92
DS4830 User’s Guide
11.1.8 – Clock Stretching
If a slave device cannot receive or transmit another complete byte of data, it may hold SCL low, forcing the master to wait.
Data transfer will continue when the slave is ready for another byte of data and releases SCL.
The I2C slave controller is capable of holding SCL low at the completion of each byte being transferred. If the I2C Clock
Stretch Enable bit (I2CSTREN) is set to a 1, the I2C controller will hold SCL low after the clock pulse defined by the I2C
Clock Stretch Select bit (I2CSTRS). If I2CSTRS=0, the I2C controller will hold SCL low after the falling edge of the 9th
clock pulse. Otherwise, if I2CSTRS=1, the I2C controller will hold SCL low after the falling edge of the 8th clock pulse.
When the I2C controller is holding SCL low, the I2C Clock Stretch Interrupt bit (I2CSTRI) will be set. The I2C slave
controller will hold SCL low until I2CSTRI is cleared to '0' by software. Figure 11-3 shows the I2C slave controller clock
stretching after receiving the 9th clock of a byte.
Figure 11-3: Slave I2C Clock Stretching
Normally when the I2C slave controller is receiving data, the value of I2CACK will be output after the 8th clock falling
edge. However, if clock stretching is enabled after the 8th clock, the I2C slave controller will continually output the I2CACK
bit until clock stretching is released by software. This allows software time to inspect data that was received before
responding with an appropriate acknowledge bit.
Most applications that use the DS4830’s I
will be set to only respond to interrupts from the I2C slave controller, thus not having to continuously poll the slave I2C
controller. After each byte transfer is complete, the I2C slave controller needs to either read the received byte from
I2CBUF_S or write the next byte to transmit to I2CBUF_S. Without using clock stretching, the host can begin clocking the
next byte before the I2C slave controller is prepared. A few conditions that may require clock stretching to be enabled are
listed below.
When a slave address match is made and the R/W bit is set, the I2C slave controller will be expected to transmit a
byte of data to the host. This byte of data needs to be written to I2CBUF_S after the 8th clock of the slave
address (when I2CBUSY is cleared) and prior to the 1st clock of the data byte. If clock stretching is not used,
software may not be able to write the correct data into I2CBUF_S prior to the 1st clock of the data byte.
Following the transmission of one byte of data to the host, another byte may be requested by the host sending an
ACK bit. The I2C slave controller has between the 9th clock of the first data byte (when I2CBUSY is cleared) and
the 1st clock of the second byte to write to I2CBUF_S. If clock stretching is not used, software may not be able to
write the next byte to I2CBUF_S prior to the 1st clock of the second byte.
After a byte is received by the I2C slave controller it may be necessary to stretch the clock. This will allow
software time to read the byte from I2CBUF_S and do any data processing. Without using clock stretching, there
is a chance that a second byte could be sent prior to the software reading the first byte, creating a receive overrun
condition. Any additional data that is sent after this time will be lost.
11.1.9 – SMBus Timeout
The I2C slave controller can also be used for SMBus or PMBus™ communication. To maintain SMBus compatibility, a
30ms timer is implemented by the I2C slave controller. The purpose of this timer is to issue a timeout interrupt when SCL
is low for greater than 30ms. The timer only starts when none of the following conditions are true:
2
C slave controller will need to use clock stretching. Generally the application
93
DS4830 User’s Guide
1. The I2C slave controller is in the idle state and there is no communications on the I2C bus. The timer should not
generate interrupts if the I2C slave controller is in the idle state regardless of how long SCL is low.
2. The SMBUS mode bit is not set. This ensures the SMBUS timeout functionality does not interfere with normal I2C
functionality.
3. SCL is high. The timer is inactive whenever SCL is high. The timer resets when it is inactive.
4. The I2C slave controller is disabled or used as a master I2C controller. The timer is not needed in this case.
The following description explains when the SMBus timer starts, assuming that all other start conditions are met. When
the DS4830’s I2C slave controller is idle and it receives a START, it will exit the idle state and the timer will become active
(starts counting) any time SCL goes low. If following the start, the master addresses a different slave on the bus, the I2C
slave controller will return to the idle state and the timer will reset and become inactive. In short, as soon as SCL goes low
following a START, the SMBus timer will become active until the I2C slave controller re-enters idle state.
When a timeout occurs, the timeout bit (I2CTOI) will be set, which can generate an interrupt if enabled. If a timeout
occurs, it may be necessary to reset the I2C slave controller. See Resetting the I2C Slave Controller for more details.
SMBus mode selection is controlled by the SMB_MOD bit in I2CCN_S register. When the Slave SMBus Mode Operation
bit (SMB_MOD) is set to 1, the SMBUS timeout functionality will be enabled.
11.1.10 – Resetting the I2C Slave Controller
2
The I
C Slave Controller can be reset by disabling the I2C Slave controller by writing ‘0’ at I2CEN = 0 in I2CCN register.
A reset will force the I2C slave controller to release both SDA and SCL if they are being held low by the I2C slave
controller. The reset may reset few or all bits of I2CCN, I2CST and I2CBUF registers and reset the internal state machine
of the I2C slave controller. Following a reset, the I2C slave controller must be re-initialized.
11.1.11 – Operation as a Master
The DS4830 contains two I2C interfaces, the slave (SDA and SCL) and master (MSDA and MSCL). These are two totally
separate blocks within the DS4830. However, both of the blocks are identical. Because of this, it is possible to operate
the slave as a master and also operate the master as a slave.
To operate the slave (SDA and SCL) as a master I2C interface, the I2CMST bit in I2CCN_S needs to be set to a 1. When
the slave is operating as a master, it will use the same registers (I2CCN_S, I2CST_S, etc) that it uses for slave operation.
However the bits in these registers will have different functionality, as described in the I2C Master Interface Section. The
I2CCN_S.SMB_MOD bit has no effect when the interface is operating in master mode. See the I2C Master Interface
section for details on initializing and using a master I2C interface.
Note: When the I2C slave interface is changed to operate in master mode, the I2C bootloader will not be available.
Note: When the I2C slave interface is disabled, the I2C bootloader will not be available.
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DS4830 User’s Guide
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - -
SMB_MOD
I2CSTREN
I2CGCEN
I2CSTOP
I2CSTART
I2CACK
I2CSTRS - -
I2CMST
I2CEN
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Access
r r r r r r rw*
rw* r r
rw*
rw* r r r rw*
BIT
NAME
DESCRIPTION
15:11
Reserved
Reserved. The user should write 0 to these bits.
10
SMB_MOD
Slave SMBUS Mode Operation. When this bit is set to a ‘1’, SMBus timeout functionality is enabled for the
I2C slave interface. When this bit is cleared to ‘0’, the SMBus timeout functionality is disabled. See the
SMBus Timeout section for more details.
9
I2CSTREN
I2C Slave Clock Stretch Enable. Setting this bit to '1' will stretch the clock (holds SCL low) at the end of the
clock cycle specified in I2CSTRS. Clearing this bit disables clock stretching.
8
I2CGCEN
I2C Slave General Call Enable. Setting this bit to '1' will enable the I2C to respond to a general call address
(address = 0000 0000). Clearing this bit to '0' will disable response to general call address.
7
I2CSTOP
This bit has no function when operating in slave mode.
6
I2CSTART
This bit has no function when operating in slave mode.
5
I2CACK
I2C Slave Data Acknowledge Bit. This bit selects the acknowledge bit returned by the I2C controller while
acting as a receiver. Setting this bit to ‘1’ will generate a NACK (leaving SDA high). Clearing the I2CACK bit
to ‘0’ will generate an ACK (pulling SDA LOW) during the acknowledgement cycle. This bit will retain its
value unless changed by software or hardware.
4
I2CSTRS
I2C Slave Clock Stretch Select. Setting this bit to ‘1’ will enable clock stretching after the falling edge of the
8th clock cycle. Clearing this bit to ‘0’ will enable clock stretching after the falling edge of the 9th clock cycle.
This bit has no effect when clock stretching is disabled (I2CSTREN=0).
3:2
Reserved
Reserved. The user should write 0 to these bits.
1
I2CMST
I2C Master Mode Enable. Setting this bit to ‘1’ will enable I2C master functionality on the SDA and SCL
pins. See the I2C Master Interface section for more details. Setting this bit to ‘0’ enables I2C slave
functionality.
0
I2CEN
I2C Slave Enable. This bit enables the I2C Slave function. When set to ’1’, I2C Slave communication is
enabled. When cleared to ‘0’, the I2C function is disabled.
11.2 – I2C Slave Controller Register Description
Following are the registers that are used to control the I2C Slave Interface, which is the SDA and SCL pins. These
registers are used to control the I2C slave interface if it is operating as either a slave or master. The bit descriptions below
detail how to use these registers when operating in slave mode. When operating in master mode, some of the bits and
registers have different functionality. See the I2C Master Interface for more information on how to control the I2C Slave
Interface when it is operating as a master.
11.2.1 – I2C Slave Control Register (I2CCN_S)
Address: M2[0Ch]
* Unrestricted Read. Unrestricted write access when I2CBUSY=0. Writes to I2CEN are disabled when I2CBUSY=1.
95
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
I2CBUS
I2CBUSY - -
I2CSPI
I2CSCL
I2CROI
I2CGCI
I2CNACKI
-
I2CAMI
I2CTOI
I2CSTRI
I2CRXI
I2CTXI
I2CSRI
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r*
r* r r
rw
r*
rw
rw
rw* r rw
rw
rw*
rw*
rw
rw
BIT
NAME
DESCRIPTION
15
I2CBUS
I2C Slave Bus Busy. This bit is set to ‘1’ when a START/repeated START condition is detected and cleared
to '0' when the STOP condition is detected. This bit is reset to ‘0’ on all forms of reset or when I2CEN=0.
This bit is controlled by hardware and is read only.
14
I2CBUSY
I2C Slave Busy. This bit is used to indicate the current status of the I2C module. The I2CBUSY is set to '1'
when the I2C controller is actively participating in a transaction. This bit is controlled by hardware and is read
only.
13:12
Reserved
Reserved. The user should write 0 to these bits.
11
I2CSPI
I2C Slave STOP Interrupt Flag. This bit is set to '1' when a STOP condition is detected. This bit must be
cleared to '0' by software once set. Setting this bit to '1' by software will cause an interrupt if enabled.
10
I2CSCL
I2C Slave SCL Status. This bit reflects the logic state of SCL signal. This bit is set to '1' when SCL is at a
logic high (1), and cleared to '0' when SCL is at a logic low (0). This bit is controlled by hardware and is read
only.
9
I2CROI
I2C Slave Receiver Overrun Flag. This bit indicates a receive overrun when set to '1'. This bit is set to ‘1’ if
the receiver has received two bytes since the last CPU read of I2CBUF_S. This bit can only be cleared to '0'
by software reading the I2CBUF_S. Setting this bit to 1 by software will cause an interrupt if enabled.
8
I2CGCI
I2C Slave General Call Interrupt Flag. This bit is set to '1' when the general call is enabled (I2CGCEN=1)
and the general call address (00h) is received. This bit must be cleared to '0' by software once set. Setting
this bit to '1' by software will cause an interrupt if enabled.
7
I2CNACKI
I2C Slave NACK Interrupt Flag. This bit is set by hardware to either a ‘1’ if a NACK was received from the
host or a ‘0’ if an ACK was received from the host. The setting of this bit to a ‘1’ will cause an interrupt if
enabled. This bit can be cleared to ‘0’ by software once set.
6
-
Reserved. The user should write 0 to this bit.
5
I2CAMI
I2C Slave Address Match Interrupt Flag. This bit is set to '1' when the I2C controller receives an address
that matches the contents of the slave address register (I2CSLA_S). This bit must be cleared to '0' by
software once set. Setting this bit to ‘1’ by software will cause an interrupt if enabled.
4
I2CTOI
I2C Slave Timeout Interrupt Flag. This bit is set to ‘1’ if SMBUS timeout is enabled and SCL is low longer
than 30ms. This bit must be cleared to ‘0’ by software once set. Setting this to ’1’ will cause an interrupt if
enabled.
3
I2CSTRI
I2C Slave Clock Stretch Interrupt Flag. This bit indicates that the I2C slave controller is operating with
clock stretching enabled and is currently holding the SCL clock signal low. The I2C controller will release
SCL after this bit has been cleared to '0'. This bit must be cleared to '0' by software once set. This bit is set
by hardware only.
2
I2CRXI
I2C Slave Receive Ready Interrupt Flag. This bit indicates that a data byte has been received in the I2C
buffer. This bit must be cleared by software once set. This bit is set by hardware only.
1
I2CTXI
I2C Slave Transmit Complete Interrupt Flag. This bit indicates that an address or a data byte has been
successfully shifted out and the I2C controller has received an acknowledgment from the receiver (NACK or
ACK). This bit must be cleared by software once set. Setting this bit to ‘1’ by software will cause an interrupt
if enabled.
0
I2CSRI
I2C Slave START Interrupt Flag. This bit is set to '1' when a START condition (or restart) is detected. This
bit must be cleared to '0' by software once set. Setting this bit to '1' by software will cause an interrupt if
enabled.
11.2.2 – I2C Slave Status Register (I2CST_S)
Address: M2[01h]
* Set by hardware only.
DS4830 User’s Guide
96
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - I2CSPIE
-
I2CROIE
I2CGCIE
I2CNACKIE
-
I2CAMIE
I2CTOIE
I2CSTRIE
I2CRXIE
I2CTXIE
I2CSRIE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r rw r rw
rw
rw r rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:12
Reserved
Reserved. The user should write 0 to these bits.
11
I2CSPIE
I2C Slave STOP Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU when a STOP
condition is detected (I2CSPI=1). Clearing this bit to ‘0’ will disable the STOP detection interrupt.
10
Reserved
Reserved. The user should write 0 to this bit.
9
I2CROIE
I2C Slave Receiver Overrun Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU when
a receiver overrun condition is detected (I2ROI=1). Clearing this bit to ‘0’ will disable the receiver overrun
detection interrupt.
8
I2CGCIE
I2C Slave General Call Interrupt Enable. Setting this bit to '1' will cause an interrupt to the CPU when a
general call is detected (I2CGCI=1). Clearing this bit to '0' will disable the general call interrupt.
7
I2CNACKIE
I2C Slave NACK Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU when a NACK is
detected (I2CNACKI=1). Clearing this bit to ‘0’ will disable the NACK detection interrupt.
6
-
Reserved. The user should write 0 to this bit.
5
I2CAMIE
I2C Slave Address Match Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU when
the I2C controller detects an address that matches the I2CSLA_S value (I2CAMI=1). Clearing this bit to ‘0’
will disable the address match interrupt.
4
I2CTOIE
I2C Slave Timeout Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU when an
SMBUS timeout condition is detected (I2CTOI=1). Clearing this bit to ‘0’ will disable the timeout interrupt.
3
I2CSTRIE
I2C Slave Clock Stretch Interrupt Enable. Setting this bit to '1' will generate an interrupt to the CPU when
the clock stretch interrupt flag is set (I2CSTRI=1). Clearing this bit will disable the clock stretch interrupt.
2
I2CRXIE
I2C Slave Receive Ready Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU when
the receive ready interrupt flag is set (I2CRXI=1). Clearing this bit to ‘0’ will disable the receive ready
interrupt.
1
I2CTXIE
I2C Slave Transmit Complete Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU
when the transmit complete interrupt flag is set (I2CTXI=1). Clearing this bit to ‘0’ will disable the transmit
complete interrupt.
0
I2CSRIE
I2C Slave START Interrupt Enable. Setting this bit to ‘1’ will cause an interrupt to the CPU when a START
condition is detected (I2CSRI=1). Clearing this bit to ‘0’ will disable the START detection interrupt.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - - - - - A6
A5
A4
A3
A2
A1
A0
I2CMode
Reset
0 0 0 0 0 0 0 0 0 0 1 1 0 1 1
0
Access
r r r r r r r r rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:8
Reserved
Reserved. The user should write 0 to these bits.
7:1
A[6:0]
Slave Address. These address bits contain the address of the I2C slave interface. When a match to this
address is detected, the I2C controller will automatically acknowledge the host with the I2CACK bit value
and the I2CAMI flag will be set to ‘1’. An interrupt will be generated if enabled.
0
I2CMode
I2C Transfer Mode Select. This bit reflects the actual R/W bit value in current value in I2C transfer and set
by hardware.
11.2.3 – I2C Slave Interrupt Enable Register (I2CIE_S)
Address: M2[02h]
DS4830 User’s Guide
11.2.4 – I2C Slave Address Register (I2CSLA_S)
Address: M2[0Fh]
97
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
- - - - - - - - D7
D6
D5
D4
D3
D2
D1
D0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Access
r r r r r r r r rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
BIT
NAME
DESCRIPTION
15:8
Reserved
Reserved. The user should write 0 to these bits.
7:0
D[7:0]
Data for I2C transfer is read from or written to this location. The I2C transmit and receive buffers are
separate but both are addressed at this location.
Bit
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Name
I2CCKH7
I2CCKH6
I2CCKH5
I2CCKH4
I2CCKH3
I2CCKH2
I2CCKH1
I2CCKH0
I2CCKL7
I2CCKL6
I2CCKL5
I2CCKL4
I2CCKL3
I2CCKL2
I2CCKL1
I2CCKL0
Reset
0 0 0 1 0 0 1 0 0 0 0 0 0 1 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit 7 6 5 4 3 2 1 0
Name
I2CTO7
I2CTO6
I2CTO5
I2CTO4
I2CTO3
I2CTO2
I2CTO1
I2CTO0
Reset
0 0 0 0 0 0 0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
11.2.5 – I2C Slave Data Buffer Register (I2CBUF_S)
Address: M2[00h]
* Unrestricted read access. This register can be written to only when I2CBUSY = 0.
11.2.6 – I2C Slave Clock Control Register (I2CCK_S)
Address: M2[0Dh]
This register has no function when operating in slave mode.
11.2.7 – I2C Slave Timeout Register (I2CTO_S)
Address: M2[0Eh]
DS4830 User’s Guide
This register has no function when operating in slave mode.
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DS4830 User’s Guide
SPI Status and Control Unit
SHIFT Register15/7
15/7
Receive Data Buffer
0
0
SPIB
Writes
SPIB
Reads
MOSI
MISO
SPICK
SSEL
SPI Master
SPICN.MSTM = 1
SPIEN =
SPICN.0
SPI Status and Control Unit
SHIFT Register15/7
15/7
Receive Data Buffer
0
0
SPIB
Writes
SPIB
Reads
MISO
MOSI
SPICK
SSEL
SPI Slave
SPICN.MSTM = 0
SPIEN =
SPICN.0
SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI)
The DS4830 provides two independent Serial Peripheral Interfaces (SPI) – one defined as SPI Master and SPI Slave.
Each SPI module of the DS4830 microcontroller provides an independent serial communication channel to communicate
synchronously with peripheral devices in a multiple master or multiple slave system. Each interface allows independent
access to a four-wire full-duplex serial bus that can be operated in either master mode or slave mode. The SPI
functionality must be enabled by setting the SPI Enable (SPIEN) bit of the SPI Control register to ‘1’. The maximum data
rate of the SPI interface is 1/2 the system clock frequency for master mode operation and 1/4 the system clock frequency
for slave mode operation.
Note: Even though SPI Master and SPI Slave interfaces are defined, each interface can operate as SPI Master or SPI
Slave or both.
The four external interface signals used by the SPI module are MOSI (Master Out Slave In), MISO (Master In Slave Out),
SPI Clock (SPICK), and Slave Select (SSEL).
Figure 12-1: SPI Master and Slave Block Diagram
12.1 – Serial Peripheral Interface (SPI) Detailed Description
The block diagram Figure 12-1 shows the SPI external interface signals, control unit, read buffer, and single shift register
common to the transmit and receive data path for both the master and slave blocks. SPI can be viewed as a synchronous
serial I/O port that shifts data stream of variable length (8 or 16 bits) between peripheral devices. Data is shifted out of the
SPI through the programmable shift register which is formed by serially connecting the master’s shift register and a slave
shift register.
Each time that an SPI transfer completes, the received character is transferred to the read buffer, giving double buffering
on the receive side. The CPU has read/write access to the control unit and the SPI data buffer (SPIB). Writes to SPIB are
always directed to the shift register while reads always come from the receive data buffer. During an SPI transfer, data is
simultaneously transmitted and received. The serial clock signal (SPICK) synchronizes shifting and sampling of the bit
stream on the two serial data pins.
For both the master and the slave, data is shifted out of the shift register on one edge of SPICK and latched into the shift
register on the opposite SPICK clock edge. The master can initiate data transfer at any time since it controls the serial
clock. The slave select signal (SSEL) allows individual selection of slave SPI device in the network.
12.1.1 – SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted and received over two serial data lines with respect to a single
serial shift clock. The polarity and phase of the serial shift clock are the primary components in defining the SPI data
transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and therefore also
defines which clock edge is the active edge. To define a serial shift clock signal that idles in a logic low state (active clock
edge = rising), the Clock Polarity Select (CKPOL; SPICF.0) bit should be configured to a 0, while setting CKPOL = 1 will
cause the shift clock to idle in a logic high state (active clock edge = falling). The phase of the serial clock selects which
99
DS4830 User’s Guide
CKPOL
CKPHA
Mode
Sample Point
0 0 Mode 0
Rising edge
0 1 Mode 1
Falling edge
1 0 Mode 2
Falling edge
1 1 Mode 3
Rising edge
CK PO L=0
CK PH A=1
CK PO L=1
CK PH A=1
MOSI/M ISO
SSEL
SAS=1
Sampling Points
Transfer Cycle
LSBMS B
1 2 3 4 5 6 7 8
CKPOL=0
CKPHA=0
CKPOL=1
CKPHA=0
MOSI/MISO
SSEL
SAS=1
Sampling Points
Transfer Cycle
LSBMSB
1 2 3 4 5 6 7 8
MSB
MSB of
Next
Transfer
edge is used to sample the serial shift data. The Clock Phase Select (CKPHA; SPICF.1) bit controls whether the active or
inactive clock edge is used to latch the data. When CKPHA is set to 1, data is sampled on the inactive clock edge (clock
returning to the idle state). When CKPHA is set to 0, data is sampled on the active clock edge (clock transition to the
active state). Together, the CKPOL and CKPHA bits allow four possible SPI data transfer formats illustrated in Figure 12-2
and Figure 12-3. The Slave Select signal can remain asserted between successive transfers. Table 12-1 illustrates the
SPI modes.
Table 12-1 SPI Modes
Figure 12-2: SPI Transfer Formats (CKPHA=1)
Figure 12-3: SPI Transfer Formats (CKPHA=0)
100
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