Maxim Integrated DS4830 User Manual
DS4830
OpticalMicrocontroller
User’sGuide
Rev 0.3 8/2012
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves
the right to change the circuitry and specifications without notice at any time.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
DS4830 User’s Guide
Contents
SECTION 1 – OVERVIEW ...................................................................................................................................................... 9
SECTION 2 – ARCHITECTURE ........................................................................................................................................... 11
2.1 – Instruction Decoding ................................................................................................................................................. 11
2.2 – Register Space ......................................................................................................................................................... 12
2.3 – Memory Types .......................................................................................................................................................... 13
2.3.1 – Flash Memory .................................................................................................................................................... 13
2.3.2 – SRAM Memory ................................................................................................................................................... 13
2.3.3 – Utility ROM ......................................................................................................................................................... 13
2.3.4 – Stack Memory .................................................................................................................................................... 13
2.4 – Program and Data Memory Mapping and Access ................................................................................................... 14
2.4.1 – Program Memory Access .................................................................................................................................. 14
2.4.2 – Program Memory Mapping ................................................................................................................................ 15
2.4.3 – Data Memory Access ......................................................................................................................................... 15
2.4.4 – Data Memory Mapping ...................................................................................................................................... 16
2.5 – Data Alignment ......................................................................................................................................................... 20
2.6 – Reset Conditions ...................................................................................................................................................... 20
2.6.1 – Power-On/Brownout Reset ................................................................................................................................ 20
2.6.2 – Watchdog Timer Reset ...................................................................................................................................... 21
2.6.3 – External Reset ................................................................................................................................................... 21
2.6.4 – Internal System Resets ...................................................................................................................................... 22
2.7 – Clock Generation ...................................................................................................................................................... 22
SECTION 3 – SYSTEM REGISTER DESCRIPTIONS ......................................................................................................... 23
SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS ................................................................................................. 31
SECTION 5 – INTERRUPTS ................................................................................................................................................ 36
5.1 – Servicing Interrupts ................................................................................................................................................... 37
5.2 – Module Interrupt Identification Registers .................................................................................................................. 39
5.3 – Interrupt System Operation ...................................................................................................................................... 40
5.3.1 – Synchronous vs. Asynchronous Interrupt Sources ............................................................................................ 40
5.3.2 – Interrupt Prioritization by Software ..................................................................................................................... 40
5.3.3 – Interrupt Exception Window ............................................................................................................................... 40
SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC) ................................................................................................ 42
6.1 – Detailed Description ................................................................................................................................................. 42
6.1.1 – Reference Selection.......................................................................................................................................... 43
6.1.2 – Requirement for Enabled DACs ....................................................................................................................... 43
6.2 – DAC Register Descriptions ....................................................................................................................................... 43
6.3 –DAC Code Examples ................................................................................................................................................. 45
SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC) ................................................................................................ 46
7.1 – Detailed Description ................................................................................................................................................. 46
7.1.1 – ADC Controller ................................................................................................................................................... 46
7.1.2 – ADC Conversion Sequencing ............................................................................................................................ 47
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7.1.3 – Temperature Conversion ................................................................................................................................... 48
7.1.4 – Sample and Hold Conversion ............................................................................................................................ 48
7.1.5 – ADC Frame Sequence ....................................................................................................................................... 48
7.1.6 – ADC Conversion Time ....................................................................................................................................... 49
7.1.7 – Location Override............................................................................................................................................... 50
7.1.8 – ADC Data Reading ............................................................................................................................................ 50
7.1.9 – ADC Interrupts ................................................................................................................................................... 51
7.1.10 – ADC Internal Offset .......................................................................................................................................... 51
7.2 – ADC Register Descriptions ....................................................................................................................................... 52
7.3 –ADC Code Examples ................................................................................................................................................. 58
SECTION 8 – SAMPLE AND HOLD ..................................................................................................................................... 60
8.1 – Detailed Description ................................................................................................................................................. 60
8.1.1 – Operation ........................................................................................................................................................... 60
8.1.2 – Fast Mode Operation ......................................................................................................................................... 61
8.1.3 – Sampling Control ............................................................................................................................................... 61
8.1.4 – Pin Capacitance Discharge ............................................................................................................................... 63
8.1.5 – Sample and Hold Data Reading ........................................................................................................................ 64
8.1.6 – Sample and Hold Interrupts ............................................................................................................................... 64
8.2 – Sample and Hold Register Descriptions ................................................................................................................... 65
SECTION 9 – QUICK TRIP (FAST COMPARATOR) ........................................................................................................... 68
9.1 – Detailed Description ................................................................................................................................................. 68
9.1.1 – Quick Trip List Sequencing ................................................................................................................................ 69
9.1.2 – Operation ........................................................................................................................................................... 69
9.1.3 – Quick Trip Interrupts .......................................................................................................................................... 71
9.2 – Quick Trip Register Descriptions .............................................................................................................................. 72
SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE .................................................................................................. 76
10.1 – Detailed Description .............................................................................................................................................. 76
10.1.1 – Description of Master I2C Interface ................................................................................................................. 76
10.1.2 – Default Operation ............................................................................................................................................. 76
10.1.3 – I2C Clock Generation ...................................................................................................................................... 76
10.1.4 – Timeout ............................................................................................................................................................ 77
10.1.5 – Generating a START ....................................................................................................................................... 78
10.1.6 – Generating a STOP ......................................................................................................................................... 79
10.1.7 – Transmitting a Slave Address .......................................................................................................................... 80
10.1.8 – Transmitting Data............................................................................................................................................. 80
10.1.9 – Receiving Data................................................................................................................................................. 81
10.1.10 – I2C Master Clock Stretching .......................................................................................................................... 83
10.1.11 – Resetting the I2C Master Controller .............................................................................................................. 83
10.1.12 – Operation as a Slave ..................................................................................................................................... 84
10.1.13 – GPIO .............................................................................................................................................................. 84
10.2 – I2C Master Controller Register Description ........................................................................................................... 85
SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE ...................................................................................................... 89
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DS4830 User’s Guide
11.1 – Detailed Description .............................................................................................................................................. 90
11.1.1 – Default Operation ............................................................................................................................................. 90
11.1.2 – Slave Address .................................................................................................................................................. 90
11.1.3 – I2C Start Detection........................................................................................................................................... 90
11.1.4 – I2C Stop Detection ........................................................................................................................................... 90
11.1.5 – Slave Address Matching .................................................................................................................................. 90
11.1.6 – Transmitting Data............................................................................................................................................. 91
11.1.7 – Receiving Data................................................................................................................................................. 92
11.1.8 – Clock Stretching ............................................................................................................................................... 93
11.1.9 – SMBus Timeout ............................................................................................................................................... 93
11.1.10 – Resetting the I2C Slave Controller ................................................................................................................ 94
11.1.11 – Operation as a Master ................................................................................................................................... 94
11.2 – I2C Slave Controller Register Description .............................................................................................................. 95
SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI) .................................................................................................. 99
12.1 – Serial Peripheral Interface (SPI) Detailed Description ........................................................................................... 99
12.1.1 – SPI Transfer Formats .......................................................................................................................................... 99
12.1.2 – SPI Character Lengths ...................................................................................................................................... 101
12.2 – SPI System Errors ................................................................................................................................................ 101
12.2.1 – Mode Fault ......................................................................................................................................................... 101
12.2.2 – Receive Overrun ................................................................................................................................................ 101
12.2.3 – Write Collision While Busy ................................................................................................................................ 102
12.3 – SPI Interrupts ........................................................................................................................................................ 102
12.4 – SPI Master ............................................................................................................................................................ 103
12.4.1 – SPI Transfer Baud Rates .................................................................................................................................. 103
12.4.2 – SPI Master Operation ........................................................................................................................................ 103
12.4.3 – SPI Master Register Descriptions ..................................................................................................................... 105
12.5 – SPI Slave .............................................................................................................................................................. 107
12.5.1 – SPI Slave Select ................................................................................................................................................ 107
12.5.2 – SPI Transfer Baud Rates .................................................................................................................................. 107
12.5.3 – SPI Slave Operation .......................................................................................................................................... 107
12.5.4 – SPI Slave Register Descriptions ....................................................................................................................... 108
SECTION 13 – 3-WIRE ....................................................................................................................................................... 110
13.1 – Detailed Description ............................................................................................................................................. 110
13.1.1 – Operation ....................................................................................................................................................... 110
13.2 – 3-Wire Register Descriptions ................................................................................................................................ 112
SECTION 14 – PWM .......................................................................................................................................................... 113
14.1 – Detailed Description ............................................................................................................................................. 113
14.1.1 – PWMCN and PWMDATA SFRs .................................................................................................................... 113
14.1.2 – PWMSYNC SFR ............................................................................................................................................ 114
14.2 – Individual PWM Channel Operation ..................................................................................................................... 115
14.2.1 – Duty Cycle Register (DCYCn) ....................................................................................................................... 115
14.2.2 – PWM Configuration Register (PWMCFGn) ................................................................................................... 116
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DS4830 User’s Guide
14.2.3 – Pulse Spreading............................................................................................................................................. 116
14.2.4 – Alternate PWM Output ................................................................................................................................... 119
14.2.5 – PWM DELAY Register (PWMDLYn).............................................................................................................. 119
14.3 – PWM Output Register Descriptions ...................................................................................................................... 120
14.4 – PWM Output Code Examples .............................................................................................................................. 125
SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS ............................................................................. 126
15.1 – Overview ............................................................................................................................................................... 126
15.2 – GPIO Port 0 Register Descriptions ....................................................................................................................... 129
15.2.1 – GPIO Direction Register Port 0 (PD0) ........................................................................................................... 129
15.2.2 – GPIO Output Register Port 0 (PO0) .............................................................................................................. 129
15.2.3 – GPIO Input Register for Port 0 (PI0) .............................................................................................................. 129
15.2.4 – GPIO Port 0 External Interrupt Edge Select Register (EIES0) ..................................................................... 129
15.2.5 – GPIO Port 0 External Interrupt Flag Register (EIF0) ..................................................................................... 130
15.2.6 – GPIO Port 0 External Interrupt Enable Register (EIE0)................................................................................. 130
15.3 – GPIO Port 1 Register Descriptions ....................................................................................................................... 130
15.3.1 – GPIO Direction Register Port 1 (PD1) ........................................................................................................... 130
15.3.2 – GPIO Output Register Port 1 (PO1) .............................................................................................................. 130
15.3.3 – GPIO Input Register for Port 1 (PI1) .............................................................................................................. 131
15.3.4 – GPIO Port 1 External Interrupt Edge Select Register (EIES1) ..................................................................... 131
15.3.5 – GPIO Port 1 External Interrupt Flag Register (EIF1) ..................................................................................... 131
15.3.6 – GPIO Port 1 External Interrupt Enable Register (EIE1)................................................................................. 131
15.4 – GPIO Port 2 Register Descriptions ....................................................................................................................... 131
15.4.1 – GPIO Direction Register Port 2 (PD2) ........................................................................................................... 131
15.4.2 – GPIO Output Register Port 2 (PO2) .............................................................................................................. 132
15.4.3 – GPIO Input Register for Port 2 (PI2) .............................................................................................................. 132
15.4.4 – GPIO Port 2 External Interrupt Edge Select Register (EIES2) ..................................................................... 132
15.4.5 – GPIO Port 2 External Interrupt Flag Register (EIF2) ..................................................................................... 132
15.4.6 – GPIO Port 2 External Interrupt Enable Register (EIE2)................................................................................. 132
15.5 – GPIO Port 6 Register Descriptions ....................................................................................................................... 133
15.5.1 – GPIO Direction Register Port 6 (PD6) ........................................................................................................... 133
15.5.2 – GPIO Output Register Port 6 (PO6) .............................................................................................................. 133
15.5.3 – GPIO Input Register for Port 6 (PI6) .............................................................................................................. 133
15.5.4 – GPIO Port 6 External Interrupt Edge Select Register (EIES6) ..................................................................... 133
15.5.5 – GPIO Port 6 External Interrupt Flag Register (EIF6) ..................................................................................... 134
15.5.6 – GPIO Port 6 External Interrupt Enable Register (EIE6)................................................................................. 134
SECTION 16 – GENERAL-PURPOSE TIMERS ................................................................................................................ 135
16.1 – Detailed Description ............................................................................................................................................. 135
16.1.1 – Timer Modes .................................................................................................................................................. 135
16.1.2 – Clock Selection .............................................................................................................................................. 136
16.1.3 – Timer Clock Prescaler ................................................................................................................................... 136
16.2 – Timer Register Descriptions ................................................................................................................................. 137
SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM) ..................................................................................................... 139
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DS4830 User’s Guide
SECTION 18 – HARDWARE MULTIPLIER MODULE ....................................................................................................... 140
18.1 – Hardware Multiplier Organization ......................................................................................................................... 140
18.2 – Hardware Multiplier Controls ................................................................................................................................ 140
18.3 – Register Output Selection..................................................................................................................................... 141
18.3.1 – Signed-Unsigned Operand Selection ............................................................................................................ 141
18.3.2 – Operand Count Selection .............................................................................................................................. 141
18.4 – Hardware Multiplier Operations ............................................................................................................................ 141
18.4.1 – Accessing the Multiplier ................................................................................................................................. 141
18.5 – Hardware Multiplier Peripheral Registers ............................................................................................................. 142
18.6 – Hardware Multiplier Examples .............................................................................................................................. 145
SECTION 19 – WATCHDOG TIMER.................................................................................................................................. 146
19.1 - Overview ............................................................................................................................................................... 146
19.2 – Watchdog Timer Description ................................................................................................................................ 146
19.2.1 – Watchdog Timer Interrupt Operation ............................................................................................................. 147
19.2.2 – Watchdog Timer Reset Operation ................................................................................................................. 147
19.2.3 – Watchdog Timer Applications ........................................................................................................................ 147
SECTION 20 – TEST ACCESS PORT (TAP) ..................................................................................................................... 149
20.1 – TAP Controller ...................................................................................................................................................... 150
20.2 – TAP State Control ................................................................................................................................................. 151
20.2.1 – Test-Logic-Reset............................................................................................................................................ 151
20.2.2 – Run-Test-Idle ................................................................................................................................................. 151
20.2.3 – IR-Scan Sequence ......................................................................................................................................... 151
20.2.4 – DR-Scan Sequence ....................................................................................................................................... 152
20.3 – Communication via TAP ....................................................................................................................................... 152
20.3.1 - TAP Communication Examples – IR-Scan and DR-Scan .............................................................................. 153
SECTION 21 – IN-CIRCUIT DEBUG MODE ...................................................................................................................... 155
21.1 – Background Mode Operation ............................................................................................................................... 156
21.1.1 – Breakpoint Registers ..................................................................................................................................... 157
21.1.2 – Using Breakpoints .......................................................................................................................................... 159
21.2 – Debug Mode ......................................................................................................................................................... 160
21.2.1 – Debug Mode Commands ............................................................................................................................... 160
21.2.2 – Read Register Map Command Host-ROM Interaction .................................................................................. 162
21.2.3 – Single Step Operation (Trace) ....................................................................................................................... 163
21.2.4 – Return ............................................................................................................................................................ 164
21.2.5 – Debug Mode Special Considerations ............................................................................................................ 164
21.3 – In-Circuit Debug Peripheral Registers .................................................................................................................. 165
SECTION 22 – IN-SYSTEM PROGRAMMING .................................................................................................................. 169
22.1 – Detailed Description ............................................................................................................................................. 169
22.1.1 - Password Protection ....................................................................................................................................... 170
22.1.2 – Entering JTAG Bootloader ............................................................................................................................. 170
22.1.3 – Entering I2C Bootloader ................................................................................................................................ 171
22.2 – Bootloader Operation ........................................................................................................................................... 171
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DS4830 User’s Guide
22.2.1 – JTAG Bootloader Protocol ............................................................................................................................. 172
22.2.2 – I2C Bootloader Protocol ................................................................................................................................. 172
22.3 – Bootloader Commands ......................................................................................................................................... 173
22.3.1 - Command 00h – No Operation ....................................................................................................................... 173
22.3.2 - Command 01h – Exit Loader .......................................................................................................................... 173
22.3.3 - Command 02h – Master Erase ....................................................................................................................... 173
22.3.4 - Command 03h – Password Match ................................................................................................................. 174
22.3.5 - Command 04h – Get Status ........................................................................................................................... 174
22.3.6 - Command 05h – Get Supported Commands ................................................................................................. 175
22.3.7 - Command 06h – Get Code Size ..................................................................................................................... 175
22.3.8 - Command 07h – Get Data Size ...................................................................................................................... 175
22.3.9 - Command 08h – Get Loader Version ............................................................................................................. 175
22.3.10 - Command 09h – Get Utility ROM Version .................................................................................................... 175
22.3.11 - Command 10h – Load Code ........................................................................................................................ 176
22.3.12 - Command 11h – Load Data ......................................................................................................................... 176
22.3.13 - Command 20h – Dump Code ....................................................................................................................... 176
22.3.14 - Command 21h – Dump Data ........................................................................................................................ 177
22.3.15 - Command 30h – CRC Code ......................................................................................................................... 177
22.3.16 - Command 31h – CRC Data .......................................................................................................................... 177
22.3.17 - Command 40h – Verify Code ....................................................................................................................... 177
22.3.18 - Command 41h – Verify Data ........................................................................................................................ 177
22.3.19 - Command 50h – Load and Verify Code ....................................................................................................... 178
22.3.20 - Command 51h – Load and Verify Data ........................................................................................................ 178
22.3.21 - Command E0h – Code Page Erase ............................................................................................................. 178
SECTION 23 – PROGRAMMING ....................................................................................................................................... 179
23.1 – Addressing Modes ................................................................................................................................................ 179
23.2 – Prefixing Operations ............................................................................................................................................. 179
23.3 – Reading and Writing Registers ............................................................................................................................. 179
23.3.1 – Loading an 8-bit register with an immediate value ........................................................................................ 180
23.3.2 – Loading a 16-bit register with a 16-bit immediate value ................................................................................ 180
23.3.3 – Moving values between registers of the same size ....................................................................................... 180
23.3.4 – Moving values between registers of different sizes ....................................................................................... 180
23.4 – Reading and Writing Register Bits ....................................................................................................................... 181
23.5 – Using the Arithmetic and Logic Unit ..................................................................................................................... 182
23.5.1 – Selecting the active accumulator ................................................................................................................... 182
23.5.2 – Enabling auto-increment and auto-decrement .............................................................................................. 182
23.5.3 – ALU operations using the active accumulator and a source ......................................................................... 184
23.5.4 – ALU operations using only the active accumulator........................................................................................ 184
23.5.5 – ALU bit operations using only the active accumulator ................................................................................... 184
23.5.6 – Example: Adding two four-byte numbers using auto-increment .................................................................... 184
23.6 - Processor Status Flag Operations ........................................................................................................................ 184
23.6.1 - Sign Flag ......................................................................................................................................................... 184
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DS4830 User’s Guide
23.6.2 - Zero Flag ........................................................................................................................................................ 185
23.6.3 - Equals Flag ..................................................................................................................................................... 185
23.6.4 - Carry Flag ....................................................................................................................................................... 185
23.6.5 - Overflow Flag .................................................................................................................................................. 186
23.7 - Controlling Program Flow ...................................................................................................................................... 186
23.7.1 - Obtaining the next execution address ............................................................................................................ 186
23.7.2 - Unconditional jumps ....................................................................................................................................... 186
23.7.3 - Conditional jumps ........................................................................................................................................... 187
23.7.4 - Calling subroutines ......................................................................................................................................... 187
23.7.5 - Looping operations ......................................................................................................................................... 187
23.7.6 - Conditional returns.......................................................................................................................................... 188
23.8 - Handling Interrupts ................................................................................................................................................ 188
23.8.1 - Conditional return from interrupt ..................................................................................................................... 189
23.9 - Accessing the Stack .............................................................................................................................................. 189
23.10 - Accessing Data Memory ..................................................................................................................................... 190
SECTION 24 – INSTRUCTION SET................................................................................................................................... 192
SECTION 25 – UTILITY ROM ............................................................................................................................................ 220
25.1 – Overview ............................................................................................................................................................... 220
25.2 – In-Application Programming Functions ................................................................................................................ 221
25.2.1 – UROM_flashWrite .......................................................................................................................................... 221
25.2.2 – UROM_flashErasePage ................................................................................................................................ 221
25.3 – Data Transfer Functions ....................................................................................................................................... 222
25.3.1 – UROM_moveDP0 .......................................................................................................................................... 223
25.3.2 – UROM_moveDP0inc ..................................................................................................................................... 223
25.3.3 – UROM_moveDP0dec .................................................................................................................................... 223
25.3.4 – UROM_moveDP1 .......................................................................................................................................... 224
25.3.5 – UROM_moveDP1inc ..................................................................................................................................... 224
25.3.6 – UROM_moveDP1dec .................................................................................................................................... 224
25.3.7 – UROM_moveBP ............................................................................................................................................ 225
25.3.8 – UROM_moveBPinc ........................................................................................................................................ 225
25.3.9 – UROM_moveBPdec ...................................................................................................................................... 225
25.3.10 – UROM_copyBuffer ....................................................................................................................................... 226
25.4 – Utility ROM Examples ........................................................................................................................................... 227
25.4.1 – Reading Constant Word Data from Flash ...................................................................................................... 227
25.4.2 – Reading Constant Byte Data from Flash (Indirect Function Call) .................................................................. 227
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DS4830 User’s Guide
SECTION 1 – OVERVIEW
The DS4830 System Management Microcontroller provides a complete optical control, calibration, and monitor solution.
The IC is based on the high-performance 16-bit family of MAXQ
microcontrollers, and provides generous amounts of flash program memory and SRAM data memory.
Some of the resources and features that the DS4830 provides for monitoring and controlling an optical sy stem include the
following:
16-Bit MAXQ20 Low-Power Microcontroller
13-Bit ADC with a 26 Input Mux
Single and Differential Mode
4 User-Selectable Gains for Individual Channel
V
, Internal Reference and DAC External Reference Measurement
DD
40ksps with Fastest ADC Clock
10 PWM Channels
Normal and Pulse Spreading Operation Modes
PWM Output Synchronization
User-Selectable 7- to 12-Bit Resolution
1MHz Switching Using 133MHz External Clock
8-bit Fast Comparator with 16 Input Mux
Single and Differential Mode
Low and High Threshold Configurations
3.2s Conversion Time per Channel
Two Independent Sample and Hold
Single, Fast and Dual Mode Operation
Internal and External Trigger Option
Pin Discharge
Temperature Sensors
Internal Die Temperature Measurement
Remote Temperature Measurement of Two Diode Connected Transistors
8 Voltage DAC Channels having 12-Bit Resolution with Selectable Internal or External Reference Option
SPI or 400kHz I
SPI, 400kHz I
2
C-Compatible Slave Communication Interface
2
C-Compatible, or Maxim Integrated 3-Wire Laser Driver Master Communication Interface
Two 16-bit Timers with Synchronous and Compare modes
Watchdog Timer
Maskable Interrupt Sources
Hardware Multiplier Unit
Supply Voltage Monitoring
32KWords of Flash and 1KWords of SRAM Memory
Included ROM Routines that allow Bootloading and In-Application Programming of Flash Memory
In-System Debugging
®
reduced instruction set computing (RISC)
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
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DS4830 User’s Guide
Figure 1-1 DS4830 Block Diagram
This document is provided as a supplement to the DS4830 IC data sheet. This user’s guide provides the information
necessary to develop applications using the DS4830. All electrical and timing specifications, pin descriptions, package
information, and ordering information can be found in the DS4830 IC data sheet.
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DS4830 User’s Guide
FORMAT DESTINATION SOURCE
s sd
f s s
s s s sd d d d
d d
SECTION 2 – ARCHITECTURE
The DS4830 contains a MAXQ20 low-cost, high-performance, CMOS, fully static microcontroller with flash memory. It is
structured on a highly advanced, 16-accumulator-based, 16-bit RISC architecture. Fetch and execution operations are
completed in one cycle without pipelining, since the instruction contains both the op code and data. The highly efficient
core is supported by 16 accumulators and a 16-level hardware stack, enabling fast subroutine calling and task switching.
Data can be quickly and efficiently manipulated with three internal data pointers. Two of these data pointers, DP0 and
DP1, are stand-alone 16-bit pointers. The third data pointer, Frame Pointer, is composed of a 16-bit base pointer (BP) and
an 8-bit offset register (OFFS). All three pointers support post-increment/decrement functionality for read operations and
pre-increment/decrement for write operations. For the Frame Pointer (FP=BP[OFFS]), the increment/decrement operation
is executed on the OFFS register and does not affect the base pointer. Multiple data pointers allow more than one
function to access data memory without having to save and restore data pointers each time.
Stack functionality is provided by dedicated memory with a 16-bit width and a depth of 16. An on-chip memory
management unit (MMU) allows logical remapping of the program and data spaces, and thus facilitates in-system
programming and fast access to data tables, arrays, and constants located in flash memory.
This section provides details on the following topics.
1. Instruction decoding
2. Register space
3. Memory types
4. Program and data memory mapping and access
5. Data alignment
6. Reset conditions
7. Clock generation
8. Power modes
2.1 – Instruction Decoding
The DS4830 uses the standard 16-bit MAXQ20 core instruction set, which is described in the Instruction Set section.
Every instruction is encoded as a single 16-bit word. The instruction word format is shown in Figure 2-1.
Figure 2-1: Instruction Word Format
Bit 15 (f) indicates the format for the source field of the instruction as follows:
o If f equals 0, the instruction is an immediate source instruction. The source field represents an immediate
8-bit value.
o If f equals 1, the instruction is a register source instruction. The source field represents the register that
the source value will be read from.
Bits 14 to 8 (ddddddd) represent the destination for the transfer. This value always represents a destination
register. The lower four bits contain the module specifier and the upper three bits contain the register index in
that module.
Bits 7 to 0 (ssssssss) represent the source for the transfer. Depending on the value of the format field, this can
either be an immediate value or a source register. If this field represents a register, the lower four bits contain the
module specifier and the upper four bits contain the register index in that module.
This instruction word format presents the following limitations.
1. There are 32 registers per register module, but only four bits are allocated to designate the source register and
only three bits are allocated to designate the destination register.
2. The source field only provides 8 bits of data for an immediate value; however a 16-bit immediate value may be
required.
The DS4830 uses a prefix register (PFX) to address these limitations. The prefix register provides the additional bits
required to access all 32 register within a module. The prefix register also provides the additional 8 bits of data required
to make a 16-bit immediate data source. The data that is written to the prefix register survives for only one clock cycle.
This means the write to the prefix register must occur immediately prior to the instruction requiring the prefix register. The
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DS4830 User’s Guide
prefix register is cleared to zero after one cycle so it will not affect any other instructions. The write to the prefix register is
done automatically by the assembler and requires one additional execution cycle. So, while most instructions execute in
a single cycle, two cycles are needed for instructions that require the prefix register.
The architecture of the DS4830 is transport-triggered. This means that writing to or reading from certain register locations
will also cause side effects to occur. These side effects form the basis of the DS4830’s higher level op codes, such as
ADDC, OR, and JUMP. While these op codes are actually implemented as MOVE instructions between certain register
locations, the encoding is handled by the assembler and need not be a concern to the programmer. The unused "empty"
locations in the System Register Modules are used for these higher level op codes.
The instruction set is designed to be highly orthogonal. All arithmetic and logical operations that use two registers can use
any register along with the accumulator. Data can be transferred between any two registers in a single instruction.
2.2 – Register Space
The DS4830 provides a total of 13 register modules broken up into two different groups. These groupings are descriptive
only, as there is no difference between accessing the two register groups from a programming perspective. The two
groups are:
1. Peripheral Registers: These are the lower six modules (Modules 0h through 5h). The Peripheral Registers in the
DS4830 are used for functionalities such as ADC, PWM Outputs, Sample and Hold, 3Wire, I2C Master and Slave,
SPI Master and Slave, GPIO, etc. The Peripheral Registers are not used to implement op codes.
2. System Registers: These are modules 8h, 9h, and Bh through Fh. The System Registers in the DS4830 are used
to implement higher level op codes as well as the following common system features.
16-bit ALU and associated status flags (zero, equals, carry, sign, overflow)
16 working accumulator registers, each 16-bit, along with associated control registers
Instruction pointer
Registers for interrupt control, handling, and identification
Auto-decrementing Loop Counters for fast, compact looping
Two Data Pointer registers and a Frame Pointer for data memory access
Each System Register module has 16 registers, while each Peripheral Register module has 32 registers. The number of
cycles required to access a particular register depends upon the register’s index within the module. The access times
based upon the register index are grouped as follows:
The first eight registers (index 0h to 7h) in each module may be read from or written to in a single cycle
The second eight registers (index 8h to 0Fh) may be read from in a single cycle and written to in two cycles (by
using the prefix register PFX).
The last sixteen registers (10h to 1Fh) in Peripheral Register modules may be read or written in two cycles
(always requiring use of the prefix register PFX).
Registers may be 8 or 16 bits in length. Some registers may contain reserved bits. The user should not write to any
reserved bits. Data transfers between registers of different sizes are handled as shown in Table 2-1.
If the source and destination registers are both 8 bits wide, data is copied bit to bit.
If the source register is 8 bits wide and the destination register is 16 bits wide, the data from the source register is
transferred into the lower 8 bits of the destination register. The upper 8 bits of the destination register are set to
the current value of the prefix register; this value is normally zero, but it can be set to a different value by the
previous instruction if needed. The prefix register reverts back to zero after one cycle, so this must be done by the
instruction immediately before the one that will be using the value.
If the source register is 16 bits wide and the destination register is 8 bits wide, the lower 8 bits of the source are
transferred to the destination register.
If both registers are 16 bits wide, data is copied bit to bit.
The above rules apply to all data movements between defined registers. Data transfer to/from undefined register locations
has the following behavior:
If the destination is an undefined register, the MOVE is a dummy operation but may trigger an underlying
operation according to the source register (e.g., @DPn--).
If the destination is a defined register and the source is undefined, the source data for the transfer will depend
upon the source module width. If the source is from a module containing 8-bit or 8-bit and 16-bit source registers,
the source data will be equal to the prefix data as the upper 8 bits and 00h as the lower 8 bits. If the source is
from a module containing only 16-bit source registers, 0000h source data is used for the transfer.
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DS4830 User’s Guide
SOURCE REGISTER
SIZE (BITS)
DESTINATION REGISTER
SIZE (BITS)
PREFIX
SET?
DESTINATION SET TO VALUE
HIGH 8 BITS
LOW 8 BITS
8
8
X — Source [7:0] 8 16
No
00h
Source [7:0] 8 16
Yes
PFX [7:0]
Source [7:0]
16
8
X — Source [7:0]
16
16
X
Source [15:8]
Source [7:0]
Table 2-1. Register-to-Register Transfer Operations
2.3 – Memory Types
In addition to the internal register space, the DS4830 incorporates the following memory types:
32KWords of flash memory
4KWords of utility ROM contain a debugger and program loader
1KWords of SRAM
16-level stack memory for storage of program return addresses
The memory on the DS4830 is organized according to a Harvard architecture. This means that there are separate busses
for both program and data memory. Stack memory is also separate and is accessed through a dedicated register set.
2.3.1 – Flash Memory The DS4830 contains 32KWords (32K x 16) of flash memory. The flash memory begins at address 0000h and is contiguous through word address 7FFFh. The flash memory can also be used for storing lookup tables and other nonvolatile data.
The incorporation of flash memory allows the contents of the flash memory to be upgraded in the field, either by the
application or by one of the bootloaders (JTAG or I2C). Writing to flash memory must be done indirectly by using routines
that are provided by the utility ROM. See the Utility ROM and In-System Programming sections for more details.
2.3.2 – SRAM Memory
The DS4830 contains 1KWords (1K x 16) of SRAM memory. The SRAM memory address begins at address 0000h and
is contiguous through word address 03FFh. The contents of the SRAM are indeterminate after power-on reset, but are
maintained during non-POR resets.
When using the in-circuit debugging features, the highest 19 bytes of the SRAM must be reserved for saved state storage
and working space for the debugging routines. If in-circuit debug is not used, the entire 1KWords of SRAM is available for
application use.
2.3.3 – Utility ROM
The utility ROM is a 4kWord segment of memory. The utility ROM memory address begins at word address 8000h and is
contiguous through word address 8FFFh. The utility ROM is programmed at the factory and cannot be modified. The
utility ROM provides the following system utility functions:
Reset vector (not user code reset vector)
In-system programming (bootstrap loader) over JTAG or I2C-compatible interfaces
In-circuit debug routines
Routines for in-application flash programming
Following any reset, the DS4830 automatically starts execution at the Reset Vector which is address 8000h in the utility
ROM. The ROM code determines whether the program execution should immediately jump to the start of application code
(flash address 0000h), or to one of the special routines mentioned. Routines within the utility ROM are firmwareaccessible and can be called as subroutines by the application software. See the Utility ROM, In-System Programming,
and In-Circuit Debug sections for more information on the routines provided by the utility ROM.
2.3.4 – Stack Memory
A 16-bit, 16-level on-chip stack provides storage for program return addresses and temporary storage of system registers.
The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed, and when an
interrupt is serviced. The stack can also be used explicitly to store and retrieve data by using the @SP- - source, @++SP
destination, or the PUSH, POP, and POPI instructions. The POPI instruction acts identically to the POP instruction except
that it additionally clears the INS bit.
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DS4830 User’s Guide
The width of the stack is 16 bits to accommodate the instruction pointer size. On reset, the stack pointer SP initializes to
the top of the stack (0Fh). The CALL, PUSH, and interrupt vectoring operations first increment SP and then store a value
at @SP. The RET, RETI, POP, and POPI operations first retrieve the value at @SP and then decrement SP.
The stack memory is initialized to indeterminate values upon reset or power-up. Stack memory is dedicated for stack
operations only and cannot be accessed by the DS4830 program or data busses.
When using the in-circuit debugging features, one word of the stack must be reserved for the debugging routines. If incircuit debug is not used, the entire stack is available for application use.
2.4 – Program and Data Memory Mapping and Access
The memory on the DS4830 is implemented using a Harvard architecture, with separate busses for program and data
memory. The Memory Management Unit (MMU) allows the DS4830 to also support a pseudo-Von Neumann memory
map. The pseudo Von Neumann memory map allows each of the memory segments (flash, SRAM, and utility ROM) to
be logically mapped into a single contiguous memory map. This allows all of the memory segments to be accessed as
both program and memory data. The advantages the pseudo-Von Neumann memory map provides are:
Program execution can occur from the flash, SRAM, or utility ROM memory segments
The SRAM and flash memory segments can both be used for data memory.
Using the pseudo-Von Neumann memory map does have one restriction. This restriction is that a particular memory
segment cannot be simultaneously accessed as both program and data memory.
2.4.1 – Program Memory Access
The instructions that the DS4830 is executing reside in what is defined as the program memory. The MMU fetches the
instructions using the program bus. The Instruction Pointer (IP) register designates the program memory address of the
next instruction to fetch. The Instruction Pointer is read/write accessible by the user software. A write to the Instruction
Pointer will force program flow to the new address on the next cycle following the write. The content of the Instruction
Pointer will be incremented by 1 automatically after each fetch operation. From an implementation perspective, system
interrupts and branching instructions simply change the contents of the Instruction Pointer and force the op code to fetch
from a new program location.
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DS4830 User’s Guide
2.4.2 – Program Memory Mapping
The DS4830’s mapping of the three memory segments (flash, SRAM, and utility ROM) as program memory is shown in
Figure 2-2. The mapping of memory segments into program space is always the same. When referring to memory as
program memory, all addresses are given as word addresses. The 32KWord flash memory segment is located at
memory location 0000h through 7FFFh and is logically divided into two pages, each containing 16KWords. The utility
ROM is located from location 8000h through 8FFFh, followed by the SRAM memory segment at location A000h through
A3FFh. The user code reset vector, which is the first instruction of user program code that is executed, is located at flash
memory address 0000h. User program code should always begin at this address.
Figure 2-2: Program Memory Mapping
2.4.3 – Data Memory Access
Data memory mapping and access control are handled by the memory management unit (MMU). Read/write access to
data memory can be in word or in byte mode. The DS4830 provides three pointers that can be used for indirect
accessing of data memory. The DS4830 has two data pointers (@DPn) and one frame pointer (@BP[OFFS]). These
pointers are implemented as registers that can be directly accessed by user software. A data memory access requires
only one system clock period.
2.4.3.1 – Data Pointers
To access data memory, the data pointers are used as one of the operands in a MOVE instruction. If the data pointer is
used as a source, the core performs a load operation that reads data from the memory location addressed by the data
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DS4830 User’s Guide
CDA0
Selected Page in Byte Mode
Selected Page in Word Mode
0
P0
P0 and P1
1
P1
P0 and P1
pointer. If the data pointer is used as destination, the core performs a store operation that writes data to the memory
location addressed by the data pointer. Following are some examples of setting and using a data pointer.
move DP[0], #0100h ; set pointer DP[0] to address 100h
move Acc, @DP[0] ; read data from location 100h
move @DP[0], Acc ; write to location 100h
The address pointed to by the data pointers can be automatically incremented or decremented. If the data pointer is used
as a source, the pointer can be incremented or decremented after the data access. If the data pointer is used as a
destination, the increment or decrement can occur prior to the data access. Following are examples of using the data
pointers increment/decrement features.
move Acc, @DP[0]++ ; increment DP[0] after read
move Acc, @DP[1]-- ; decrement DP[1] after read
move @++DP[0], Acc ; increment DP[0] before write
move @--DP[1], Acc ; decrement DP[0] before write
2.4.3.2 – Frame Pointer
The frame pointer (BP[OFFS]) is formed by the 16-bit unsigned addition of the 16-bit Frame Pointer Base Register (BP)
and the 8-bit Frame Pointer Offset Register (OFFS). The method the DS4830 uses to access data using the frame
pointer is similar to the data pointers. When increments or decrements are used, only the value of OFFS is incremented
or decremented. The base pointer (BP) will remain unaffected by increments or decrements of the OFFS register,
including when the OFFS register rolls over from FFh to 00h or from 00h to FFh. Following are examples of how to use
the frame pointer.
move BP, #0100h ; set base pointer to address 100h
move OFFS, #10h ; set the offset to 10h,
move Acc, @BP[OFFS] ; read data from location 0110h
move @BP[OFFS], Acc ; write data to location 0110h
move Acc, @BP[OFFS++] ; increment OFFS after read
move Acc, @BP[OFFS++] ; decrement OFFS after read
move @BP[++OFFS], Acc ; increment OFFS before write
move @BP[--OFFS], Acc ; decrement OFFS before write
2.4.4 – Data Memory Mapping
The DS4830’s pseudo-Von Neumann memory map allows the MMU to read data from each of the three memory
segments (flash, SRAM, utility ROM). The MMU can also write data directly to the SRAM memory segment. Data
memory can be written to the flash memory segment, but because writing to flash requires the use of the utility ROM
routines, this is not a direct access. The logical mapping of the three memory segments as data memory varies
depending upon:
which memory segment instructions are currently being executed from
if data memory is being accessed in word or byte mode
In all cases, whichever memory segment is currently being used as program memory cannot be accessed as data
memory.
When the program is currently executing instructions from either the SRAM or utility ROM memory segments, the flash
memory will be mapped to half of the data memory space. If word access mode is selected, both pages (32KWords) can
be logically mapped to data memory space. If byte access mode is selected, only one page (32KBytes) can be logically
mapped to half of the data memory space. When operating in byte access mode, the selection of which flash page is
mapped into data memory space is determined by the Code Data Access bit (CDA0):
The next three sections detail the mapping of the different memory segments as data memory depending upon which
memory segment instructions are currently being executed from.
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DS4830 User’s Guide
2.4.4.1 – Memory Map When Executing from Flash Memory
When executing from the flash memory:
Read and write operations of SRAM memory are executed normally.
The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written.
Figure 2-3 illustrates the mapping of the SRAM and utility ROM memory segments into data memory space when code is
executing from the flash memory segment.
Figure 2-3: Memory Map When Executing from Flash Memory
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DS4830 User’s Guide
2.4.4.2 – Memory Map When Executing from Utility ROM
When executing from the utility ROM:
Read and write operations of SRAM memory are executed normally.
Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM
routines.
One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data
with an offset of 8000h as determined by the CDA0 bit.
Figure 2-4 illustrates the mapping of the SRAM and flash memory segments into data memory space when code is
executing from the utility ROM memory segment.
Figure 2-4: Memory Map When Executing from Utility ROM
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DS4830 User’s Guide
2.4.4.3 – Memory Map When Executing from SRAM
When executing from the SRAM:
The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written.
Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM
routines.
One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data
with an offset of 0000h. For byte access mode, the page of flash accessed is determined by the CDA0 bit.
Figure 2-5 illustrates the mapping of the flash and utility ROM memory segments into data memory space when code is
executing from the SRAM memory segment.
Figure 2-5: Memory Map When Executing from SRAM
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DS4830 User’s Guide
2.5 – Data Alignment
To support merged program and data memory operation while maintaining efficient memory space usage, the data
memory must be able to support both byte and word mode accessing. Data is aligned in data memory as words, but the
effective data address is resolved to bytes. This data alignment allows program instruction fetching in words while
maintaining data accessibility at the byte level. It is important to realize that this accessibility requires strict word
alignment. All executable or data words must align to an even address in byte mode. Care must be taken when updating
a code segment as misalignment of words will likely result in loss of program execution control.
Memory will always be read as a complete word, whether for program fetch or data access. The program decoder always
uses a full 16-bit word. The data access can utilize a word or an individual byte. Data memory is organized as two bytewide memory banks with common word address decode but two 8-bit data buses. In byte mode, data pointer hardware
reads out the full word containing the selected byte using the effective data word address pointer (the least significant bit
of the byte data pointer is not initially used). Then, the least significant data pointer bit functions as the byte select that is
used to place the correct byte on the data bus. For write access, data pointer hardware addresses a particular word using
the effective data word address while the least significant bit selects the corresponding data bank for write. The contents
of the other byte are left unaffected.
2.6 – Reset Conditions
The DS4830 has several possible sources of reset.
Power-On/Brownout Reset
Watchdog Timer Reset
External Reset
Internal System Reset
Once a reset condition has completed or been removed, code execution begins at the beginning of utility ROM, which is
address 8000h. The utility ROM code interrogates the I2C_SPE, JTAG_SPE, and PWL bits to determine if bootloading is
necessary. If bootloading is not required, execution will jump to the user code reset vector, which is at flash memory
address 0000h.
The /RST\ pin is an output as well as an input. If a reset condition is generated by one of the DS4830’s internal reset
sources (brownout, watchdog timer, or internal reset), an output reset pulse is generated on the /RST\ pin while the
DS4830 remains in reset.
2.6.1 – Power-On/Brownout Reset
The DS4830 provides a power-on reset (POR) circuit to ensure proper initialization of internal device states and analog
circuits. The POR voltage threshold range is between approximately 1.1V and 1.7V. When VDD is below the POR level,
the state of all the DS4830 pins, including /RST\, is weak pull up.
The DS4830 also includes brownout detection capability. This is an on-chip precision reference and comparator that
monitors the supply voltage, VDD, to ensure that it is within acceptable limits. If VDD is below the brownout level (VBO), the
power monitor generates a reset. This can occur when:
The DS4830 is being powered up and VDD is above the POR level but still less than VBO.
VDD drops from an acceptable level to less than VBO.
Once VDD exceeds VBO, the DS4830 exits the reset condition and the internal oscillator starts up. After approximately 1ms
(t
The transition between POR, Brownout, and normal operation is detailed in Figure 2-6: DS4830 State Diagram.
Note: If VDD is below VBO, there is a chance that the SRAM was corrupted. If the POR flag in WDCN is set, all data in
SRAM should be re-initialized.
) the DS4830 performs the following tasks.
SU:MOSC
All registers and circuits enter their reset state
The POR flag in the Watchdog Control Register is set to indicate the source of the reset
The DS4830 begins normal operation (CPU State)
Code execution begins at utility ROM location 8000h
20
BROWNOUT STATE
CPU DISABLED
ANALOG ACTIVE
SYSTEM CLOCK
STARTUP DELAY
CPU MODE
DIGITAL CORE ON
ANALOG ON
CODE EXECUTION
VDD > V
BO
VDD < VBO
POR
VDD < VBO
DS4830 User’s Guide
Figure 2-6: DS4830 State Diagram
2.6.2 – Watchdog Timer Reset
The watchdog timer is a programmable hardware timer that can be used to reset the processor in case a software lockup
or other unrecoverable error occurs. Once the watchdog is enabled, software must reset the watchdog timer periodically.
If the processor does not reset the watchdog timer before it elapses, the watchdog can initiate a reset.
If the watchdog resets the processor, the DS4830 will remain in reset and hold the /RST\ pin low for 12 clock cycles.
When a reset occurs due to a watchdog timeout, the Watchdog Timer Reset Flag (WTRF) in the WDCN register is set to
indicate the source of the reset.
2.6.3 – External Reset
During normal operation, the DS4830 is placed into external reset when the /RST\ pin is held at logic 0 for at least four
clock cycles. Once the DS4830 enters reset mode, it remains in reset as long as the /RST\ pin is held at logic 0. After the
/RST\ pin returns to logic 1, the processor exits reset within 12 clock cycles.
An external reset pulse on the /RST\ pin will reset the DS4830 and return to normal CPU mode operation within 10 clock
cycles.
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DS4830 User’s Guide
2.6.4 – Internal System Resets
There are two possible sources of internal system resets. An internal reset will hold the DS4830 in reset mode for 12
clock cycles.
1. When data BBh is written to the special I2C slave address 34h.
2. When in-system programming is complete and the ROD bit is set to 1.
2.7 – Clock Generation
The DS4830 generates its 20MHz peripheral clock using an internal oscillator and generates 10MHz instruction clock by
divide 2.This oscillator will startup when VDD exceeds the brownout voltage level, VBO. There is a delay of approximately
1msec between when the oscillator starts and when clocking of the DS4830 begins. This delay ensures that the clock is
stable prior to beginning normal operation.
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DS4830 User’s Guide
REGISTER
INDEX
REGISTER MODULE
AP (8h)
A (9h)
PFX (Bh)
IP (Ch)
SP (Dh)
DPC (Eh)
DP (Fh)
00h
AP
A[0]
PFX[0]
IP 01h
APC
A[1]
PFX[1]
SP
02h A[2]
PFX[2]
IV
03h A[3]
PFX[3]
OFFS
DP[0]
04h
PSF
A[4]
PFX[4]
DPC
05h
IC
A[5]
PFX[5]
GR
06h
IMR
A[6]
PFX[6]
LC[0]
GRL
07h
A[7]
PFX[7]
LC[1]
BP
DP[1]
08h
SC
A[8] GRS
09h
A[9] GRH
0Ah
A[10] GRXL
0Bh
IIR
A[11] FP
0Ch
A[12] 0Dh
A[13] 0Eh
A[14] 0Fh
WDCN
A[15]
SECTION 3 – SYSTEM REGISTER DESCRIPTIONS
Most functions of the DS4830 are controlled by sets of registers. These registers provide a working space for memory
operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major
types: system registers and peripheral registers. The common register set, also known as the system registers, includes
ALU access and control registers, accumulator registers, data pointers, interrupt vectors and control, and stack pointer.
The peripheral registers define additional functionality and the functionality is broken up into discrete modules.
This section describes the DS4830’s system registers. Table 3-1 shows the DS4830 system register map. Table 3-2
explains system register bit functions. This is followed by a detailed bit description.
Table 3-1. System Register Map
23
REGISTER
REGISTER BIT NUMBER
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
AP
— — — —
AP (4 bits)
APC
CLR
IDS
— — —
MOD2
MOD1
MOD0
PSF
Z S — GPF1
GPF0
OV C E
IC
—
— — — — —
INS
IGE
IMR
IMS — IM5
IM4
IM3
IM2
IM1
IM0
SC
TAP
—
—
CDA0
—
ROD
PWL
—
IIR
IIS — II5
II4
II3
II2
II1
II0
WDCN
POR
EWDI
WD1
WD0
WDIF
WTRF
EWT
RWT
A[n] (n=15:0)
A[n] (16 bits)
PFX[n] (n=7:0)
PFX[n] (16 bits)
IP
IP (16 bits)
SP
— — — — — — — — — — — — SP (4 bits)
IV
IV (16 bits)
LC[0]
LC[0] (16 bits)
LC[1]
LC[1] (16 bits)
OFFS
OFFS (8 bits)
DPC
— — — — — — — — — — —
WBS2
WBS1
WBS0
SDPS1
SDPS0
GR
GR (16 bits)
GRL
GRL (8 bits)
BP
BP (16 bits)
GRS
GRS (16 bits) = (GRL : GRH)
GRH
GRH (8 bits)
GRXL
GRXL (16 bits) = (GRL.7, 8 bits) : (GRL, 8 bits)
FP
FP = BP[OFFS] (16 bits)
DP[0]
DP[0] (16 bits)
DP[1]
DP[1] (16 bits)
Table 3-2. System Register Bit Functions
DS4830 User’s Guide
24
Bit
Name
Function
7:4
Reserved
Reserved. All reads return 0.
3:0
AP[3:0]
Active Accumulator Select. These bits select which of the 16 accumulator registers are used for arithmetic and logical
operations. If the APC register has been set to perform automatic increment/decrement of the active accumulator, this setting
will be automatically changed after each arithmetic or logical operation. If a ‘MOVE AP, Acc’ instruction is executed, any enabled
AP inc/dec/modulo control will take precedence over the transfer of Acc data into AP.
Bit
Name
Function
7
CLR
AP Clear. Writing this bit to 1 clears the accumulator pointer AP to 0. Once set, this bit will automatically be reset to 0 by
hardware. If a ‘MOVE APC, Acc’ instruction is executed requesting that AP be set to 0 (i.e., CLR = 1), the AP clear function
overrides any enabled inc/dec/modulo control. All reads from this bit return 0.
6
IDS
Increment/Decrement Select. If this bit is set to 0, the accumulator pointer AP is incremented following each arithmetic or logical
operation according to MOD[2:0]. If this bit is set to 1, the accumulator pointer AP is decremented following each arithmetic or
logical operation according to MOD[2:0]. If MOD[2:0] is set to 000, the setting of this bit is ignored.
5:3
Reserved
Reserved. All reads return 0.
2:0
MOD[2:0]
Accumulator Pointer Auto Increment/Decrement Modulus. If these bits are set to a nonzero value, the accumulator pointer
(AP[3:0]) will be automatically incremented or decremented following each arithmetic or logical operation. The mode for the
auto-increment/ decrement is determined as follows:
MOD[2:0]
AUTO INCREMENT/DECREMENT MODE
000
No auto-increment/decrement (default)
001
Increment/decrement AP[0] modulo 2
010
Increment/decrement AP[1:0] modulo 4
011
Increment/decrement AP[2:0] modulo 8
100
Increment/decrement AP modulo 16
101 to 111
Reserved (modulo 16 when set)
Bit
Name
Function
7
Z
Zero Flag. The value of this bit flag equals 1 whenever the active accumulator is equal to zero. This bit equals 0 if the active
accumulator is not equal to 0.
6 S Sign Flag. This bit flag mirrors the current value of the high bit of the active accumulator (Acc.15).
5
Reserved
Reserved. All reads return 0.
4:3
GPF[1:0]
General-Purpose Flags. These general-purpose flag bits are provided for user software control.
2
OV
Overflow Flag. This flag is set to 1 if there is a carry out of bit 14 but not out of bit 15, or a carry out of bit 15 but not out of bit 14
from the last arithmetic operation, otherwise, the OV flag remains as 0. OV indicates a negative number resulted as the sum of
two positive operands, or a positive sum resulted from two negative operands.
1
C
Carry Flag. This bit flag is set to 1 whenever an add or subtract operation (ADD, ADDC, SUB, SUBB) returns a carry or borrow.
This bit flag is cleared to 0 whenever an add or subtract operation does not return a carry or borrow. Many other instructions
potentially affect the carry bit. Reference the instruction set documentation for details.
0
E
Equals Flag. This bit flag is set to 1 whenever a compare operation (CMP) returns an equal result. If a CMP operation returns not
equal, this bit is cleared.
Bit
Name
Function
7:2
Reserved
Reserved. All reads return 0.
1
INS
Interrupt In Service. The INS is set by hardware automatically when an interrupt is acknowledged. No further interrupts occur as
long as the INS remains set. The interrupt service routine can clear the INS bit to allow interrupt nesting. Otherwise, the INS bit is
cleared by hardware upon execution of an RETI or POPI instruction.
0
IGE
Interrupt Global Enable. If this bit is set to 1, interrupts are globally enabled, but still must be locally enabled to occur. If this bit is
set to 0, all interrupts are disabled.
3.1 Accumulator Pointer Register (AP, 8h[0h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.2 Accumulator Pointer Control Register (APC, 8h[1h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.3 Processor Status Flags Register (PSF, 8h[4h])
Initialization: This register is cleared to 80h on all forms of reset.
Access: Bit 7 (Z), bit 6 (S), and bit 2 (OV) are read only. Bits [4:3] (GPF[1:0]), bit 1 (C), and bit 0 (E) are unrestricted
read/write.
3.4 Interrupt and Control Register (IC, 8h[5h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
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DS4830 User’s Guide
Bit
Name
Function
7
IMS
Interrupt Mask for System Modules
6
Reserved
Reserved. All reads return 0.
5
IM5
Interrupt Mask for Register Module 5
4
IM4
Interrupt Mask for Register Module 4
3
IM3
Interrupt Mask for Register Module 3
2
IM2
Interrupt Mask for Register Module 2
1
IM1
Interrupt Mask for Register Module 1
0
IM0
Interrupt Mask for Register Module 0
Bit
Name
Function
7
TAP
Test Access Port (JTAG) Enable. This bit controls whether the Test Access Port special-function pins are enabled. The TAP
defaults to being enabled. Clearing this bit to 0 disables the TAP special function pins.
6:5
Reserved
Reserved. All reads return 0.
4
CDA0
Code Data Access Bit 0.
The CDA0 bit is used to logically map the flash memory pages to the data space for read/write access. The logical data memory
addresses of the flash depend on whether execution is from Utility ROM or SRAM. The CDA0 bit is not needed if data memory is
accessed in word mode.
CDA0
Byte Mode Active Page
Word Mode Active Page
0
P0
P0 and P1
1
P1
P0 and P1
3
Reserved
Reserved. All reads return 0.
2
ROD
ROM Operation Done. This bit is used to signify completion of a ROM operation sequence to the control units. This allows the
Debug engine to determine the status of a ROM sequence. Setting this bit to logic 1 causes an internal system reset if the JTAG
SPE bit is also set. Setting the ROD bit will clear the JTAG SPE and I2C_SPE bits if set. The ROD bit will be automatically
cleared by hardware once the control unit acknowledges the done indication.
1
PWL
Password Lock. This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte password to be matched with
the password in the program space before allowing access to the password protected in-circuit debug or bootstrap loader ROM
routines. Clearing this bit to 0 disables the password protection for these ROM routines.
0
Reserved
Reserved. All reads return 0.
Bit
Name
Function
7
IIS
Interrupt Identifier Flag for System Modules
6
Reserved
Reserved. All reads return 0.
5
II5
Interrupt Identifier Flag for Register Module 5
4
II4
Interrupt Identifier Flag for Register Module 4
3
II3
Interrupt Identifier Flag for Register Module 3
2
II2
Interrupt Identifier Flag for Register Module 2
1
II1
Interrupt Identifier Flag for Register Module 1
0
II0
Interrupt Identifier Flag for Register Module 0
3.5 Interrupt Mask Register (IMR, 8h[6h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted read/write access.
The first six bits in this register are interrupt mask bits for modules 0 to 5, one bit per module. The eighth bit, IMS, serves
as a mask for any system module interrupt sources. Setting a mask bit allows the enabled interrupt sources for the
associated module or system (for the case of IMS) to generate interrupt requests. Clearing the mask bit effectively
disables all interrupt sources associated with that specific module or all system interrupt sources (for the case of IMS).
The interrupt mask register is intended to facilitate user-definable interrupt prioritization.
3.6 System Control Register (SC, 8h[8h])
Initialization: This register is reset to 1000 00s0b on all reset. Bit 1 (PWL) is set to 1 on a power-on reset only.
Access: Unrestricted read/write access.
3.7 Interrupt Identification Register (IIR, 8h[Bh])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Read only.
The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module. The eighth bit, IIS,
indicates a pending system interrupt, such as from the watchdog timer. The interrupt pending flags will be set only for
enabled interrupt sources waiting for service. The interrupt pending flag will be cleared when the pending interrupt
sources within that module are disabled or when the interrupt flags are cleared by software
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DS4830 User’s Guide
BIT
NAME
DESCRIPTION
7
POR
Power-On Reset Flag: This bit is set to 1 whenever a power-on/brownout reset occurs. It is unaffected by other forms of reset.
This bit can be checked by software following a reset to determine if a power-on/brownout reset occurred. It should always be
cleared by software following a reset to ensure that the sources of following resets can be determined correctly.
6
EWDI
Enable Watchdog Timer Interrupt: If this bit is set to 1, an interrupt request can be generated when the WDIF bit is set to 1 by any
means. If this bit is cleared to 0, no interrupt will occur when WDIF is set to 1, however, it does not stop the watchdog timer or
prevent watchdog resets from occurring if EWT = 1. If EWT = 0 and EWDI = 0, the watchdog timer will be stopped. If the
watchdog timer is stopped (EWT = 0 and EWDI = 0), setting the EWDI bit will reset the watchdog interval and reset counter, and
enable the watchdog timer. This bit is cleared to 0 by power-on reset and is unaffected by other forms of reset.
5:4
WD[1:0]
Watchdog Timer Interval Control Bits: These bits determine the watchdog timeout interval. The timeout interval is set in terms of
system clocks. Modifying the watchdog interval will automatically reset the watchdog timer unless the 512 system clock reset
counter is already in progress, in which case, changing the WD[1:0] bits will not affect the watchdog timer or reset counter.
WD1
WD0
CLOCKS UNTIL INTERRUPT
CLOCKS UNTIL RESET
0
0
212
212 + 512
0
1
215
215 + 512
1
0
218
218 + 512
1
1
221
221 + 512
3
WDIF
Watchdog Interrupt Flag: This bit will be set to 1 when the watchdog timer interval has elapsed or can be set to 1 by user
software. When WDIF = 1, an interrupt request will occur if the watchdog interrupt has been enabled (EWDI = 1) and not
otherwise masked or prevented by an interrupt already in service (i.e., IGE = 1, IMS = 1, and INS = 0 must be true for the
interrupt to occur). This bit should be cleared by software before exiting the interrupt service routine to avoid repeated interrupts.
Furthermore, if the watchdog reset has been enabled (EWT = 1), a reset is scheduled to occur 512 system clock cycles following
setting of the WDIF bit.
2
WTRF
Watchdog Timer Reset Flag: This bit is set to 1 when the watchdog resets the processor. Software can check this bit following a
reset to determine if the watchdog was the source of the reset. Setting this bit to 1 in software will not cause a watchdog reset.
This bit is cleared by power-on reset only and is unaffected by other forms of reset. It should also be cleared by software
following any reset so that the source of the next reset can be correctly determined by software. This bit is only set to 1 when a
watchdog reset actually occurs. If EWT is cleared to 0 when the watchdog timer elapses, this bit will not be set.
1
EWT
Enable Watchdog Timer Reset: If this bit is set to 1 when the watchdog timer elapses, the watchdog resets the DS4830 512
system clock cycles later unless action is taken to disable the reset event. Clearing this bit to 0 prevents a watchdog reset from
occurring but does not stop the watchdog timer or prevent watchdog interrupts from occurring if EWDI = 1. If EWT = 0 and EWDI
= 0, the watchdog timer will be stopped. If the watchdog timer is stopped (EWT = 0 and EWDI = 0), setting the EWT bit will reset
the watchdog interval and reset counter, and enable the watchdog timer. This bit is cleared on power-on reset and is unaffected
by other forms of reset.
0
RWT
Reset Watchdog Timer: Setting this bit to 1 resets the watchdog timer count. If watchdog interrupt and/or reset modes are
enabled, the software must set this bit to 1 before the watchdog timer elapses to prevent an interrupt or reset from occurring.
This bit always returns 0 when read.
BIT
DESCRIPTION
A[n][15:0]
These registers (n=0 to 15) act as the accumulator for all ALU arithmetic and logical operations when selected by the
accumulator pointer (AP). They can also be used as a general-purpose working register.
3.8 Watchdog Control Register (WDCN, 8h[Fh])
Initialization: Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions.
Access: Unrestricted direct read/write access.
3.9 Accumulator n Register (A[n], 9h[nh])
Initialization: These registers are cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
27
BIT
NAME
DESCRIPTION
15:0
PFX[n][15:0]
The Prefix register provides a means of supplying an additional 8 bits of high-order data for use by the succeeding instruction
as well as providing additional indexing capabilities. This register will only hold any data written to it for one execution cycle,
after which it will revert to 0000h. Although this is a 16-bit register, only the lower 8 bits are actually used for prefixing purposes
by the next instruction. Writing to or reading from any index in the Prefix module will select the same 16-bit register. However,
when the Prefix register is written, the index n used for the PFX[n] write also determines the high-order bits for the register
source and destination specified in the following instruction.
The index selection reverts to 0 (default mode allowing selection of registers 0h to 7h for destinations) after one cycle in the
same manner as the contents of the Prefix register.
WRITE TO
SOURCE REGISTER
RANGE
DESTINATION REGISTER
RANGE
PFX[0]
0h to Fh
0h to 7h
PFX[1]
10h to 1Fh
0h to 7h
PFX[2]
0h to Fh
8h to Fh
PFX[3]
10h to 1Fh
8h to Fh
PFX[4]
0h to Fh
10h to 17h
PFX[5]
10h to 1Fh
10h to 17h
PFX[6]
0h to Fh
18h to 1Fh
PFX[7]
10h to 1Fh
18h to 1Fh
BIT
DESCRIPTION
15:0
This register contains the address of the next instruction to be executed and is automatically incremented by 1 after each
program fetch. Writing an address value to this register will cause program flow to jump to that address. Reading from this
register will not affect program flow.
BIT
DESCRIPTION
15:4
Reserved; all reads return 0.
3:0
These four bits indicate the current top of the hardware stack, from 0h to Fh. This pointer is incremented after a value is
pushed on the stack and decremented before a value is popped from the stack.
BIT
DESCRIPTION
15:0
This register contains the address of the interrupt service routine. The interrupt handler will generate a CALL to this address
whenever an interrupt is acknowledged.
BIT
DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[0], src operation. This operation decrements LC[0] by one and
then jumps to the address specified in the instruction by src if LC[0] = 0.
BIT
DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[1], src operation. This operation decrements LC[1] by one and
then jumps to the address specified in the instruction by src if LC[1] = 0.
3.10 Prefix Register (PFX[n], Bh[n])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.11 Instruction Pointer Register (IP, Ch[0h])
Initialization: This register is cleared to 8000h on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.12 Stack Pointer Register (SP, Dh[1h])
Initialization: This register is cleared to 000Fh on all forms of reset.
Access: Unrestricted direct read/write access.
3.13 Interrupt Vector Register (IV, Dh[2h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.14 Loop Counter 0 Register (LC[0], Dh[6h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.15 Loop Counter 1 Register (LC[1], Dh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
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BIT
DESCRIPTION
7:0
This 8-bit register provides the Frame Pointer (FP) offset from the base pointer (BP). The Frame Pointer is formed by
unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset Register (Offs). The contents of this
register can be post-incremented or post-decremented when using the Frame Pointer for read operations and may be
pre-incremented or pre-decremented when using the Frame Pointer for write operations. A carry out or borrow resulting
from an increment/decrement operation has no effect on the Frame Pointer Base Register (BP).
BIT
NAME
DESCRIPTION
15:5
RESERVED
Reserved. All reads return 0.
4
WBS2
Word/Byte Select 2. This bit selects access mode for BP[Offs]. When WBS2 is set to logic 1, the BP[Offs] is operated in word
mode for data memory access; when WBS2 is cleared to logic 0, BP[Offs] is operated in byte mode for data memory access.
3
WBS1
Word/Byte Select 1. This bit selects access mode for DP[1]. When WBS1 is set to logic 1, the DP[1] is operated in word mode
for data memory access; when WBS1 is cleared to logic 0, DP[1] is operated in byte mode for data memory access.
2
WBS0
Word/Byte Select 0. This bit selects access mode for DP[0]. When WBS0 is set to logic 1, the DP[0] is operated in word mode
for data memory access; when WBS0 is cleared to logic 0, DP[0] is operated in byte mode for data memory access.
1:0
SDPS[1:0]
Source Data Pointer Select Bits[1:0]. These bits select one of the three data pointers as the active source pointer for the load
operation. A new data pointer must be selected before being used to read data memory:
SDPS1
SDPS0
SOURCE POINTER SELECTION
0
0
DP[0]
0
1
DP[1]
1
0
FP (BP[Offs])
1 1 Reserved (select FP if set)
These bits default to 00b but do not activate DP[0] as an active source pointer until the SDPS bits are explicitly cleared to 00b or
the DP[0] register is written by an instruction. Also, modifying the register contents of a data/frame pointer register (DP[0],
DP[1], BP or Offs) will change the setting of the SDPS bits to reflect the active source pointer selection.
BIT
DESCRIPTION
15:0
This register is intended primarily for supporting byte operations on 16-bit data. The 16-bit register is byte-readable, bytewriteable through the corresponding GRL and GRH 8-bit registers and byte-swappable through the GRS 16-bit register.
BIT
DESCRIPTION
7:0
This register reflects the low byte of the GR register and is intended primarily for supporting byte operations on 16-bit data.
Any data written to the GRL register will also be stored in the low byte of the GR register.
BIT
DESCRIPTION
15:0
This register serves as the base pointer for the Frame Pointer (FP). The Frame Pointer is formed by unsigned addition of
Frame Pointer Base Register (BP) and Frame Pointer Offset Register (Offs). The content of this base pointer register is not
affected by increment/decrement operations performed on the offset (OFFS) register.
BIT
DESCRIPTION
15:0
This register is intended primarily for supporting byte operations on 16-bit data. This 16-bit read only register returns the
byte-swapped value for the data contained in the GR register.
3.16 Frame Pointer Offset Register (OFFS, Eh[3h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.17 Data Pointer Control Register (DPC, Eh[4h])
Initialization: This register is cleared to 001Ch on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.18 General Register (GR, Eh[5h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.19 General Register Low Byte (GRL, Eh[6h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.20 Frame Pointer Base Register (BP, Eh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
3.21 General Register Byte-Swapped (GRS, Eh[8h])
Initialization: This register is cleared to 0000h on all forms of reset
Access: Unrestricted read-only access.
29
BIT
DESCRIPTION
7:0
This register reflects the high byte of the GR register and is intended primarily for supporting byte operations on 16-bit data.
Any data written to the GRH register will also be stored in the high byte of the GR register.
BIT
DESCRIPTION
15:0
This register provides the sign extended low byte of GR as a 16-bit source.
BIT
DESCRIPTION
15:0
This register provides the current value of the frame pointer (BP[Offs]).
BIT
DESCRIPTION
15:0
This register is used as a pointer to access data memory. DP[0] can be automatically incremented or decremented
following each read operation or can be automatically incremented or decremented before each write operation.
BIT
DESCRIPTION
15:0
This register is used as a pointer to access data memory. DP[1] can be automatically incremented or decremented
following each read operation or can be automatically incremented or decremented before each write operation.
3.22 General Register High Byte (GRH, Eh[9h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
3.23 General Register Sign Extended Low Byte (GRXL, Eh[Ah])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read-only access.
3.24 Frame Pointer Register (FP, Eh[Bh])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read-only access.
3.25 Data Pointer 0 Register (DP[0], Fh[3h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
DS4830 User’s Guide
3.26 Data Pointer 1 Register (DP[1], Fh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
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