The DS33Z41 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over up to four
interleaved PDH/TDM data streams using robust,
balanced, and programmable inverse multiplexing.
The Interleave Bus (IBO) serial link supports
seamless bidirectional interconnection with Dallas
Semiconductor’s T1/E1 framers and transceivers.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) Controller
provides fractional bandwidth allocation up to the
line rate in increments of 512kbps.
FUNCTIONAL DIAGRAM
Serial
BERT
HDLC/X.86
Mapper
10/100
MAC
DS33Z41
IBO
Config.
Loader
MII/RMII
Up to 4
Transceivers
or Framers
C
SDRAM
10/100
Ethernet
PHY
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Layer 1 Inverse Multiplexing Allows Bonding of
Up to 4 T1/E1/J1 or DSL Links
Supports Up to 7.75ms Differential Delay
Channel (Byte) Interleaved Bus Operation
In-Band OAM and Signaling Capability
HDLC/LAPS Encapsulation with Programmable
FCS, Interframe Fill
Committed Information Rate Controller Provides
Fractional Allocation in 512kbps Increments
Programmable BERT for the Serial Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V Operation with 3.3V Tolerant I/O
IEEE 1149.1 JTAG Support
Features continued on page 8.
APPLICATIONS
Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1,
G.SHDSL, or HDSL2/4
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS33Z41
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
8.1.2 Clear on Read.....................................................................................................................................23
8.1.3 Interrupt and Pin Modes......................................................................................................................23
8.9.3 Out of Frame (OOF) Monitoring..........................................................................................................36
8.9.4 Data Transfer ......................................................................................................................................36
8.10 CONNECTIONS AND QUEUES........................................................................................................37
8.14.1 MII Mode .............................................................................................................................................47
8.15.1 BERT Features ...................................................................................................................................48
8.15.2 Receive Data Interface .......................................................................................................................49
9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................112
9.6.2 MAC Registers..................................................................................................................................124
Figure 8-1. Clocking for the DS33Z41..................................................................................................................... 25
Figure 8-2. Device Interrupt Information Flow Diagram .......................................................................................... 30
Figure 8-3. IMUX Interface to T1/E1 Transceivers.................................................................................................. 32
Figure 8-4. Diagram of Data Transmission with IMUX Operation ........................................................................... 32
Figure 8-5. Command Structure for IMUX Function................................................................................................ 34
Figure 8-6. Flow Control Using Pause Control Frame ............................................................................................ 41
Figure 8-11. MII Management Frame...................................................................................................................... 48
Figure 8-12. PRBS Synchronization State Diagram................................................................................................ 49
Figure 8-13. Repetitive Pattern Synchronization State Diagram............................................................................. 50
Figure 8-14. LAPS Encoding of MAC Frames Concept .......................................................................................... 55
Figure 8-15. X.86 Encapsulation of the MAC field .................................................................................................. 56
Figure 8-16. CIR in the WAN Transmit Path ........................................................................................................... 59
Figure 10-1. MII Transmit Functional Timing......................................................................................................... 140
Figure 10-2. MII Transmit Half Duplex with a Collision Functional Timing............................................................ 140
Figure 10-3. MII Receive Functional Timing.......................................................................................................... 141
Figure 12-2. TAP Controller State Diagram .......................................................................................................... 162
Table 8-3. Commands Sent and Received on the IMUX Links............................................................................... 34
Table 8-4. Command and Status for the IMUX for Processor Communication....................................................... 35
Table 8-5. Registers Related to Connections and Queues ..................................................................................... 38
Table 8-6. Options for Flow Control......................................................................................................................... 39
Table 8-7. Registers Related to the Ethernet Port .................................................................................................. 43
Table 8-8. MAC Control Registers........................................................................................................................... 46
Table 8-9. MAC Status Registers ............................................................................................................................ 46
Table 9-2. Global Register Bit Map ......................................................................................................................... 61
Table 9-3. Arbiter Register Bit Map ......................................................................................................................... 62
Table 9-4. BERT Register Bit Map .......................................................................................................................... 62
Table 9-5. Serial Interface Register Bit Map ........................................................................................................... 63
Table 9-6. Ethernet Interface Register Bit Map ....................................................................................................... 65
Table 9-7. MAC Indirect Register Bit Map............................................................................................................... 66
Table 11-1. Recommended DC Operating Conditions.......................................................................................... 142
Table 11-2. DC Electrical Characteristics.............................................................................................................. 142
Table 12-1. Instruction Codes for IEEE 1149.1 Architecture ................................................................................ 163
Table 12-2. ID Code Structure............................................................................................................................... 164
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DS33Z41 Quad IMUX Ethernet Mapper
1 DESCRIPTION
The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN
Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a
10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86 (LAPS) Mapper,
SDRAM interface, control ports, and Bit Error Rate Tester (BERT). The packet interface consists of an Ethernet
interface using several physical layer protocols. The Ethernet interface can be configured for 10Mbps or 100Mbps
service. The DS33Z41 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) to be transmitted over the WAN
interface. The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets
over the Ethernet port. The WAN physical interface is based on the Dallas Semiconductor Interleaved Bus
Operation (IBO), running at 8.192Mbps. The IBO interface can be configured to allow up to four bonded T1 or E1
data streams. The IBO interface provides for seamless connection to the Dallas Semiconductor/Maxim multi-port
T1/E1/J1 Framers and Single-Chip Transceivers (SCTs). See Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN solution.
The DS33Z41 is controlled through an 8-bit microcontroller port. The DS33Z41 has a 100MHz SDRAM controller
and interfaces to a 32-bit wide 128Mb SDRAM. The SDRAM is used to buffer the data from the Ethernet and
WAN ports for transport. The external SDRAM can accommodate up to 8192 frames with a maximum frame size
of 2016 bytes. The DS33Z41 operates with a 1.8V core supply and 3.3V I/O supply.
7 of 167
2 FEATURE HIGHLIGHTS
2.1 General
• 169-pin, 14mm x 14mm CSBGA package
• 1.8V supply with 3.3V tolerant inputs and outputs
• IEEE 1149.1 JTAG boundary scan
• Software access to device ID and silicon revision
• Development support includes evaluation kit, driver source code, and reference designs
2.2 Link Aggregation (Inverse Multiplexing)
• Link aggregation for up to 4 T1/E1 Links
• 8.192Mbps IBO interface to Dallas Semiconductor Framers/Transceivers
• Differential delay compensation up to 7.75ms for the 4 T1/E1 links
• Handshaking protocol between local and distant end for establishment of aggregation
2.3 HDLC
• HDLC controller engine
• Compatible with polled or interrupt driven environments
• Programmable FCS insertion and extraction
• Programmable FCS type
• Supports FCS error insertion
• Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)
• Supports bit stuffing/destuffing
• Selectable packet scrambling/descrambling (X
• Separate FCS errored packet and aborted packet counts
• Programmable inter-frame fill for transmit HDLC
43
DS33Z41 Quad IMUX Ethernet Mapper
+1)
2.4 Committed Information Rate (CIR) Controller
• CIR controller limits transmission of data from the Ethernet Interface to the Serial Interface.
• CIR granularity at 512kbps
• CIR Averaging for smoothing traffic peaks
2.5 X.86 Support
• Programmable X.86 address/control fields for transmit and receive
• Programmable 2-byte protocol (SAPI) field for transmit and receive
• 32 bit FCS
• Transmit Transparency processing - 7E is replaced by 7D, 5E
• Transmit Transparency processing – 7D replaced by 7D, 5D
• Receive rate adaptation (7D, DD) is deleted.
• Receive Transparency processing - 7D, 5E is replaced by 7E
• Receive Transparency processing – 7D, 5D is replaced by 7D
• Receive Abort Sequence the LAPS packet is dropped if 7D7E is detect
• Self-synchronizing X
• Frame indication due to bad Address/Control/SAPI, FCS error, abort sequence or frame size longer
than preset max.
43
+1 payload scrambling.
8 of 167
2.6 SDRAM Interface
• Interface for 128Mb, 32-bit-wide SDRAM
• SDRAM Interface speed up to 100MHz
• Auto Refresh Timing
• Automatic Precharge
• Master clock provided to the SDRAM
• No external components required for SDRAM connectivity
2.7 MAC Interface
• MAC port with standard MII (less TX_ER) or RMII
• 10Mbps and 100Mbps Data rates
• Configurable DTE or DCE modes
• Facilitates auto-negotiation by host microprocessor
• Programmable half and full-duplex modes
• Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
• Programmable Maximum MAC frame size up to 2016 bytes
• Minimum MAC frame size: 64 bytes
• Discards frames greater than Programmed Maximum MAC frame size and Runt, non-octet bounded,
or bad-FCS frames upon reception
• Programmable threshold for SDRAM queues to initiate flow control and status indication
• MAC Loopback support for Transmit data looped to Receive Data at the MII/RMII interface
DS33Z41 Quad IMUX Ethernet Mapper
2.8 Microprocessor Interface
• 8 bit data bus
• Non-multiplexed Intel and Motorola Timing Modes
• Internal software reset and External Hardware reset input pin
• Global interrupt output pin
2.9 Test and Diagnostics
• IEEE 1149.1 Support
• Programmable on-chip Bit Error Rate Tester (BERT)
• Patterns include Pseudorandom QRSS, Daly, and user-defined repetitive patterns
• Loopbacks (remote, local, analog, and per-channel loopback)
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DS33Z41 Quad IMUX Ethernet Mapper
2.10 Specifications compliance
The DS33Z41 meets relevant telecommunications specifications. The following table provides the specifications
and relevant sections that are applicable to the DS33Z41.
Table 2-1. T1 Related Telecommunications Specifications
IEEE 802.3-2002—CSMA/CD access method and physical layer specifications
RFC1662—PPP in HDLC-like Framing
RFC2615—PPP over SONET/SDH
X.86—Ethernet over LAPS
RMII—Industry Implementation Agreement for “Reduced MII Interface” (Sept. 1997)
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DS33Z41 Quad IMUX Ethernet Mapper
3 APPLICATIONS
• Bonded Transparent LAN Service
• LAN Extension
• Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4
Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of
a complete LAN to WAN design.
Figure 3-1. Quad T1/E1 SCT to DS33Z41
T1/E1
Framer/LIU
DS21455
DS21458
DS26528
HDLC/X.86
Serial
Stream
(IBO)
RMII, MII
10 Base T
100 Base T
EthernetDS33Z41
Clock
Sources
SDRAM
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DS33Z41 Quad IMUX Ethernet Mapper
4 ACRONYMS AND GLOSSARY
• BERT—Bit Error Rate Tester
• DCE—Data Communication Interface
• DTE—Data Terminating Interface
• FCS—Frame Check Sequence
• HDLC—High Level Data Link Control
• MAC—Media Access Control
• MII—Media Independent Interface
• RMII—Reduced Media Independent Interface
• WAN—Wide Area Network
Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interface function.
The register names have been allowed to remain with a “SU.” prefix to avoid register renaming.
Note 2: Previous versions of this document used the term “Line” to refer to the Serial Interface. The register
names have been allowed to remain with a “LI.” prefix to avoid register renaming.
Note 3: The terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet Interface. The
Receive Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and
stored in the SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and
stored in the SDRAM to be sent to the MAC transmitter.
Note 4: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each
125µs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first
followed by channel 1.
Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link
aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information
on microprocessor control is available in Section 8.1
.
6 BLOCK DIAGRAMS
Figure 6-1. Detailed Block Diagram
50 or 25 Mhz Oscillator
Microport
Buffer
Div by 1,2,4,8,10
Output clocks:
50,25 Mhz,2.5 Mhz
REF_CLK
TSER
TCLKI1
RCLKI1
RSER
Line 1
IMUX
HDLC
Serial
Interface
JTAG
+
X.86
CIR
SDRAM
Arbiter
SDRAM
Interface
SDCLKO
MAC
RMII
MII
Buffer Dev
Div by 2,4,12
Output Clocks
25,50
Mhz
REF_CLKO
50 or 25 Mhz
TX_CLK1
RXD
RX_CLK1
TXD
MDC
100 Mhz Oscillator
SYSCLKI
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DS33Z41 Quad IMUX Ethernet Mapper
7 PIN DESCRIPTIONS
7.1 Pin Functional Description
Note that all digital pins are inout pins in JTAG mode. This feature increases the effectiveness of board level
ATPG patterns.
Table 7-1. Detailed Pin Descriptions
Note: I = Input; O = Output; Ipu = Input with pullup; Oz = Output with tri-state; IO = Bidirectional pin; IOz = Bidirectional pin with tri-state.
NAME PIN TYPE FUNCTION
SERIAL INTERFACE IO PINS
Serial Interface Transmit Clock Input. The clock reference for TSER,
TCLKIF1 I
TSERF2 O
TSYNC G3 I
RCLKIG2 I
RSER H1 I
RSYNCG1 I
REF_CLKD13 I
REF_CLKOE13 O
which is output on the rising edge of the clock. TCLKI supports gapped
clocking, up to a maximum frequency of 52MHz.
Transmit Serial Data Output. Output on the rising edge of TCLKI.
Selective clock periods can be skipped for output of TSER with a
gapped clock input on TCLKI. The maximum data rate is 52Mbps.
Transmit Synchronization Input. An 8lHz synchronization pulse, used
to denote the first Channel 1 of the 8.192Mbps byte-interleaved IBO
data stream. Note that this input is also used to generate the transmit
byte synchronization if X.86 mode is enabled.
Serial Interface Receive Clock Input. Reference clock for receive
serial data on RSER. Gapped clocking is supported, up to the
maximum RCLKI frequency of 52MHz.
Receive Serial Data Input. Receive Serial data arrives on the rising
edge of the clock.
Receive Synchronization Input. An 8kHz synchronization pulse, used
to denote the first Channel 1 of the 8.192Mbps byte-interleaved IBO
data stream. Note that this input is also used to generate the receive
byte synchronization if X.86 mode is enabled.
MII/RMII PORT
Reference Clock (RMII and MII). When in RMII mode, all signals from
the PHY are synchronous to this clock input for both transmit and
receive. This required clock can be up to 50MHz and should have
±100ppm accuracy.
When in MII mode in DCE operation, the DS33Z41 uses this input to
generate the RX_CLK and TX_CLK outputs as required for the
Ethernet PHY interface. When the MII interface is used with DTE
operation, this clock is not required and should be tied low.
In DCE and RMII modes, this input must have a stable clock input
before setting the RST pin high for normal operation.
Reference Clock Output (RMII and MII). A derived clock output up to
50MHz, generated by internal division of the SYSCLKI signal.
Frequency accuracy of the REF_CLKO signal will be proportional to the
accuracy of the user-supplied SYSCLKI signal. See Section 8.2.2
more information.
for
14 of 167
DS33Z41 Quad IMUX Ethernet Mapper
NAME PIN TYPE FUNCTION
Transmit Clock (MII). Timing reference for TX_EN and TXD[3:0]. The
TX_CLK frequency is 25MHz for 100Mbps operation and 2.5MHz for
10Mbps operation.
TX_CLK A8 IO
In DTE mode, this is a clock input provided by the PHY. In DCE mode,
this is an output derived from REF_CLK providing 2.5MHz (10Mbps
operation) or 25MHz (100Mbps operation).
Transmit Enable (MII):
This pin is asserted high when data TXD [3:0] is being provided by the
DS33Z41. The signal is deasserted prior to the first nibble of the next
frame. This signal is synchronous with the rising edge TX_CLK. It is
TX_EN E10 O
asserted with the first bit of the preamble.
Transmit Enable (RMII):
When this signal is asserted, the data on TXD [1:0] is valid. This signal
is synchronous to the REF_CLK.
Transmit Data 0 through 3(MII). TXD [3:0] is presented synchronously
TXD[0]
TXD[1]
TXD[2]
TXD[3]
B9
C9
D9
E9
with the rising edge of TX_CLK. TXD [0] is the least significant bit of the
data. When TX_EN is low the data on TXD should be ignored.
O
Transmit Data 0 through 1(RMII). Two bits of data TXD [1:0]
presented synchronously with the rising edge of REF_CLK.
Receive Clock (MII). Timing reference for RX_DV, RX_ERR and
RXD[3:0], which are clocked on the rising edge. RX_CLK frequency is
RX_CLK A10 IO
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In
DTE mode, this is a clock input provided by the PHY. In DCE mode,
this is an output derived from REF_CLK providing 2.5MHz (10Mbps
operation) or 25MHz (100Mbps operation).
Receive Data 0 through 3(MII). Four bits of received data, sampled
synchronously with the rising edge of RX_CLK. For every clock cycle,
the PHY transfers 4 bits to the DS33Z41. RXD[0] is the least significant
RXD[0]
RXD[1]
RXD[2]
RXD[3]
B11
C11
D11
A11
bit of the data. Data is not considered valid when RX_DV is low.
I
Receive Data 0 through 1(RMII). Two bits of received data, sampled
synchronously with REF_CLK with 100Mbps mode. Accepted when
CRS_DV is asserted. When configured for 10Mbps mode, the data is
sampled once every 10 clock periods.
RX_DV D10 I
Receive Data Valid (MII). This active high signal indicates valid data
from the PHY. The data RXD is ignored if RX_DV is not asserted high.
Receive Carrier Sense (MII). Should be asserted (high) when data
from the PHY (RXD[3:0) is valid. For each clock pulse 4 bits arrive from
RX_CRS/
CRS_DV
C8 I
the PHY. Bit 0 is the least significant bit. In DCE mode, connect to V
Carrier Sense/Receive Data Valid (RMII). This signal is asserted
(high) when data is valid from the PHY. For each clock pulse 2 bits
arrive from the PHY. In DCE mode, this signal must be grounded.
Receive Error (MII). Asserted by the MAC PHY for one or more
RX_CLK periods indicating that an error has occurred. Active High
indicates Receive code group is invalid. If CRS_DV is low, RX_ERR
RX_ERR B12 I
has no effect. This is synchronous with RX_CLK. In DCE mode, this
signal must be grounded.
Receive Error (RMII). Signal is synchronous to REF_CLK.
DD
.
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DS33Z41 Quad IMUX Ethernet Mapper
NAME PIN TYPE FUNCTION
Collision Detect (MII). Asserted by the MAC PHY to indicate that a
COL_DET B13 I
collision is occurring. In DCE Mode this signal should be connected to
ground. This signal is only valid in half duplex mode, and is ignored in
full duplex mode
Management Data Clock (MII). Clocks management data between the
MDC C12 O
PHY and DS33Z41. The clock is derived from SYSCLKI, with a
maximum frequency is 1.67MHz. The user must leave this pin
unconnected in the DCE Mode.
MII Management data IO (MII). Data path for control information
between the PHY and DS33Z41. When not used, pull to logic high
MDIO C13 IO
externally through a 10kΩ resistor. The MDC and MDIO pins are used
to write or read up to 32 Control and Status Registers in 32 PHY
Controllers. This port can also be used to initiate Auto-Negotiation for
the PHY. The user must leave this pin unconnected in the DCE Mode.
MICROPROCESSOR PORT
A0 A1 I
Address Bit 0. Address bit 0 of the microprocessor interface. Least
Significant Bit.
A1 B1 I Address Bit 1. Address bit 1 of the microprocessor interface.
A2 A2 I Address Bit 2. Address bit 2 of the microprocessor interface.
A3 B2 I Address Bit 3. Address bit 3 of the microprocessor interface.
A4 C2 I Address Bit 4. Address bit 4 of the microprocessor interface.
A5 A3 I Address Bit 5. Address bit 5 of the microprocessor interface.
A6 B3 I Address Bit 6. Address bit 6 of the microprocessor interface.
A7 C3 I Address Bit 7. Address bit 7 of the microprocessor interface.
A8 A4 I Address Bit 8. Address bit 8 of the microprocessor interface.
A9 B4 I
D0 A5 IOZ
D1 A6 IOZ
D2 A7 IOZ
D3 B5 IOZ
D4 B6 IOZ
D5 B7 IOZ
D6 C5 IOZ
D7 C6 IOZ
CS
C1 I
Address Bit 9. Address bit 9 of the microprocessor interface. Most
Significant Bit.
Data Bit 0. Bidirectional data bit 0 of the microprocessor interface.
Least Significant Bit. Not driven when CS = 1 or RST = 0.
Data Bit 1. Bidirectional data bit 1 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 2. Bidirectional data bit 2 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 3. Bidirectional data bit 3 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 4. Bidirectional data bit 4 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 5. Bidirectional data bit 5 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 6. Bidirectional data bit 6 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 7. Bidirectional data bit 7 of the microprocessor interface. Most
Significant Bit. Not driven when CS = 1 or RST = 0.
Chip Select. This pin must be taken low for read/write operations.
When CS is high, the RD/DS and WR signals are ignored.
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DS33Z41 Quad IMUX Ethernet Mapper
NAME PIN TYPE FUNCTION
Read Data Strobe (Intel Mode). The DS33Z41 drives the data bus
(D0-D7) with the contents of the addressed register while RD and CS
are both low.
RD/DS
E1 I
Data Strobe (Motorola Mode). Used to latch data through the
microprocessor interface. DS must be low during read and write
operations.
Write (Intel Mode). The DS33Z41 captures the contents of the data
bus (D0:D7) on the rising edge of WR and writes them to the addressed
register location. CS must be held low during write operations.
WR/RW
E2 I
Read Write (Motorola Mode). Used to indicate read or write
operation. RW must be set high for a register read cycle and low for a
register write cycle.
Interrupt Output. Outputs a logic zero when an unmasked interrupt
event is detected. Outputs a logic zero when an unmasked interrupt
event is detected. INT is deasserted when all interrupts have been
INT
F3 OZ
acknowledged and serviced. Active low. Inactive state is programmable
in register GL.CR1. is deasserted when all interrupts have been
acknowledged and serviced. Active low. Inactive state is programmable
in register GL.CR1.
Reset. An active-low signal on this pin resets the internal registers and
logic. This pin should remain low until power, SYSCLKI, RX_CLK, and
RST
D8 I
TX_CLK are stable, then set high for normal operation. This input
requires a clean edge with a rise time of 25ns or less to properly reset
the device.
Mode Control
MODEC[0]
MODEC[1]
D6
D7
00 = Read/Write Strobe Used (Intel Mode)
I
01 = Data Strobe Used (Motorola Mode)
10 = Reserved. Do not use.
11 = Reserved. Do not use.
DCE or DTE Selection. The user must set this pin high for DCE Mode
selection or low for DTE Mode. In DCE Mode, the DS33Z41 MAC port
can be directly connected to another MAC. In DCE Mode, the Transmit
DCEDTES A13 I
clock (TX_CLK) and Receive clock (RX_CLK) are output by the
DS33Z41. Note that there is no software bit selection of DCEDTES.
Note that DCE Mode is only relevant when the MAC interface is in MII
mode.
RMIIMIIS C4 I
RMII or MII Selection. Set high to configure the MAC for RMII
SDRAM Data Bus Bits 0 to 31: The 32 pins of the SDRAM data bus
are inputs for read operations and outputs for write operations. At all
other times, these pins are high impedance.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SDRAM Address Bus 0 to 11. The 12 pins of the SDRAM address bus
output the row address first, followed by the column address. The row
address is determined by SDA0 to SDA11 at the rising edge of clock.
Column address is determined by SDA0-SDA9 and SDA11 at the rising
edge of the clock. SDA10 is used as an auto-precharge signal.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SDRAM Bank Select. These 2 bits select 1 of 4 banks for the
SBA[0]
SBA[1]
M6
N7
read/write/precharge operations.
I
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SDRAM Row Address Strobe. Active-low output, used to latch the row
SRAS
K6 O
address on rising edge of SDCLKO. It is used with commands for Bank
Activate, Precharge, and Mode Register Write.
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DS33Z41 Quad IMUX Ethernet Mapper
NAME PIN TYPE FUNCTION
SDRAM Column Address Strobe. Active-low output, used to latch the
SCAS
H4 O
column address on the rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SWE
SDMASK[0]
SDMASK[1]
SDMASK[2]
SDMASK[3]
M4 O
N6
G4
M10
M9
SDCLKO N5
(4mA)
SDRAM Write Enable. This active-low output enables write operation
and auto precharge.
SDRAM Mask 0 to 3. When high, a write is done for that byte. The
O
least significant byte is SDATA7 to SDATA0. The most significant byte
is SDATA31 to SDATA24.
O
SDRAM CLK Out. System clock output to the SDRAM. This clock is a
buffered version of SYSCLKI.
System Clock In. 100MHz System Clock input to the DS33Z41, used
for internal operation. This clock is buffered and provided at SDCLKO
SYSCLKI G13 I
for the SDRAM interface. The DS33Z41 also provides a divided version
output at the REF_CLKO pin. A clock supply with ±100ppm frequency
accuracy is suggested.
SDCS
L6 O SDRAM Chip Select. Active-low output enables SDRAM access.
QUEUE STATUS
Queue Overflow. This pin goes high when the transmit or receive
QOVF C7 O
queue has overflowed. This pin will go low when the high watermark is
reached again.
JTAG INTERFACE
JTAG Reset. JTRST is used to asynchronously reset the test access
port controller. After power-up, a rising edge on JTRST will reset the
JTRST
E6 Ipu
test port and cause the device I/O to enter the JTAG DEVICE ID mode.
Pulling JTRST low restores normal device operation. JTRST is pulled
HIGH internally via a 10kΩ resistor operation. If boundary scan is not
used, this pin should be held low.
JTCLK D4 Ipu
JTAG Clock. This signal is used to shift data into JTDI on the rising
edge and out of JTDO on the falling edge.
JTAG Data Out. Test instructions and data are clocked out of this pin
JTDO E5 Oz
on the falling edge of JTCLK. If not used, this pin should be left
unconnected.
JTDI E4 Ipu
JTAG Data In. Test instructions and data are clocked into this pin on
the rising edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK
JTMS F7 Ipu
and is used to place the test access port into the various defined IEEE
1149.1 states. This pin has a 10kΩ pullup resistor.
The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN
Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a
10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86(LAPS) Mapper,
SDRAM interface, Serial IBO interface, control ports, and Bit Error Rate Tester (BERT).
The Ethernet Packet interfaces support MII and RMII interfaces allowing DSZ33Z41 to connect to commercially
available Ethernet PHY and MAC devices. The Ethernet interfaces can be individually configured for 10Mbps or
100Mbps service, in DTE and DCE configurations. The DS33Z41 MAC interface can be configured to reject
frames with bad FCS and short frames (less than 64 bytes).
Ethernet frames are queued and stored in external 32-bit SDRAM. The DS33Z41 SDRAM controller enables
connection to a 128Mbit SDRAM without external glue logic, at clock frequencies up to 100MHz. The SDRAM is
used for both the Transmit and Receive Data Queues. The Receive Queue stores data to be sent from the Packet
interface to the WAN interface. The Transmit Queue stores data to be sent from the WAN interface to the Packet
interface. The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes.
The sizing of the queues can be adjusted by software. The user can also program high and low watermarks for
each queue that can be used for automatic or manual flow control. The packet data stored in the SDRAM is
encapsulated in HDLC or X.86 (LAPS) to be transmitted over the WAN interfaces. The device also provides the
capability for bit and packet scrambling.
The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet port. The WAN physical interface supports up to four serial data streams on a 8.192Mbps IBO bus. The
WAN serial port can operate with a gapped clock, and can be connected to a framer or T/E-Carrier transceiver for
transmission to the WAN. The WAN interface can be seamlessly connected to the Dallas Semiconductor/Maxim
T1/E1/J1 Framers and Single-Chip Transceivers (SCTs).
The DS33Z41 can be configured through an 8-bit Microprocessor interface port. The DS33Z41 also provides two
on-board clock dividers for the System Clock input and Reference Clock Input for the 802.3 interfaces, further
reducing the need for ancillary devices.
22 of 167
DS33Z41 Quad IMUX Ethernet Mapper
8.1 Processor Interface
Microprocessor control of the DS33Z41 is accomplished through the 20 interface pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0]
pins. When MODEC[1:0] = 00, bus timing is in Intel mode, as shown in Figure 11-11
MODEC[1:0] = 01, bus timing is in Motorola mode, as shown in Figure 11-13
space is mapped through the use of 8 address lines, A0 - A7. Multiplexed Mode is not supported on the processor
interface.
The Chip Select (CS) pin must be brought to a logic low level to gain read and write access to the microprocessor
port. With Intel timing selected, the Read (RD) and Write (WR) pins are used to indicate read and write operations
and latch data through the interface. With Motorola timing selected, the Read-Write (RW) pin is used to indicate
read and write operations while the Data Strobe (DS) pin is used to latch data through the interface.
The interrupt output pin (INT) is an open-drain output that will assert a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The register
map is shown in Table 9-1
.
and Figure 11-14. The address
8.1.1 Read-Write/Data Strobe Modes
The processor interface can operate in either read-write strobe mode or data strobe mode. When MODEC[1:0] =
00 the read-write strobe mode is enabled and a negative pulse on RD performs a read cycle, and a negative
pulse on WR performs a write cycle. When MODEC[1:0] pins = 01 the data strobe mode is enabled and a
negative pulse on DS when RW is high performs a read cycle, and a negative pulse on DS when RW is low
performs a write cycle. The read-write strobe mode is commonly called the “Intel” mode, and the data strobe
mode is commonly called the “Motorola” mode.
and Figure 11-12. When
8.1.2 Clear on Read
The latched status registers will clear on a read access. It is important to note that in a multi-task software
environment, the user should handle all status conditions of each register at the same time to avoid inadvertently
clearing status conditions. The latched status register bits are carefully designed so that an event occurrence
cannot collide with a user read access.
8.1.3 Interrupt and Pin Modes
The interrupt (INT) pin is configurable to drive high or float when not active. The INTM bit controls the pin
configuration, when it is set the INT pin will drive high when not active. After reset, the INT pin is in high
impedance mode until an interrupt source is active and enabled to drive the interrupt pin.
23 of 167
DS33Z41 Quad IMUX Ethernet Mapper
8.2 Clock Structure
The DS33Z41 clocks sources and functions are as follows:
• Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from
the serial interface. These clocks can be gapped.
• System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with ±100ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is
provided on REF_CLKO for the RMII/MII interface.
• Packet Interface Reference clock (REF_CLK) input that can be 25MHz or 50MHz. This clock is used as
the timing reference for the RMII/MII interface.
• The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are
input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and
will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal
division of REF_CLK. In RMII mode, only the REF_CLK input is used.
• REF_CLKO is an output clock that is generated by dividing the 100MHz System clock (SYSCLKI) by 2 or
4.
• A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67MHz.
The following table provides the different clocking options for the Ethernet interface.
Table 8-1. Clock Selection for the Ethernet (LAN) Interface
RMIIMIIS
PIN
0 (MII) 10 DTE 25
0 (MII) 10 DCE 25
0 (MII) 10 DCE 25
1 (RMII) 10 — 50
1 (RMII) 10 — 50
SPEED
(Mbps)
DCE/
DTE
REF_CLKO
OUTPUT
(MHz)
REF_CLK
INPUT
25MHz
±100ppm
25MHz
±100ppm
25MHz
±100ppm
50MHz
±100ppm
50MHz
±100ppm
RX_CLK TX_CLK
Input from
PHY
2.5MHz
(Output)
25MHz
(Output)
Not Applicable Not Applicable 1.67
Not Applicable Not Applicable 1.67
Input from
PHY
2.5MHz
(Output)
25MHz
(Output)
MDC
OUTPUT
(MHz)
1.67
1.67
1.67
24 of 167
Figure 8-1. Clocking for the DS33Z41
Microport
DS33Z41 Quad IMUX Ethernet Mapper
50 or 25 Mhz Oscillator
Buffer
Div by 1,2,4,8,10
Output clocks:
50,25 Mhz,2.5 Mhz
REF_CLK
TSER
TCLKI1
RCLKI1
RSER
Line 1
IMUX
HDLC
Serial
Interface
JTAG
+
X.86
CIR
SDRAM
Arbiter
SDRAM
Interface
SDCLKO
MAC
RMII
MII
Buffer Dev
Div by 2,4,12
Output Clocks
25,50
Mhz
REF_CLKO
50 or 25 Mhz
TX_CLK1
RXD
RX_CLK1
TXD
MDC
100 Mhz Oscillator
SYSCLKI
25 of 167
DS33Z41 Quad IMUX Ethernet Mapper
8.2.1 Serial Interface Clock Modes
The Serial Interface timing is determined by the line clocks. 8.192MHz is the required clock rate for interfacing the
IBO bus to Dallas Semiconductor Framers and Single-Chip Transceivers. Both the transmit and receive clocks
(TCLKI and RCLKI) are inputs.
8.2.2 Ethernet Interface Clock Modes
The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation.
Table 8-1 outlines the possible clocking modes for the Ethernet Interface. The buffered REF_CLKO output is
generated by division of the 100MHz system clock input by the user on SYSCLKI. The frequency of the
REF_CLKO pin is automatically determined by the DS33Z41 based on the state of the RMIIMIIS pin. The
REF_CLKO function can be turned off with the GL.CR1
the REF_CLKO signal should not be used to provide an input to REF_CLK, due to the reset requirements in these
operating modes.
In RMII mode, receive and transmit timing is always synchronous to a 50MHz clock input on the REF_CLK pin.
The source of REF_CLK is expected to be the external PHY. More information on RMII mode can be found in
Section 8.14.2
While using MII mode with DTE operation, the MII clocks (RX_CLK and TX_CLK) are inputs that are expected to
be provided by the external PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and
RX_CLK) are output by the DS33Z41, and are derived from the 25MHz REF_CLK input. More information on MII
mode can be found in Section 8.14.1
.
.
.RFOO bit. Note that in DCE and RMII operating modes,
26 of 167
DS33Z41 Quad IMUX Ethernet Mapper
8.3 Resets and Low-Power Modes
The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset
signal resets the status and control registers on the chip (except the GL.CR1. RST bit) to their default values and
resets all the other flops to their reset values. The device should be reset after all power supplies, SYSCLKI,
RX_CLK, and TX_CLK are stable. The processor bus output signals are also placed in high-impedance mode
when the RST pin is active (low). The global reset bit (GL.CR1
reset to zero when the external RST pin is active or when a zero is written to it. Allow 5ms after initiating a reset
condition for the reset operation to complete.
. RST) stays set after a one is written to it, but is
The Serial Interface reset bit in LI.RSTPD
default values, except for the LI.RSTPD.RST bit. The Serial Interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The Serial Interface reset bit (LI.RSTPD.RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
resets all the status and control registers on the Serial Interface to their
Table 8-2. Reset Functions
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset
Hardware JTAG Reset
Global Software Reset GL.CR1 Writing to this bit resets the device.
Serial interface Reset LI.RSTPD
Queue Pointer Reset GL.C1QPR
There are several features in the DS33Z41 to reduce power consumption. The reset bit in the LI.RSTPD register
minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization
and configuration. For the lowest possible standby current, clocks may be externally gated.
RST Pin
JTRST Pin
Transition to a logic 0 level resets the
device.
Resets the JTAG test port.
Writing to this bit resets a Serial
Interface.
Writing to this bit resets the Queue
Pointers.
.RST bit may be held in reset
27 of 167
8.4 Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
DS33Z41 Quad IMUX Ethernet Mapper
STEP 1: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.3
Clear all reset bits. Allow 5 milliseconds for the reset recovery.
STEP 2: Check the Device ID in the GL.IDRL
STEP 3: Configure the system clocks. Allow the clock system to properly adjust.
STEP 4: Initialize the entire remainder of the register space with 00h (or otherwise if specifically noted in the
register’s definition), including the reserved bits and reserved register locations.
STEP 5: Write FFFFFFFFh to the MAC indirect addresses 010Ch through 010Fh.
STEP 6: Setup connection in the GL.CON1 register.
STEP 7: Configure the Serial Port register space as needed.
STEP 8: Configure the Ethernet Port register space as needed.
STEP 9: Configure the Ethernet MAC indirect registers as needed.
STEP 10: Configure the external Ethernet PHYs through the MDIO interface.
STEP 11: Clear all counters and latched status bits.
STEP 12: Set Queue sizes in the Arbiter and reset the queue pointers for the Ethernet and Serial interfaces.
STEP 13: Enable Interrupts as needed.
STEP 14: Initiate link aggregation as discussed in Section 8.9
STEP 15: Begin handling interrupts and latched status events.
and GL.IDRH registers.
.
.
8.5 Global Resources
In order to maintain software compatibility with the multiport devices in the product family, a set of Global registers
are located at 0F0h-0FFh. The global registers include Global resets, global interrupt status, interrupt masking,
clock configuration, and the Device ID registers. See the Global Register Definitions in Table 9-2
.
8.6 Per-Port Resources
Multi-port devices in this product family share a common set of global registers, BERT, and Arbiter. All other
resources are per-port.
28 of 167
DS33Z41 Quad IMUX Ethernet Mapper
8.7 Device Interrupts
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global
Latched Status registers GL.LIS
to initially determine the source of the interrupt. The host can then read the LI.TQCTLS
LI.RX86S, SU.QCRLS, and BSRL registers to further identify the source of the interrupt(s). In order to maintain
software compatibility with the multiport devices in the product family, the global interrupt status and interrupt
enable registers have been preserved, but do not need to be used. If GL.TRQIS
source, the host will then read the LI.TPPSRL and LI.RPPSRL registers for the cause of the interrupt. If GL.LIS is
determined to be the interrupt source, the host will then read the LI.TQCTLS
LI.RX86S registers for the source of the interrupt. If GL.SIS is the source, the host will then read the SU.QCRLS
register for the source of the interrupt. If GL.IBIS is the source, the host will then read the BSRL register for the
source of the interrupt. All Global Interrupt Status Register bits are real-time bits that will clear once the
appropriate interrupt has been serviced and cleared, as long as no additional, enabled interrupt conditions are
present in the associated status register. All Latched Status bits must be cleared by the host writing a “1” to the bit
location of the interrupt condition that has been serviced. In order for individual status conditions to transmit their
status to the next level of interrupt logic, they must be enabled by placing a “1” in the associated bit location of the
correct Interrupt Enable Register. The Interrupt enable registers are LI.TPPSRIE
BSRIE, SU.QRIE, GL.LIE, GL.SIE, GL.IBIE, GL.TRQIE, GL.IMXSIE, GL.IMXDFEIE, and GL.IMXOOFIE. Latched
Status bits that have been enabled via Interrupt Enable registers are allowed to pass their interrupt conditions to
the Global Interrupt Status Registers. The Interrupt enable registers allow individual Latched Status conditions to
generate an interrupt, but when set to zero, they do not prevent the Latched Status bits from being set. Therefore,
when servicing interrupts, the user should AND the Latched Status with the associated Interrupt Enable Register
in order to exclude bits for which the user wished to prevent interrupt service. This architecture allows the
application host to periodically poll the latched status bits for non-interrupt conditions, while using only one set of
registers. Note the bit-orders of SU.QRIE and SU.QCRLS are different.
, GL.SIS, GL.IBIS, GL.TRQIS, GL.IMXSLS, GL.IMXDFDELS, and GL.IMXOOFLS
, LI.TPPSRL, LI.RPPSRL,
is determined to be the interrupt
, LI.TPPSRL, LI.RPPSRL, and
, LI.RPPSRIE, LI.RX86LSIE,
Note that the inactive state of the interrupt output pin is configurable. The INTM bit in GL.CR1
state of the interrupt pin, allowing selection of a pull-up resistor or active driver.
The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The
latched status bits for the interrupting entity must be read to clear the interrupt. Also reading the latched status bit
will reset all bits in that register. During a reset condition, interrupts cannot be generated. The interrupts from any
source can be blocked at a global level by the placing a zero in the global interrupt enable registers (GL.LIE
GL.SIE, GL.IBIE, GL.TRQIE, GL.IMXSIE, GL.IMXDFEIE, and GL.IMXOOFIE). Reading the Latched Status bit for
all interrupt generating events will clear the interrupt status bit and Interrupt signal will be deasserted.
controls the inactive
,
29 of 167
Figure 8-2. Device Interrupt Information Flow Diagram
Receive FCS Errored Packet
Receive Aborted Packet
Receive Invalid Packet Detected
Receive Small Packet Detected
Receive Large Packet Detected
Receive FCS Errored Packet Count
Receive Aborted Packet Count
Receive Size Violation Packet Count
<Reserved>
<Reserved>
<Reserved>
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Transmit Errored Packet Insertion Finished
<Reserved>
<Reserved>
<Reserved>
<Reserved>
SAPI High is not equal to LI.TRX86SAPIH
SAPI Low is not equal to LI.TRX86SAPIL
Control is not equal to LI.TRX8C
Address is not equal to LI.TRX86A
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Transmit Queue FIFO Overflowed
Transmit Queue Overflow
Transmit Queue for Connection Exceeded Low Threshold
Transmit Queue for Connection Exceeded High
Threshold
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Receive Queue FIFO Overflowed
Receive Queue Overflow
Receive Queue for Connection Exceeded Low Threshold
Receive Queue for Connection Exceeded High Threshold
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Performance Monitor Update
Bit Error Detected
Bit Error Count
Out Of Synchronization
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
LI.RPPSL
LI.RPPSRIE
LI.TPPSRL
LI.TPPSRIE
LI.RX86S
LI.RX86LSIE
LI.TQTIE
LI.TQCTLS
SU.QRIE
SU.QCRLS
BSRL
BSRIE
DS33Z41 Quad IMUX Ethernet Mapper
Drawing Legend:
Interrupt Status
Registers
Interrupt Enable
Registers
Register Name
Register Name
6
5
4
3
2
GL.TRQIS
1
0
6
5
4
3
GL.LIS
2
1
0
...
GL.SIS
...
GL.TRQIE
GL.LIE
GL.SIE
Interrupt Pin
GL.IBIS
GL.IBIE
GL.IMXSIE
GL.IMXSLS
GL.IMXDFEIE
GL.IMXDFDELS
GL.IMXOOFIE
GL.IMXOOFLS
30 of 167
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