Maxim Integrated DS33R11 User Manual
r
www.maxim-ic.com
Ethernet Mapper with Integrated
GENERAL DESCRIPTION
The DS33R11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a T1/E1/J1 data
stream.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) Controller
provides fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33R11 can
operate with an inexpensive external processor.
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1
FUNCTIONAL DIAGRAM
SERIAL STREAM
T1/E1/J1
TRANSCEIVER
T1/E1
LINE
DS33R11
T1/E1/J1 Transceive
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Integrated T1/E1/J1 Framer and LIU
HDLC/LAPS Encapsulation with
Programmable FCS and Interframe Fill
Committed Information Rate Controller
Provides Fractional Allocations in 512kbps
Increments
Programmable BERT for Serial (TDM)
Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V, 3.3V Supplies
Reference Design Routes on Two Signal
Layers
IEEE 1149.1 JTAG Support
Features continued on page 11.
BERT
HDLC/X.86
MAPPER
10/100
MAC
MII/RMII
μC
SDRAM
10/100
ETHERNET
PHY
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS33R11 -40°C to +85°C 256 BGA
DS33R11
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
1 of 344
REV: 030807
.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
TABLE OF CONTENTS
1 DESCRIPTION ................................................................................................................................... 9
2 FEATURE HIGHLIGHTS.................................................................................................................. 11
2.1 GENERAL...................................................................................................................................... 11
2.2 MICROPROCESSOR INTERFACE...................................................................................................... 11
2.3 HDLC ETHERNET MAPPING .......................................................................................................... 11
2.4 X.86 (LINK ACCESS PROTOCOL FOR SONET/SDH) ETHERNET MAPPING....................................... 11
2.5 ADDITIONAL HDLC CONTROLLERS IN THE INTEGRATED T1/E1/J1 TRANSCEIVER ............................ 12
2.6 COMMITTED INFORMATION RATE (CIR) CONTROLLER .................................................................... 12
2.7 SDRAM INTERFACE...................................................................................................................... 12
2.8 MAC INTERFACE........................................................................................................................... 12
2.9 T1/E1/J1 LINE INTERFACE ............................................................................................................ 13
2.10 CLOCK SYNTHESIZER .................................................................................................................... 13
2.11 JITTER ATTENUATOR..................................................................................................................... 13
2.12 T1/E1/J1 FRAMER ........................................................................................................................14
2.13 TDM BUS ..................................................................................................................................... 14
2.14 TEST AND DIAGNOSTICS ................................................................................................................ 15
2.15 SPECIFICATIONS COMPLIANCE....................................................................................................... 16
3 APPLICATIONS ............................................................................................................................... 17
4 ACRONYMS AND GLOSSARY ....................................................................................................... 18
5 MAJOR OPERATING MODES ........................................................................................................ 19
6 BLOCK DIAGRAMS......................................................................................................................... 20
7 PIN DESCRIPTIONS........................................................................................................................ 25
7.1 PIN FUNCTIONAL DESCRIPTION...................................................................................................... 25
8 FUNCTIONAL DESCRIPTION ......................................................................................................... 41
8.1 PROCESSOR INTERFACE ............................................................................................................... 42
8.1.1 Read-Write/Data Strobe Modes............................................................................................................42
8.1.2 Clear on Read.......................................................................................................................................42
8.1.3 Interrupt and Pin Modes........................................................................................................................42
9 ETHERNET MAPPER ...................................................................................................................... 43
9.1 ETHERNET MAPPER CLOCKS......................................................................................................... 43
9.1.1 Ethernet Interface Clock Modes............................................................................................................45
9.1.2 Serial Interface Clock Modes................................................................................................................45
9.2 RESETS AND LOW POWER MODES................................................................................................. 46
9.3 INITIALIZATION AND CONFIGURATION.............................................................................................. 47
9.4 GLOBAL RESOURCES .................................................................................................................... 47
9.5 PER-PORT RESOURCES ................................................................................................................ 47
9.6 DEVICE INTERRUPTS ..................................................................................................................... 48
9.7 INTERRUPT INFORMATION REGISTERS ........................................................................................... 50
9.8 STATUS REGISTERS ...................................................................................................................... 50
9.9 INFORMATION REGISTERS ............................................................................................................. 50
9.10 SERIAL INTERFACE ........................................................................................................................ 50
9.11 CONNECTIONS AND QUEUES ......................................................................................................... 51
9.12 ARBITER .......................................................................................................................................52
9.13 FLOW CONTROL............................................................................................................................ 53
9.13.1 Full Duplex Flow Control.......................................................................................................................54
9.13.2 Half Duplex Flow Control......................................................................................................................55
9.13.3 Host-Managed Flow Control.................................................................................................................55
9.14 ETHERNET INTERFACE PORT......................................................................................................... 56
2 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.14.1 DTE and DCE Mode .............................................................................................................................58
9.15 ETHERNET MAC ........................................................................................................................... 59
9.15.1 MII Mode Options..................................................................................................................................61
9.15.2 RMII Mode.............................................................................................................................................61
9.15.3 PHY MII Management Block and MDIO Interface................................................................................62
9.16 BERT IN THE ETHERNET MAPPER ................................................................................................. 62
9.16.1 Receive Data Interface .........................................................................................................................63
9.16.2 Repetitive Pattern Synchronization.......................................................................................................64
9.16.3 Pattern Monitoring.................................................................................................................................64
9.16.4 Pattern Generation................................................................................................................................64
9.17 TRANSMIT PACKET PROCESSOR .................................................................................................... 65
9.18 RECEIVE PACKET PROCESSOR ...................................................................................................... 66
9.19 X.86 ENCODING AND DECODING.................................................................................................... 68
9.20 COMMITTED INFORMATION RATE CONTROLLER .............................................................................. 71
10 INTEGRATED T1/E1/J1 TRANSCEIVER ........................................................................................ 72
10.1 T1/E1/J1 CLOCKS ........................................................................................................................ 72
10.2 PER-CHANNEL OPERATION............................................................................................................ 73
10.3 T1/E1/J1 TRANSCEIVER INTERRUPTS ............................................................................................ 73
10.4 T1 FRAMER/FORMATTER CONTROL AND STATUS ........................................................................... 74
10.4.1 T1 Transmit Transparency....................................................................................................................74
10.4.2 AIS-CI and RAI-CI Generation and Detection ......................................................................................74
10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation..............................................................................75
10.5 E1 FRAMER/FORMATTER CONTROL AND STATUS........................................................................... 76
10.5.1 Automatic Alarm Generation.................................................................................................................77
10.6 PER-CHANNEL LOOPBACK ............................................................................................................. 77
10.7 ERROR COUNTERS........................................................................................................................ 78
10.7.1 Line-Code Violation Counter (TR.LCVCR)...........................................................................................78
10.7.2 Path Code Violation Count Register (TR.PCVCR)...............................................................................79
10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) ..............................................................................80
10.7.4 E-Bit Counter (TR.EBCR).....................................................................................................................80
10.8 DS0 MONITORING FUNCTION ........................................................................................................ 81
10.9 SIGNALING OPERATION ................................................................................................................. 82
10.9.1 Processor-Based Receive Signaling ....................................................................................................82
10.9.2 Hardware-Based Receive Signaling.....................................................................................................83
10.9.3 Processor-Based Transmit Signaling ...................................................................................................84
10.9.4 Hardware-Based Transmit Signaling....................................................................................................85
10.10 PER-CHANNEL IDLE CODE GENERATION ........................................................................................86
10.10.1 Idle-Code Programming Examples.......................................................................................................87
10.11 CHANNEL BLOCKING REGISTERS ...................................................................................................88
10.12 ELASTIC STORES OPERATION........................................................................................................ 88
10.12.1 Receive Elastic Store............................................................................................................................88
10.12.2 Transmit Elastic Store...........................................................................................................................89
10.12.3 Elastic Stores Initialization....................................................................................................................89
10.12.4 Minimum Delay Mode...........................................................................................................................89
10.13 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)............................................................ 90
10.14 T1 BIT-ORIENTED CODE (BOC) CONTROLLER ............................................................................... 91
10.14.1 Transmit BOC.......................................................................................................................................91
10.15 RECEIVE BOC .............................................................................................................................. 91
10.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)........................................... 92
10.16.1 Method 1: Internal Register Scheme Based on Double-Frame............................................................92
10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe.......................................................92
10.17 ADDITIONAL HDLC CONTROLLERS IN T1/E1/J1 TRANSCEIVER ....................................................... 93
10.17.1 HDLC Configuration..............................................................................................................................93
10.17.2 FIFO Control.........................................................................................................................................95
10.17.3 HDLC Mapping......................................................................................................................................95
3 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
10.17.4 FIFO Information...................................................................................................................................96
10.17.5 Receive Packet-Bytes Available...........................................................................................................96
10.18 LEGACY FDL SUPPORT (T1 MODE) ............................................................................................... 97
10.18.1 Overview...............................................................................................................................................97
10.18.2 Receive Section....................................................................................................................................97
10.18.3 Transmit Section...................................................................................................................................98
10.19 D4/SLC-96 OPERATION................................................................................................................ 98
10.20 PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ............................................ 99
10.21 LINE INTERFACE UNIT (LIU)......................................................................................................... 100
10.21.1 LIU Operation......................................................................................................................................100
10.21.2 Receiver..............................................................................................................................................100
10.21.3 Transmitter..........................................................................................................................................102
10.22 MCLK PRESCALER ..................................................................................................................... 103
10.23 JITTER ATTENUATOR................................................................................................................... 103
10.24 CMI (CODE MARK INVERSION) OPTION........................................................................................ 103
10.25 RECOMMENDED CIRCUITS ........................................................................................................... 104
10.26 T1/E1/J1 TRANSCEIVER BERT FUNCTION ...........................................................................108
10.26.1 BERT Status .......................................................................................................................................108
10.26.2 BERT Mapping....................................................................................................................................108
10.26.3 BERT Repetitive Pattern Set..............................................................................................................110
10.26.4 BERT Bit Counter................................................................................................................................110
10.26.5 BERT Error Counter............................................................................................................................110
10.26.6 BERT Alternating Word-Count Rate...................................................................................................110
10.27 PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) ...........................................................111
10.27.1 Number-of-Errors Registers................................................................................................................111
10.28 PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER..................................................................... 112
10.29 FRACTIONAL T1/E1 SUPPORT ..................................................................................................... 112
10.30 T1/E1/J1 TRANSMIT FLOW DIAGRAMS ......................................................................................... 113
11 DEVICE REGISTERS..................................................................................................................... 117
11.1 REGISTER BIT MAPS ................................................................................................................... 118
11.1.1 Global Ethernet Mapper Register Bit Map..........................................................................................118
11.1.2 Arbiter Register Bit Map......................................................................................................................119
11.1.3 BERT Register Bit Map.......................................................................................................................119
11.1.4 Serial Interface Register Bit Map........................................................................................................120
11.1.5 Ethernet Interface Register Bit Map....................................................................................................122
11.1.6 MAC Register Bit Map ........................................................................................................................123
11.2 GLOBAL REGISTER DEFINITIONS FOR ETHERNET MAPPER............................................................ 134
11.3 ARBITER REGISTERS ................................................................................................................... 143
11.3.1 Arbiter Register Bit Descriptions.........................................................................................................143
11.4 BERT REGISTERS ...................................................................................................................... 144
11.5 SERIAL INTERFACE REGISTERS.................................................................................................... 151
11.5.1 Serial Interface Transmit and Common Registers..............................................................................151
11.5.2 Serial Interface Transmit Register Bit Descriptions............................................................................151
11.5.3 Transmit HDLC Processor Registers..................................................................................................152
11.5.4 X.86 Registers.....................................................................................................................................159
11.5.5 Receive Serial Interface......................................................................................................................161
11.6 ETHERNET INTERFACE REGISTERS .............................................................................................. 174
11.6.1 Ethernet Interface Register Bit Descriptions.......................................................................................174
11.6.2 MAC Registers....................................................................................................................................186
11.7 T1/E1/J1 TRANSCEIVER REGISTERS ........................................................................................... 201
11.7.1 Number-of-Errors Left Register...........................................................................................................299
12 FUNCTIONAL TIMING................................................................................................................... 300
12.1 FUNCTIONAL SERIAL I/O TIMING .................................................................................................. 300
12.2 MII AND RMII INTERFACES .......................................................................................................... 301
12.3 TRANSCEIVER T1 MODE FUNCTIONAL TIMING .............................................................................. 303
4 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
12.4 E1 MODE.................................................................................................................................... 308
13 OPERATING PARAMETERS ........................................................................................................ 313
13.1 THERMAL CHARACTERISTICS ....................................................................................................... 314
13.2 MII INTERFACE............................................................................................................................ 315
13.3 RMII INTERFACE ......................................................................................................................... 317
13.4 MDIO INTERFACE ....................................................................................................................... 319
13.5 TRANSMIT WAN INTERFACE ........................................................................................................ 320
13.6 RECEIVE WAN INTERFACE .......................................................................................................... 321
13.7 SDRAM TIMING.......................................................................................................................... 322
13.8 MICROPROCESSOR BUS AC CHARACTERISTICS ........................................................................... 324
13.9 AC CHARACTERISTICS: RECEIVE-SIDE ........................................................................................ 327
13.10 AC CHARACTERISTICS: BACKPLANE CLOCK TIMING ..................................................................... 331
13.11 AC CHARACTERISTICS: TRANSMIT SIDE....................................................................................... 332
13.12 JTAG INTERFACE TIMING ............................................................................................................ 335
14 JTAG INFORMATION.................................................................................................................... 336
14.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION............................................................. 337
14.2 INSTRUCTION REGISTER.............................................................................................................. 339
14.3 JTAG ID CODES......................................................................................................................... 341
14.4 TEST REGISTERS ........................................................................................................................ 341
14.4.1 Boundary Scan Register.....................................................................................................................341
14.4.2 Bypass Register..................................................................................................................................341
14.4.3 Identification Register .........................................................................................................................341
14.5 JTAG FUNCTIONAL TIMING ......................................................................................................... 342
15 PACKAGE INFORMATION............................................................................................................ 343
15.1 PACKAGE OUTLINE DRAWING OF 256-BGA (VIEW FROM BOTTOM OF DEVICE).............................. 343
16 DOCUMENT REVISION HISTORY ................................................................................................ 344
5 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17
Figure 6-1. Main Block Diagram ................................................................................................................................20
Figure 6-2. Block Diagram of T1/E1/J1 Transceiver ................................................................................................. 21
Figure 6-3. Receive and Transmit T1/E1/J1 LIU ....................................................................................................... 22
Figure 6-4. Receive and Transmit T1/E1/J1 Framer ................................................................................................. 23
Figure 6-5. T1/E1/J1 Backplane Interface ................................................................................................................. 24
Figure 7-1. 256-Ball BGA Pinout ............................................................................................................................... 40
Figure 9-1. Clocking for the DS33R11....................................................................................................................... 44
Figure 9-2. Device Interrupt Information Flow Diagram ............................................................................................ 49
Figure 9-3. Flow Control Using Pause Control Frame .............................................................................................. 55
Figure 9-4. IEEE 802.3 Ethernet Frame .................................................................................................................... 56
Figure 9-5. Configured as DTE Connected to an Ethernet PHY in MII Mode ........................................................... 58
Figure 9-6. DS33R11 Configured as a DCE in MII Mode.......................................................................................... 59
Figure 9-7. RMII Interface.......................................................................................................................................... 61
Figure 9-8. MII Management Frame.......................................................................................................................... 62
Figure 9-9. PRBS Synchronization State Diagram.................................................................................................... 63
Figure 9-10. Repetitive Pattern Synchronization State Diagram............................................................................... 64
Figure 9-11. HDLC Encapsulation of MAC Frame .................................................................................................... 67
Figure 9-12. LAPS Encoding of MAC Frames Concept ............................................................................................ 68
Figure 9-13. X.86 Encapsulation of the MAC frame.................................................................................................. 69
Figure 10-1. T1/E1/J1 Clock Map.............................................................................................................................. 72
Figure 10-2. Simplified Diagram of Receive Signaling Path...................................................................................... 82
Figure 10-3. Simplified Diagram of Transmit Signaling Path..................................................................................... 84
Figure 10-4. CRC-4 Recalculate Method .................................................................................................................. 90
Figure 10-5. Typical Monitor Application ................................................................................................................. 101
Figure 10-6. CMI Coding ......................................................................................................................................... 103
Figure 10-7. Basic Interface..................................................................................................................................... 104
Figure 10-8. E1 Transmit Pulse Template............................................................................................................... 105
Figure 10-9. T1 Transmit Pulse Template ............................................................................................................... 105
Figure 10-10. Jitter Tolerance ................................................................................................................................. 106
Figure 10-11. Jitter Tolerance (E1 Mode)................................................................................................................ 106
Figure 10-12. Jitter Attenuation (T1 Mode).............................................................................................................. 107
Figure 10-13. Jitter Attenuation (E1 Mode) ............................................................................................................. 107
Figure 10-14. Optional Crystal Connections ........................................................................................................... 108
Figure 10-15. Simplified Diagram of BERT in Network Direction............................................................................ 109
Figure 10-16. Simplified Diagram of BERT in Backplane Direction ........................................................................ 109
Figure 10-17. T1/J1 Transmit Flow Diagram........................................................................................................... 113
Figure 10-18. E1 Transmit Flow Diagram................................................................................................................ 115
Figure 12-1. Tx Serial Interface Functional Timing ................................................................................................. 300
Figure 12-2. Rx Serial Interface Functional Timing ................................................................................................. 300
Figure 12-3. Transmit Byte Sync Functional Timing ............................................................................................... 301
Figure 12-4. Receive Byte Sync Functional Timing ................................................................................................ 301
Figure 12-5. MII Transmit Functional Timing........................................................................................................... 301
Figure 12-6. MII Transmit Half Duplex with a Collision Functional Timing.............................................................. 302
Figure 12-7. MII Receive Functional Timing............................................................................................................ 302
Figure 12-8. RMII Transmit Interface Functional Timing ......................................................................................... 302
Figure 12-9. RMII Receive Interface Functional Timing .......................................................................................... 303
Figure 12-10. Receive-Side D4 Timing ................................................................................................................... 303
Figure 12-11. Receive-Side ESF Timing ................................................................................................................. 303
Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled).................................................................. 304
Figure 12-13. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)................................................. 304
Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................. 305
Figure 12-15. Transmit-Side D4 Timing .................................................................................................................. 305
Figure 12-16. Transmit-Side ESF Timing ................................................................................................................ 306
Figure 12-17. Transmit-Side Boundary Timing (with Elastic Store Disabled) ......................................................... 306
Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)................................................ 307
6 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................ 307
Figure 12-20. Receive-Side Timing ......................................................................................................................... 308
Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled) .......................................................... 308
Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled)................................... 309
Figure 12-23. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (E-Store Enabled)................................... 309
Figure 12-24. G.802 Timing, E1 Mode Only............................................................................................................ 310
Figure 12-25. Transmit-Side Timing ........................................................................................................................ 310
Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled)................................................................. 311
Figure 12-27. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) ......................... 311
Figure 12-28. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) .......................... 312
Figure 13-1. Transmit MII Interface Timing ............................................................................................................. 315
Figure 13-2. Receive MII Interface Timing .............................................................................................................. 316
Figure 13-3. Transmit RMII Interface Timing........................................................................................................... 317
Figure 13-4. Receive RMII Interface Timing............................................................................................................ 318
Figure 13-5. MDIO Interface Timing ........................................................................................................................ 319
Figure 13-6. Transmit WAN Interface Timing.......................................................................................................... 320
Figure 13-7. Receive WAN Interface Timing........................................................................................................... 321
Figure 13-8. SDRAM Interface Timing .................................................................................................................... 323
Figure 13-9. Intel Bus Read Timing (MODEC = 00)................................................................................................ 325
Figure 13-10. Intel Bus Write Timing (MODEC = 00).............................................................................................. 325
Figure 13-11. Motorola Bus Read Timing (MODEC = 01) ...................................................................................... 326
Figure 13-12. Motorola Bus Write Timing (MODEC = 01)....................................................................................... 326
Figure 13-13. Receive-Side Timing ......................................................................................................................... 328
Figure 13-14. Receive-Side Timing, Elastic Store Enabled .................................................................................... 329
Figure 13-15. Receive Line Interface Timing .......................................................................................................... 330
Figure 13-16. Receive Timing Delay RCLKO to BPCLK......................................................................................... 331
Figure 13-17. Transmit-Side Timing ........................................................................................................................ 333
Figure 13-18. Transmit-Side Timing, Elastic Store Enabled ................................................................................... 334
Figure 13-19. Transmit Line Interface Timing ......................................................................................................... 334
Figure 13-20. JTAG Interface Timing Diagram ....................................................................................................... 335
Figure 14-1. JTAG Functional Block Diagram......................................................................................................... 336
Figure 14-2. TAP Controller State Diagram............................................................................................................. 339
Figure 14-3. JTAG Functional Timing...................................................................................................................... 342
7 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 25
Table 9-1. Clocking Options for the Ethernet Interface ............................................................................................. 43
Table 9-2. Reset Functions........................................................................................................................................ 46
Table 9-3. Registers Related to Connections and Queues....................................................................................... 52
Table 9-4. Options for Flow Control........................................................................................................................... 53
Table 9-5. Registers Related to Setting the Ethernet Port ........................................................................................ 57
Table 9-6. MAC Control Registers............................................................................................................................. 60
Table 9-7. MAC Status Registers .............................................................................................................................. 60
Table 10-1. T1/E1/J1 Transmit Clock Source ........................................................................................................... 73
Table 10-2. T1 Alarm Criteria .................................................................................................................................... 75
Table 10-3. E1 Sync/Resync Criteria ........................................................................................................................ 76
Table 10-4. E1 Alarm Criteria .................................................................................................................................... 77
Table 10-5 T1 Line Code Violation Counting Options ............................................................................................... 78
Table 10-6. E1 Line-Code Violation Counting Options.............................................................................................. 78
Table 10-7. T1 Path Code Violation Counting Arrangements ................................................................................... 79
Table 10-8. T1 Frames Out-of-Sync Counting Arrangements .................................................................................. 80
Table 10-9. Time Slot Numbering Schemes.............................................................................................................. 85
Table 10-10. Idle-Code Array Address Mapping ....................................................................................................... 86
Table 10-11. Elastic Store Delay After Initialization .................................................................................................. 89
Table 10-12. HDLC Controller Registers................................................................................................................... 94
Table 10-13. Transformer Specifications................................................................................................................. 104
Table 10-14. Transmit Error-Insertion Setup Sequence.......................................................................................... 111
Table 10-15. Error Insertion Examples.................................................................................................................... 111
Table 11-1. Register Address Map.......................................................................................................................... 117
Table 11-2. Global Ethernet Mapper Register Bit Map ........................................................................................... 118
Table 11-3. Arbiter Register Bit Map ....................................................................................................................... 119
Table 11-4. BERT Register Bit Map ........................................................................................................................ 119
Table 11-5. Serial Interface Register Bit Map.......................................................................................................... 120
Table 11-6. Ethernet Interface Register Bit Map ..................................................................................................... 122
Table 11-7. MAC Indirect Register Bit Map ............................................................................................................. 123
Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0) .......................................................... 125
Table 13-1. Recommended DC Operating Conditions............................................................................................ 313
Table 13-2. DC Electrical Characteristics................................................................................................................ 313
Table 13-3. Thermal Characteristics ....................................................................................................................... 314
Table 13-4. Theta-JA vs. Airflow ............................................................................................................................. 314
Table 13-5. Transmit MII Interface .......................................................................................................................... 315
Table 13-6. Receive MII Interface ........................................................................................................................... 316
Table 13-7. Transmit RMII Interface........................................................................................................................ 317
Table 13-8. Receive RMII Interface......................................................................................................................... 318
Table 13-9. MDIO Interface ..................................................................................................................................... 319
Table 13-10. Transmit WAN Interface ..................................................................................................................... 320
Table 13-11. Receive WAN Interface ...................................................................................................................... 321
Table 13-12. SDRAM Interface Timing.................................................................................................................... 322
Table 13-13. AC Characteristics—Microprocessor Bus Timing .............................................................................. 324
Table 13-14. AC Characteristics: Receive Side ...................................................................................................... 327
Table 13-15. AC Characteristics: Backplane Clock Synthesis................................................................................ 331
Table 13-16. AC Characteristics: Transmit Side ..................................................................................................... 332
Table 13-17. JTAG Interface Timing ....................................................................................................................... 335
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture .................................................................................. 340
Table 14-2. ID Code Structure................................................................................................................................. 341
8 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
1 DESCRIPTION
The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1
WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet
Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM interface, control ports,
Bit Error Rate Tester (BERT), and integrated T1/E1/J1 Transceiver. The packet interface consists of a MII/RMII
Ethernet PHY interface. The Ethernet interface can be configured for 10Mbit/s or 100Mbit/s service. The DS33R11
encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over a T1, E1, or J1 line. The
T1/E1/J1 interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet ports. Access is provided to the signals between the Serial port and the integrated T1/E1/J1 Transceiver.
The device includes a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul
applications. The transceiver is composed of an LIU, framer, and two additional HDLC controllers. The transceiver
is software compatible with the DS2155 and DS2156.
The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible
for generating the necessary waveshapes for driving the network and providing the correct source impedance
depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line
build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax
and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the
network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB
or 0 to 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications. The jitter attenuator removes
phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be
placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for
interfacing to optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up
and loop-down code generation and detection.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and receive data
through the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a
time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte FIFOs, thus reducing the amount of
processor overhead required to manage the flow of data. In addition, built-in support for reducing the processor
time is required in SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface).
An 8-bit parallel microcontroller port provides access for control and configuration of all the features of the device.
The internal 100MHz SDRAM controller interfaces to a 32-bit wide 128Mb SDRAM. The SDRAM is used to buffer
the data from the Ethernet and WAN ports for transport. The external SDRAM can accommodate up to 8192
frames with a maximum frame size of 2016 bytes. Diagnostic capabilities include SDRAM BIST, loopbacks, PRBS
pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. The DS33R11
operates with a 1.8V core supply and 3.3V I/O supply.
9 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
The integrated Ethernet Mapper is software compatible with the DS33Z11 Ethernet mapper. There are a few things
to note when porting a DS33Z11 application to this device:
• The SPI and hardware modes are not supported.
• RSER has been renamed to RSERI.
• RCLK has been renamed to RCLKI.
• TSER has been renamed to TSERO.
• TCLK has been renamed to TCLKE.
The integrated T1/E1/J1 transceiver is software compatible with the DS2155 T1/E1/J1 transceiver. There are a few
things to note when porting a DS2155 application to this device:
• The Facilities Data Link (FDL) support is available through software only. The TLINK, RLINK, TLCLK,
RLCLK pins are not available on the DS33R11.
• Multiplexed Microprocessor Bus mode is not supported on the DS33R11.
• The Extended System Information Bus (ESIB) is not supported on the DS33R11.
• The MODEC pins serve the function of the DS2155’s BTS pin.
• The interim LIU/Framer clock signals RCLKI, RCLKO have been renamed to RDCLKI, RDCLKO to avoid
confusion with the receive clock connections between the transceiver and the Ethernet mapper.
• The interim LIU/Framer clock signals TCLKI, TCLKO have been renamed to TDCLKI, TDCLKO to avoid
confusion with the receive clock connections between the transceiver and the Ethernet mapper.
• RSER has been renamed RSERO.
• RCLK has been renamed RCLKO.
• TSER has been renamed TSERI.
• TCLK has been renamed TCLKT.
10 of 344
2 FEATURE HIGHLIGHTS
2.1 General
• 256-pin, 27mm BGA package
• 1.8V and 3.3V supplies
• IEEE 1149.1 JTAG boundary scan
• Software access to device ID and silicon revision
• Development support includes evaluation kit, driver source code, and reference designs
• Reference design routes on a two-layer PC board
• Programmable output clocks for fractional T1, E1, H0, and H12 applications
2.2 Microprocessor Interface
• Parallel control port with 8-bit data bus
• Nonmultiplexed Intel and Motorola timing modes
• Internal software reset and external hardware reset-input pin
• Supports polled or interrupt-driven environments
• Software access to device ID and silicon revision
• Global interrupt-output pin
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.3 HDLC Ethernet Mapping
• Dedicated HDLC controller engine for protocol encapsulation
• Compatible with polled or interrupt driven environments
• Programmable FCS insertion and extraction
• Programmable FCS type
• Supports FCS error insertion
• Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)
• Supports bit stuffing/destuffing
• Selectable packet scrambling/descrambling (X
• Separate FCS errored packet and aborted packet counts
• Programmable inter-frame fill for transmit HDLC
43
+1)
2.4 X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping
• Programmable X.86 address/control fields for transmit and receive
• Programmable 2-byte protocol (SAPI) field for transmit and receive
• 32 bit FCS
• Transmit transparency processing—7E is replaced by 7D, 5E
• Transmit transparency processing—7D replaced by 7D, 5D
• Receive rate adaptation (7D, DD) is deleted.
• Receive transparency processing—7D, 5E is replaced by 7E
• Receive transparency processing—7D, 5D is replaced by 7D
• Receive abort sequence the LAPS packet is dropped if 7D7E is detect
• Self-synchronizing X
• Frame indication due to bad address/control/SAPI, FCS error, abort sequence or frame size longer
than preset max
43
+1 payload scrambling.
11 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver
• Two additional independent HDLC controllers
• Fast load and unload features for FIFOs
• SS7 support for FISU transmit and receive
• Independent 128-byte Rx and Tx buffers with interrupt support
• Access FDL, Sa, or single/multiple DS0 channels
• DS0 access includes Nx64 or Nx56
• Compatible with polled or interrupt driven environments
• Bit-oriented code (BOC) support
2.6 Committed Information Rate (CIR) Controller
• CIR Rate controller limits transmission of data from the Ethernet interface to the serial interface
• CIR granularity at 512kbit/s
• CIR averaging for smoothing traffic peaks
2.7 SDRAM Interface
• Interface for 128Mb, 32-bit-wide SDRAM
• SDRAM Interface speed up to 100MHz
• Auto refresh timing
• Automatic precharge
• Master clock provided to the SDRAM
• No external components required for SDRAM connectivity
2.8 MAC Interface
• MAC port with standard MII (less TX_ER) or RMII
• 10Mbps and 100Mbps Data rates
• Configurable DTE or DCE modes
• Facilitates auto-negotiation by host microprocessor
• Programmable half and full-duplex modes
• Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
• Programmable Maximum MAC frame size up to 2016 bytes
• Minimum MAC frame size: 64 bytes
• Discards frames greater than programmed maximum MAC frame size and runt, nonoctet bounded, or
bad-FCS frames upon reception
• Configurable for promiscuous broadcast-discard mode.
• Programmable threshold for SDRAM queues to initiate flow control and status indication
• MAC loopback support for transmit data looped to receive data at the MII/RMII interface
12 of 344
2.9 T1/E1/J1 Line Interface
• Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz
for T1 operation
• Fully software configurable
• Short-haul and long-haul applications
• Automatic receive sensitivity adjustments
• Ranges include 0 to 43dB or 0 to 12dB for E1 applications and 0 to 13dB or 0 to 36dB for T1
applications
• Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
• Internal receive termination option for 75Ω, 100Ω, and 120Ω lines
• Internal transmit termination option for 75Ω, 100Ω, and 120Ω lines
• Monitor application gain settings of 20dB, 26dB, and 32dB
• G.703 receive synchronization-signal mode
• Flexible transmit waveform generation
• T1 DSX-1 line build-outs
• T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB
• E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
• AIS generation independent of loopbacks
• Alternating ones and zeros generation
• Square-wave output
• Open-drain output option
• NRZ format option
• Transmitter power-down
• Transmitter 50mA short-circuit limiter with current-limit-exceeded indication
• Transmit open-circuit-detected indication
• Line interface function can be completely decoupled from the framer/formatter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.10 Clock Synthesizer
• Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
• Derived from recovered receive clock
2.11 Jitter Attenuator
• 32-bit or 128-bit crystal-less jitter attenuator
• Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz
for T1 operation
• Can be placed in either the receive or transmit path or disabled
• Limit trip indication
13 of 344
2.12 T1/E1/J1 Framer
• Fully independent transmit and receive functionality
• Full receive and transmit path transparency
• T1 framing formats include D4 (SLC-96) and ESF
• Detailed alarm and status reporting with optional interrupt support
• Large path and line error counters for:
o T1: BPV, CV, CRC6, and framing bit errors
o E1: BPV, CV, CRC4, E-bit, and frame alignment errors
• Timed or manual update modes
• DS1 idle code generation on a per-channel basis in both transmit and receive paths
o User-defined
o Digital milliwatt
• ANSI T1.403-1998 Support
• RAI-CI detection and generation
• AIS-CI detection and generation
• E1 ETS 300 011 RAI generation
• G.965 V5.2 link detect
• Ability to monitor one DS0 channel in both the transmit and receive paths
• In-band repeating pattern generators and detectors
o Three independent generators and detectors
o Patterns from 1 to 8 bits or 16 bits in length
• RCL, RLOS, RRA, and RAIS alarms interrupt on change-of-state
• Flexible signaling support
o Software or hardware based
o Interrupt generated on change of signaling data
o Receive signaling freeze on loss-of-sync, carrier loss, or frame slip
• Addition of hardware pins to indicate carrier loss and signaling freeze
• Automatic RAI generation to ETS 300 011 specifications
• Access to Sa and Si bits
• Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
• Japanese J1 support
o
Ability to calculate and check CRC6 according to the Japanese standard
o
Ability to generate Yellow Alarm according to the Japanese standard
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.13 TDM Bus
• Dual two-frame independent receive and transmit elastic stores
o Independent control and clocking
o Controlled slip capability with status
o Minimum delay mode supported
• Programmable output clocks for fractional T1, E1, H0, and H12 applications
• Hardware signaling capability
o Receive signaling reinsertion to a backplane multiframe sync
o Availability of signaling in a separate PCM data stream
o Signaling freezing
• Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
• Access to the data streams in between the framer/formatter and the elastic stores
• User-selectable synthesized clock output
14 of 344
2.14 Test and Diagnostics
• IEEE 1149.1 support
• Programmable on-chip bit error-rate tester (BERT)
• Pseudorandom patterns including QRSS
• User-defined repetitive patterns
• Daly pattern
• Error insertion single and continuous
• Total bit and errored bit counts
• Payload error insertion
• Error insertion in the payload portion of the T1 frame in the transmit path
• Errors can be inserted over the entire frame or selected channels
• Insertion options include continuous and absolute number with selectable insertion rates
• F-bit corruption for line testing
• Loopbacks: remote, local, analog, and per-channel loopback
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
15 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.15 Specifications Compliance
The DS33R11 meets relevant telecommunications specifications. The following table provides the specifications
and relevant sections that are applicable to the DS33R11.
Table 2-1. T1-Related Telecommunications Specifications
IEEE 802.3-2002—CSMA/CD access method and physical layer specifications.
RFC1662—PPP in HDLC-like Framing
RFC2615—PPP over SONET/SDH
X.86—Ethernet over LAPS
RMII—Industry Implementation Agreement for “Reduced MII Interface,” Sept 1997
ANSI: T1.403-1995, T1.231–1993, T1.408
AT&T: TR54016, TR62411
ITU-T: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161,
Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer Specification
ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4
Japanese: JTG.703, JTI.431, JJ-20.11 (CMI Coding Only)
16 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
3 APPLICATIONS
The DS33R11 is ideal for application areas such as transparent LAN service, LAN extension, and Ethernet delivery
over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4.
For an example of a complete LAN-to-WAN design, refer to Application Note 3411: DS33Z11—Ethernet LAN to
Unframed T1/E1 WAN Bridge, available on our website at
Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing)
www.maxim-ic.com/telecom.
T1/E1/J1
Stream
Inter-Building
LAN Extension
SDRAM
RMII, MII
10 Base T
100 Base T
EthernetDS33R11
Clock
Sources
17 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
4 ACRONYMS AND GLOSSARY
• BERT: Bit Error-Rate Tester
• DCE: Data Communication Interface
• DTE: Data Terminating Interface
• FCS: Frame Check Sequence
• HDLC: High-Level Data Link Control
• MAC: Media Access Control
• MII: Media Independent Interface
• RMII: Reduced Media Independent Interface
• WAN: Wide Area Network
Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interface function.
The register names have been allowed to remain with a “SU.” prefix to avoid register renaming.
Note 2: Previous versions of this document used the term “Line” to refer to the Serial Interface. The register names
have been allowed to remain with a “LI.” prefix to avoid register renaming.
Note 3: The terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet Interface. The Receive
Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and stored in the
SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and stored in the
SDRAM to be sent to the MAC transmitter.
Note 4: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125μs frame
there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1.
Each channel is made up of eight bits that are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first.
Bit number 8 is the LSB and is transmitted last. The term “locked” is used to refer to two clock signals that are
phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz
clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations are used:
B8ZS Bipolar with 8 Zero Substitution
BOC Bit-Oriented Code
CRC Cyclical Redundancy Check
D4 Superframe (12 frames per multiframe) Multiframe Structure
ESF Extended Superframe (24 frames per multiframe) Multiframe Structure
FDL Facility Data Link
FPS Framing Pattern Sequence in ESF
Fs Signaling Framing Pattern in D4
Ft Terminal Framing Pattern in D4
HDLC High-Level Data Link Control
MF Multiframe
SLC–96 Subscriber Loop Carrier—96 Channels
18 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
5 MAJOR OPERATING MODES
Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the
features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86
encapsulation.
The integrated transceiver can be software configured for T1, E1, or J1 operation. It is composed of a line interface
unit (LIU), framer, two additional HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit
parallel port configured for Intel or Motorola bus operations.
The LIUs are composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for
both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be
programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 15dB or 0dB to 36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications) and can be placed in either transmit or receive data paths.
More information on microprocessor control is available in Section
8.1.
19 of 344
s
K
K
C
WR RD I
S
S
S
E
K
JTAG Pins
6 BLOCK DIAGRAMS
Figure 6-1. Main Block Diagram
TTIP
TRING
RTIP
RRING
MCLK
TDCLKI
TDCLKO
TPOSI
TPOSO
TNEGI
TNEGO TCHBLK
CLAD
MUX
LIU
TRANSMIT
TRANSMIT
HDLC
BERT
HDLC
MUX
LIU
RECEIVE
RECEIVIE
JTAG2 JTAG1
TCHCLK
TCLKT
FRAMER
T1/E1/J1
FRAMER
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
TSERI
TSERO
TCLKE
TDEN
ST CS
A0-A9
D0-D7
NT
μP Port
CLAD
SYSCLKI
(RMII MODE)
PORT
SERIAL
TRANSMIT
CIR
PACKET
HDLC/X.86
CONTROLLER
RXD[0:1]
RX_CLK
CRS_DV
RX_ERR
REF_CLK
REF_CLKO
ETHERNET MAC
MAPPER
TRANSCEIVER
ETHERNET
ARBITER
BERT
TX_EN
TXD[0:1]
MDC
PORT
SERIAL
RECEIVE
PACKET
HDLC/X.86
MDIO
SDRAM PORT
]
LIUC
JTAG Pin
RPOSI
RDCLKI
RDCLKO
RNEGI
RPOSO
RNEGO
RCLKO
RCHBL
RCHCL
RSERO
RCLKI
RSERI
RDEN
SDC
NOTE: SOME PINS NOT SHOWN. THE BLOCK IN THE DIAGRAM LABELED “T1/E1/J1 TRANSCEIVER” IS
DIVIDED INTO THREE FUNCTIONAL BLOCKS: LIU, FRAMER, AND BACKPLANE INTERFACE OUTLINED IN
THE FOLLOWING DIAGRAMS.
SRA
SCA
SW
SBA[0:1]
SDATA[0:32]
SDCL
SDMASK[0:4
20 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-2. Block Diagram of T1/E1/J1 Transceiver
CLOCK
CLOCK
ADAPTER
EXTERNAL ACCESS
TO RECEIVE SIGNALS
BACKPLANE
CLOCK SYNTH
BACKPLANE
RX
LIU
MUX
HDB3 / B8ZS
SYNC
SINGALING
ALARM DET
HDLCs
INTERFACE
T1/E1/J1
NETWORK
TX
LIU
LIU
LOCAL LOOPBACK
JITTER ATTENUATOR
EXTERNAL ACCESS
TO TRANSMIT SIGNALS
REMOTE LOOPBACK
MUX
FRAMER LOOPBACK
FRAMER
SINGALING
ALARM GEN
HDLCs
CRC GEN
HDB3 / B8ZS
PAYLOAD LOOPBACK
FRAMER BACKPLANE
CIRCUIT
BACKPLANE
INTERFACE
JTAG ESIB
HOST INTERFACE
21 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-3. Receive and Transmit T1/E1/J1 LIU
XTALD
MCLK
8XCLK
RPOSO
RDCLKO
RNEGO
RDCLKI
RNEGI
RPOSI
RCL
RRING
RTIP
TRING
TTIP
VCO / PLL
MUX
32.768MHz
RECEIVE
LINE I/F
LOCAL LOOPBACK
JITTER ATTENUATOR
OR RECEIVE PATH
TRANSMIT
REMOTE LOOPBACK
JACLK
RPOS
RCLK
RNEG
TRANSMIT
LINE I/F
TNEG
TCLK
TPOS
INTERNAL
MUX
SIGNALS
TO
FRAMER
LIUC
TNEGO
TPOSI
TNEGI
TDCLKI
TPOSO
TDCLKO
22 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-4. Receive and Transmit T1/E1/J1 Framer
REC
HDLC #1
128 Byte
FIFO
REC
HDLC #2
128 Byte
FIFO
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
INTERNAL
SIGNALS
FROM
LIU
DATA
FRAMER LOOPBACK
RECEIVE
FRAMER
TRANSMIT
FRAMER
CLOCK
SYNC
SYNC
CLOCK
DATA
MAPPER MAPPER
MAPPER
MAPPER
PAYLOAD LOOPBACK
DATA
CLOCK
SYNC
SYNC
CLOCK
DATA
INTERNAL
XMIT
HDLC #1
128 Byte
FIFO
XMIT
HDLC #2
128 Byte
FIFO
SIGNALS
TO
BACKPLANE
INTERFACE
23 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-5. T1/E1/J1 Backplane Interface
DATA
CLOCK
SYNC
INTERNAL
SIGNALS
FROM
FRAMER
SYNC
DATA
Sa/FDL
INSERT
ELASTIC
STORE
Sa BIT/FDL
EXTRACTION
SIGNALING
BUFFER
ELASTIC
STORE
CHANNEL
TIMING
SIGNALING
BUFFER
RLINK
RLCLK
RSIG
RSIGFR
RSYSCLK
RSERO
RCLKO
RSYNC
RMSYNC
RFSYNC
RDATA
RCHCLK
RCHBLK
TSERI
TSIG
TSSYNC
CLOCK
JACLK
CHANNEL
TIMING
24 of 344
TSYSCLK
TSYNC
TESO
TDATA
TLCLK
TLINK
TCHCLK
TCHBLK
TCLK
MUX
TCLKT
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
7 PIN DESCRIPTIONS
7.1 Pin Functional Description
Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG
patterns.
LEGEND: I = input, O = output, Ipu = input with pullup, Oz = output with tri-state, IO = bidirectional pin, IOz = bidirectional pin with tri-state.
Table 7-1. Detailed Pin Descriptions
NAME PIN TYPE FUNCTION
MICROPROCESSOR PORT
A0 A18 I
A1 B18 I
A2 C18 I
A3 A17 I
A4 B17 I
A5 C17 I
A6 A16 I
A7 B16 I
A8 C16 I
A9 C15 I
D0 A14 IOZ
D1 B14 IOZ
D2 C14 IOZ
D3 A13 IOZ
D4 B13 IOZ
D5 C13 IOZ
D6 A12 IOZ
D7 B12 IOZ
WR/RW
C11 I
Address Bit 0: Address bit 0 of the microprocessor interface.
Least Significant Bit.
Address Bit 1: Address bit 1 of the microprocessor interface.
Address Bit 2: Address bit 2 of the microprocessor interface.
Address Bit 3: Address bit 3 of the microprocessor interface.
Address Bit 4: Address bit 4 of the microprocessor interface.
Address Bit 5: Address bit 5 of the microprocessor interface.
Address Bit 6: Address bit 6 of the microprocessor interface.
Address Bit 7: Address bit 7 of the microprocessor interface.
Address Bit 8: Address bit 8 of the microprocessor interface.
Address Bit 9: Address bit 9 of the microprocessor interface.
Data Bit 0: Bidirectional data bit 0 of the microprocessor interface.
Least Significant Bit. Not driven when CS =1 or RST = 0.
Data Bit 1: Bidirectional data bit 1 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 2: Bidirectional data bit 2 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 3: Bidirectional data bit 3 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 4: Bidirectional data bit 4 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 5: Bidirectional data bit 5 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 6: Bidirectional data bit 6 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 7: Bidirectional data bit 7 of the microprocessor interface.
Most Significant Bit. Not driven when CS = 1 or RST = 0.
Write (Intel Mode): The DS33R11 captures the contents of the
data bus (D0-D7) on the rising edge of WR and writes them to the
addressed register location. CS must be held low during write
operations.
Read Write (Motorola Mode): Used to indicate read or write
operation. RW must be set high for a register read cycle and low for
a register write cycle.
25 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
Read Data Strobe (Intel Mode): The DS33R11 drives the data bus
(D0-D7) with the contents of the addressed register while RD and
CS are both low.
RD/DS
B11 I
Data Strobe (Motorola Mode): Used to latch data through the
microprocessor interface. DS must be low during read and write
operations.
Chip Select for Protocol Conversion Device: This pin must be
CS
A11 I
taken low for read/write operations. When CS is high, the RD/DS
and WR signals are ignored.
CST
D7 I
Chip Select for the T1/E1/J1 Transceiver: Must be low to read or
write the T1/E1/J1 transceiver.
Interrupt Output: Outputs a logic zero when an unmasked
interrupt event is detected. INT is deasserted when all interrupts
INT
A10 OZ
have been acknowledged and serviced. Active low. Inactive state is
programmable in register
GL.CR1. is deasserted when all
interrupts have been acknowledged and serviced. Active low.
Inactive state is programmable in register
GL.CR1.
26 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
MII/RMII PHY PORT
Collision Detect (MII): Asserted by the MAC PHY to indicate that a
COL_DET N18 I
collision is occurring. In DCE Mode this signal should be connected
to ground. This signal is only valid in half duplex mode, and is
ignored in full duplex mode.
Receive Carrier Sense (MII): Should be asserted (high) when data
from the PHY (RXD[3:0) is valid. For each clock pulse 4 bits arrive
from the PHY. Bit 0 is the least significant bit. In DCE mode,
RX_CRS/
CRS_DV
M19 I
connect to V
DD
.
Carrier Sense/Receive Data Valid (RMII): This signal is asserted
(high) when data is valid from the PHY. For each clock pulse 2 bits
arrive from the PHY. In DCE mode, this signal must be grounded.
Receive Clock (MII): Timing reference for RX_DV, RX_ERR and
RXD[3:0], which are clocked on the rising edge. RX_CLK frequency
RX_CLK M20 IO
is 25MHz for 100Mbit/s operation and 2.5MHz for 10Mbit/s
operation. In DTE mode, this is a clock input provided by the PHY.
In DCE mode, this is an output derived from REF_CLK providing
2.5MHz (10Mbit/s operation) or 25MHz (100Mbit/s operation).
Receive Data 0 through 3 (MII): Four bits of received data,
RXD[0] L18
sampled synchronously with the rising edge of RX_CLK. For every
clock cycle, the PHY transfers 4 bits to the DS33R11. RXD[0] is the
RXD[1] L19
O
RXD[2] L20
least significant bit of the data. Data is not considered valid when
RX_DV is low.
Receive Data 0 through 1 (RMII): Two bits of received data,
sampled synchronously with REF_CLK with 100Mbit/s mode.
RXD[3] M18
Accepted when CRS_DV is asserted. When configured for
10Mbit/s mode, the data is sampled once every 10 clock periods.
Receive Data Valid (MII): This active high signal indicates valid
RX_DV K19 I
data from the PHY. The data RXD is ignored if RX_DV is not
asserted high.
Receive Error (MII): Asserted by the MAC PHY for one or more
RX_CLK periods indicating that an error has occurred. Active High
indicates Receive code group is invalid. If CRS_DV is low,
RX_ERR K18 I
RX_ERR has no effect. This is synchronous with RX_CLK. In DCE
mode, this signal must be grounded.
Receive Error (RMII): Signal is synchronous to REF_CLK.
Transmit Clock (MII): Timing reference for TX_EN and TXD[3:0].
The TX_CLK frequency is 25MHz for 100Mbit/s operation and
2.5MHz for 10Mbit/s operation.
TX_CLK H19 IO
In DTE mode, this is a clock input provided by the PHY. In DCE
mode, this is an output derived from REF_CLK providing 2.5MHz
(10Mbit/s operation) or 25MHz (100Mbit/s operation).
27 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
TXD[0] F19
Transmit Data 0 through 3(MII): TXD [3:0] is presented
synchronously with the rising edge of TX_CLK. TXD [0] is the least
TXD[1] F18
TXD[2] E20
TXD[3] E19
O
significant bit of the data. When TX_EN is low the data on TXD
should be ignored.
Transmit Data 0 through 1(RMII): Two bits of data TXD [1:0]
presented synchronously with the rising edge of REF_CLK.
Transmit Enable (MII): This pin is asserted high when data TXD
[3:0] is being provided by the DS33R11. The signal is deasserted
prior to the first nibble of the next frame. This signal is synchronous
TX_EN F20 O
with the rising edge TX_CLK. It is asserted with the first bit of the
preamble.
Transmit Enable (RMII): When this signal is asserted, the data on
TXD [1:0] is valid. This signal is synchronous to the REF_CLK.
Reference Clock (RMII and MII): When in RMII mode, all signals
from the PHY are synchronous to this clock input for both transmit
and receive. This required clock can be up to 50MHz and should
have ±100ppm accuracy.
REF_CLK A19 I
When in MII mode in DCE operation, the DS33R11 uses this input
to generate the RX_CLK and TX_CLK outputs as required for the
Ethernet PHY interface. When the MII interface is used with DTE
operation, this clock is not required and should be tied low.
In DCE and RMII modes, this input must have a stable clock input
before setting the RST pin high for normal operation.
Reference Clock Output (RMII and MII): A derived clock output
up to 50MHz, generated by internal division of the SYSCLKI signal.
REF_CLKO A20 O
Frequency accuracy of the REF_CLKO signal will be proportional
to the accuracy of the user-supplied SYSCLKI signal. See Section
9.1.1 for more information.
DCE or DTE Selection: The user must set this pin high for DCE
Mode selection or low for DTE Mode. In DCE Mode, the DS33R11
MAC port can be directly connected to another MAC. In DCE
DCEDTES G20 I
Mode, the Transmit clock (TX_CLK) and Receive clock (RX_CLK)
are output by the DS33R11. Note that there is no software bit
selection of DCEDTES. Note that DCE Mode is only relevant when
the MAC interface is in MII mode.
RMIIMIIS G19 I
RMII or MII Selection: Set high to configure the MAC for RMII
interfacing. Set low for MII interfacing.
28 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
PHY MANAGEMENT BUS
Management Data Clock (MII): Clocks management data between
MDC C19 O
the PHY and DS33R11. The clock is derived from theSYSCLKI,
with a maximum frequency is 1.67MHz. The user must leave this
pin unconnected in the DCE Mode.
MII Management data IO (MII): Data path for control information
between the PHY and DS33R11. When not used, pull to logic high
externally through a 10kΩ resistor. The MDC and MDIO pins are
MDIO C20 IO
used to write or read up to 32 Control and Status Registers in 32
PHY Controllers. This port can also be used to initiate AutoNegotiation for the PHY. The user must leave this pin unconnected
in the DCE Mode.
SDRAM INTERFACE
SDRAM Column Address Strobe: Active-low output, used to latch
SCAS
W7 O
the column address on the rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SDRAM Row Address Strobe: Active-low output, used to latch
SRAS
W9 O
the row address on rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SDCS
V10 O
SDRAM Chip Select: Active-low output enables SDRAM access.
SWE
W10 O
SBA[0] Y11
SBA[1] V11
SDRAM Write Enable: This active-low output enables write
operation and auto precharge.
SDRAM Bank Select: These 2 bits select 1 of 4 banks for the
read/write/precharge operations.
O
Note: All SDRAM operations are controlled entirely by the
DS33R11. No user programming for SDRAM buffering is required.
29 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
SDATA[0] W2
SDATA[1] Y4
SDATA[2] Y2
SDATA[3] Y5
SDATA[4] Y3
SDATA[5] W5
SDATA[6] V5
SDATA[7] W6
SDATA[8] V6
SDATA[9] W4
SDATA[10] V4
SDATA[11] V2
SDATA[12] V3
SDATA[13] V1
SDATA[14] W3
SDATA[15] W1
SDATA[16] Y16
SDATA[17] Y17
SDATA[18] V18
O
SDRAM Data Bus Bits 0 to 31: The 32 pins of the SDRAM data
bus are inputs for read operations and outputs for write operations.
At all other times, these pins are high-impedance.
Note: All SDRAM operations are controlled entirely by the
DS33R11. No user programming for SDRAM buffering is required.
SDATA[19] Y19
SDATA[20] V19
SDATA[21] Y20
SDATA[22] U19
SDATA[23] W20
SDATA[24] U20
SDATA[25] T19
SDATA[26] T20
SDATA[27] Y18
SDATA[28] W19
SDATA[29] V17
SDATA[30] W17
SDATA[31] W16
SDA[0] W14
SDA[1] W12
SDA[2] Y15
SDA[3] W15
SDA[4] Y14
SDA[5] V13
SDA[6] W13
SDA[7] Y12
SDA[8] V12
SDA[9] Y10
O
SDRAM Address Bus 0 to 11: The 12 pins of the SDRAM address
bus output the row address first, followed by the column address.
The row address is determined by SDA0 to SDA11 at the rising
edge of clock. Column address is determined by SDA0-SDA9 and
SDA11 at the rising edge of the clock. SDA10 is used as an autoprecharge signal.
Note: All SDRAM operations are controlled entirely by the
DS33R11. No user programming for SDRAM buffering is required.
SDA[10] V14
SDA[11] W11
SDMASK[0] Y6
SDMASK[1] V7
SDMASK[2] V16
SDMASK[3] V15
SDCLKO Y8
O
O
(4mA)
SDRAM Mask 0 through 3: When high, a write is done for that
byte. The least significant byte is SDATA7 to SDATA0. The most
significant byte is SDATA31 to SDATA24.
SDRAM CLK Out: System clock output to the SDRAM. This clock
is a buffered version of SYSCLKI.
30 of 344
Loading...