Maxim Integrated Corona User Manual

Corona (MAXREFDES12#) Nexys 3

Quick Start Guide

Rev 0; 4/13

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Corona (MAXREFDES12#) Nexys 3 Quick Start Guide

Table of Contents

1. Required Equipment ................................................................................................. 3

2. Overview ................................................................................................................... 3

3. Included Files............................................................................................................ 5

4. Procedure ................................................................................................................. 6

5. Code Documentation .............................................................................................. 17

6. Appendix A: Project Structure and Key Filenames ................................................. 18

7. Trademarks............................................................................................................. 18

8. Revision History ...................................................................................................... 19

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Corona (MAXREFDES12#) Nexys 3 Quick Start Guide

1. Required Equipment

• PC with Windows® OS with Xilinx® ISE®/SDK version 13.4 or later and one
USB port

• License for Xilinx EDK/SDK version 13.4 or later

• Corona (MAXREFDES12#) board

• Nexys™3 development kit

• One 24V 1A DC power supply

2. Overview

Below is a high-level overview of the steps required to quickly get the Corona design
running by downloading and running the FPGA project. Detailed instructions for each
step are provided in the following pages. The Corona (MAXREFDES12#) subsystem
reference design will be referred to as Corona throughout this document.

1) Connect the Corona board to the JA1 port of a Nexys 3 development kit as
shown in Figure 1

2) Download the latest RD12V01_00.ZIP file located at the Corona page.

3) Extract the RD12V01_00.ZIP file to a directory on your PC.

4) Open the Xilinx SDK.

5) Download the bitstream (.BIT) file to the board. This bitstream contains the F PGA
hardware design and software bootloader.

6) Use Xilinx SDK to download and run the executable file (.ELF) on the
MicroBlaze™.

. Ensure the connector is aligned as shown in Figure 2.

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Corona (MAXREFDES12#) Nexys 3 Quick Start Guide

Figure 1. Corona Board Connected to Nexys 3 Development Kit

Figure 2. Pmod™ Connector Alignment

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Corona (MAXREFDES12#) Nexys 3 Quick Start Guide

3. Included Files

The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for
Xilinx ISE version 13.4. The Verilog-based HDL design instantiates the MicroBlaze core,
the support hardware required to run the MicroBlaze, and the peripherals that interface
to the Pmod ports. This is supplied as a Xilinx software development kit (SDK) project
that includes a demonstration software application to evaluate the Corona subsystem
reference design. The lower level c-code driver routines are portable to the user’s own
software project.

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Figure 3. Block Diagram of FPGA Hardware Design

Corona (MAXREFDES12#) Nexys 3 Quick Start Guide

4. Procedure

1. Connect the Corona board to the JA1 port of a Nexys 3 development kit as
shown in Figure 1.

2. Connect the 24V DC power-supply positive terminal to the TP3 connector on the
Corona board. Connect the 24V DC power-supply ground terminal to the TP4
connector on the Corona board.

3. Power up the Nexys 3 development kit by sliding the SW8 switch on the Nexys 3
board to the ON position.

4. Download the latest RD12V01_00.ZIP file at

www.maximintegrated.com/AN5611. All files available for downl oa d are

available at the bottom of the page.

5. Extract the RD12V01_00.ZIP file to a directory on your PC. The location is
arbitrary but the maximum path length limitation in Windows (260 characters)
should not be exceeded.

In addition, the Xilinx tools require the path to not contain any spaces.

C:\Do Not Use Spaces In The Path\RD12V01_00.ZIP

(This path has spaces.)

For the purposes of this document, it will be C:\designs\maxim\RD12V01_00\.
See Appendix A: Project Structure and Key Filenames in this document for
the project structure and key filenames.

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