Maxim Integrated Carmel User Manual

Carmel (MAXREFDES18#) ZedBoard

Quick Start Guide

Rev 0; 8/13

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

Table of Contents

1. Required Equipment ................................................................................................. 3

2. Overview ................................................................................................................... 3

3. Included Files ........................................................................................................... 5

4. Procedure ................................................................................................................. 6

5. Code Documentation ............................................................................................ 199

6. Appendix A: Project Structure and Key Filenames ................................................. 20

7. Trademarks ............................................................................................................ 20

8. Revision History ...................................................................................................... 21

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

1. Required Equipment

• PC with Windows® OS with Xilinx® ISE®/SDK version 14.2 or later and two USB
ports (Refer to Xilinx AR# 51895 if you installed ISE WebPackTM design software
on your PC.)

• License for Xilinx EDK/SDK version 14.2 or later (free WebPack license is OK)

• Carmel (MAXREFDES18#) board

• ZedBoardTM development kit

• One ±24V 25mA minimum DC power supply

• One 750Ω 0.25W resistor

2. Overview

Below is a high-level overview of the steps required to quickly get the Carmel design
running by downloading and running the FPGA project. Detailed instructions for each
step are provided in the following pages. The Carmel (MAXREFDES18#) subsystem
reference design will be referred to as Carmel throughout this document.

1) Connect the Carmel board to the JA1 port of a ZedBoard as shown in Figure 1.
Ensure the connector is aligned as shown in

2) Download the latest RD18V01_00.ZIP file located at the Carmel page.

3) Extract the RD18V01_00.ZIP file to a directory on your PC.

4) Open the Xilinx SDK.

5) Download the bitstream (.BIT) file to the board. This bitstream contains the FPGA
hardware design and software bootloader.

6) Use Xilinx SDK to download and run the executable file (.ELF) on one of the two

®

ARM

CortexTM-A9 processors.

Figure 2.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

Figure 1. Carmel Board Connected to ZedBoard Kit

Figure 2. Pmod™ Connector Alignment

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

3. Included Files

The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for
Xilinx ISE version 14.2. The Verilog-based top.v module provides FPGA/board net
connectivity, allows HDL interaction with peripherals, a nd instantiates the wrapper that
carries both the Zynq® Processing System and (I2C, SPI, GPIO, UART) soft peripherals
that inter face to the Pmod ports. This is supplied as a Xilinx software development kit
(SDK) project that includes a demonstration software application to evaluate the Carmel
subsystem reference design. The lower level c-code driver r outines are portable to the
user’s own software project.

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Figure 3. Block Diagram of FPGA Hardware Design

Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

4. Procedure

1. Connect the Carmel board to the JA1 port of a ZedBoard as shown in Figure 1.

2. Connect the ±24V power supply positive terminal, negative terminal, and the
ground terminal to the AVDD, AVSS, and AGND connectors, respectively, on the
Carmel board.

3. Connect one end of the 750Ω load resistor to the OUT and SENSEVP
connectors on the Carmel board.

4. Connect the other end of the 750Ω load resistor to the AGND and SENSEVN
connectors on the Carmel board.

5. Ver if y t hat the JU1 and JU4 jumpers are on the 1-2 position.

6. Verify that the JU2 jumper is on the pin 1 only.

7. Power up t he ZedBoard by sliding the SW8 switch on the ZedBoard to the ON
position.

8. Download the latest RD18V01_00.ZIP file at

www.maximintegrated.com/Carmel. All files available for download are

available at the bottom of the page.

9. Extract the RD18V01_00.ZIP file to a directory on your PC. The location is
arbitrary but the maximum path length limitation in Windows (260 characters)
should not be exceeded.

In addition, the Xilinx tools require the path to not contain any spaces.

C:\Do Not Use Spaces In The Path\RD18V01_00.ZIP

(This path has spaces.)

For the purposes of this document, it will be C:\designs\maxim\RD18V01_00\.
See Appendix A: Project Structure and Key Filenames in this document for
the project structure and key filenames.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

10. Open the Xilinx Software Development Kit (SDK) from the Windows Start
menu.

11. SDK will prompt for a workspace directory, which is the location where the
software project is located. For this example, it is:

C:\designs\maxim\RD18V01_00\RD18_ZED_V01_00\Design_Files\sdkWorkspace

Click OK and SDK will open. The Xilinx SDK is based on an Eclipse™-based
IDE, so it will be a familiar flow for many software developers.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

12. Review the SDK IDE. The Project Explorer in the upper left tab should have
three components as shown in the image below. If all three subfolders are
present, you can skip the next step.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

13. If the Project Explorer does not contain these three subfolders, launch the

File | Import menu, expand the General folder, and select Existing Projects
into Workspace. Click Next. Set the root directory to:

C:\designs\maxim\RD18V01_00\RD18_ZED_V01_00\Design_Files\sdkWorkspace

and the missing projects should appear in SDK Project Explorer with their
checkboxes checked.

Click Finish to import the projects.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

14. To download the bitstream (.BIT) file to the board, click on the Program FPGA
icon (which looks like a green chain of devices).

The Program FPGA dialog box appears. From here, an FPGA bitstream (.BIT)
file is selected. Be sure to select the .BIT file by using the paths below.

Bitstream:

C:\designs\maxim\RD18V01_00\RD18_ZED_V01_00\Design_Files\top.bit

Press Program.

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It takes approximately 10 seconds to download the FPGA, then a message box
indicating FPGA configuration complete appears.

Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

15. Setup of the terminal program to run on the PC using the following steps. Before
loading the executable firmware file on the FPGA, the term inal pr ogr am on the
PC should be running. The example firmware running on the FPGA
communicates with the PC via a USB port set up to emulate a serial port (UART).
To establish this communication link, the PC must be configured with the
appropriate Windows drivers. A suitable terminal program such as Tera Term or
HyperTerminal should be invoked.

The ZedBoard utilizes the Cypress USB-UART bridge IC. If the Windows cannot
automatically install the driver for the Cypress USB-UART bridge IC, the driver is
available for download from www.cypress.com/?rID=63794. The driver is WHQL
certified for the default Cypress VID / PID of 0x04B4 / 0x0008.

Once installed, Windows will assign a previously unused COM port. Use the
Windows Control Panel | System | Device Manager to determine the COM port
number. (It will be named Cypress Serial.) Make a note of which COM port this
is. That information is needed in the next step.

Next, a terminal emulation program needs to be installed and launched. For
Windows XP® and earlier systems, the HyperTerminal program is the usual
choice. However, since HyperTerminal was eliminated from Windows 7, it may
be necessary to locate an alternative. Several are available; one good choice is
called Tera Term (http://ttssh2.sourceforge.jp/). Whatever terminal program you
choose, the communication should be set up by opening the COM port number
previously described above and the port configured as:

bits per second: 460,800;
data bits: 8;
parity: none;
stop bits: 1;
flow control: none.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

16. Use the Xilinx SDK to download and run the executable ELF (.ELF) file on the
ARM Cortex-A9 processor using the following steps.

Right-click the mouse while the MAXREFDES18 C project is selected, c hoose
the Run As menu, and then Run Configurations… menu as shown below.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

Next, double-click the mouse on the Xilinx C/C++ ELF menu.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

Next, press the Search Project button.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

Double-click on the MAXREFDES18.elf binary.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

Verify the application is selected on the Main tab.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

On the Device Initialization tab, click Browse… button to select the right
initialization TCL file and press the Run button.

Once the Debug/MAXREFDES18 configuration is set up once, you just need to
press the Run button if you ever want to run the program again.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

At this point, the application will be running on the Cortex-A9 and the terminal
program should show the menu below. Make the desired selections by pressing
the appropriate keys on the keyboard. For example, to select current output,
press 0.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

5. Code Documentation

Code documentation can be found at:
C:\...\RD18V01_00\RD18_ZED_V01_00\Code_Documentation\

To view the code documentation in HTML format with a browser, open the
MainPage.html file.

To view the code documentation in .PDF format with a PDF reader, open the
MAXREFDES18_Code_Documentation.pdf file.

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

6. Appendix A: Project Structure and Key Filenames

7. Trademarks

ARM is a registered trademark of ARM Ltd.
Cortex is a trademark of ARM Ltd.
Eclipse is a trademark of Eclipse Foundation, Inc.
MicroBlaze is a trademark of Xilinx, Inc.
Pmod is a trademark of Digilent Inc.
WebPACK is a trademark of Xilinx, Inc.
Windows is a registered trademark and registered service mark and Windows XP is a
registered trademark of Microsoft Corporation.
Xilinx is a registered trademark and registered service mark of Xilinx, Inc.
ZedBoard is a trademark of Avnet, Inc.
Zync is a registered trademark of Xilinx, Inc.

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8. Revision History

REVISION

NUMBER

REVISION

DATE

PAGES

CHANGED

0

8/13

Initial release

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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide

DESCRIPTION

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