Maxim Integrated Carmel User Manual
Carmel (MAXREFDES18#) ZedBoard
Quick Start Guide
Rev 0; 8/13
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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide
Table of Contents
1. Required Equipment ................................................................................................. 3
2. Overview ................................................................................................................... 3
3. Included Files ........................................................................................................... 5
4. Procedure ................................................................................................................. 6
5. Code Documentation ............................................................................................ 199
6. Appendix A: Project Structure and Key Filenames ................................................. 20
7. Trademarks ............................................................................................................ 20
8. Revision History ...................................................................................................... 21
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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide
1. Required Equipment
• PC with Windows® OS with Xilinx® ISE®/SDK version 14.2 or later and two USB
ports (Refer to Xilinx AR# 51895 if you installed ISE WebPackTM design software
on your PC.)
• License for Xilinx EDK/SDK version 14.2 or later (free WebPack license is OK)
• Carmel (MAXREFDES18#) board
• ZedBoardTM development kit
• One ±24V 25mA minimum DC power supply
• One 750Ω 0.25W resistor
2. Overview
Below is a high-level overview of the steps required to quickly get the Carmel design
running by downloading and running the FPGA project. Detailed instructions for each
step are provided in the following pages. The Carmel (MAXREFDES18#) subsystem
reference design will be referred to as Carmel throughout this document.
1) Connect the Carmel board to the JA1 port of a ZedBoard as shown in Figure 1.
Ensure the connector is aligned as shown in
2) Download the latest RD18V01_00.ZIP file located at the Carmel page.
3) Extract the RD18V01_00.ZIP file to a directory on your PC.
4) Open the Xilinx SDK.
5) Download the bitstream (.BIT) file to the board. This bitstream contains the FPGA
hardware design and software bootloader.
6) Use Xilinx SDK to download and run the executable file (.ELF) on one of the two
®
ARM
CortexTM-A9 processors.
Figure 2.
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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide
Figure 1. Carmel Board Connected to ZedBoard Kit
Figure 2. Pmod™ Connector Alignment
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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide
3. Included Files
The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for
Xilinx ISE version 14.2. The Verilog-based top.v module provides FPGA/board net
connectivity, allows HDL interaction with peripherals, a nd instantiates the wrapper that
carries both the Zynq® Processing System and (I2C, SPI, GPIO, UART) soft peripherals
that inter face to the Pmod ports. This is supplied as a Xilinx software development kit
(SDK) project that includes a demonstration software application to evaluate the Carmel
subsystem reference design. The lower level c-code driver r outines are portable to the
user’s own software project.
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Figure 3. Block Diagram of FPGA Hardware Design
Carmel (MAXREFDES18#) ZedBoard Quick Start Guide
4. Procedure
1. Connect the Carmel board to the JA1 port of a ZedBoard as shown in Figure 1.
2. Connect the ±24V power supply positive terminal, negative terminal, and the
ground terminal to the AVDD, AVSS, and AGND connectors, respectively, on the
Carmel board.
3. Connect one end of the 750Ω load resistor to the OUT and SENSEVP
connectors on the Carmel board.
4. Connect the other end of the 750Ω load resistor to the AGND and SENSEVN
connectors on the Carmel board.
5. Ver if y t hat the JU1 and JU4 jumpers are on the 1-2 position.
6. Verify that the JU2 jumper is on the pin 1 only.
7. Power up t he ZedBoard by sliding the SW8 switch on the ZedBoard to the ON
position.
8. Download the latest RD18V01_00.ZIP file at
www.maximintegrated.com/Carmel. All files available for download are
available at the bottom of the page.
9. Extract the RD18V01_00.ZIP file to a directory on your PC. The location is
arbitrary but the maximum path length limitation in Windows (260 characters)
should not be exceeded.
In addition, the Xilinx tools require the path to not contain any spaces.
C:\Do Not Use Spaces In The Path\RD18V01_00.ZIP
(This path has spaces.)
For the purposes of this document, it will be C:\designs\maxim\RD18V01_00\.
See Appendix A: Project Structure and Key Filenames in this document for
the project structure and key filenames.
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Carmel (MAXREFDES18#) ZedBoard Quick Start Guide
10. Open the Xilinx Software Development Kit (SDK) from the Windows Start
menu.
11. SDK will prompt for a workspace directory, which is the location where the
software project is located. For this example, it is:
C:\designs\maxim\RD18V01_00\RD18_ZED_V01_00\Design_Files\sdkWorkspace
Click OK and SDK will open. The Xilinx SDK is based on an Eclipse™-based
IDE, so it will be a familiar flow for many software developers.
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