Maxim Integrated Alameda User Manual
Alameda (MAXREFDES24#) ZedBoard
Quick Start Guide
Rev 0; 3/14
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit
patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Alameda (MAXREFDES24#) ZedBoard Quick Start Guide
Table of Contents
1. Required Equipment ................................................................................................. 3
2. Overview ................................................................................................................... 3
3. Included Files ........................................................................................................... 5
4. Procedure ................................................................................................................. 6
5. Code Documentation .............................................................................................. 19
6. Appendix A: Project Structure and Key Filenames ................................................. 20
7. Trademarks ............................................................................................................ 20
8. Revision History ...................................................................................................... 21
2
Alameda (MAXREFDES24#) ZedBoard Quick Start Guide
1. Required Equipment
• PC with Windows® OS with Xilinx® ISE®/SDK version 14.2 or later and two USB
ports (Refer to Xilinx AR# 52495 if you installed ISE WebPACKTM design
software on your PC.)
• License for Xilinx EDK/SDK version 14.2 or later (free WebPACK license is OK)
• Alameda (MAXREFDES24#) board
• ZedBoardTM development kit
• One +24V 1A DC power supply
• One 750Ω 0.25W resistor
2. Overview
Below is a high-level overview of the steps required to quickly get the Alameda design
running by downloading and running the FPGA project. Detailed instructions for each
step are provided in the following pages. The Alameda (MAXREFDES24#) subsystem
reference design will be referred to as Alameda throughout this document.
1) Connect the Alameda board to the JA1 and JB1 ports of a ZedBoard as shown in
Figure 1. Ensure the connectors are aligned as shown in Figure 2
communication between the Alameda board and the ZedBoard is through the
pins on the JB1 connector. The JA1 connector is for the board physical support
only.
2) Download the latest RD24V01_00.ZIP file located at the Alameda page.
3) Extract the RD24V01_00.ZIP file to a directory on your PC.
4) Open the Xilinx SDK.
5) Download the bitstream (.BIT) file to the board. This bitstream contains the FPGA
hardware design and software bootloader.
6) Use Xilinx SDK to download and run the executable file (.ELF) on one of the two
ARM® CortexTM -A9 processors.
. The
3
Alameda (MAXREFDES24#) ZedBoard Quick Start Guide
Figure 1. Alameda Board Connected to ZedBoard Kit
Figure 2. Pmod™ Connector Alignment
4
Alameda (MAXREFDES24#) ZedBoard Quick Start Guide
3. Included Files
The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for
Xilinx ISE version 14.2. The Verilog-based top.v module provides FPGA/board net
connectivity, allows HDL interaction with peripherals, a nd instantiates the wrapper that
carries both the Zynq® Processing System and (I2C, SPI, GPIO, UART) soft peripherals
that inter face to the Pmod ports. This is supplied as a Xilinx software development kit
(SDK) project that includes a demonstration software application to evaluate the
Alameda subsystem reference design. The lower level c-code driver routines are
portable to the user’s own software project.
5
Figure 3. Block Diagram of FPGA Hardware Design
Alameda (MAXREFDES24#) ZedBoard Quick Start Guide
4. Procedure
1. Connect the Alameda board to the JA1 and JB1 ports of a ZedBoard as shown in
Figure 1.
2. Connect the +24V power supply positive terminal and the ground terminal to the
+24V and the PGND connectors on the Alameda board, respectively.
3. Connect one end of the 750Ω load resistor to the OUT1 connector on the
Alameda board. Connect the other end of the 750Ω load resistor to the AGND1
connector on the Alameda board.
4. Ver if y t hat the JU1, JU3, JU5, and JU7 jumpers are on the 2-3 position.
5. Ver if y t hat the JU2, JU4, JU6, and JU8 jumpers are on the 1-2 position.
6. Connect the J14 USB connector of the ZedBoard to a PC. This connection is
used to communicate with a PC through a terminal program. See step 16 for
USB driver installation.
7. Connect the J17 USB connector of the ZedBoard to a PC. This connection is
used to program and debug the FPGA.
8. Power up t he ZedBoard by sliding the SW8 switch on the ZedBoard to the ON
position.
9. Download the latest RD24V01_00.ZIP file at
www.maximintegrated.com/Alameda. All files available for download are
available at the bottom of the page.
10. Extract the RD24V01_00.ZIP file to a directory on your PC. The location is
arbitrary but the maximum path length limitation in Windows (260 characters)
should not be exceeded.
In addition, the Xilinx tools require the path to not contain any spaces.
C:\Do Not Use Spaces In The Path\RD24V01_00.ZIP
(This path has spaces.)
For the purposes of this document, it will be C:\designs\maxim\RD24V01_00\.
See Appendix A: Project Structure and Key Filenames in this document for
the project structure and key filenames.
6
Alameda (MAXREFDES24#) ZedBoard Quick Start Guide
11. Open the Xilinx Software Development Kit (SDK) from the Windows Start
menu.
12. SDK will prompt for a workspace directory, which is the location where the
software project is located. For this example, it is:
C:\designs\maxim\RD24V01_00\RD24_ZED_V01_00\Design_Files\sdkWorkspace
Click OK and SDK will open. The Xilinx SDK is based on an Eclipse™-based
IDE, so it will be a familiar flow for many software developers.
7
Loading...