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General Description
The MAX7317 serial-interfaced peripheral provides
microprocessors with 10 I/O ports rated to 7V. Each
port can be individually configured as either an opendrain output, or an overvoltage-protected Schmitt input.
The MAX7317 supports hot insertion. All port pins
remain high impedance in power-down (V+ = 0V) with
up to 8V asserted on them.
The MAX7317 is available in 16-pin thin QFN and QSOP
packages and operates in the -40°C to +125°C range.
For a similar part with constant-current outputs and
8-bit PWM controls, refer to the MAX6966/MAX6967
data sheet.
Applications
Portable Equipment
Cellular Phones
White Goods
Industrial Controllers
Automotive
System Monitoring
Features
♦ High-Speed, 26MHz SPI™-/QSPI-™/MICROWIRE™-
Compatible Serial Interface
♦ 2.25V to 3.6V Operation
♦ I/O Port Inputs are Overvoltage Protected to 7V
♦ I/O Port Outputs are 7V-Rated Open Drain
♦ I/O Ports Support Hot Insertion
♦ 0.7µA (typ), 1.9µA (max) Standby Current
♦ Tiny 3mm x 3mm, 0.8mm High Thin QFN Package
♦ -40°C to +125°C Temperature Range
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
________________________________________________________________ Maxim Integrated Products 1
THIN QFN
MAX7317ATE
13
14
15
1234
5
6
16
12 11 10 9
8
7
V+
DIN
SCLK
P0
P1
P2
P3
P9
P8
P7
CS
P5
P6
GND
P4
DOUT
TOP VIEW
Pin Configurations
Ordering Information
Typical Application Circuit
19-3380; Rev 2; 4/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART
TEMP
PINPACKAGE
TOP
PKG
CODE
MAX7317ATE
-40°C to
16 Thin QFN
3mm x 3mm x
0.8mm
T1633-4
MAX7317AEE
-40°C to
16 QSOP — —
Pin Configurations continued at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
RANGE
+125°C
MARK
ACH
+3.3V
µC
MAX7317
SCLK
DIN
DOUT
CS
GND
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
SCLK
MOSI
MISO
CS
+125°C
I/O PORTS
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.25V to 3.6V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 3.3V, TA= +25°C.)
(Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with respect to GND)
V+ .............................................................................-0.3V to +4V
SCLK, DIN, CS, DOUT .................................-0.3V to (V+ + 0.3V)
P_ .............................................................................-0.3V to +8V
DC Current into P_ .............................................................24mA
DC Current into DOUT ........................................................10mA
Total GND Current ............................................................200mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin Thin QFN
(derate 14.7mW/°C above +70°C).........................1176mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
Operating Temperature Range
(T
MIN
to T
MAX
) ..............................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
Operating Supply Voltage V+
V
Output Load External Supply
Voltage P0–P9
V
EXT
7V
TA = +25°C
1.5
1.7
Standby Current
(Interface Idle)
I
STBY
All digital inputs at V+
or GND
1.9
µA
TA = +25°C
Supply Current I
+
f
SCLK
= 26MHz; other
digital inputs at V+ or
µA
Input High Voltage
(P0–P9, DIN, SCLK, CS)
V
IH
P0–P9 output register set to 0x01
V
Input Low Voltage
(P0–P9, DIN, SCLK, CS)
V
IL
P0–P9 output register set to 0x01
V
Input Leakage Current
(P0–P9, DIN, SCLK, CS)
I
IH
, I
IL
µA
Input Capacitance
(P0–P9, DIN, SCLK, CS
(Note 2) 10 pF
Output Low Voltage (P0–P9) V
OLP_
I
SINK
= 0.5mA, output register set to 0x00 0.4 V
Output Low Short-Circuit Current
(P0–P9)
V
OLPOUT
= 5V
20 mA
Output High Voltage (DOUT)
I
SOURCE
= -6mA V+ - 0.3V V
Output Low Voltage (DOUT)
I
SINK
= 6mA 0.3 V
Power-On Reset Voltage V
POR
2V
SYMBOL
MIN TYP MAX
2.25 3.60
T
A
T
A
T
GND; DOUT unloaded
V
OHDOUT
V
OLDOUT
A
T
A
to +85°C
= T
MIN
to T
= T
MIN
MAX
to +85°C 680
= T
MIN
to T
= T
MIN
MAX
0.7 x V+
-0.2 +0.2
0.70
385 620
730
0.3 x V+
10.8
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
_______________________________________________________________________________________ 3
Note 1: All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
TIMING CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.25V to 3.6V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 3.3V, TA= +25°C.)
(Note 1)
PARAMETER
CONDITIONS
UNITS
SCLK Clock Period t
CP
ns
SCLK Pulse-Width High t
CH
19 ns
SCLK Pulse-Width Low t
CL
19 ns
CS Fall to SCLK Rise Setup
t
CSS
ns
SCLK Rise to CS Rise Hold
t
CSH
ns
DIN Setup Time t
DS
ns
DIN Hold Time t
DH
ns
Output Data Propagation Delay
t
DO
19 ns
DOUT Output Rise and Fall
Times
t
FT
C
LOAD
= 20pF (Note 2) 10 ns
Minimum CS Pulse High t
CSW
ns
MAX7317 Block Diagram
SYMBOL
MIN TYP MAX
38.4
9.5
2.5
9.5
2.5
38.4
SCLK
CS
DIN
DOUT
MAX7317
I/O REGISTER
I/O PORTS
4-WIRE SERIAL INTERFACE
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
4 _______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
0
3
9
6
12
15
PORT SINK CURRENT
vs. PORT VOLTAGE
MAX7317 toc01
PORT VOLTAGE (V)
PORT SINK CURRENT (mA)
04268
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0.4
0.6
0.5
0.8
0.7
0.9
1.0
-40 -10 5 20-25 35 50 65 80 95 110 125
STANDBY CURRENT
vs. TEMPERATURE
MAX7317 toc02
TEMPERATURE (°C)
STANDBY CURRENT (µA)
V+ = 3.6V
V+ = 3.3V
V+ = 2.7V
V+ = 2.25V
0
0.1
0.3
0.2
0.4
0.5
-40 -10 5 20-25 35 50 65 80 95 110 125
SUPPLY CURRENT (I+)
vs. TEMPERATURE
MAX7317 toc03
TEMPERATURE (°C)
STANDBY CURRENT (mA)
V+ = 3.6V
V+ = 3.3V
V+ = 2.7V
V+ = 2.25V
PIN
QSOP
QFN
NAME FUNCTION
115SCLK
Serial-Clock Input. On SCLK’s rising edge, data shifts into the internal shift register. On
SCLK’s falling edge, data is clocked out of DOUT. SCLK is active only while CS is low.
216CS
Chip-Select Input. Serial data is loaded into the shift register while CS is low. The most recent
16 bits of data latch on CS’s rising edge.
3–7, 9–13
P0–P9
I/O Ports. P0 to P9 can be configured as open-drain, current-sink outputs rated at 20mA
maximum, or as CMOS inputs, or as open-drain outputs. Loads should be connected to a
supply voltage no higher than 7V.
86GND Ground
14 12 DOUT
Serial-Data Output. The data into DIN is valid at DOUT 15.5 clock cycles later. Use this pin to
daisy-chain several devices or allow data readback. Output is push-pull.
15 13 DIN
Serial-Data Input. Data from DIN loads into the internal 16-bit shift register on SCLK’s rising
edge.
16 14 V+ Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic capacitor.
— PAD
Exposed
pad
Exposed Pad on Package Underside. Connect to GND.
Pin Description
1–5, 7–11
Detailed Description
The MAX7317 is a general-purpose input/output (GPIO)
peripheral that provides 10 I/O ports, P0 to P9, controlled through a high-speed SPI-compatible serial
interface. The 10 I/O ports can be used as inputs or
open-drain outputs in any combination. Ports withstand
7V independent of the MAX7317’s supply voltage
whether used as inputs or outputs.
Figure 1 shows the I/O port structure of the MAX7317.
Register Structure
The MAX7317 contains 10 internal registers, addressed
as 0x00–0x09, which control the peripheral (Table 2).
Two further addresses, 0x0E and 0x0F, do not store
data but return the port input status when read. Four
virtual addresses, 0x0A–0x0D, allow more than one
register to be written with the same data to simplify software. The RAM register provides 1 byte of memory that
can be used for any purpose. The no-op address,
0x20, causes no action when written or read, and is
used as a dummy register when accessing one
MAX7317 out of multiple cascaded devices.
Initial Power-Up
On power-up, all control registers are reset (Table 2).
Power-up status sets I/O ports P0 to P9 high impedance, and puts the device into shutdown mode.
RAM Register
The RAM register provides a byte of memory that can
be used for any purpose.
GPIO Port Direction Configuration
The 10 I/O ports P0 through P9 can be configured to
any combination of inputs and outputs. Ports withstand
7V independent of the MAX7317’s supply voltage,
whether used as inputs or outputs. Configure a port as
an input by setting its output register to 0x01, which
sets the port output high impedance (Table 4).
Input Port Registers
Reading an input port register returns the logic levels at
the I/O port pins. The input port registers are read only.
A write to an input port register is ignored.
Output Registers
The MAX7317 uses one 8-bit register to control each
output port (Table 4). Each port can be configured as
an input or open-drain output. Write 0x00 to the output
register to set the port as a logic-low output, or 0x01 to
set the port as a logic-high output or logic input.
The 10 registers, 0x00 through 0x09, control an I/O port
each (Table 4). Four pseudo-register addresses, 0x0A
through 0x0D, allow groups of outputs to be set to the
same value with a single command by writing the same
data to multiple output registers.
Serial Interface
The MAX7317 communicates through an SPI-compatible 4-wire serial interface. The interface has three
inputs: clock (SCLK), chip select (CS), and data in
(DIN), and one output, data out (DOUT). CS must be
low to clock data into or out of the device, and DIN
must be stable when sampled on the rising edge of
SCLK. DOUT is stable on the rising edge of SCLK.
SCLK and DIN can be used to transmit data to other
peripherals. The MAX7317 ignores all activity on SCLK
and DIN except when CS is low.
Note that the SPI protocol expects DOUT to be high
impedance when the MAX7317 is not being accessed;
DOUT on the MAX7317 is never high impedance. Go to
www.maxim-ic.com/an1879 for ways to convert the
MAX7317 to tri-state, if required.
Control and Operation Using
the 4-Wire Interface
Controlling the MAX7317 requires sending a 16-bit
word. The first byte, D15 through D8, is the command,
and the second byte, D7 through D0, is the data byte
(Table 5).
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
_______________________________________________________________________________________ 5
Figure 1. Simplified Schematic of I/O Ports
N
READ PULSE
INPUT
PORT REGISTER
D
Q
FF
CK
Q
INPUT PORT
REGISTER DATA
D
Q
FF
CK
Q
DATA FROM
SHIFT REGISTER
WRITE PULSE
OUTPUT
PORT REGISTER
OUTPUT PORT
REGISTER DATA
I/O PIN
GND
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
6 _______________________________________________________________________________________
COMMAND ADDRESS
REGISTER
CODE
(hex)
Port P0 output level
0
00
0 0x00
Port P1 output level
0
00
1 0x01
Port P2 output level
0
00
0 0x02
Port P3 output level
0
00
1 0x03
Port P4 output level
0
01
0 0x04
Port P5 output level
0
01
1 0x05
Port P6 output level
0
01
0 0x06
Port P7 output level
0
01
1 0x07
Port P8 output level
0
10
0 0x08
Port P9 output level
0
10
1 0x09
Write ports P0 through P9 with same output level 0
Read port P0 output level 1
0
10
0 0x0A
Write ports P0 through P3 with same output level 0
Read port P0 output level 1
0
10
1 0x0B
Write ports P4 through P7 with same output level 0
Read port P4 output level 1
0
11
0 0x0C
Write ports P8 or P9 with same output level 0
Read port P8 output level 1
0
11
1 0x0D
Read ports P7 through P0 inputs 1
0
11
0 0x0E
Read ports P9 and P8 inputs 1
0
11
1 0x0F
RAM
0
00
1 0x13
No-op
1
00
0 0x20
Factory reserved; do not write to this register
1
11
1 0x7D
Table 1. Register Address Map
REGISTER DATA
REGISTER POWER-UP CONDITION
ADDRESS
CODE
(hex)
D0
Port P0 output level Port 0 high impedance 0x00
1
1
Port P1 output level Port 1 high impedance 0x01
1
1
Port P2 output level Port 2 high impedance 0x02
1
1
Port P3 output level Port 3 high impedance 0x03
1
1
Port P4 output level Port 4 high impedance 0x04
1
1
Port P5 output level Port 5 high impedance 0x05
1
1
Port P6 output level Port 6 high impedance 0x06
1
1
Port P7 output level Port 7 high impedance 0x07
1
1
Port P8 output level Port 8 high impedance 0x08
1
1
Port P9 output level Port 9 high impedance 0x09
1
1
RAM 0x00 0x13
0
0
Table 2. Initial Power-Up Register Status
D15 D14 D13 D12 D11 D10 D9 D8
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
R/W 0
R/W 0
R/W 1
D7 D6 D5 D4 D3 D2 D1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
11111
11111
11111
11111
11111
11111
11111
11111
11111
11111
00000
1
1
0
0
1
1
1
0
0
Connecting Multiple MAX7317s
to the 4-Wire Bus
Multiple MAX7317s can be interfaced to a common SPI
bus by connecting DIN inputs together, SCLK inputs
together, and providing an individual CS per the
MAX7317 device (Figure 2). This connection works
regardless of the configuration of DOUT/OSC, but does
not allow the MAX7317s to be read.
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
_______________________________________________________________________________________ 7
REGISTER DATA
REGISTER
ADDRESS
CODE
(hex)
D0
Read input ports P7–P0 1 0X0E
Port
P0
Read input ports P9, P8 1 0X0F 0 0 0 0 0 0
Port
P8
Table 3. Input Ports Register
REGISTER DATA
BINARYREGISTER
ADDRESS
CODE
(hex)
hex
Port P0 level —
Output P0 level and PWM
Port P0 is open-drain logic low — 00000000
0x00
Port P0 is open-drain logic high (high
impedance without external pullup) or
logic input
—
0x00
00000001
0x01
Port P1 level — 0x01
Port P1 level
Port P2 level — 0x02
Port P2 level
Port P3 level — 0x03
Port P3 level
Port P4 level —- 0x04
Port P4 level
Port P5 level — 0x05
Port P5 level
0x00or0x01
Port P6 level — 0x06
Port P6 level
Port P7 level — 0x07
Port P7 level
Port P8 level — 0x08
Port P8 level
Port P9 level — 0x09
Port P9 level
Writes ports P0 through P9
with same level
0
Ports P0 through P9 level
Reads port P0 level 1
0x0A
Port P0 level
Writes ports P0 through P3
with same level
0
Ports P0 through P3 level
Reads port P0 level 1
0x0B
Port P0 level
Writes ports P4 through P7
with same level
0
Ports P4 through P7 level
Reads port P4 level 1
0x0C
Port P4 level
Write ports P8 and P9 with same level 0
Ports P8, P9 level
Read port P8 level 1
0x0D
Port P8 level
Table 4. Output Registers Format
R/W
D7 D6 D5 D4 D3 D2 D1
PortP7PortP6PortP5PortP4PortP3PortP2Port
R/W
D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
P1
Port
P9
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
MAX7317
Alternatively, MAX7317s can be daisy-chained by connecting the DOUT of one device to the DIN of the next,
and driving SCLK and CS lines in parallel (Figure 3).
This connection allows the MAX7317s to be read. Data
at DIN propagates through the internal shift registers
and appears at DOUT 15.5 clock cycles later, clocked
out on the falling edge of SCLK. When sending commands to daisy-chained MAX7317s, all devices are
accessed at the same time. An access requires (16 x n)
clock cycles, where n is the number of MAX7317s connected together. The serial interface speed (maximum
SCLK) is limited to 10MHz when multiple devices are
daisy-chained due to the DOUT propagation delay and
DIN setup time.
The MAX7317 is written to using the following
sequence (Figure 5):
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK low).
5) Take SCLK low (if not already low).
If fewer or greater than 16 bits are clocked into the
MAX7317 between taking CS low and taking CS high
again, the MAX7317 stores the last 16 bits received,
including the previous transmission(s). The general
case is when n bits (where n > 16) are transmitted to
the MAX7317. The last bits comprising bits {n-15} to
{n}, are retained, and are parallel loaded into the 16-bit
latch as bits D15 to D0, respectively (Figure 6).
Reading Device Registers
Any register data within the MAX7317 can be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last.
D15 is high, indicating a read command and bits
D14 through D8 contain the address of the register
to read. Bits D7 to D0 contain dummy data, which is
discarded.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low). Positions D7 through D0 in the shift register are
now loaded with the register data addressed by bits
D15 through D8.
5) Take SCLK low (if not already low).
6) Issue another read or write command, and examine
the bit stream at DOUT; the second 8 bits are the
contents of the register addressed by bits D14
through D8 in step 3.
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
8 _______________________________________________________________________________________
D15
D14
D13
D12
D11
D10D9D8D7D6D5D4D3D2
D1D0R/ W
ADDRESS
DATA
LSB
Table 5. Serial-Data Format
Figure 2. MAX7317 Multiple CS Connection
MSB
CS3
CS2
µC
CS1
MOSI
SCLK
CS1
DIN
SCLK
LSB MSB
CS2
DIN
SCLK
CS3
DIN
SCLK
MAX7317MAX7317MAX7317
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
_______________________________________________________________________________________ 9
Figure 3. MAX7317 Daisy-Chain Connection
Figure 5. 16-Bit Write Transmission to the MAX7317
Figure 4. Timing Diagram
.
D15
= 0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 = 0
CS
SCLK
DIN
DOUT
MOSI
CS CS CS CS
SCLK
µC
MISO
CS
t
CSS
SCLK
t
DS
t
DIN DOUT DOUT
SCLK
DH
t
CL
t
CH
SCLK
MAX7317MAX7317
t
CP
DOUTDIN DIN
MAX7317
SCLK
t
CSW
t
CSH
DIN
DOUT
D1D14D15
D0
t
DO
D15
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
10 ______________________________________________________________________________________
Applications Information
Hot Insertion
The I/O ports P0–P9 remain high impedance with up to
8V asserted on them when the MAX7317 is powered
down (V+ = 0V). The MAX7317 can therefore be used
in hot-swap applications.
SPI Routing Considerations
The MAX7317’s SPI interface is guaranteed to operate
at 26Mbps on a 2.5V supply, and on a 3.3V supply typically operates at 35Mbps. This means that transmission
line issues should be considered when the interface
connections are longer than 100mm, particularly with
higher supply voltages. Avoid running long adjacent
tracks for SCLK, DIN, and CS without interleaving GND
traces; otherwise, the signals may cross-couple, giving
false clock or chip-select transitions. Ringing may manifest itself as communication issues, often intermittent,
typically due to double clocking caused by ringing at
the SCLK input. Fit a 1kΩ to 10kΩ parallel termination
resistor to either GND or V+ at the DIN, SCLK, and CS
inputs to damp ringing for moderately long interface
runs. Use line-impedance-matching terminations when
making connections between boards.
Output-Level Translation
The open-drain output architecture allows the ports to
level translate the outputs to higher or lower voltages
than the MAX7317 supply. An external pullup resistor
can be used on any output to convert the high-impedance logic-high condition to a positive voltage level.
The resistor can be connected to any voltage up to 7V.
When using a pullup on a constant-current output,
select the resistor value to sink no more than a few hundred µA in logic-low condition. This ensures that the
current sink output saturates close to GND. For interfacing CMOS inputs, a pullup resistor value of 220kΩ is
a good starting point. Use a lower resistance to
improve noise immunity in applications where power
consumption is less critical, or where a faster rise time
is needed for a given capacitive load.
Power-Supply Considerations
The MAX7317 operates with a power-supply voltage of
2.25V to 3.6V. Bypass the power supply to GND with a
0.047µF ceramic capacitor as close to the device as
possible. For the QFN version, connect the underside
exposed pad to GND.
Chip Information
TRANSISTOR COUNT: 14,865
PROCESS: BiCMOS
.
N-15
N-31 N-30 N-29 N-28 N-27 N-26 N-25 N-24 N-23 N-22 N-21 N-20 N-19 N-18 N-17 N-16
BIT1BIT
2
N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N
CS
SCLK
DIN
DOUT
Pin Configurations (continued)
Figure 6. Transmission of More than 16 Bits to the MAX7317
TOP VIEW
SCLK
1
CS
2
P0
3
4
P1
P2
5
P3
6
P4
7
GND
8
16
V+
15
DIN
14
DOUT
MAX7317AEE
QSOP
13
P9
12
P8
P7
11
10
P6
9
P5
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
______________________________________________________________________________________ 11
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
QSOP.EPS
E
1
1
21-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
12x16L QFN THIN.EPS
0.10 C 0.08 C
0.10 M
C A B
D
D/2
E/2
E
A1
A2
A
E2
E2/2
L
k
e
(ND - 1) X e
(NE - 1) X e
D2
D2/2
b
L
e
L
C
L
e
C
L
L
C
L
C
E
1
2
21-0136
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
EXPOSED PAD VARIATIONS
1.10
T1633-1 0.95
CODES
PKG.
T1233-1
MIN.
0.95
NOM.
1.10
D2
1.25
1.10
0.95
1.25
NOM.
1.10
MAX.
1.25
MIN.
0.95
MAX.
1.25
E2
12
N
k
A2
0.25
NE
A1
ND
0
0.20 REF
-
-
3
0.0230.05
L
e
E
0.45
2.90
b
D
A
0.20
2.90
0.70
0.50 BSC.
0.55
3.00
0.65
3.10
0.25
3.00
0.75
0.30
3.10
0.80
16
0.20 REF
0.25
-
0
4
0.02
4
-
0.05
0.50 BSC.
0.30
2.90
0.40
3.00
0.20
2.90
0.70
0.25
3.00
0.75
3.10
0.50
0.80
3.10
0.30
PKG
REF. MIN.
12L 3x3
NOM. MAX. NOM.
16L 3x3
MIN. MAX.
0.35 x 45∞
PIN ID
JEDEC
WEED-1
0.35 x 45∞ WEED-2
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
NOTES:
E
2
2
21-0136
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
T1233-3
1.10
1.25
0.95 1.10
0.35 x 45∞1.25 WEED-1
0.95
T1633F-3 0.65
T1633-4
0.95
0.80
0.95
0.65
0.80
1.10
1.25
0.95
1.10
0.225 x 45∞
0.95
WEED-2
0.35 x 45∞
1.25
WEED-2
T1633-2
0.95
1.10
1.25
0.95
1.10
0.35 x 45∞
1.25
WEED-2
NO
DOWN
BONDS
ALLOWED
YES
NO
YES
N/A
NO
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