MAXIM ZLR16300 User Manual

19-4622; Rev 0; 5/09

Crimzon® ZLR16300

Low-Voltage ROM MCUs

with Infrared Timers

Product Specification

Maxim Integrated Products Inc.

120 San Gabriel Drive, Sunnyvale CA 94086

Maxim Integrated Products 120 San Gabriel Drive Sunnyvale, CA 94086 United States

408-737-7600 www.maxim-ic.com

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Maxim for its use. Furthermore, the information contained herein does not convey to the purch aser of microelectronic devices any license under the patent right of any manufacturer.

Maxim is a registered trademark of Maxim Integrated Products, Inc.

All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders.

Z8 is a registered trademark of Zilog, Inc. Crimzon is a registered trademark of Universal Electronics Inc.

19-4622; Rev 0; 5/09

Revision History

Each instance in the Revision History table reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below.

Date

April 2009 19 Changed to Maxim product All

Crimzon® ZLR16300

Product Specification

iii

Revision Level Description Page No

February 2008

January 2008 17 Updated the Ordering Information section. 85 August

2007 February

2007 April

2006 December

2005

18 Updated the Ordering Information section.

16 Updated the Disclaimer section and implemented

style guide.

15 Updated Low-Voltage Detection.

14 Added pin P22 to the SMR block input, Figure 30.

13 Updated Input output port and Clock. 12, 47

All

19-4622; Rev 0; 5/09 Revision History

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . 54

Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . 60

Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Crimzon® ZLR16300

Product Specification

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

19-4622; Rev 0; 5/09 Table of Contents

Architectural Overview

Maxim’s Crimzon® ZLR16300 MCU is a ROM-based member of the Crimzon ZLR16300 family of general-purpose microcontrollers. With 1 KB to 16 KB of Program Memory and 237 B of general-purpose RAM, Maxim’s CMOS microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output (I/O) bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors.

The Crimzon ZLR16300 architecture (see Figure 1 on page 3 and Figure 2 on page 4) is based on Maxim’s 8-bit microcontroller core with an Expanded Register File allowing access to register-mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z8 structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery-operated hand-held applications.

core offers a flexible I/O scheme, an efficient register and address space

Crimzon® ZLR16300

Product Specification

Features

There are three basic address spaces available to support a wide range of configurations:

1. Program Memory

2. Register File

3. Expanded Register File The Register file is composed of 256 B of RAM. It includes three I/O port registers, 16

control and status registers, and 237 general-pu rpose registers. The Expanded Register file consists of two additional register groups (F and D).

To unburden the program from coping with such real-time problems like generating complex waveforms or receiving and demodulating complex waveform/pulses, the Crimzon ZLR16300 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see Figure 2 on page 4). Also included are a large number of user-selectable modes and two on-board comparators to process analog signals with separate reference voltages.

Table 1 lists the features of Crimzon ZLR16300 family.

Table 1. Crimzon ZLR16300 ROM MCU Features

Device ROM (KB) RAM* (Bytes) I/O Lines Voltage Range

Crimzon ZLR16300 1, 2, 4, 8, 16 237 24, 16 2.0–3.6 V

*General-purpose

19-4622; Rev 0; 5/09 Architectural Overview

Crimzon® ZLR16300

Product Specification

The additional features include:

•

Low power consumption–5 mW (typical)

•

Three standby modes:

–

STOP—1.3 A (typical)

–

HALT—0.5 mA (typical)

–

Low-voltage reset

•

Special architecture to automate both generation and reception of complex pulses or signals:

–

One programmable 8-bit counter/timer with two capture registers and two load registers

–

One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair

–

Programmable input glitch filter for pulse reception

•

Six priority interrupts

–

Three external

–

Two assigned to counter/timers

–

One low-voltage detection interrupt

•

Low-Voltage Detection and High-Voltage Detection Flags

•

Programmable Watchdog Timer (WDT)

•

Power-On Reset (POR)

•

Two independent comparators with programmable interrupt polarity

•

Selectable pull-up transistors on ports 0, 2, and 3

•

Mask options

–

Port 0: 0–3 pull-ups

–

Port 0: 4–7 pull-ups

–

Port 2: 0–7 pull-ups

–

Port 3: 0–3 pull-ups

–

Watchdog Timer at Power-On Reset

Power connections use the conventional descriptions listed in Table 2.

Table 2. Power Connections

Connection Circuit Device

Power V Ground GND V

19-4622; Rev 0; 5/09 Architectural Overview

DD SS

Functional Block Diagram

Z8® Core

Port 2

Port 0

P21 P22 P23 P24 P25 P26 P27

P20

I/O Bit

Programmable

P04 P05 P06 P07

P00 P01 P02 P03

I/O Nibble

Programmable

256 x 8-Bit

Internal

Address Bus

Internal

Data Bus

Expanded

File

Expanded

Core

Counter/Timer 8

8-Bit

Counter/Timer 16

16-Bit

XTAL

Pref1/P30 P31 P32 P33 P34 P35 P36 P37

Port 3

Machine Timing &

Instruction

Control

Power

ROM

Up to 16K x 8

Watchdog

Timer

Low-Voltage

Detection

High-Voltage

Detection

Power-On

Reset

Note: Refer to the specific package for available pins.

Figure 1 displays the Crimzon ZLR16300 MCU functional block diagram.

Crimzon® ZLR16300

Product Specification

Figure 1. Crimzon ZLR16300 MCU Functional Block Diagram

19-4622; Rev 0; 5/09 Architectural Overview

Crimzon® ZLR16300

HI16

LO16

16-Bit

T16

TC16H

TC16L

HI8 LO8

And/Or Logic

Clock Divider

Glitch Filter

Edge Detect Circuit

8-Bit T8

TC8H

TC8L

Input

SCLK

Timer 16

Timer 8/16

Timer 8

Product Specification

Figure 2. Counter/Timers Diagram

19-4622; Rev 0; 5/09 Architectural Overview

Pin Description

P25 P26 P27 P07 V

XTAL2 XTAL1

P31 P32 P33

P24 P23 P22 P21 P20 Vss P01 P00/Pref1/P30 P36 P34

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

20-Pin

DIP

SOIC

SSOP

The pin configuration for the 20-pin DIP/SOIC/SSOP is displayed in Figure 3 and described in Table 3. The pin configuration for the 28-pin DIP/SOIC/SSOP are displayed in Figure 4 on page 6 and described in Table 4 on page 6.

Crimzon® ZLR16300

Product Specification

Figure 3. 20-Pin DIP/SOIC/SSOP Pin Configuration

Table 3. 20-Pin DIP/SOIC/SSOP Pin Identification

Pin No Symbol Function Direction

1–3 P25–P27 Port 2, Bits 5,6,7 Input/Output 4 P07 Port 0, Bit 7 Input/Output 5V

6 XTAL2 Crystal Oscillator Clock Output 7 XTAL1 Crystal Oscillator Clock Input 8–10 P31–P33 Port 3, Bits 1,2,3 Input 11,12 P34, P36 Port 3, Bits 4,6 Output 13 P00/Pref1/P30 Port 0, Bit 0/Analog reference input

19-4622; Rev 0; 5/09 Pin Description

14 P01 Port 0, Bit 1 Input/Output 15 V 16–20 P20–P24 Port 2, Bits 0,1,2,3,4 Input/Output

Power Supply

Input/Output for P00

Port 3, Bit 0

Ground

Input for Pref1/P30

Crimzon® ZLR16300

P24 P23 P22 P21 P20 P03 V

P02 P01 P00 Pref1/P30 P36 P37 P35

P25 P26 P27 P04 P05 P06 P07 V

XTAL2 XTAL1

P31 P32 P33 P34

28-Pin

PDIP SOIC

SSOP

2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

Product Specification

Figure 4. 28-Pin DIP/SOIC/SSOP Pin Configuration

Table 4. 28-Pin DIP/SOIC/SSOP Pin Identification

Pin No Symbol Function Direction

1-3 P25-P27 Port 2, Bits 5,6,7 Input/Output 4-7 P04-P07 Port 0, Bits 4,5,6,7 Input/Output 8V

9 XTAL2 Crystal, oscillator clock Output 10 XTAL1 Crystal, oscillator clock Input 11–13 P31-P33 Port 3, Bits 1,2,3 Input 14 P34 Port 3, Bit 4 Output 15 P35 Port 3, Bit 5 Output 16 P37 Port 3, Bit 7 Output 17 P36 Port 3, Bit 6 Output 18 Pref1 Analog ref input; connect to V

19-21 P00-P02 Port 0, Bits 0,1,2 Input/Output 22 V 23 P03 Port 0, Bit 3 Input/Output 24-28 P20-P24 Port 2, Bits 0-4 Input/Output

19-4622; Rev 0; 5/09 Pin Description

Power supply

not used Port 3 Bit 0

Ground

Input

Pin Functions

Caution:

XTAL1 Crystal 1 (Time-Based Input)

This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. Additionally, an external single-phase clock can be connected to the on-chip oscillator input.

XTAL2 Crystal 2 (Time-Based Output)

This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output.

Input/Output Ports

Crimzon® ZLR16300

Product Specification

The CMOS input buffer for each ports 0, 1, or 2 pin is always connected to the pin, even when the pin is configured as an output. If the pin is configured as an open-drain output and no external signal is applied, a High output state causes the CMOS input buffer to float. This leads to excessive leakage current o f more than 10 0 A. T o pr event this leakage, connect the pin to an external signal with a defined logic level or ensure its output state is Low, especially during STOP mode.

Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode.

Port 0, 1, and 2 have both input and output capability. The input logic is always present no matter whether the port is configured as input or output. While performing a READ instruction, the MCU reads the actual value at the input logic but not from the output buffer. In addition, the instructions of OR, AND, and XOR have the Read-Modify-Write sequence. The MCU first reads the port, modifies the value, and loads back to the port.

Precaution must be taken if the port is configured as open-drain output or if the port is driving any circuit that makes the voltage different from the desired output logic. For example, pins P00–P07 are not connected to anything else. If it is configured as opendrain output with output logic as ONE, it is a floating port and reads back as ZERO. The following instruction sets P00-P07 all Low.

AND P0,#%F0

19-4622; Rev 0; 5/09 Pin Description

Crimzon® ZLR16300

Note:

ZLR16300

Port 0 (I/O)

Pad

Out

I/O

Open-Drain

Resistive Transistor Pull-up

Mask Option

Product Specification

Port 0 (P07–P00)

Port 0 is an 8-bit, bidirectional, and CMOS-compatible port. These eight I/O lines ar e configured under software control as a nibble I/O port. The output drivers are push-pull or open-drain controlled by bit D2 in the PCON register.

If one or both nibbles are required for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured (see Figure 5) as an input port.

An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select.

The Port 0 direction is reset to be input following an Stop Mode Recovery.

Figure 5. Port 0 Configuration

19-4622; Rev 0; 5/09 Pin Description

Crimzon® ZLR16300

Port 2 (I/O)

Pad

Out

I/O

Open-Drain

Resistive Transistor Pull-up

Mask Option

ZLR16300 ROM

Product Specification

Port 2 (P27–P20)

Port 2 is an 8-bit, bidirectional, and CMOS-compatible I/O port (see Figure 6). These eight I/O lines are independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option connects eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push-pull or open-drain. The POR resets with the eight bits of Port 2 configured as inputs.

Port 2 also has an 8-bit input OR and AND gate which can be used to wake up the part. P20 is programmed to access the edge-detection circuitry in DEMODULATION mode.

19-4622; Rev 0; 5/09 Pin Description

Figure 6. Port 2 Configuration

Crimzon® ZLR16300

Port 3 (I/O)

P32 (AN2)

P31 (AN1) Pref1

From Stop Mode Recovery Source of SMR

IRQ2, P31 Data Latch

Pref1/P30 P31

P32 P33

P34 P35

P36 P37

1 = Analog 0 = Digital

R247 = P3M

IRQ0, P32 Data Latch

IRQ1, P33 Data Latch

Comp1

Comp2

Dig.

An.

ZLR16300 ROM

P33 (REF2)

Product Specification

Port 3 (P37–P30)

Port 3 is an 8-bit, CMOS-compatible fixed I/O port (see Figure 7). Port 3 consists of four fixed input (P33–P30) and four fixed output (P37–P34), which are configured under software control for interrupt and as output from the counter/timers. P30, P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs.

19-4622; Rev 0; 5/09 Pin Description

Figure 7. Port 3 Configuration

Crimzon® ZLR16300

Note:

Product Specification

Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer edge-detection circuit is through P31 or P20 (see T8 and T16 Common Functions—CTR1(0D)01h on page 23). Other edge detect and IRQ modes are described in Table 5.

Comparators are powered down by entering STOP mode. For P31–P33 to be used in a SMR source, these inputs must be placed into DIGITAL mode.

Table 5. Port 3 Pin Function Summary

Pin I/O Counter/Timers Comparator Interrupt

Pref1/P30 IN RF1 P31 IN IN AN1 IRQ2 P32 IN AN2 IRQ0 P33 IN RF2 IRQ1 P34 OUT T8 AO1 P35 OUT T16 P36 OUT T8/16 P37 OUT AO2 P20 I/O IN

Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see

Figure 8). Control is performed by programming bits D5–D4 of CTR1, bit 0 of CTR0, and

bit 0 of CTR2.

19-4622; Rev 0; 5/09 Pin Description

Pad

P34

Comp1

MUX

PCON, D0

MUX

CTR0, D0

P31

P30 (Pref1)

P34 data

T8_Out

Pad

P35

MUX

CTR2, D0

Out 35

T16_Out

Pad

P36

MUX

CTR1, D6

Out 36

T8/T16_Out

Pad P37

MUX

PCON, D0

P37 data

P31

P3M D1

Comp2

P32

P33

P32

P3M D1

Crimzon® ZLR16300

Product Specification

Figure 8. Port 3 Counter/Timer Output Configuration

19-4622; Rev 0; 5/09 Pin Description

Crimzon® ZLR16300

Note:

Product Specification

Comparator Inputs

In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and P

. In this mode, the P33 internal data latch and its

REF1

corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as displayed in Figure 7 on page 10. In DIGITAL mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1.

Comparators are powered down by entering STOP mode. For P31–P33 to be used in a Stop Mode Recovery source, these inputs must be placed into DIGITAL mode.

Comparator Outputs

These channels are programmed to be output on P34 and P37 through the PCON register.

19-4622; Rev 0; 5/09 Pin Description

Functional Description

Crimzon® ZLR16300

Product Specification

The Crimzon ZLR16300 family of devices incorporate special functions to enhance the functionality of Z8

Program Memory

These devices address from 1 KB to 16 KB of Program Memory. The first 12 bytes are reserved for interrupt vectors. These locations contain the six 16-bit vectors that correspond to the six available interrupts. See Figure 9 on page 15.

in consumer and battery-operated applications.

19-4622; Rev 0; 5/09 Functional Description

RAM

On-Chip ROM

Reset Start Address

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ1 IRQ0

IRQ0

12 11

Maximum ROM Size

Location of first byte of instruction executed after RESET

Interrupt Vector (Lower Byte)

Interrupt Vector (Upper Byte)

Not Accessible

Crimzon® ZLR16300

Product Specification

The Crimzon ZLR16300 product family features 237 bytes of RAM.

Figure 9. Program Memory Map

19-4622; Rev 0; 5/09 Functional Description

Expanded Register File

Note:

The register file has been expanded to allow for additional system control registers and for mapping additional peripheral devices into the register address area. The Z8 register address space (0 through15 (OFh)) has been implemented as 16 banks, with 16 registers per bank. These register banks are known as the ERF (Expanded Register File). Bits 7–4 of register RP select the working register group. Bits 3–0 of register RP select the expanded register file bank.

An expanded register bank is also referr ed to as an expanded r egister gr oup (see Figure 10 on page 17).

Crimzon® ZLR16300

Product Specification

19-4622; Rev 0; 5/09 Functional Description

Crimzon® ZLR16300

UUUUUUU0

00000000 00000000

00000000

FF SPL

00000000

UUUUUUUU 00000000

UUUUUUUU

UUUUUUUU UUUUUUUU

11111111

00000000

11001111

UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU

FE SPH FD RP FC FLAGS FB IMR FA IRQ F9 IPR F8 P01M F7 P3M F6 P2M F5 Reserved F4 Reserved F3 Reserved F2 Reserved F1 Reserved F0 Reserved

D7D6D5 D4 D3D2 D1 D0

UU001101

U01000U0

11111110

(F) 0F WDTMR (F) 0E Reserved (F) 0D SMR2 (F) 0C Reserved (F) 0B SMR (F) 0A Reserved (F) 09 Reserved (F) 08 Reserved (F) 07 Reserved (F) 06 Reserved (F) 05 Reserved (F) 04 Reserved (F) 03 Reserved (F) 02 Reserved (F) 01 Reserved (F) 00 PCON

76543210

Expanded Register Bank Pointer

Working Register

UUUUUUUU

00000000

(D) 0C LVD (D) 0B HI8 (D) 0A LO8 (D) 09 HI16 (D) 08 LO16 (D) 07 TC16H (D) 06 TC16L (D) 05 TC8H (D) 04 TC8L (D) 03 CTR3 (D) 02 CTR2 (D) 01 CTR1 (D) 00 CTR0

Group Pointer

00011111

* *

00000000

00000000 00000000 00000000 00000000

U = Unknown. *Is not reset with a Stop Mode Recovery.

**All addresses are in hexadecimal.



Is not reset with a Stop Mode Recovery, except Bit 0.



Bit 5 is not reset with a Stop Mode Recovery.



Bits 5,4,3,2 not reset with a Stop Mode Recovery.



Bits 5 and 4 not reset with a Stop Mode Recovery.



Bits 5,4,3,2,1 not reset with a Stop Mode Recovery.

Expanded Reg. Bank 0/Group (0)

(0) 03 P3 (0) 02 P2









* * *

* * * *

Expanded Reg. Bank F/Group 0**

Z8 Standard Control Registers

Expanded Reg. Bank D/Group 0



Reset Condition

(0) 00 P0

Reserved

NOTE: A write has no effect. Will always read back FF.

NOTE

Product Specification

19-4622; Rev 0; 5/09 Functional Description

Figure 10. Expanded Register File Architecture

Crimzon® ZLR16300

Product Specification

The upper nibble of the register pointer (see Figure 11) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and in the case of the Crimzon ZLR16300 family, banks 0, F, and D are implemented. A file (bank 0) to be addressed. Any other value from

0h in the lower nibble allows the normal register

1h to Fh exchanges the lower 16 reg-

isters to the selected expanded register bank.

R253 RP D7 D6 D5 D4 D3 D2 D1 D0

Expanded Register File Pointer

Working Register

Default Setting After Reset = 0000 0000

Pointer

Figure 11. Register Pointer

Example: (See Figure 10 on page 17) R253 RP = 00h

R0 = Port 0 R2 = Port 2 R3 = Port 3

But if:

R253 RP = 0Dh R0 = CTR0 R1 = CTR1 R2 = CTR2 R3 = CTR3

The counter/timers are mapped into ERF group D. Access is easily performed using the following:

LD RP, #0Dh ;Select ERF D

for access to

bank D ;(working register group

LD R0,#xx ;load CTR0

19-4622; Rev 0; 5/09 Functional Description

Crimzon® ZLR16300

Note:

Product Specification

LD 1, #xx ;load CTR1 LD R1, 2 ;CTR2CTR1

LD RP, #0Dh ;Select ERF D

for access to bank D ; (working register group

LD RP, #7Dh ;Select

expanded register bank D and working ;register group 7 of bank 0 for access.

LD 71h, 2

;CTRL2register 71h LD R1, 2 ;CTRL2register 71h

Register File

The Register file (bank 0) consists of three I/O port registers, 237 general-purpose registers, 16 control and status registers (R0, R2, R3, R4–R239, and R2 40–R255, respectively), and two expanded register Banks D (see Table 6 on page 22) and F . Instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4bit register address to use the Register Pointer (see Figure 12 on page 20). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group.

19-4622; Rev 0; 5/09 Functional Description

Crimzon® ZLR16300

R7R6R5R4R3R2R1R

The upper nibble of the register file addr es s provided by the register pointer specifies the active working-register group.

Specified Working

R253

The lower nibble of the register file address provided by the instruction points to the specified register.

* RP = 00: Selects Register Bank 0, Working Register Group 0

R15 to R0 R15 to R4 *

R3 to R0 *

40 3F

30 2F

20 1F

10 0F

FF F0

Product Specification

Figure 12. Register Pointer—Detail

Stack

The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used for the internal stack that resides in the general-purpose registers (R4–R239). SPH (R254) is used as a general-purpose register.

Timers

T8_Capture_HI—HI8(0D)0Bh

This register stores the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 1.

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Field Bit Position Description

T8_Capture_HI [7:0] R/W Captured Data—No Effect

Crimzon® ZLR16300

Product Specification

T8_Capture_LO—L08(0D)0Ah

This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 0.

Field Bit Position Description

T8_Capture_L0 [7:0] R/W Captured Data—No Effect

T16_Capture_HI—HI16(0D)09h

This register holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the MS-Byte of the data.

Field Bit Position Description

T16_Capture_HI [7:0] R/W Captured Data—No Effect

T16_Capture_LO—L016(0D)08h

This register holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the LS-Byte of the data.

Field Bit Position Description

T16_Capture_LO [7:0] R/W Captured Data—No Effect

Counter/Timer2 MS-Byte Hold Register—TC16H(0D)07h

Field Bit Position Description

T16_Data_HI [7:0] R/W Data

Counter/Timer2 LS-Byte Hold Register—TC16L(0D)06h

Field Bit Position Description

T16_Data_LO [7:0] R/W Data

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Counter/Timer8 High Hold Register—TC8H0(D)05h

Field Bit Position Description

T8_Level_HI [7:0] R/W Data

Counter/Timer8 Low Hold Register—TC8L(0D)04h

Field Bit Position Description

T8_Level_LO [7:0] R/W Data

CTR0 Counter/Timer8 Control Register—CTR0(0D)00h

Crimzon® ZLR16300

Product Specification

Table 6 lists and briefly describes the fields for this register.

Table 6. CTR0(0D)00h Counter/Timer8 Control Register

Field Bit Position Value Description

T8_Enable 7------- R/W 0*

1 0 1

Single/Modulo-N -6------- R/W 0*

Time_Out --5------ R/W 0**

1 0 1

T8 _Clock ---43--- R/W 0 0**

0 1 1 0 1 1

Capture_INT_Mask -----2-- R/W 0**

Counter Disabled Counter Enabled Stop Counter Enable Counter

Modulo-N Single-Pass

No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0

SCLK SCLK/2 SCLK/4 SCLK/8

Disable Data Capture Interrupt Enable Data Capture Interrupt

Counter_INT_Mask ------1- R/W 0**

P34_Out -------0 R/W 0*

*Indicates the value at Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.

19-4622; Rev 0; 5/09 Functional Description

Disable Time-Out Interrupt Enable Time-Out Interrupt

P34 as Port Output T8 Output on P34

Crimzon® ZLR16300

Caution:

Note:

Product Specification

T8 Enable

This field enables T8 when set to 1.

Single/Modulo-N

When set to 0 (MODULO-N), the counter reloads the initial value when the terminal count is reached. When set to 1 (Single-Pass), the counter stops when the terminal count is reached.

Timeout

This bit is set when T8 times out (terminal count reached). T o r eset this bit, write a 1 to its location.

Writing a 1 is the only way to reset the Terminal Count status condition. Reset this bit before using/enabling the counter/timers.

The first clock of T8 might not have complete clock width and can occur any time when enabled.

Ensure to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (DEMODULATION mode) while using the OR or AND commands. These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers.

T8 Clock

These bits define the frequency of the input signal to T8.

Capture_INT_Mask

Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in CAPTURE Mode.

Counter_INT_Mask

Set this bit to allow an interrupt when T8 has a timeout.

P34_Out

This bit defines whether P34 is used as a normal output pin or the T8 output.

T8 and T16 Common Functions—CTR1(0D)01h

This register controls the functions common with the T8 and T16.

Table 7 lists and briefly describes the fields for this register.

19-4622; Rev 0; 5/09 Functional Description

Product Specification

Table 7. CTR1(0D)01h T8 and T16 Common Functions

Field Bit Position Value Description

Mode 7------- R/W 0*

P36_Out/ Capture_Input

T8/T16_Logic/ Edge _Detect

Transmit_Submode/ Glitch_Filter

Initial_T8_Out/ Rising Edge

-6------ R/W

--54---- R/W

----32-- R/W

------1-

R/W

R W

0* 1

00** 01 10 11

00 01 10 11

0 1

0 1 0 1

TRANSMIT Mode DEMODULATION Mode

TRANSMIT Mode Port Output T8/T16 Output DEMODULATION Mode P31 P20

TRANSMIT Mode AND OR NOR NAND DEMODULATION Mode Falling Edge Rising Edge Both Edges Reserved

TRANSMIT Mode Normal Operation PING-PONG Mode T16_Out = 0 T16_Out = 1 DEMODULATION Mode No Filter 4 SCLK Cycle 8 SCLK Cycle Reserved

TRANSMIT Mode T8_OUT is 0 Initially T8_OUT is 1 Initially DEMODULATION Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0

Crimzon® ZLR16300

19-4622; Rev 0; 5/09 Functional Description

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