19-0255; Rev 2; 4/94
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________General Description
The MAX154/MAX158 and MX7824/MX7828 are highspeed, multi-channel analog-to-digital converters
(ADCs). The MAX154 and MX7824 have four analog
input channels, while the MAX158 and MX7828 have
eight channels. Conversion time for all devices is 2.5µs.
The MAX154/MAX158 also feature a 2.5V on-chip reference, forming a complete high-speed data acquisition
system.
All four converters include a built-in track/hold, eliminating the need for an external track/hold with many input
signals. The analog input range is 0V to +5V, although
the ADC operates from a single +5V supply.
Microprocessor interfaces are simplified by the ADC’s
ability to appear as a memory location or I/O port without
the need for external logic. The data outputs use latched,
three-state buffer circuitry to allow direct connection to a
microprocessor data bus or system input port.
The MX7824 and MX7828 are pin compatible with
Analog Devices’ AD7824 and AD7828. The MAX154
and MAX158, which feature internal references, are also
compatible with these products.
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
High-Speed Servo Control
Audio Instrumentation
____________________________Features
♦ One-Chip Data Acquisition System
♦ Four or Eight Analog Input Channels
♦ 2.5µs per Channel Conversion Time
♦ Internal 2.5V Reference (MAX154/MAX158 only)
♦ Built-In Track/Hold Function
1
LSB Error Specification
/
♦
2
♦ Single +5V Supply Operation
♦ No External Clock
♦ New Space-Saving SSOP Package
______________Ordering Information
PART
MX7824LN
MX7824KN
MX7824LCWG 0°C to +70°C
MX7824KCWG
MX7824LCAG
MX7824KCAG 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
0°C to +70°C
0°C to +70°C
24 Narrow
Plastic DIP
24 Narrow
Plastic DIP
24 Wide SO
0°C to +70°C 24 Wide SO
0°C to +70°C
24 SSOP
24 SSOP
Ordering Information continued on last page.
ERROR
(LSB)
1
±
/
±1
1
±
/
±1
1
/
±
±1
__________________________________________________________Pin Configurations
MX7824/MX7828
2
2
2
TOP VIEW
AIN4
1
AIN3
2
AIN2
3
AIN1
4
TP (REF OUT)
DB0
DB1
DB2
DB3
GND
( ) ARE FOR MAX154/MAX158 ONLY.
5
6
7
8
9
RD
10
INT
11
12
MAX154
MX7824
DIP/SO/SSOP
V
DD
24
NC
23
A0
22
A1
21
DB7
20
DB6
19
DB5
18
DB4
17
CS
16
RDY
15
+
V
14
REF
V
-
13
REF
________________________________________________________________
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
TP (REF OUT)
DB0
DB1
DB2
DB3
GND
1
2
3
4
5
6
7
8
9
10
11
RD
12
INT
13
14
MAX158
MX7828
DIP/SO/SSOP
Maxim Integrated Products
Call toll free 1-800-998-8800 for free samples or literature.
AIN7
28
AIN8
27
V
26
DD
A0
25
A1
24
A2
23
DB7
22
DB6
21
DB5
20
DB4
19
CS
18
RDY
17
V
+
16
REF
V
-
15
REF
1
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD to GND........................................0V, +10V
Voltage at Any Other Pins......................GND - 0.3V, V
Output Current (REF OUT)..................................................30mA
Power Dissipation (any package) to +75°C ....................450mW
Derate above +25°C by..............................................6mW/°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DD
+ 0.3V
ELECTRICAL CHARACTERISTICS
(VDD= +5V, V
MX7824/MX7828
ACCURACY
Resolution 8 Bits
Total Unadjusted Error (Note 1)
No Missing Codes Resolution 8 Bits
Channel to Channel Mismatch ±1/4 LSB
REFERENCE INPUT
Reference Resistance 14kΩ
V
+ Input Voltage Range V
REF
V
- Input Voltage Range GND V
REF
REFERENCE OUTPUT—MAX154/MAX158 Only (Note 2)
Output Voltage REF OUT 2.47 2.50 2.53 V
Load Regulation -6 -10 mV
Power-Supply Sensitivity ±1 ±3 mV
Output Noise e
Capacitive Load 0.01 µF
ANALOG INPUT
Analog Input Voltage Range A
Analog Input Capacitance C
Analog Input Current I
Slew Rate, Tracking SR 0.7 0.157 V/µs
LOGIC INPUTS (–R—D–, –C—S–, A0, A1, A2)
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
Input Capacitance (Note 4) C
+ = +5V, V
REF
PARAMETER SYMBOL MIN TYP MAX UNITS
- = GND, Mode 0, TA= T
REF
N
INR
AIN
AIN
INH
INL
INH
INL
IN
MIN
MAX15_A, MX782_L/C/U
TA= +25°C
IL= 0mA to 10mA, TA= +25°C
VDD±5%, TA= +25°C
MAX15_C
MAX15_E
MAX15_M
Any channel, AIN = 0V to 5V
Operating Temperature Ranges
MX7824, MX7828
KN/LN/KCW_/LCW_............................................0°C to +70°C
BQ/CQ .............................................................-40°C to +85°C
TQ/UQ............................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
to T
, unless otherwise noted.)
MAX
CONDITIONS
-VDDV
REF
40 70
40 70Temperature Drift (Note 3)
60 100
200 µV/rms
V
-V
REF
2.4 V
45 pF
58pF
±1/2
±1MAX15_B, MX782_K/B/T
+ V
REF
ppm/°C
+ V
REF
±3 µA
0.8 V
1 µA
-1 µA
LSB
2 _______________________________________________________________________________________
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
ELECTRICAL CHARACTERISTICS
(VDD= +5V, V
LOGIC OUTPUTS
Output High Voltage
Output Low Voltage
Output Capacitance (Note 4)
POWER SUPPLY
Supply Voltage
Supply Current
Note 1: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 2: Specified with no external load unless otherwise noted.
Note 3: Temperature drift is defined as change in output voltage from +25°C to T
Note 4: Guaranteed by design.
+ = +5V, V
REF
- = GND, Mode 0, TA= T
REF
DB0–DB7, –I—N—T–; I
OH
DB0–DB7, –I—N—T–; RDY
V
OL
DB0–DB7, RDY; V
OUT
5V ±5% for specified performance
DD
–C—S–= –R—D–
DD
VDD= ±5%
MIN
= 2.4V
to T
, unless otherwise noted.)
MAX
CONDITIONS
= -360µA
OUT
I
= 1.6mA
OUT
I
= 2.6mA
OUT
= 0V to V
OUT
DD
MIN
or T
MAX
divided by (25 - T
MIN
TIMING CHARACTERISTICS (Note 5)
(VDD= +5V, V
–C—S–
to –R—D–Setup Time
–C—S–
to –R—D–Hold Time
Multiplexer Address
Setup Time
Multiplexer Address
Hold Time
–C—S–
to RDY Delay
Conversion Time (Mode 0)
Data Access Time After –R—D
Data Access Time
After –I—N—T–, Mode 0
–R—D–
to –I—N—T–Delay (Mode 1)
Data Hold Time
Delay Time
Between Conversions
–R—D–
Pulse Width (Mode 1)
Note 5: All input control signals are specified with t
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
+ = +5V, V
REF
- = GND, Mode 0, TA= T
REF
SYMBOLPARAMETER
t
CSS
t
CSH
t
AS
t
AH
t
t
–
t
ACC1
t
ACC2
t
CL= 50pF, RL= 5kΩ
RDY
CRD
(Note 6)
(Note 6)
CL= 50pF
INTH
(Note 7)
t
DH
t
P
t
RD
to T
MIN
CONDITIONS
, unless otherwise noted.)
MAX
TA= +25°C
MAX15_ _C/E
MX782_K/L/B/C
MAX15_ _M
MX782_T/U
MIN MAX MIN MAXMIN TYP MAX
0
0
0
30
30 40
1.6 2.0
20 50
40 75
500
60 600
= tF= 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
R
0
0
0
35
60
2.4
85
110
60
100
60
70
500
80 500 80 400
0
0
0
40
600
0.4
0.4
) or (T
60
2.8
120
70
100
70
MAX
MX7824/MX7828
UNITSMIN TYP MAXSYMBOLPARAMETER
V4.0V
V
µA±3Three-State Output Current
pF58C
V4.75 5.25V
mA15I
mW25 75Power Dissipation
LSB±1/16 ±1/4PSSPower-Supply Sensitivity
- 25).
UNITS
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
_______________________________________________________________________________________ 3
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
REFERENCE TEMPERATURE
DRIFT (MAX154/MAX158 ONLY)
2.520
2.510
2.500
REF OUT VOLTAGE (V)
2.490
MX7824/MX7828
2.480
-50 150
050
AMBIENT TEMPERATURE (°C)
LINEARITY ERROR (LSB)
100
ACCURACY vs. V
(V
2.0
1.5
1.0
0.5
0
REF
05
OUTPUT CURRENT
20
MX7824/28-1
16
12
8
OUTPUT CURRENT (mA)
4
0
= V
REF
+ - V
REF
REF
3412
V
(V)
REF
vs. TEMPERATURE
VDD = 5V
I
I
SINK VOUT
-100 150
-50 0 50
AMBIENT TEMPERATURE (°C)
-)
V
= 5V
DD
MX7824/28-4
SOURCE VOUT
= 0.4V
ACCURACY vs. DELAY BETWEEN
2.0
MX7824/28-2
= 2.4V
100
POWER-SUPPLY CURRENT vs. TEMPERATURE
(NOT INCLUDING REFERENCE LADDER)
8
7
6
5
4
– SUPPLY CURRENT (mA)
DD
I
3
2
-100 150
1.5
1.0
LINEARITY ERROR (LSB)
0.5
0
V
= 4.75V
DD
AMBIENT TEMPERATURE (°C)
CONVERSIONS (tp)
300 900
V
= 5.25V
DD
V
50 100-50 0
V
= 5V
DD
V
REF
700 800400 500 600
tp (ns)
MX7824/28-5
= 5V
DD
= 5V
MX7824/28-3
+5V
3k
DBN
3k
100pF
DGND
a. High-Z to V
Figure 1. Load Circuits for Data-Access Time Test
OH
DBN
100pF
b. High-Z to V
DGND
DBN
3k
10pF
DBN
DGND
OL
a. V
High-Z b. V
OH to
Figure 2. Load Circuits for Data-Hold Time Test
4 _______________________________________________________________________________________
+5V
OL to
3k
10pF
DGND
High-Z
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_____________________________________________________________Pin Descriptions
PIN
MAX154
MX7824
5
10
16
24
REF OUT
TP
–R—D–
INT11
V
REF
V
+14
REF
RDY15
–C—S–
DD
FUNCTIONNAME
Analog Input Channel 4AIN41
Analog Input Channel 3AIN32
Analog Input Channel 2AIN23
Analog Input Channel 1AIN14
Reference Output (2.5V) for MAX154.
Test point for MX7824. Do not connect.
Three-State Data Output, bit 0 (LSB)DBO6
Three-State Data Output, bit 1DB17
Three-State Data Output, bit 2DB28
Three-State Data Output, bit 3DB39
Read Input. –R—D–controls conversions
and data access. See
section.
Interrupt Output. INT going low indicates the completion of a conversion.
See
Digital Interface
GroundGND12
Lower Limit of Reference Span. Sets
the zero-code voltage.
-13
Range: GND to V
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: V
Ready Output. Open-drain output with
no active pull-up device. Goes low
when –C—S–goes low and high impedance at the end of a conversion.
Chip-Select Input. –C—S–must be low for
the device to be selected.
Three-State Data Output, bit 4DB417
Three-State Data Output, bit 5DB518
Three-State Data Output, bit 6DB619
Three-State Data Output, bit 7 (MSB)DB720
Channel Address 1 InputA121
Channel Address 0 InputA022
No ConnectNC23
Power-Supply Voltage, +5VV
REF
REF
- to VDD.
Digital Interface
section.
+.
PIN
MAX158
MX7828
7
12
18
26
REF OUT
TP
–R—D–
INT13
V
REF
V
+16
REF
RDY17
–C—S–
DD
FUNCTIONNAME
Analog Input Channel 6AIN61
Analog Input Channel 5AIN52
Analog Input Channel 4AIN43
Analog Input Channel 3AIN34
Analog Input Channel 2AIN25
Analog Input Channel 1AIN16
Reference Output (2.5V) for MAX158.
Test point for MX7828. Do not connect.
Three-State Data Output, bit 0 (LSB)DB08
Three-State Data Output, bit 1DB19
Three-State Data Output, bit 2DB210
Three-State Data Output, bit 3DB311
Read Input.–R—D–controls conversions
and data access. See
section.
Interrupt Output. INT going low indicates the completion of a conversion.
See
Digital Interface
GroundGND14
Lower Limit of Reference Span. Sets
the zero-code voltage.
-15
Range: GND to V
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: V
Ready Output. Open-drain output with
no active pull-up device. Goes low
when –C—S–goes low and high impedance at the end of a conversion.
Chip-Select Input. –C—S–must be low for
the device to be selected.
Three-State Data Output, bit 4DB419
Three-State Data Output, bit 5DB520
Three-State Data Output, bit 6DB621
Three-State Data Output, bit 7 (MSB)DB722
Channel Address 2 InputA223
Channel Address 1 InputA124
Channel Address 0 InputA025
Power-Supply Voltage, +5VV
Analog Input Channel 8AIN827
Analog Input Channel 7AIN728
REF
- to V
Digital Interface
section.
+.
REF
.
DD
MX7824/MX7828
_______________________________________________________________________________________ 5
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________Detailed Description
The MAX154/MAX158 and MX7824/MX7828 use what is
commonly called a “half-flash” conversion technique
(Figure 3). Two 4-bit flash ADC sections are used to
achieve an 8-bit result. Using 15 comparators, the
upper 4-bit MS (most significant) flash ADC compares
the unknown input voltage to the reference ladder and
provides the upper four data bits.
An internal DAC uses the MS bits to generate an analog
signal from the first flash conversion. A residue voltage
representing the difference between the unknown input
and the DAC voltage is then compared to the reference
ladder by 15 LS (least significant) flash comparators to
obtain the lower four output bits.
MX7824/MX7828
The operating sequence is shown in Figure 4. A conversion is initiated by a falling edge of RD and CS. The
comparator inputs track the analog input voltage for
approximately 1µs. After this first cycle, the MS flash
result is latched into the output buffers and the LS conversion begins. INT goes low approximately 600ns
later, indicating the end of the conversion, and that the
lower four bits are latched into the output buffers. The
data can then be accessed using the CS and RD
inputs.
V
+
REF
V
-
REF
AIN1
Converter Operation
Operating Sequence
___________________Digital Interface
The MAX154/MAX158 and MX7824/MX7828 use only
Chip Select (CS) and Read (RD) as control inputs. A
READ operation, taking CS and RD low, latches the multiplexer address inputs and starts a conversion (Table 1).
Table 1. Truth Table for Input Channel
Selection
MAX154/MX7824
A1 A0
00
01
10
11
There are two interface modes, which are determined
by the length of the RD input. Mode 0, implemented by
keeping RD low until the conversion ends, is designed
for microprocessors that can be forced into a WAIT
state. In this mode, a conversion is started with a READ
operation (taking CS and RD low), and data is read
when the conversion ends. Mode 1, on the other hand,
4-BIT
FLASH
ADC
(4MSB)
MAX158/MX7828
A2 A1 A0
000
001
010
011
100
101
110
111
SELECTED
CHANNEL
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
DB7
DB6
DB5
DB4
AIN4
AIN8
REF OUT**
*MAX154/MX7824 – 4-Channel Mux
MAX158/MX7828 – 8-Channel Mux
** REF OUT on MAX154/MAX158 only
Figure 3. Functional Diagram
6 _______________________________________________________________________________________
2.5V
REF
MUX*
ADDRESS
LATCH
DECODE
A0
A1 A2
V
REF
16
4-BIT
DAC
+
4-BIT
FLASH
ADC
(4LSB)
TIMING AND CONTROL
CIRCUITRY
RDY CS RD
THREE-
STATE
DRIVERS
DB3
DB2
DB1
DB0
INT
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
INT GOING LOW
RD
500ns
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
V
IN
BY INTERNAL
COMPARATORS
1000ns
IS TRACKED
600ns
IS SAMPLED
V
IN
AND THE FOUR MSBs
ARE LATCHED
INDICATES THAT
CONVERSION IS
COMPLETE AND
THAT DATA CAN
BE READ
Figure 4. Operating Sequence
does not require microprocessor WAIT states. A READ
operation simultaneously initiates a conversion and
reads the previous conversion result.
Interface Mode 0
Figure 5 shows the timing diagram for Mode 0 operation. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extended to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
CS
There are two status outputs: Interrupt (INT
) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the RDY
output is not required, its external pull-up resistor can be
omitted. INT goes low when the conversion is complete
and returns high on the rising edge of CSor RD.
Interface Mode 1
Mode 1 is designed for applications where the microprocessor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous conversion is immediately read from the outputs (DB0–DB7).
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ operation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
MX7824/MX7828
t
RD
ANALOG
CHANNEL
ADDRESS
RDY
INT
DATA
CSS
t
AS
ADDR
VALID
Figure 5. Mode 0 Timing Diagram
_______________________________________________________________________________________ 7
t
AH
t
RDY
HIGH IMPEDANCE
t
CSH
t
INTH
t
CRD
t
ACC2
DATA
VALID
t
DH
t
CSS
t
P
t
AS
ADDR
VALID
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
CS
t
CSS
RD
t
AS
ANALOG
CHANNEL
ADDRESS
RDY
MX7824/MX7828
INT
DATA
ADDR
VALID
t
RDY
t
AH
t
ACCI
t
RD
t
CRD
t
INTH
OLD
DATA
Figure 6. Mode 1 Timing Diagram
_____________Analog Considerations
The V
REF
+ and V
R
E
F
zero and the full-scale of the ADC. In other words, the
voltage at V
- is equal to the input voltage that pro-
REF
duces an output code of all zeros, and the voltage at
V
+ is equal to input voltage that produces an output
REF
code of all ones (Figure 7).
Figure 8 shows some possible reference configura-
tions. For the MAX154/MAX158, a 0.01µF bypass
capacitor to GND should be used to reduce the highfrequency output impedance of the internal reference.
Larger capacitors should not be used, as this degrades
the stability of the reference buffer. The 2.5V reference
output is with respect to the GND pin.
A 47µF electrolytic and 0.1µF ceramic capacitor should
be used to bypass the VDDpin to GND. These capacitors must have minimum lead length, since excess lead
length may contribute to conversion errors and instability.
If the reference inputs are driven by long lines, they
should be bypassed to GND with 0.1µF capacitors at
the reference input pins.
Reference and Input
- inputs of the converter define the
Bypassing
NEW
DATA
FULL-SCALE
TRANSITION
t
CSH
t
INTH
t
DH
+ - V
-
REF
REF
+
V
REF
FS
FS–1LSB
t
t
CSS
CSH
t
P
t
AS
t
DH
OUTPUT
CODE
11111111
11111110
11111101
00000011
00000010
00000001
00000000
V
REF
1
-
23
ADDR
VALID
t
RDY
t
ACCI
t
AH
t
RD
1LSB = F8 = V
256 256
AIN INPUT VOLTAGE
(IN TERMS OF LSBs)
Figure 7. Transfer Function
8 _______________________________________________________________________________________
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
(+)
+5V
0.1µF47µF
AIN
x
(-)
AIN
x
0.01µF
V
IN
GND
V
DD
REF OUT
V
+
REF
V
-
REF
MAX154
MAX158
Figure 8a. Internal Reference (MAX154/MAX158 only)
(+)
+5V
0.1µF
47µF
AIN
AINx(-)
x
MX584
2.5V
V
GND
V
V
V
IN
MX7824
DD
MX7828
+
REF
-
REF
Figure 8b. External Reference +2.5V Full-Scale
(+)
+5V
0.1µF
47µF
AIN
AINx(-)
x
V
GND
V
V
V
IN
MAX154
DD
MAX158
MX7824
+
REF
MX7828
-
REF
Figure 8c. Power Supply as Reference
* Current path must
still exist from
to Ground
V
IN(-)
+5V
0.1µF47µF
(+)
AIN
x
2.5V
(-)
AIN
x
*
V
IN
GND
V
DD
V
+
REF
V
-
REF
MAX154
MAX158
MX7824
MX7828
The converters’ analog inputs behave somewhat differ-
Input Current
ently from conventional ADCs. The sampled data comparators take varying amounts of current from the input,
depending on the cycle they are in. The equivalent circuit of the converter is shown in Figure 9a. When the
conversion starts, AIN(n) is connected to the MS and
LS comparators. Thus, AIN(n) is connected to thirty-one
1pF capacitors.
To acquire the input signal in approximately 1µs, the
input capacitors must charge to the input voltage
through the on-resistance of the multiplexer (about
600Ω) and the comparator’s analog switches (2kΩ to
5kΩ per comparator). In addition, about 12pF of stray
capacitance must be charged. The input can be modeled as an equivalent RC network shown in Figure 9b.
As RS(source impedance) increases, the capacitors
take longer to charge.
Since the length of the input acquisition time is internally set, large source resistances (greater than 100Ω) will
cause settling errors. The output impedance of an opamp is its open-loop output impedance divided by the
loop gain at the frequency of interest. It is important
that the amplifier driving the converter input have sufficient loop gain at approximately 1MHz to maintain low
output impedance.
Input Filtering
The transients in the analog input caused by the sampled data comparators do not degrade the converter’s
performance, since the ADC does not “look” at the
input when these transients occur. The comparator’s
outputs track the input during the first 1µs of the conversion, and are then latched. Therefore, at least 1µs
will be provided to charge the ADC’s input capacitance. It is not necessary to filter these transients with
an external capacitor on the AIN terminals.
Sinusoidal Inputs
The MAX154/MAX158 and MX7824/MX7828 can measure input signals with slew rates as high as 157mV/µs
to the rated specifications. This means that the analog
input frequency can be as high as 10kHz without the
aid of an external track/hold. The maximum sampling
rate is limited by the conversion time (typical t
CRD
2µs) plus the time required between conversions (tp=
500ns). It is calculated as:
f
MAX
1
=
t
+ tp(2.0 + 0.5) µs
CRD
=
1 =400kHz
MX7824/MX7828
=
Figure 8d. Inputs Not Referenced to GND
_______________________________________________________________________________________ 9
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
f
permits a maximum sampling rate of 50kHz per
MAX
channel when using the MAX158/MX7828 and 100kHz
per channel when using the MAX154/MX7824. These
rates are well above the Nyquist requirement of 20kHz
sampling rate for a 10kHz input bandwidth.
Bipolar Input Operation
The circuit in Figure 10a can be used for bipolar input
operation. The input voltage is scaled by an amplifier so
11.5Ω
V
IN
10.0k
0.01µF
that only positive voltages appear at the ADC’s inputs.
An external reference should be used for the MX7824/
MX7828, but is not needed with the MAX154/MAX158.
The analog input range is ±4V and the output code is
complementary offset binary. The ideal input/output
characteristic is shown in Figure 10b.
MX7824/MX7828
C
S
2pF
R
12pF
MUX
R
ON
TO LS
LADDER
R
ON
TO MS
LADDER
R
S
AIN1
V
IN
Figure 9a. Equivalent Input Circuit
AIN1
C
2pF
B MUX
600Ω
S1
R
S
V
IN
1pF
•
•
•
15 LSB COMPARATORS
1pF
•
•
•
16 MSB COMPARATORS
R
ON
350Ω
C
S2
2pF
1pFCS
1pF
32pF
ONLY CHANNEL 1 SHOWN
Figure 10a. Bipolar ±4V Input Operation
11111111
11111110
11111101
10000010
10000001
10000000
01111111
01111110
00000010
00000001
00000000
+5V
0.1µF
-FS
2
+ 1LSB
16.2k
47µF
3.57k
0.01µF
AIN1
MAX154
MAX158
+
V
REF
REF OUT
V
DD
V
-
REF
GND
FS = 8V
1LSB = FS / 256
RDY
DB0–DB7
CS
RD
INT
+FS
2
0V
AIN INPUT VOLTAGE (LSBs)
Figure 9b. RC Network Model
Figure 10b. Transfer Function for ±4V Input Operation
10 ______________________________________________________________________________________
A15
A0
MREQ
ZBO
WAIT
D0–D7
*A2 ON MAX158/MX7828 ONLY.
EN
5V
5k
RD
ADDRESS BUS
ADDRESS
DECODE
DATA BUS
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
+5V
26
V
DD
6
AIN1 CS
5
AIN2
MAX158
MX7828
28
AIN7
27
AIN8
16
V
REF+
V
REF-
15 14
DB0–DB7
GND
18
12
RD
DATA
23
A2
24
A1
25
A0
CS
RDY
RD
DB0–DB7
A1 A2*A0
MAX154
MAX158
MX7824
MX7828
SPEECH
INPUT
AMP
BANDPASS
FILTER 1
BANDPASS
FILTER 2
BANDPASS
FILTER 7
BANDPASS
FILTER 8
+5V
MX7824/MX7828
Figure 11. Simple Mode 0 Interface
+5V
4
3
2
1
14
13
12
24 16 10
V
DD
AIN1
AIN2
AIN3
AIN4
V
REF+
V
REF-
GND
CS
MAX154
MX7824
A0
A1
RD
INT
DB0–DB7
A1
A0
Figure 13. 4-Channel Fast Sample and Infinite Hold
______________________________________________________________________________________ 11
Figure 12. Speech Analysis Using Real-Time Filtering
SAMPLE
PULSE
11
21
22
15
16
17
WR
DB0–DB7
A1
A0
+15V
V
MX7226
V
18
DD
4
V
REF
2
A
V
OUT
1
B
V
OUT
20
V
C
OUT
19
V
D
OUT
6
DGND
5
AGND
SS
3
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
___________________Chip Topography_Ordering Information (continued)
PART
PIN-PACKAGETEMP. RANGE
24 SSOP-40°C to +85°CMX7824LEAG
MX7824CQ
MX7824BQ
-40°C to +85°C
-40°C to +85°C
-55°C to +125°CMX7824UQ
MX7824TQ
MX7828LN
0°C to +70°C
0°C to +70°CMX7828KN
MX7828LCWI
MX7828KCWI
MX7824/MX7828
0°C to +70°C
24 CERDIP
24 CERDIP
24 CERDIP
24 CERDIP-55°C to +125°C
28 Plastic DIP
28 Plastic DIP
28 Wide SO0°C to +70°C
28 Wide SO
28 SSOP0°C to +70°CMX7828LCAI
28 PLCC0°C to +70°CMX7828LP
28 SSOP-40°C to +85°CMX7828LEAI
28 CERDIP-40°C to +85°CMX7828CQ
28 CERDIP-55°C to +125°CMX7828UQ
ERROR
(LSB)
1
±
/
2
±124 SSOP-40°C to +85°CMX7824KEAG
1
±
/
2
±1
1
±
/
2
±1
1
±
/
2
±1
1
±
/
2
±1
1
±
/
2
±128 SSOP0°C to +70°CMX7828KCAI
1
±
/
2
±128 PLCC0°C to +70°CMX7828KP
1
±
/
2
±128 SSOP-40°C to +85°CMX7828KEAI
1
±
/
2
±128 CERDIP-40°C to +85°CMX7828BQ
1
±
/
2
±128 CERDIP-55°C to +125°CMX7828TQ
AIN2 (N.C.)
AIN1 (N.C.)
TP (REF OUT)
DB0
DB1
DB2
DB3
AIN4
AIN6
AIN5
(AIN1)
A0
(AIN2)
AIN7
(AIN3)
INT
AIN8
(AIN4)
GND
V
REF
V
-
REF
0.124"
(3.150mm)
(N.C.)
AIN3
(N.C.)
( ) ARE FOR MAX154/MX7824
VDDA0
+ ADY
A1
A2 (N.C.)
(3.228mm)
DB7
DB6
DB5
DB4
CS
0.127"
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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