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MAXQ610
User Manual
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MAXIM MAXQ610 User Manual

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General Description
The MAXQ610 is a low-power, 16-bit MAXQ®micro­controller designed for low-power applications includ­ing universal remote controls, consumer electronics, and white goods. The MAXQ610 combines a powerful 16-bit RISC microcontroller and integrated peripherals including two USARTs and an SPI™ master/slave com­munications port, along with an IR module with carrier frequency generation and flexible port I/O capable of multiplexed keypad control.
The MAXQ610 includes 64KB of flash memory and 2KB of data SRAM. Intellectual property (IP) protection is provided by a secure MMU that supports multiple application privilege levels and protects code against copying and reverse engineering. Privilege levels enable vendors to provide libraries and applications to execute on the MAXQ610, while limiting access to only data and code allowed by their privilege level.
For the ultimate in low-power battery-operated perfor­mance, the MAXQ610 includes an ultra-low-power stop mode (0.2µA, typ). In this mode, the minimum amount of circuitry is powered. Wake-up sources include exter­nal interrupts, the power-fail interrupt, and a timer inter­rupt. The microcontroller runs from a wide 1.70V to 3.6V operating voltage.
Applications
Remote Controls
Battery-Powered Portable Equipment
Consumer Electronics
Home Appliances
White Goods
Features
♦ High-Performance, Low-Power 16-Bit RISC Core
♦ DC to 12MHz Operation Across Entire Operating
Range
♦ 1.70V to 3.6V Operating Voltage Range
♦ 33 Total Instructions for Simplified Programming
♦ Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
♦ Dedicated Pointer for Direct Read from Code Space
♦ 16-Bit Instruction Word, 16-Bit Data Bus
♦ 16 x 16-Bit General-Purpose Working Registers
♦ Secure MMU for Application Partitioning and IP
Protection
♦ Memory Features
64KB Flash:
512 Byte Sectors
20,000 Erase/Write Cycles per Sector Masked ROM Available 2KB Data SRAM
♦ Additional Peripherals
Power-Fail Warning Power-On Reset/Brownout Reset Automatic IR Carrier Frequency Generation and
Modulation
Two 16-Bit, Programmable Timers/Counters with
Prescaler and Capture/Compare SPI and Two USART Communication Ports Programmable Watchdog Timer 8kHz Nanopower Ring Oscillator Wake-Up Timer Up to 24 (MAXQ610A) or 32 (MAXQ610B)
General-Purpose I/Os
♦ Low-Power Consumption
0.2µA (typ), 2.0µA (max) in Stop Mode
TA= +25°C, Power-Fail Monitor Disabled
3.75mA (typ) at 12MHz in Active Mode
MAXQ610
16-Bit Microcontroller with Infrared Module
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4715; Rev 6; 7/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata
.
EVALUATION KIT
AVAILABLE
Note: The 4-digit suffix “-0000” indicates a microcontroller in the
default state with the flash memory unprogrammed. Any value other than 0000 indicates a device preprogrammed at Maxim with proprietary customer-supplied software. For more information on factory preprogramming of these devices, contact Maxim at
https://support.maxim-ic.com/micro
. Information on masked
ROM devices and tape and reel versions are also available.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
Contact factory for ordering requirements.
†
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAXQ610A-0000+ 0°C to +70°C 32 TQFN-EP
†
MAXQ610B-0000+ 0°C to +70°C 40 TQFN-EP
†
MAXQ610J-0000+ 0°C to +70°C 44 TQFN-EP
†
MAXQ610X-0000+* 0°C to +70°C Bare die
Pin Configurations and Selector Guide appear at end of data sheet.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MAXQ610
16-Bit Microcontroller with Infrared Module
2 _______________________________________________________________________________________
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
IR Transmit—Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
IR Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Carrier Burst-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
16-Bit Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
ROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Loading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
In-Circuit Debug and JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Differences for ROM Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

TABLE OF CONTENTS

MAXQ610
16-Bit Microcontroller with Infrared Module
_______________________________________________________________________________________ 3
Table 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 4. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . .25

LIST OF TABLES

Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3. IR Transmission Waveform (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. External IRTXM (Modulator) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 5. IR Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 6. Receive Burst-Count Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. SPI Master Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 8. SPI Slave Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 9. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 10. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 11. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

LIST OF FIGURES

MAXQ610
16-Bit Microcontroller with Infrared Module
4 _______________________________________________________________________________________
RECOMMENDED DC OPERATING CONDITIONS
(VDD= V
RST
to 3.6V, TA= 0°C to +70°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VDDwith Respect to GND .......-0.3V to +3.6V
Voltage Range on Any Lead with Respect
to GND except V
DD ......................................
-0.3V to (VDD+ 0.5V)
Continuous Power Dissipation (Multilayer Board, TA= +70°C)
32 TQFN (derate 34.5mW/°C above +70°C) ...........2758.6mW
40 TQFN (derate 35.7mW/°C above +70°C) ..............2963mW
44 TQFN (derate 37mW/°C above +70°C) ..............2758.6mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C

ABSOLUTE MAXIMUM RATINGS

Supply Voltage V
1.8V Internal Regulator V
Power-Fail Warning Voltage for Supply (Notes 2, 3)
Power-Fail Reset Voltage (Note 4)
Power-On Reset Voltage V
RAM Data-Retention Voltage V
Active Current (Note 6) I
Stop-Mode Current
Current Consumption During Power-Fail
Power Consumption During Power-On Reset
Stop-Mode Resume Time t
Power-Fail Monitor Startup Time t
Power-Fail Warning Detection Time
Input Low Voltage for IRTX, IRRX, RESET, and All Port Pins
Input High Voltage for IRTX, IRRX, RESET, and All Port Pins
Input Hysteres is (Schm itt) V
Input Low Voltage for HFXIN V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
DD
REG18
V
PFW
V
RST
POR
DRV
DD_1
I
S1
I
S2
I
PFR
I
POR
ON
PRM_ON
t
PFW
V
V
IHYS
IL_HFXIN
1.62 1.8 1.98 V
Monitors VDD 1.75 1.8 1.85 V
Monitors VDD 1.64 1.67 1.70 V
Monitors VDD 1.0 1.42 V
(Note 5) 1.0 V
Syscl k = 12MHz 3.75 5.1 mA
Power-Fail Off
Power-Fail On
(Notes 5, 7)
(Note 8) 100 nA
375 + 8192t
(Note 5) 150 μs
(Notes 5, 9) 10 μs
V
IL
IH
300 mV
V
3.6 V
RST
TA = +25°C 0.2 2.0
T
= 0°C to +70°C 0.2 12
A
TA = +25°C 22 29.5
T
= 0°C to +70°C 27.6 42
A
[(3 x I
) + ((PCI - 3) x
S2
(I
S1
GND
0.7 x V
DD
GND
+ I
))]/PCI
NANO
μs
HFXIN
0.3 x V
DD
VDD V
0.3 x V
DD
μA
μA
V
V
MAXQ610
16-Bit Microcontroller with Infrared Module
_______________________________________________________________________________________ 5
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= V
RST
to 3.6V, TA= 0°C to +70°C.) (Note 1)
Input High Voltage for HFXIN V
IRRX Input Filter Pulse-Width Reject
IRRX Input Filter Pulse-Width Accept
Output Low Voltage for IRTX V
Output Low Voltage for RESET and Al l Port Pins (Note 10)
Output High Voltage for IRTX and All Port Pins
Input/Output Pin Capacitance for All Port Pins
Input Leakage Current IL Internal pullup disabled -100 +100 nA Input Pullup Resistor for RESET,
IRTX, IRRX, and All Port Pins
EXTERNAL CRYSTAL/RESONATOR
Crystal/Resonator f
Crystal/Resonator Period t
Crystal/Resonator Warmup Time t
Oscillator Feedback Resi stor R
EXTERNAL CLOCK INPUT
External Cloc k Frequenc y f
External Clock Period t
External Clock Duty Cycle t
System Clock Frequency f
System Clock Period tCK 1/fCK MHz
NANOPOWER RING OSCILLATOR
Nanopower Ring O scillator Frequency
Nanopower Ring O scillator Duty Cycle
Nanopower Ring O scillator Current
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IH_HFXIN
50 ns
t
IRRX_R
300 ns
t
IRRX_A
0.7 x V
DD
VDD V
VDD = 3.6V, IOL = 25mA (Note 5) 1.0
OL_IRTX
VDD = 2.35V, IOL = 10mA (Note 5) 1.0
V
VDD = 1.85V, IOL = 4.5mA 1.0
VDD = 3.6V, IOL = 11mA (Note 5) 0.4 0.5
V
OL
VDD = 2.35V, IOL = 8mA (Note 5) 0.4 0.5
V
VDD = 1.85V, IOL = 4.5mA 0.4 0.5
V
-
V
IOH = -2mA
OH
C
(Note 5) 15 pF
IO
R
PU
HFXI N
HFXI N
XTAL_RDY
OSCF
XCLK
XCLK
XCLK_DUTY
CK
f
NANO
t
NANO
I
NANO
VDD = 3.0V, VOL = 0.4V (Note 5) 16 28 39
VDD = 2.0V, VOL = 0.4V 17 30 41
1 12 MHz
1/f
From initial oscillation 8192 x t
(Note 5) 0.5 1.0 1.5 M
DC 12 MHz
1/f
45 55 %
f
HFXOUT = GND f
TA = +25°C 3.0 8.0 20.0
TA = +25°C, VDD = POR vo ltage (Note 5) 1.7 2.4
(Note 5) 40 60 %
Typical at VDD = 1.64V, TA = +25°C (Note 5)
DD
0.5
V
V
DD
k
ns
HFXIN
ms
HFXIN
ns
XCLK
HFIN
XCLK
MHz
kHz
40 400 nA
MAXQ610
16-Bit Microcontroller with Infrared Module
6 _______________________________________________________________________________________
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= V
RST
to 3.6V, TA= 0°C to +70°C.) (Note 1)
Note 1: Specifications to 0°C are guaranteed by design and are not production tested. Note 2: It is not recommended to write to flash memory when the supply voltage drops below the power-fail warning levels as
there is uncertainty in the duration of continuous power supply. The user application should check the status of the power­fail warning flag before writing to flash to ensure complete write operations.
Note 3: The power-fail warning monitor and the power-fail reset monitor track each other with a minimum delta between the two of
0.11V.
Note 4: The power-fail reset and power-on-reset (POR) detectors operate in tandem to ensure that one or both signals are active
at all times when V
DD
< V
RST
. Doing so ensures the device maintains the reset state until the minimum operating voltage is
achieved.
Note 5: Guaranteed by design and not production tested. Note 6: Measured on the V
DD
pin and the part not in reset. All inputs are connected to GND or VDD. Outputs do not source/sink
any current. Part is executing code from flash memory.
Note 7: The power-check interval (PCI) can be set to always on, 1024, 2048, or 4096 nanopower ring oscillator clock cycles. Note 8: Current consumption during POR when powering up while V
DD
< V
POR
.
Note 9: The minimum amount of time that V
DD
must be below V
PFW
before a power-fail event is detected.
Note 10: The maximum total current, I
OH
(max) and IOL(max), for all listed outputs combined should not exceed 32mA to satisfy
the maximum specified voltage drop. This does not include the IRTX output.
Note 11: Programming time does not include overhead associated with utility ROM interface.
WAKE-UP TIMER
Wake-Up Timer Interval t
FLASH M EMORY
System Clock During Flash Programm ing/Erase
Flash Erase Time
Flash Programming Time per Word
Write/Erase Cycles 20,000 Cycles
Data Retention TA = +25°C 100 Years
IR
Carrier Frequency fIR (Note 5) fCK/2 Hz
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WAKEUP
f
FPSYSCLK
1/f
6 MHz
tME Mas s erase 20 40
t
Page erase 20 40
ERAS E
t
(Note 11) 20 100 μs
PROG
NANO
65,535/
f
NANO
s
ms
MAXQ610
16-Bit Microcontroller with Infrared Module
_______________________________________________________________________________________ 7

SPI ELECTRICAL CHARACTERISTICS

(VDD= V
RST
to 3.6V, TA= 0°C to +70°C. AC electrical specifications are guaranteed by design and are not production tested.)
SPI Master Operating Frequency 1/t
SPI Slave Operating Frequency 1/t
SPI I/O Rise/Fall T ime t
SCLK Output Pulse-Width High/Low
MOSI Output Ho ld T ime After SCLK Sample Edge
MOSI Output Valid to Sample Edge
MISO Input Valid to SCLK Sample Edge Rise/Fall Setup
MISO Input to SCLK Sample Edge Rise/Fall Ho ld
SCLK Inactive to MOSI Inactive t
SCLK Input Pulse-Width High/Low
SSEL Active to First Shift Edge t
MOSI Input to SCLK Sample Edge Rise/Fall Setup
MOSI Input from SCLK Sample Edge Transit ion Hold
MISO Output Valid After SCLK Shift Edge Transition
SSEL Inactive t
SCLK Inactive to SSEL Rising tSD t
MISO Output Di sabled After SSEL Edge Rise
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fCK/2 MHz
MCK
fCK/4 MHz
SCK
CL = 15pF, pullup = 560 8.3 23.6 ns
SPI_RF
t
, t
MCH
MCL
t
MOH
t
MOV
t
25 ns
MIS
0 ns
t
MIH
MLH
, t
t
SCH
t
SCL
t
SSE
t
t
SIS
t
t
SIH
2t
t
SOV
SSH
t
SLH
t
/2 -
MCK
t
SPI_RF
t
MCK
t
SPI_RF
t
MCK
t
SPI_RF
t
MCK
t
SPI_RF
SPI_RF
SPI_RF
SPI_RF
tCK +
t
SPI_RF
SPI_RF
/2 -
/2 -
/2 -
ns
ns
ns
ns
/2 ns
SCK
ns
ns
ns
SPI_RF
ns
ns
2t
CK
2t
SPI_RF
ns
+
ns
MAXQ610
16-Bit Microcontroller with Infrared Module
8 _______________________________________________________________________________________

Pin Description

PIN
32 TQFN 40 TQFN 44 TQFN
POWER PINS
15, 29 18, 38 19, 41 V
13, 22, 30 —
14 17 18 REGOUT
— — — EP
RESET PINS
28 37 40 RESET
CLOCK PINS
18 21 23 HFXIN
19 22 24 HFXOUT
IR FUNCTION PINS
31 39 43 IRTX
32 40 44 IRRX
17, 20,
28, 42
NAME FUNCTION
Supply Voltage
DD
Ground. These pins must be directly connected to the ground plane. The 40-pin
GND
TQFN package does not have any ground pin s and connect s to ground through the exposed pad.
Regulator Capacitor. This pin must be connected to ground through a 1.0μF external ceramic-chip capacitor. The capac itor must be placed as close to this pin as possible. No devices other than the capacitor should be connected to this pin.
Exposed Pad. For the 32-pin TQFN package, leave unconnected. For the 40-pin TQFN package, the exposed pad is internally connected to GND. Connect to the ground plane. For the 44-pin TQFN package, the EP has no internal connection to the device. Leave unconnected. Not intended as an electrical connection point.
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 4mA. This pin is driven low as an output when an internal reset condition occurs.
High-Frequency Cr ystal Input. Connect external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external, high-frequency c lock source when HFXOUT is unconnected.
IR Transmit Output. IR transmit pin capab le of s in king 25mA. Thi s pin defaults to high-impedance input with the weak pullup disabled during al l forms of reset. Software must configure thi s pin after release from reset to remove the h igh­impedance input condition.
IR Re ceive Input. IR recei ve pin. This pin defaults to high-impedance input with the wea k pullup disabled during all forms of reset. Software must configure thi s pin after relea se from reset to remove the high-impedance input condition.
MAXQ610
16-Bit Microcontroller with Infrared Module
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN
32 TQFN 40 TQFN 44 TQFN
1–8 1, 3, 5–10
9–12, 16,
17, 20, 21
11–14, 19, 20,
23, 24
1, 3,
5–10
11–14, 21, 22,
25, 26
NAME FUNCTION
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS
General-Purpose, Digital, I/O, Type-C Port. These port pins function as
bidirectional I/O pins. All port pins default to high-impedance mode after a reset. Software must configure these p in s after release from reset to remove the high-
P0.0–
P0.7;
IRTXM, RX0, TX0, RX1, TX1,
TBA0/ TBA1, TBB0/
TBB1
P1.0–
P1.7;
INT0–
INT7
impedance input condition. A ll alternate functions must be enabled from software.
32 TQFN 40 TQFN 44 TQFN PORT SPECIAL FUNCTION
1 1 1 P0.0 IRTXM
2 3 3 P0.1 RX0
3 5 5 P0.2 TX0
4 6 6 P0.3 RX1
5 7 7 P0.4 TX1
6 8 8 P0.5 TBA0/TB A1
7 9 9 P0.6 TBB0
8 10 10 P0.7 TBB1
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt.
These port pins function as bidirectional I/O pins or as interrupts. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance input condition. A ll interrupt functions must be enabled from software.
32 TQFN 40 TQFN 44 TQFN PORT SPECIAL FUNCTION
9 11 11 P1.0 INT0
10 12 12 P1.1 INT1
11 13 13 P1.2 INT2
12 14 14 P1.3 INT3
16 19 21 P1.4 INT4
17 20 22 P1.5 INT5
20 23 25 P1.6 INT6
21 24 26 P1.7 INT7
MAXQ610
16-Bit Microcontroller with Infrared Module
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
32 TQFN 40 TQFN 44 TQFN
25, 26,
24–27
—
23 — — N.C. No Connection. Reserved for future use. Leave this pin unconnected.
29–32,
35, 36
2, 4, 15,
16, 27,
28, 33, 34
27, 29, 32–35,
38, 39
2, 4, 15,
16, 30, 31, 36,
37
NAME FUNCTION
General-Purpose, Digital, I/O, Type-C Port. These port pins function as
bidirectional I/O pins. P2.0–P2.3 defau lt to h igh-impedance mode after a reset. Software must configure these p in s after release from reset to remove the high­impedance input condition. Al l alternate function s must be enabled from software. Enabling the pin’s special function disables the general-purpose I/O on the pin. The JTAG pins (P2.4–P2.7) default to their JTAG function with weak pullups
P2.0–
P2.7; MOSI, MISO,
SCLK,
SSEL,
TCK, TDI,
TMS,
TDO
P3.0–
P3.7; INT8– INT15
enabled after a reset. The JTAG function can be disabled using the TAP bit in the SC register. P2.7 function s as the JT AG test-data output on reset and defaults to an input with a weak pullup. The output function of the test data is only enabled during the TAP’s Shift_IR or Shift_DR states.
32 TQFN 40 TQFN 44 TQFN PORT SPECIAL FUNCTION
— 25 27 P2.0 MOSI
— 26 29 P2.1 MISO
— 29 32 P2.2 SCLK — 30 33 P2.3 SSEL
24 31 34 P2.4 TCK
25 32 35 P2.5 TDI
26 35 38 P2.6 TMS
27 36 39 P2.7 TDO
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt.
These port pins function as bidirectional I/O pins or as interrupts. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance input condition. A ll interrupt functions must be enabled from software.
32 TQFN 40 TQFN 44 TQFN PORT SPECIAL FUNCTION
— 2 2 P3.0 INT8
— 4 4 P3.1 INT9
— 15 15 P3.2 INT10
— 16 16 P3.3 INT11
— 27 30 P3.4 INT12
— 28 31 P3.5 INT13
— 33 36 P3.6 INT14
— 34 37 P3.7 INT15
NO CONNECTION PIN S
MAXQ610

Detailed Description

The MAXQ610 microcontroller provides integrated, low­cost solutions that simplify the design of IR communica­tions equipment such as universal remote controls. Standard features include the highly optimized, single­cycle, MAXQ 16-bit RISC core, 64KB of flash memory, 2KB data RAM, a soft stack, 16 general-purpose regis­ters, and three data pointers. The MAXQ core offers the industry’s best MIPS/mA rating, allowing developers to achieve the same performance as competing micro­controllers at substantially lower clock rates. Combining lower active-mode current with the MAXQ610 stop­mode current (0.2µA typical) results in increased bat­tery life. Application-specific peripherals include flexible timers for generating IR carrier frequencies and modulation, a high-current IR drive pin capable of sink­ing up to 25mA current, and output pins capable of sinking up to 5mA ideal for IR applications, general­purpose I/O pins ideal for keypad matrix input, and a power-fail-detection circuit to notify the application when the supply voltage is nearing the minimum oper­ating voltage of the microcontroller.
peting microcontrollers. An integrated POR circuit with brownout support resets the device to a known condi­tion following a power-up cycle or brownout condition. Additionally, a power-fail warning flag is set and a power-fail interrupt can be generated when the system voltage falls below the power-fail warning voltage, V
PFW
. The power-fail warning feature allows the appli­cation to notify the user that the system supply is low and appropriate action should be taken.

Microprocessor

The MAXQ610 is based on Maxim’s MAXQ core. The MAXQ is a low-power implementation of the new 16-bit MAXQ family of RISC cores. The core supports the Harvard memory architecture with separate 16-bit pro­gram and data address buses. A fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. The MAXQ core in the MAXQ610 family is imple­mented as a pipelined processor with performance approaching 1MIPS per MHz. The 16-bit data path is implemented around register modules, and each regis­ter module contributes specific functions to the core. The accumulator module consists of sixteen 16-bit regis­ters and is tightly coupled with the arithmetic logic unit (ALU). A configurable soft stack supports program flow.
Execution of instructions is triggered by data transfer between functional register modules or between a func­tional register module and memory. Because data movement involves only source and destination mod­ules, circuit-switching activities are limited to active modules only. For power-conscious applications, this approach localizes power dissipation and minimizes switching noise. The modular architecture also provides a maximum of flexibility and reusability that is important for a microprocessor used in embedded applications.

Memory

The MAXQ610 incorporates several memory types that include the following:
• 64KB program flash
• 2KB SRAM data memory
• 5.25KB utility ROM
• Soft stack

Block Diagram

16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 11
MAXQ610
REGULATOR
VOLTAGE
MONITOR
GPIO
4KB ROM
CLOCK
WATCHDOG
16-BIT TIMER16-BIT TIMER
16-BIT MAXQ
RISC CPU
SECURE MMU
64KB FLASH
2KB SRAM
8kHz NANO
RING
IR DRIVER
IR TIMER
SPI
USART0
USART1
MAXQ610
16-Bit Microcontroller with Infrared Module
12 ______________________________________________________________________________________

Memory Protection

The optional memory-protection feature separates code memory into three areas: system, user loader, and user application. Code in the system area can be kept confi­dential. Code in the user areas can be prevented from reading and writing system code. The user loader can also be protected from user application code.
Memory protection is implemented using privilege lev­els for code. Each area has an associated privilege level. RAM/ROM are assigned privilege levels as well. Refer to the
MAXQ610 User’s Guide
for a more thor-
ough explanation of the topic. See Table 1.

Stack Memory

A 16-bit-wide internal stack provides storage for program return addresses and can also be used general-purpose data storage. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An application can also store values in the stack explicitly by using the PUSH, POP, and POPI instructions.
On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vector­ing operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP.

Utility ROM

The utility ROM is a 5.25KB block of internal ROM mem­ory that defaults to a starting address of 8000h. The util­ity ROM consists of subroutines that can be called from application software. These include the following:
• In-system programming (bootstrap loader) using JTAG interface
• In-circuit debug routines
• Test routines (internal memory tests, memory loader, etc.)
• User-callable routines for in-application flash pro­gramming and fast table lookup
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program execution should immediately jump to location 0000h, the start of system code, or to one of the special rou­tines mentioned. Routines within the utility ROM are user accessible and can be called as subroutines by the application software. More information on the utility ROM functions is contained in the
MAXQ610 User’s
Guide
.
Some applications require protection against unautho­rized viewing of program code memory. For these applications, access to in-system programming, in­application programming, or in-circuit debugging func­tions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh.
Three password locks are provided for protection of up to three different program memory segments. When the PWL is set to 1 (POR default) and the contents of the memory at addresses 0010h to 001Fh are any value other than FFh or 00h, the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to 0, these utilities are fully accessible without password. The password is automatically set to all ones following a mass erase.

Watchdog Timer

An internal watchdog timer greatly increases system reliability. The timer resets the device if software execu­tion is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the appli­cation software. If software is operating correctly, the counter is periodically reset and never reaches its max­imum count. However, if software operation is interrupt­ed, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or ESD upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability.
Table 1. Memory Areas and Associated Maximum Privilege Levels
AREA PAGE ADDRESS MAXIMUM PRIVILEGE LEVEL
System 0 to ULDR-1 High
User Loader ULDR to UAPP-1 Medium
User Application UAPP to top Low
Utilit y ROM N/A High
Other (RAM) N/A Low
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 13
IR Carrier Generation and
Modulation Timer
The dedicated IR timer/counter module simplifies low­speed IR communication. The IR timer implements two pins (IRTX and IRRX) for supporting IR transmit and receive, respectively. The IRTX pin has no correspond­ing port pin designation, so the standard PD, PO, and PI port control status bits are not present. However, the IRTX pin output can be manipulated high or low using the PWCN.IRTXOUT and PWCN.IRTXOE bits when the IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of two separate timing enti­ties: a carrier generator and a carrier modulator. The carrier generation module uses the 16-bit IR Carrier register (IRCA) to define the high and low time of the carrier through the IR carrier high byte (IRCAH) and IR carrier low byte (IRCAL). The carrier modulator uses the IR data bit (IRDATA) and IR Modulator Time register (IRMT) to determine whether the carrier or the idle con­dition is present on IRTX.
The IR timer is enabled when the IR enable bit (IREN) is set to 1. The IR Value register (IRV) defines the begin­ning value for the carrier modulator. During transmis­sion, the IRV register is initially loaded with the IRMT value and begins down counting towards 0000h, whereas in receive mode it counts upward from the ini­tial IRV register value. During the receive operation, the IRV register can be configured to reload with 0000h when capture occurs on detection of selected edges or
can be allowed to continue free-running throughout the receive operation. An overflow occurs when the IR timer value rolls over from 0FFFFh to 0000h. The IR overflow flag (IROV) is set to 1 and an interrupt is generated if enabled (IRIE = 1).

Carrier Generation Module

The IRCAH byte defines the carrier high time in terms of the number of IR input clocks, whereas the IRCAL byte defines the carrier low time.
IR Input Clock (f
IRCLK
) = f
SYS
/2
IRDIV[1:0]
Carrier Frequency (f
CARRIER
) =
f
IRCLK
/(IRCAH + IRCAL + 2)
Carrier High Time = IRCAH + 1
Carrier Low Time = IRCAL + 1
Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for each IRV downcount interval and is sampled along with the IRTXPOL and IRDATA bits at the beginning of each new IRV downcount interval so that duty-cycle variation and frequency shifting is possible from one interval to the next, which is illustrated in Figure 1.

IR Transmission

During IR transmission (IRMODE = 1), the carrier gener­ator creates the appropriate carrier waveform, while the carrier modulator performs the modulation. The carrier modulation can be performed as a function of carrier cycles or IRCLK cycles dependent on the setting of the IRCFME bit. When IRCFME = 0, the IRV downcounter is clocked by the carrier frequency and thus the modula­tion is a function of carrier cycles. When IRCFME = 1, the IRV downcounter is clocked by IRCLK, allowing car­rier modulation timing with IRCLK resolution.
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WD[1:0] WATCHDOG CLOCK WATCHDOG INTERRUPT TIMEOUT
00 Syscl k/215 2.7ms 42.7
01 Syscl k/218 21.9m s 42.7
10 Syscl k/221 174.7ms 42.7
11 Syscl k/224 1.4s 42.7
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (μs)
MAXQ610
16-Bit Microcontroller with Infrared Module
14 ______________________________________________________________________________________
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control
CARRIER OUTPUT
(IRV)
IRDATA
IR INTERRUPT
01
IRMT = 3
0
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
IRCA
IRMT IRMT = 5
IRCA = 0202h IRCA = 0002h
IRCA, IRMT, IRDATA SAMPLED AT END OF IRV DOWNCOUNT INTERVAL
3120543210
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0)
CARRIER GENERATION
CARRIERIRCLK
IRCAL + 1IRCAH + 1
IRDATA
IRMT
IRCFME
0
1
IRTXPOL
SAMPLE
IRDATA ON
IRV = 0000h
CARRIER MODULATION
0
1
IR INTERRUPT
IRTX PIN
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 15
The IRTXPOL bit defines the starting/idle state as well as the carrier polarity for the IRTX pin. If IRTXPOL = 1, the IRTX pin is set to a logic-high when the IR timer module is enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low when the IR timer is enabled.
A separate register bit, IR data (IRDATA), is used to determine whether the carrier generator output is out­put to the IRTX pin for the next IRMT carrier cycles. When IRDATA = 1, the carrier waveform (or inversion of this waveform if IRTXPOL = 1) is output on the IRTX pin during the next IRMT cycles. When IRDATA = 0, the idle condition, as defined by IRTXPOL, is output on the IRTX pin during the next IRMT cycles.
The IR timer acts as a downcounter in transmit mode. An IR transmission starts when 1) the IREN bit is set to 1 when IRMODE = 1, 2) the IRMODE bit is set to 1 when IREN = 1, or 3) when IREN and IRMODE are both set to 1 in the same instruction. The IRMT and IRCA registers, along with the IRDATA and IRTXPOL bits, are sampled at the beginning of the transmit process and every time the IR timer value reloads its value. When the IRV reaches 0000h value, on the next carrier clock, it does the following:
1) Reloads IRV with IRMT.
2) Samples IRCA, IRDATA, and IRTXPOL.
3) Generates IRTX accordingly.
4) Sets IRIF to 1.
5) Generates an interrupt to the CPU if enabled (IRIE = 1).
To terminate the current transmission, the user can switch to receive mode (IRMODE = 0) or clear IREN to 0.
Carrier Modulation Time = IRMT + 1 carrier cycles
IR Transmit—Independent External Carrier
and Modulator Outputs
The normal transmit mode modulates the carrier based upon the IRDATA bit. However, the user has the option to input the modulator (envelope) on an external pin if desired. If the IRENV[1:0] bits are configured to 01b or 10b, the modulator/envelope is output to the IRTXM pin. The IRDATA bit is output directly to the IRTXM pin (if IRTXPOL = 0) on each IRV downcount interval bound­ary just as if it were being used to internally modulate the carrier frequency. If IRTXPOL = 1, the inverse of the IRDATA bit is output to the IRTXM pin on the IRV inter­val downcount boundaries. The envelope output is illus­trated in Figure 4. When the envelope mode is enabled, it is possible to output either the modulated (IRENV[1:0] = 01b) or unmodulated (IRENV[1:0] = 10b) carrier to the IRTX pin.
CARRIER OUTPUT
(IRV)
IRDATA
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
01
0
IRMT = 3
23102310
Figure 3. IR Transmission Waveform (IRCFME = 0)
MAXQ610
16-Bit Microcontroller with Infrared Module
16 ______________________________________________________________________________________
Figure 5. IR Capture
IRDATA
IR INTERRUPT
IRV INTERVAL
IRTXM
IRTXPOL = 1
IRTXM
IRTXPOL = 0
IRMT IRMT IRMTIRMT
01010101
Figure 4. External IRTXM (Modulator) Output

IR Receive

When configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX capture function. The IRRXSEL[1:0] bits define which edge(s) of the IRRX pin should trigger IR timer capture function.
The IR module starts operating in the receive mode when IRMODE = 0 and IREN = 1. Once started, the IR timer (IRV) starts up counting from 0000h when a quali-
fied capture event as defined by IRRXSEL happens. The IRV register is, by default, counting carrier cycles as defined by the IRCA register. However, the IR carrier frequency detect (IRCFME) bit can be set to 1 to allow clocking of the IRV register directly with the IRCLK for finer resolution. When IRCFME = 0, the IRCA defined carrier is counted by IRV. When IRCFME = 1, the IRCLK clocks the IRV register.
CARRIER GENERATION
IRCLK
IRCAL + 1IRCAH + 1
IRRX PIN
EDGE DETECT
0
1
IRCFME
CARRIER MODULATION
IR TIMER OVERFLOW
INTERRUPT TO CPU
0000h IRV
IR INTERRUPT
COPY IRV TO IRMT
ON EDGE DETECT
IRXRL
RESET IRV TO 0000h
IRDATA
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 17
On the next qualified event, the IR module does the following:
1) Captures the IRRX pin state and transfers its value to
IRDATA. If a falling edge occurs, IRDATA = 0. If a rising edge occurs, IRDATA = 1.
2) Transfers its current IRV value to the IRMT.
3) Resets IRV content to 0000h (if IRXRL = 1).
4) Continues counting again until the next qualified
event.
If the IR timer value rolls over from 0FFFFh to 0000h before a qualified event happens, the IR timer overflow (IROV) flag is set to 1 and an interrupt generated if enabled. The IR module continues to operate in receive
mode until it is stopped by switching into transmit mode (IRMODE = 1) or clearing IREN = 0.

Carrier Burst-Count Mode

A special mode reduces the CPU processing burden when performing IR learning functions. Typically, when operating in an IR learning capacity, some number of carrier cycles are examined for frequency determina­tion. Once the frequency has been determined, the IR receive function can be reduced to counting the number of carrier pulses in the burst and the duration of the combined mark-space time within the burst. To simplify this process, the receive burst-count mode (as enabled by the RXBCNT bit) can be used. When RXBCNT = 0, the standard IR receive capture functionality is in place.
1
1 4
5
6
7
8
9
TO
2 3 4 6 7
5
8
9
CARRIER FREQUENCY
CALCULATION
IRRX
IRV
IRMT
IRMT = PULSE COUNTING IRMT = PULSE COUNTING
IRV = CARRIER CYCLE COUNTING
CAPTURE INTERRUPT (IRIF = 1). IRV ≥ IRMT. IRV = 0 (IF IRXRL = 1).
SOFTWARE SETS IRCA = CARRIER FREQUENCY. SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE). SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1. SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT. IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS).
QUALIFIED EDGE DETECTED: IRMT++ IRV RESET TO 0 IF IRXRL = 1.
IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE. BURST MARK = IRMT PULSES. SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE.
QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV ≥ IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE).
SOFTWARE SET RXBCNT = 1 AS IN (5). CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED.
Figure 6. Receive Burst-Count Example
MAXQ610
16-Bit Microcontroller with Infrared Module
18 ______________________________________________________________________________________
When RXBCNT = 1, the IRV capture operation is dis­abled and the interrupt flag associated with the capture no longer denotes a capture. In the carrier burst-count mode, the IRMT register is now used only to count quali­fied edges. The IRIF interrupt flag (normally used to sig­nal a capture when RXBCNT = 0) now becomes set if ever two IRCA cycles elapse without getting a qualified edge. The IRIF interrupt flag thus denotes absence of the carrier and the beginning of a space in the receive signal. When the RXBCNT bit is changed from 0 to 1, the IRMT register is set to 0001h. The IRCFME bit is still used to define whether the IRV register is counting sys­tem IRCLK clocks or IRCA-defined carrier cycles. The IRXRL bit is still used to define whether the IRV register is reloaded with 0000h on detection of a qualified edge (per the IRXSEL[1:0] bits). Figure 6 and the descriptive sequence embedded in the figure illustrate the expect­ed usage of the receive burst-count mode.

16-Bit Timers/Counters

The MAXQ610 provides two timers/counters that sup­port the following functions:
• 16-bit timer/counter
• 16-bit up/down autoreload
• Counter function of external pulse
• 16-bit timer with capture
• 16-bit timer with compare
• Input/output enhancements for pulse-width modulation
• Set/reset/toggle output state on comparator match
• Prescaler with 2ndivider (for n = 0, 2, 4, 6, 8, 10)

General-Purpose I/O

The MAXQ610 provides port pins for general-purpose I/Os that have the following features:
• CMOS output drivers
• Schmitt trigger inputs
• Optional weak pullup to VDDwhen operating in input mode
While the microcontroller is in a reset state, all port pins become high impedance with weak pullups disabled, unless otherwise noted.
From a software perspective, each port appears as a group of peripheral registers with unique addresses. Special function pins can also be used as general-pur­pose I/O pins when the special functions are disabled. For a detailed description of the special functions avail­able for each pin, refer to the part-specific user manual. The
MAXQ610 User’s Guide
describes all special func-
tions available on the MAXQ610.

USART

The USART units are implemented with the following characteristics:
• 2-wire interface
• Full-duplex operation for asynchronous data transfers
• Half-duplex operation for synchronous data transfers
• Programmable interrupt for receive and transmit
• Independent baud-rate generator
• Programmable 9th bit parity support
• Start/stop bit support
Serial Peripheral Interface (SPI)
The integrated SPI provides an independent serial communication channel that communicates synchro­nously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time.
The maximum SPI master transfer rate is Sysclk/2. When operating as an SPI slave, the MAXQ610 can support up to a Sysclk/4 SPI transfer rate. Data is trans­ferred as an 8-bit or 16-bit value, MSB first. In addition, the SPI module supports configuration of active SSEL state through the slave active select.
Table 3. USART Mode Details
MODE TYPE START BITS DATA BITS STOP BITS
Mode 0 Synchronous N/A 8 N/A
Mode 1 As ynchronous 1 8 1
Mode 2 Asy nchronou s 1 8 + 1 1
Mode 3 Asy nchronou s 1 8 + 1 1
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 19
Figure 8. SPI Slave Communication Timing
SSEL
SCLK
CKPOL/CKPHA
0/1 OR 1/0
SCLK
CKPOL/CKPHA
0/0 OR 1/1
MOSI
MISO
LSB
LSB
SHIFT SAMPLE SHIFT SAMPLE
t
MCK
t
MCH
t
MOH
t
MIS
t
MOV
t
RF
t
MLH
t
MIH
t
MCL
MSB MSB-1
MSB MSB-1
Figure 7. SPI Master Communication Timing
SSEL
SCLK
CKPOL/CKPHA
0/1 OR 1/0
SCLK
CKPOL/CKPHA
0/0 OR 1/1
MOSI
MISO
SHIFT SAMPLE SHIFT SAMPLE
t
SSE
t
SCK
t
SCH
t
SIS
MSB MSB-1
MSB MSB-1
t
SSH
t
SD
t
SCL
t
SIH
LSB
t
SOV
t
RF
LSB
t
SLH
MAXQ610
16-Bit Microcontroller with Infrared Module
20 ______________________________________________________________________________________

On-Chip Oscillator

An external quartz crystal or a ceramic resonator can be connected between HFXIN and HFXOUT on the MAXQ610, as illustrated in Figure 9.
Noise at HFXIN and HFXOUT can adversely affect on­chip clock timing. It is good design practice to place the crystal and capacitors near the oscillator circuitry and connect HFXIN and HFXOUT to ground with a direct short trace. The typical values of external capaci­tors vary with the type of crystal to be used and should be initially selected based on the load capacitance as suggested by the crystal manufacturer.

ROM Loader

The MAXQ610 includes a ROM loader. The loader denies access to the system, user loader, or user-appli­cation memories unless an area-specific password is provided. The ROM loader is not available in ROM-only versions of the MAXQ610.

Loading Flash Memory

An internal bootstrap loader allows the device to be reloaded over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software uploads are possible that enable physically inaccessible applications to be fre­quently updated. The interface hardware can be a JTAG connection to another microcontroller, or a con­nection to a PC serial port using a serial-to-JTAG con­verter, such as the MAXQJTAG-001 available from Maxim Integrated Products. If in-system programmabili-
ty is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and loading the test access port (TAP) with the system programming instruction invokes the boot­strap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstrap­loader-mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software.
In addition, the ROM loader also enforces the memory­protection policies. 16-word passwords are required to access the ROM loader interface.
Loading memory is not possible for ROM-only versions of the MAXQ610 family.
In-Application Flash
Programming
From user-application code, flash can be programmed using the ROM utility functions from either C or assem­bly language. The function declarations that follow show examples of some of the ROM utility functions provided for in-application flash programming.
/* Write one 16-bit word to code address 'dest'.
* Dest must be aligned to 16 bits.
* Returns 0 = failure, 1 = OK.
*/
int flash_write (uint16_t dest, uint16_t data);
MAXQ610
V
DD
STOP
CLOCK CIRCUIT
R
F
C2
C1
HFXIN
HFXOUT
RF = 1MΩ ± 50% C1 = C2 = 30pF
Figure 9. On-Chip Oscillator
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 21
To erase, the following function would be used:
/* Erase the given Flash page
* addr: Flash offset (anywhere within page)
*/
int flash_erasepage(uint16_t addr);
The in-application flash programming must call ROM utility functions to erase and program any of the flash memory. Memory protection is enforced by the ROM utilty functions.
In-application programming is not available in ROM­only versions of the MAXQ610 family.
In-Circuit Debug and JTAG
Interface
Embedded debug hardware and software are devel­oped and integrated into the MAXQ610 to provide full in-circuit debugging capability in a user application environment. These hardware and software features include:
• A debug engine.
• A set of registers providing the ability to set break­points on register, code, or data using debug service routines stored in ROM.
Collectively, these hardware and software features sup­port two modes of in-circuit debug functionality:
1) Background Mode
• CPU is executing the normal user program.
• Allows the host to configure and set up the in-cir­cuit debugger.
2) Debug Mode
• The debugger takes over the control of the CPU.
• Read/write accesses to internal registers and memory.
• Single-step of the CPU for trace operation.
The interface to the debug engine is the TAP controller. The interface allows for communication with a bus mas­ter that can either be automatic test equipment or a component that interfaces to a higher level test bus as part of a complete system. The communication oper­ates across a 4-wire serial interface from a dedicated TAP that is compatible to the JTAG IEEE Std 1149. The TAP provides an independent serial channel to commu­nicate synchronously with the host system.
The debugger is not available for ROM-only versions of the MAXQ610 family.
TAP
CONTROLLER
CPU
DEBUG ENGINE
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
CONTROL
BREAKPOINT
ADDRESS
DATA
MAXQ610
TMS
TCK
TDI
TDO
Figure 10. In-Circuit Debugger
MAXQ610
16-Bit Microcontroller with Infrared Module
22 ______________________________________________________________________________________

Operating Modes

The lowest power mode of operation for the MAXQ610 is stop mode. In this mode, CPU state and memories are preserved, but the CPU is not actively running. Wake-up sources include external I/O interrupts, the power-fail warning interrupt, or a power-fail reset. Any time the microcontroller is in a state where code does not need to be executed, the user software can put the MAXQ610 into stop mode. The nanopower ring oscilla­tor is an internal ultra-low-power (400nA), 8kHz ring oscillator that can be used to drive a wake-up timer that exits stop mode. The wake-up timer is programmable by software in steps of 125µs up to approximately 8s.
(PFD) bit in the PWCN register. The reset default state for the PFD bit is 1, which disables the power-fail moni­tor function during stop mode. If power-fail monitoring is disabled (PFD = 1) during stop mode, the circuitry responsible for generating a power-fail warning or reset is shut down and neither condition is detected. Thus, the V
DD
< V
RST
condition does not invoke a reset state. However, in the event that VDDfalls below the POR level, a POR is generated. The power-fail monitor is enabled prior to stop mode exit and before code exe­cution begins. If a power-fail warning condition (V
DD
<
V
PFW
) is then detected, the power-fail interrupt flag is set on stop mode exit. If a power-fail condition is detected (VDD< V
RST
), the CPU goes into reset.

Power-Fail Detection

Figures 11, 12, and 13 show the power-fail detection and response during normal and stop mode operation.
A
B
C
D
F
G
H
I
E
V
DD
V
PFW
V
RST
V
POR
INTERNAL RESET
(ACTIVE HIGH)
t < t
PFW
t ≥ t
PFW
t ≥ t
PFW
t ≥ t
PFW
Figure 11. Power-Fail Detection During Normal Operation
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 23
If a reset is caused by a power-fail, the power-fail moni­tor can be set to one of the following intervals:
• Always on—continuous monitoring
•211nanopower ring oscillator clocks (~256ms)
•212nanopower ring oscillator clocks (~512ms)
•213nanopower ring oscillator clocks (~1.024s)
In the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two nanopower ring oscillator cycles. If V
DD
> V
RST
during
detection, V
DD
is monitored for an additional nanopow-
er ring oscillator period. If VDDremains above V
RST
for the third nanopower ring period, the CPU exits the reset state and resumes normal operation from utility ROM at 8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the RESET pin being driven low externally or the watchdog timer, the power-fail, internal regulator, and crystal remain on during the CPU reset. In these cases, the CPU exits the reset state in less than 20 crystal cycles after the reset source is removed.
Table 4. Power-Fail Detection States During Normal Operation
STATE POWER-FAIL
A On Off Off — VDD < V
B On On On —
C On On On —
D On On On —
E On On On —
F
G On On On —
H
I Off Off Off —
On
(Periodically)
On
(Periodically)
INTERNAL
REGULATOR
Off Off Yes
Off Off Yes
CRYSTAL
OSCILLATOR
SRAM
RETENTION
POR.
< VDD < V
V
POR
Crystal warmup time, t CPU held in reset.
V
> V
DD
< VDD < V
RST
< VDD < V
POR
> V
DD
< VDD < V
POR
< V
DD
RST
RST.
POR.
CPU normal operation.
Power drop too short. Power-fail not detected.
V PFI is set when V this state for at least t fail interrupt is generated (if enabled). CPU continues normal operation.
V Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodical ly.
V Crystal warmup time, t CPU resumes normal operation from 8000h.
V Power-fail detected. CPU goes into reset. Power-fail monitor is turned on periodica lly.
V Device held in reset. No operation allowed.
.
COMM ENTS
RST.
XTAL_RDY
.
PFW
< VDD < V
RST
PFW
RST.
XTAL_RDY
RST.
.
and maintains
PFW
, at which time a power-
.
MAXQ610
16-Bit Microcontroller with Infrared Module
24 ______________________________________________________________________________________
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
V
PFW
V
RST
V
POR
A
B C
D
E
F
V
DD
t < t
PFW
t ≥ t
PFW
t ≥ t
PFW
STOP
INTERNAL RESET
(ACTIVE HIGH)
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
STATE POWER-FAIL
INTERNAL
REGULATOR
A On Off Off Yes
B On Off Off Yes
C On On On Yes
D On Off Off Yes
E
(Periodically)
On
Off Off Yes
F Off Off Off —
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMM ENTS
Application enter s stop mode. VDD > V
RST.
CPU in stop mode.
Power drop too short. Power-fail not detected.
< VDD < V
V
RST
Power-fail warning detected.
PFW.
Turn on regulator and crystal. Crystal warmup time, t Exit stop mode.
XTAL_RDY
.
Application enter s stop mode. VDD > V
RST.
CPU in stop mode.
V
< VDD < V
POR
RST.
Power-fail detected. CPU goes into reset. Power-fail monitor is turned on periodica lly.
V
< V
DD
POR.
Device held in reset. No operation allowed.
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 25
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
V
PFW
V
RST
V
POR
V
DD
A
B
C
D
E
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
INTERRUPT
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
STATE POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMM ENTS
Application enter s stop mode.
A Off Off Off Yes
B Off Off Off Yes
VDD > V
RST
.
CPU in stop mode.
< V
V
DD
PFW
. Power-fail not detected because power-fail monitor is disabled.
C On On On Yes
V
< VDD < V
RST
An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a power­fail warning, and sets the power-fail interrupt flag. Turn on regulator and crystal. Crystal warmup time, t
PFW
.
XTAL_RDY
On stop mode ex it, CPU vectors to the higher priority of power-fail and the interrupt that causes stop mode exit.
.
MAXQ610
16-Bit Microcontroller with Infrared Module
26 ______________________________________________________________________________________

Applications Information

The low-power, high-performance RISC architecture of this device makes it an excellent fit for many portable or battery-powered applications. It is ideally suited for applications such as universal remote controls that require the cost-effective integration of IR transmit/ receive capability.

Grounds and Bypassing

Careful PCB layout significantly minimizes system-level digital noise that could interact with the microcontroller or peripheral components. The area under any digital components should be a continuous ground plane if possible. Keep any bypass capacitor leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible.
CMOS design guidelines for any semiconductor require that no pin be taken above V
DD
or below GND. Violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft fail­ure (unintentional modification of memory contents). Voltage spikes above or below the device’s absolute maximum ratings can potentially cause a devastating IC latchup.
Microcontrollers commonly experience negative volt­age spikes through either their power pins or general­purpose I/O pins. Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. Devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System designers must protect components against these transients that can corrupt system memory.

Differences for ROM Versions

The ROM-only versions of the MAXQ610 family devices operate in the same manner as their flash counterparts with the following exceptions:
• The ROM loader is not available in the ROM version.
• Loading memory and in-application programming are not supported.
• The debugger is not available in the ROM version.

Additional Documentation

Designers must have the following documents to fully use all the features of this device. This data sheet con­tains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user’s guides offer detailed information about device features and opera­tion. The following documents can be downloaded from
www.maxim-ic.com/microcontrollers.
• This MAXQ610 data sheet, which contains electrical/ timing specifications and pin descriptions.
• The MAXQ610 revision-specific errata sheet (www.maxim-ic.com/errata).
• The
MAXQ610 User's Guide
, which contains detailed information on core features and operation, including programming.
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled (continued)
STATE POWER-FAIL
D Off Off Off Yes
E
F Off Off Off —
On
(Periodically)
INTERNAL
REGULATOR
Off Off Yes
CRYSTAL
OSCILLATOR
SRAM
RETENTION
Application enter s stop mode.
> V
V
DD
< VDD < V
POR
< V
DD
RST
POR
CPU in stop mode.
V An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a power­fail, put s CPU in reset. Power-fail monitor is turned on periodica lly.
V Device held in reset. No operation allowed.
.
COMM ENTS
.
RST
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________ 27
Development and Technical
Support
Maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following:
• Compilers
• In-circuit emulators
• Integrated Development Environments (IDEs)
• JTAG-to-serial converters for programming and debugging
.
Technical support is available at https://support.maxim-
ic.com/micro.
THIN QFN
(5mm × 5mm)
TOP VIEW
29
30
28
27
12
11
13
P0.1/RX0
P0.3/RX1
P0.4/TX1
P0.5/TBA0/TBA1
P0.6/TBB0
14
P0.0/IRTXM
N.C.
P1.7/INT7
P1.6/INT6
P2.4/TCK
HXFOUT
HFXIN
12 4567
2324 22 20 19 18
V
DD
GND
REGOUT
GND
P1.3/INT3
P1.2/INT2
P0.2/TX0
GND
3
21
31
10
IRTX
P1.1/INT1
32
9
IRRX
P1.0/INT0
P2.7/TDO
26
15
V
DD
P2.6/TMS
25
16
P1.4/INT4
P0.7/TBB1
P1.5/INT5
8
17
P2.5/TDI
MAXQ610
RESET
*EP
*EXPOSED PAD = GND.
+
THIN QFN
(6mm
× 6mm)
TOP VIEW
35
36
34
33
12
11
13
P3.0/INT8
P3.1/INT9
P0.2/TX0
P0.3/RX1
P0.4/TX1
14
P0.0/IRTXM
P3.4/INT12
P2.0/MOSI
P1.7/INT7
P3.5/INT13
P2.2/SCLK
P2.3/SSEL
P1.6/INT6
HFXOUT
12
P3.7/INT15
4567
27282930 26 24 23 22
P2.6/TMS
P2.7/TDO
V
DD
REGOUT
P3.3/INT11
P3.2/INT10
P0.1/RX0
P2.1/MISO
3
25
37
RESET
P1.3/INT3
38
39
40
V
DD
IRTX
IRRX
P1.2/INT2
P1.1/INT1
P1.0/INT0
P3.6/INT14
32
15
P1.4/INT4
P2.5/TDI
31
16
17
18
19
20
P1.5/INT5
P0.5/TBA0/TBA1
P0.6/TBB0
P0.7/TBB1
HFXIN
8910
21
P2.4/TCK
*EP
*EXPOSED PAD = GND.
MAXQ610
+

Pin Configurations

PART
OPERATING VOLTAGE
(V)
PROGRAM MEMORY
(KB)
DATA MEMORY
(KB)
PIN-PACKAGE
MAXQ610A-0000+ 1.70 to 3.6 64 Flash 2 32 TQFN-EP
MAXQ610B-0000+ 1.70 to 3.6 64 Flash 2 40 TQFN-EP
MAXQ610J-0000+ 1.70 to 3.6 64 F lash 2 44 TQFN-EP
MAXQ610X-0000+ 1.70 to 3.6 64 F la sh 2 Bare die

Selector Guide

Note: Contact factory for information about masked ROM devices.
MAXQ610
16-Bit Microcontroller with Infrared Module
28 ______________________________________________________________________________________
Pin Configurations (continued)

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
32 TQFN-EP T3255+3
21-0140 90-0001
40 TQFN-EP T4066+2
21-0141 90-0053
44 TQFN-EP T4477+2
21-0144 90-0127
TOP VIEW
P3.5/INT13
P3.4/INT12
P2.1/MISO
GND
P2.0/MOSI
P1.7/INT7
P1.6/INT6
HFXOUT
P2.2.SCLK
P2.3/SSEL
3332313029282726252423
HFXIN
RESET
V GND IRTX IRRX
34
35
36
37
38
39
40
41
DD
42
43
44
P2.4/TCK
P2.5/TDI P3.6/INT14 P3.7/INT15
P2.6/TMS
P2.7/TDO
*EXPOSED PAD = GND.
MAXQ610
+
123456789
P0.2/TX0
P0.1/RX0
P3.0/INT8
P0.0/IRTXM
R3.1/INT9
P0.3/RX1
TQFN
P0.4/TX1
P0.5/TBA0/TBA1
*EP
P0.6/TBB0
10
11
P1.0/INT0
P0.7/TBB1
22
21
20
19
18
17
16
15
14
13
12
P1.5/INT5 P1.4/INT4 GND V
DD
REGOUT GND P3.3/INT11 P3.2/INT10 P1.3/INT3 P1.2/INT2 P1.1/INT1
MAXQ610
16-Bit Microcontroller with Infrared Module
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
29
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

REVISION
NUMBER
0 10/08 Initial release —
1 11/08
2 1/09
3 7/09
4 10/09
5 2/10 Added the 44-pin TQFN package
6 7/11
REVISION
DATE
DESCRIPTION
Removed the Sysclk = 1MH z cond ition for the Active Current parameter, changed
min values from 18k and 19k to 16k and 17k, and changed the f
the R
PU
TA = +25°C min and max values from 4.2kH z and 14.0kHz to 3.0kHz and 20.0kHz, respectively, in the Recommended DC Operating Condition s table
Added the sentence “Software must configure this pin after release from reset to remove the high-impedance input condition.” to the IRRX, P0.x, P1.x, P2.x, and P3.x descriptions in the Pin Description table
Added future status to the 32 TQFN package in the Ordering Information table 1
Changed the REGOUT pin series resistance from 1 to 2 to 10 in the Pin Description table
Changed the t Operating Condition s table
Removed the statement about the use of multi la yer boards from the Grounds and Bypassing section
Adju sted the minimum resonator frequency from DCMHz to 1MHz and the minimum programming frequency from 5MHz to 6MH z in the Recommended DC Operating Conditions table
Removed future status from the MAXQ610A-0000+ in the Ordering Information table; added the continuous power dissipation, lead temperature, and soldering temperature information to the Absolute Maximum Ratings section
minimum spec from 200ns to 300ns in the Recommended DC
IRRX_A
NANO
PAGES
CHANGED
4, 5
8, 9
8
5
25
5, 6
1, 8, 9, 10, 26,
27, 28
1, 4
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