The MAX9888 is a full-featured audio CODEC whose
high performance and low power consumption make it
ideal for portable applications.
Class D speaker amplifiers provide efficient amplification
for two speakers. Low radiated emissions enable completely filterless operation. Integrated bypass switches
optionally connect an external amplifier to the transducer
when the Class D amplifiers are disabled.
®
DirectDrive
ground-referenced output, eliminating the need for
large DC-blocking capacitors. 1.8V headphone operation ensures low power consumption. The device also
includes a differential receiver amplifier.
Three differential analog microphone inputs are available
as well as support for two PDM digital microphones.
Integrated switches allow microphone signals to be
routed out to external devices. Two flexible single-ended
or differential line inputs may be connected to an FM
radio or other sources.
Integrated FlexSoundK technology improves loudspeaker performance by optimizing the signal level and
frequency response while limiting the maximum distortion and power at the output to prevent speaker damage.
Automatic gain control (AGC) and a noise gate optimize
the signal level of microphone input signals to make best
use of the ADC dynamic range.
The device is fully specified over the -40NC to +85NC
extended temperature range.
DirectDrive is a registered trademark and FlexSound is a
trademark of Maxim Integrated Products, Inc.
headphone amplifiers provide a true
Stereo Audio CODEC
Features
S100dB DR Stereo DAC (8kHz < fS < 96kHz)
91dB DR Stereo ADC (8kHz < f
S
Stereo Low EMI Class D Amplifiers
S
950mW/Channel (8I, V
Stereo DirectDrive Headphone Amplifiers
S
Differential Receiver Amplifier
S
2 Stereo Single-Ended/Mono Differential Line
S
Inputs
3 Differential Microphone Inputs
S
FlexSound Technology
S
5-Band Parametric EQ
Automatic Level Control (ALC)
Excursion Limiter
Speaker Power Limiter
Speaker Distortion Limiter
Microphone Automatic Gain Control
and Noise Gate
(Voltages with respect to AGND.)
DVDD, AVDD, HPVDD
SPKLVDD, SPKRVDD, DVDDS1, DVDDS2
DGND, HPGND, SPKLGND, SPKRGND
HPVSS
............................... (HPGND - 2.2V) to (HPGND + 0.3V)
C1N
.................................... (HPVSS - 0.3V) to (HPGND + 0.3V)
C1P
.....................................(HPGND - 0.3V) to (HPVDD + 0.3V)
PREG
MAX9888
..................................................... -0.3V to (AVDD + 0.3V)
REF, MICBIAS
................................. -0.3V to (SPKLVDD + 0.3V)
.........................................-0.3V to +2.2V
..........-0.3V to +6.0V
..............-0.1V to +0.1V
MCLK, SDINS1, SDINS2, JACKSNS,
SDA, SCL, IRQ
LRCLKS1, BCLKS1, SDOUTS1
LRCLKS2, BCLKS2, SDOUTS2
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
.................................................-0.3V to +6.0V
......... -0.3V to (DVDDS1 + 0.3V)
......... -0.3V to (DVDDS2 + 0.3V)
ELECTRICAL CHARACTERISTICS
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
T
= T
A
PGAIN_
MIN
MICPRE_
= 0dB, AV
to T
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
Supply Voltage RangeGuaranteed by PSRR
Total Supply Current (Note 2)I
= V
HPVDD
= +20dB, AV
PGAOUT_
, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
MAX
DVDD
= J, R
HP
= V
DVDDS1
REC
MICPGA_
= 0dB, AV
= V
= J, Z
= 0dB, AV
HP_
= +1.8V, V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
Setup Time for STOP Conditiont
Bus CapacitanceC
Pulse Width of Suppressed Spiket
HPVDD
= V
DVDD
= V
DVDDS1
= V
= +25NC.) (Note 1)
A
= 1.65V to 2.0V, V
DVDDS2
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCL
t
BUF
t
HD,STA
LOW
HIGH
t
SU,STA
HD,DAT
SU,DAT
SU,STO
Guaranteed by SCL pulse-width low and
high
RPU = 475I, CB = 100pF, 400pF
(Note 10)
R
(Note 10)
F
RPU = 475I, CB = 100pF, 400pF (Note 10)
F
Guaranteed by SDA transmitting fall time400pF
B
SP
SPKLVDD
= V
SPKRVDD
= 3.7V, TA = T
MIN
to T
MAX
0400kHz
1.3
0.6
1.3
0.6
0.6
0900ns
100ns
20 +
0.1C
20 +
0.1C
20 +
0.05C
B
B
B
300ns
300ns
250ns
0.6
050ns
, unless
Fs
Fs
Fs
Fs
Fs
Fs
24
SDA
t
LOW
t
SU,DAT
Stereo Audio CODEC
with FlexSound Technology
MAX9888
t
t
t
HD,DAT
SU,STA
t
HD,STA
t
SP
t
SU,STO
BUF
t
HIGH
t
t
R
F
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 5. I
SCL
t
HD,STA
START CONDITION
2
C Interface Timing Diagram
Note 1: The IC is 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Note 2:
Analog supply current = I
+ I
DVDDS1
+ I
DVDDS2
.
AVDD
+ I
. Speaker supply current = I
HPVDD
SPKLVDD
+ I
SPKRVDD
. Digital supply current = I
DVDD
Note 3: Clocking all zeros into the DAC. Slave mode.
Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 5: Gain measured relative to the 0dB setting.
Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000.
Note 7: 0dBFS for DAC input. 1V
for INA/INB inputs.
P-P
Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some full-
scale performance degradation compared to synchronous integer related MCLK/LRCLK ratios.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10: CB is in pF.
Power Consumption
(V
= V
AVDD
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, 0.1mW/channel,
R
= 32I
HP
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, ALC enabled
HPVDD
= V
MODE
DVDD
= V
DVDDS1
= V
DVDDS2
I
AVDD
(mA)
= +1.8V, V
I
HPVDD
(mA)
SPKLVDD
= V
SPKRVDD
I
SPKLVDD
I
SPKRVDD
(mA)
+
= 3.7V)
I
DVDD
(mA)
I
DVDDS1
+ I
(mA)
DVDDS2
1.351.371.652.910.0216.25
1.354.191.653.020.0221.55
1.351.371.652.960.0216.36
POWER
(mW)
25
Stereo Audio CODEC
with FlexSound Technology
Power Consumption (continued)
(V
= V
AVDD
DAC Playback 48kHz Stereo HP
DAC à HP
MAX9888
24-bit, music filters, EQ enabled
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, digital mixing
DAC Playback 44.1kHz Stereo HP
DAC à HP
24-bit, music filters
DAC Playback 8kHz Stereo HP
DAC à HP
16-bit, voice filters
DAC Playback 8kHz Mono HP
DAC à HP
16-bit, voice filters
DAC Playback 48kHz Stereo SPK
DAC à SPK
24-bit, music filters
DAC Playback 48kHz Mono SPK
DAC à SPK
24-bit, music filters
Line Stereo Record 48kHz
INA à ADC
16-bit, music filters
Line Stereo Record 48kHz, Stereo HP
INA à ADC
INA à HP
16-bit, music filters
Line Stereo Record 48kHz, Stereo SPK
INA à ADC
INA à SPK
16-bit, music filters
Differential Line Record 48kHz
INA à ADCL
INB à ADCR
Differential input
Microphone Stereo Record 48kHz
MIC1/2 à ADC
16-bit, music filters
Microphone Stereo Record 8kHz
MIC1/2 à ADC
16-bit, voice filters
HPVDD
= V
MODE
DVDD
= V
DVDDS1
= V
= +1.8V, V
DVDDS2
I
AVDD
(mA)
1.351.361.653.270.0216.90
1.341.361.652.910.0216.27
1.351.371.692.850.0216.29
1.351.371.651.460.0113.65
1.000.711.011.360.019.27
1.830.028.222.920.0239.09
1.250.024.312.820.0223.32
9.910.020.391.620.1122.48
10.642.650.661.630.1129.51
10.97
10.490.020.391.630.1623.58
10.880.030.691.620.1725.43
10.770.020.641.030.0623.78
SPKLVDD
I
HPVDD
(mA)
0.037.151.630.1249.50
= V
SPKRVDD
I
SPKLVDD
I
SPKRVDD
(mA)
+
= 3.7V)
I
DVDD
(mA)
I
DVDDS1
+ I
(mA)
DVDDS2
POWER
(mW)
26
Stereo Audio CODEC
with FlexSound Technology
Power Consumption (continued)
(V
AVDD
= V
HPVDD
= V
DVDD
= V
DVDDS1
= V
DVDDS2
= +1.8V, V
SPKLVDD
= V
SPKRVDD
= 3.7V)
MAX9888
MODE
Microphone Mono Record 48kHz
MIC1/2 à ADC
16-bit, music filters
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters, AGC
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters, AGC, noise gate
Full-Duplex 48kHz Stereo HP
MIC1/2 à ADC
DAC à HP
24-bit, music filters
Full-Duplex 8kHz Mono RCV
MIC1 à ADC
DAC à REC
16-bit, voice filters
Full-Duplex 8kHz Mono HP
MIC1 à ADC
DAC à HP
16-bit, voice filters
Full-Duplex 8kHz Stereo HP
MIC1/2 à ADC
DAC à HP
16-bit, voice filters
Line Playback Stereo HP
INA à HP
Single-ended inputs
Line Playback Stereo SPK
INA à SPK
Single-ended inputs
Line Playback Mono SPK
INA à SPK
Single-ended inputs
Differential Line Playback Stereo HP
INA à HPL
INB à HPR
Differential input
(mA)
+
I
DVDD
(mA)
I
DVDDS1
+ I
(mA)
DVDDS2
POWER
(mW)
I
I
AVDD
(mA)
6.010.020.661.370.1015.97
5.950.020.640.980.0414.94
5.950.020.640.980.0415.00
5.960.020.640.980.0414.98
11.381.371.703.560.1936.06
6.350.021.981.470.0321.47
6.090.711.011.460.0318.72
10.921.371.091.510.0528.95
1.892.650.580.030.0110.41
2.210.027.050.040.0230.19
1.680.023.700.030.0216.90
2.462.650.580.030.0111.42
I
HPVDD
(mA)
SPKLVDD
I
SPKRVDD
27
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
MAX9888
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
= V
MICBIAS
DACGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
Microphone to ADC
SPKRVDD
= C
PREG
= 0dB, AV
= 3.7V. Speaker loads (Z
= C
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
MCLK = 13MHz
-10
LRCLK = 8kHz
FREQ MODE
-20
V
= 1V
IN
-30
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
P-P
AV
= 0dB
MICPRE_
1010,000
FREQUENCY (Hz)
1000100
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
MCLK = 12.288MHz
-10
LRCLK = 96kHz
NI MODE
-20
V
= 1V
IN
-30
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
P-P
AV
= 0dB
MICPRE_
10100,000
FREQUENCY (Hz)
10,0001000100
MAX9888 toc01
THD+N RATIO (dB)
MAX9888 toc04
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
MCLK = 13MHz
-10
LRCLK = 44.1kHz
PLL MODE
-20
V
= 1V
IN
P-P
AV
MICPRE_
= 0dB
10,0001000100
FREQUENCY (Hz)
-30
-40
-50
-60
-70
-80
-90
10100,000
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
MCLK = 13MHz
-10
LRCLK = 8kHz
FREQ MODE
-20
V
= 0.1V
IN
AV
MICPRE_
P-P
= +20dB
FREQUENCY (Hz)
1000100
-30
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
1010,000
MAX9888 toc02
THD+N RATIO (dB)
MAX9888 toc05
THD+N RATIO (dB)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
MCLK = 12.288MHz
-10
LRCLK = 48kHz
NI MODE
-20
V
= 1V
IN
-30
-40
-50
-60
-70
-80
-90
-100
P-P
AV
= 0dB
MICPRE_
10100,000
FREQUENCY (Hz)
10,0001000100
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
MCLK = 13MHz
-10
LRCLK = 8kHz
FREQ MODE
-20
V
= 0.032V
IN
MICPRE_
P-P
= +30dB
FREQUENCY (Hz)
1000100
-30
AV
-40
-50
-60
-70
-80
-90
-100
1010,000
MAX9888 toc03
MAX9888 toc06
28
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
GAIN vs. FREQUENCY (MIC TO ADC)
5
-5
-15
-25
-35
-45
MCLK = 13MHz
-55
LRCLK = 8kHz
NORMALIZED GAIN (dB)
FREQ MODE
-65
VIN = 1V
-75
-85
P-P
AV
= 0dB
MICPRE_
1010,000
MODE = 1
MODE = 0
1000100
FREQUENCY (Hz)
FFT, 0dBFS (MIC TO ADC)
0
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
AV
MICPRE_
= 0dB
MAX9888 toc07
MAX9888 toc10
COMMON-MODE REJECTION
RATIO vs. FREQUENCY (MIC TO ADC)
90
80
AV
70
60
50
40
CMRR (dB)
30
20
10
V
OUT, DIFF
0
10100,000
= +30dB
MICPRE_
AV
MICPRE_
AV
MICPRE_
= 0dBFS
FREQUENCY (Hz)
= +20dB
= 0dB
10,0001000100
FFT, -60dBFS (MIC TO ADC)
0
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
AV
MICPRE_
= 0dB
MAX9888 toc08
PSRR (dB)
MAX9888 toc11
AMPLITUDE (dBV)
POWER-SUPPLY REJECTION
RATIO vs. FREQUENCY (MIC TO ADC)
0
V
= 200mV
RIPPLE
INPUTS AC GROUNDED
-20
-40
-60
-80
-100
-120
10100,000
P-P
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON
SPKLVDD, SPKRVDD
10,0001000100
FREQUENCY (Hz)
FFT, 0dBFS (MIC TO ADC)
0
-20
-40
-60
-80
-100
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
AV
MICPRE_
MAX9888 toc09
MAX9888 toc12
= 0dB
-120
-140
04000
FREQUENCY (Hz)
-120
-140
350030002500200015001000500
04000
FREQUENCY (Hz)
350030002500200015001000500
-120
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
29
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
HPVSS
= 0dB,
FFT, -60dBFS (MIC TO ADC)
0
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
-120
-140
020,000
FREQUENCY (Hz)
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
AV
MICPRE_
FFT, -60dBFS (MIC TO ADC)
0
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
AV
MICPRE_
0
MAX9888 toc13
= 0dB
15,00010,0005000
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
-120
-140
020,000
FREQUENCY (Hz)
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
AV
= 0dB
MICPRE_
15,00010,0005000
MAX9888 toc14
FFT, 0dBFS (MIC TO ADC)
FFT, 0dBFS (MIC TO ADC)
= 0dB
MAX9888 toc15
0
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
AV
= 0dB
MICPRE_
MAX9888 toc16
30
-120
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
-120
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
FFT, -60dBFS (MIC TO ADC)
0
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
-120
-140
020,000
FREQUENCY (Hz)
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
AV
MICPRE_
15,00010,0005000
= 0dB
SCL
2V/div
ADC
OUTPUT
0.5V/div
MAX9888 toc17
SCL
2V/div
ADC
OUTPUT
0.5V/div
SOFTWARE TURN-ON/OFF RESPONSE
(MIC TO ADC)
MAX9888 toc19
ADC ENABLE/DISABLE RESPONSE
(MIC TO ADC)
10ms/div
MAX9888 toc18
10ms/div
31
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
MAX9888
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
Line to ADC
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
HPVSS
= 0dB,
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
0
-10
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
10100,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
V
IN
AV
C
IN
FREQUENCY (Hz)
= 1.4V
PGAIN_
= 1µF
10,0001000100
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
0
-10
-20
-30
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
10100,000
P-P
= -6dB
FREQUENCY (Hz)
MAX9888 toc20
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
V
IN
EXTERNAL GAIN MODE
RIN = 56kI, CIN = 1µF
-10
-20
-30
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
= 1V
RMS
10,0001000100
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
0
10100,000
MAX9888 toc23
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
V
IN
C
IN
AV
FREQUENCY (Hz)
= 1V
P-P
= 1µF
= 0dB
PGAIN_
10,0001000100
0
-20
-40
-60
PSRR (dB)
-80
-100
-120
10100,000
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
0
-10
MAX9888 toc21
-20
-30
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
10100,000
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO ADC)
V
= 200mV
INPUTS AC GROUNDED
RIPPLE ON AVDD,
DVDD, HPVDD
FREQUENCY (Hz)
RIPPLE
SPKLVDD, SPKRVDD
P-P
RIPPLE ON
10,0001000100
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
V
= 0.1V
IN
P-P
AV
= +20dB
PGAIN_
10,0001000100
MAX9888 toc24
MAX9888 toc22
32
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
= V
MICBIAS
DACGAIN
SPK_
Digital Loopback
SPKRVDD
= C
PREG
= 0dB, AV
= 3.7V. Speaker loads (Z
= C
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
(SDINS1 TO SDOUTS2 DIGITAL LOOPBACK)
FFT, 0dBFS
0
-20
-40
-60
-80
-100
AMPLITUDE (dBFS)
-120
-140
-160
-180
020,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
15,00010,0005000
FREQUENCY (Hz)
MAX9888 toc25
(SDINS1 TO SDOUTS2 DIGITAL LOOPBACK)
FFT, -60dBFS
0
-20
-40
-60
-80
-100
AMPLITUDE (dBFS)
-120
-140
-160
-180
020,000
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
15,00010,0005000
FREQUENCY (Hz)
MAX9888 toc26
33
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
MAX9888
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
= V
MICBIAS
DACGAIN
SPK_
Analog Loopback
SPKRVDD
= C
PREG
= 0dB, AV
= 3.7V. Speaker loads (Z
= C
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
HPVSS
= 0dB,
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE)
0
MCLK = 13MHz
-10
LRCLK = 44.1kHz
PLL MODE
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
= 32I, CIN = 1µF
R
HP
P
= 0.025W
OUT
P
= 0.01W
OUT
10100,000
FREQUENCY (Hz)
10,0001000100
FFT, -60dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
0
-20
-40
-60
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
= 32I
R
HP
MAX9888 toc27
THD+N RATIO (dB)
MAX9888 toc30
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE )
0
MCLK = 12.288MHz
-10
LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
-60
-70
-80
-90
= 32I, CIN = 1µF
R
HP
P
= 0.025W
OUT
P
= 0.01W
OUT
10100,000
FREQUENCY (Hz)
10,0001000100
FFT, 0dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
0
-20
-40
-60
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
= 32I
R
HP
MAX9888 toc28
AMPLITUDE (dBV)
MAX9888 toc31
(LINE TO ADC TO DAC TO HEADPHONE)
FFT, 0dBFS
0
-20
-40
-60
-80
-100
-120
-140
020,000
FREQUENCY (Hz)
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
= 32I
R
HP
15,00010,0005000
FFT, -60dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
0
-20
-40
-60
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
= 32I
R
HP
MAX9888 toc29
MAX9888 toc32
-80
AMPLITUDE (dBV)
-100
-120
-140
020,000
FREQUENCY (Hz)
34
-80
AMPLITUDE (dBV)
-100
-120
15,00010,0005000
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
-80
AMPLITUDE (dBV)
-100
-120
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
REF
DACATTN
REC
SPKLVDD
= 2.2FF, C
= 0dB, AV
= 0dB, AV
MICBIAS
DACGAIN
SPK_
DAC to Receiver
= V
SPKRVDD
= C
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER (DAC TO RECEIVER)
0
MCLK = 13MHz
-10
LRCLK = 8kHz
FREQ MODE
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
= 32I
R
REC
AV
= +8dB
REC
f = 3000Hz
f = 1000Hz
f = 100Hz
00.12
OUTPUT POWER (W)
GAIN vs. FREQUENCY
(DAC TO RECEIVER)
5
MCLK = 13MHz
4
LRCLK = 8kHz
FREQ MODE
3
= 32I
R
REC
2
1
0
-1
-2
NORMALIZED GAIN (dB)
-3
-4
-5
1010,000
FREQUENCY (Hz)
1000100
TOTAL HARMONIC DISTORTION
vs. FREQUENCY (DAC TO RECEIVER)
0
MCLK = 13MHz
-10
MAX9888 toc33
0.100.080.060.040.02
LRCLK = 8kHz
FREQ MODE
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
= 32I
R
REC
P
= 0.05W
OUT
P
= 0.025W
OUT
1010,000
FREQUENCY (Hz)
1000100
MAX9888 toc34
POWER CONSUMPTION vs. OUTPUT
POWER (DAC TO RECEIVER)
0.25
MCLK = 13MHz
MAX9888 toc36
LRCLK = 8kHz
FREQ MODE
0.20
0.15
0.10
POWER CONSUMPTION (W)
0.05
= 32I
R
REC
AV
= +8dB
REC
0
00.12
OUTPUT POWER (W)
MAX9888 toc37
0.100.080.060.040.02
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO RECEIVER)
140
130
120
110
100
90
80
OUTPUT POWER PER CHANNEL (mW)
70
60
2.55.5
THD+N = 10%
THD+N = 1%
SUPPLY VOLTAGE (V)
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
R
REC
AV
REC
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO RECEIVER)
0
V
= 200mV
RIPPLE
ALL ZEROS AT INPUT
-20
-40
PSRR (dB)
-60
-80
-100
10100,000
P-P
RIPPLE ON SPKLVDD,
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
10,0001000100
FREQUENCY (Hz)
MAX9888 toc35
= 32I
= +8dB
5.04.53.03.54.0
MAX9888 toc38
35
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
HPVSS
= 0dB,
SCL
2V/div
RECEIVER
OUTPUT
1V/div
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
-120
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO RECEIVER, VSEN = 0)
10ms/div
FFT, -60dBFS (DAC TO RECEIVER)
0
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
R
REC
MAX9888 toc39
= 32I
RECEIVER
OUTPUT
MAX9888 toc42
AMPLITUDE (dBm)
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO RECEIVER, VSEN = 1)
SCL
2V/div
1V/div
10ms/div
WIDEBAND FFT, 0dBFS
(DAC TO RECEIVER)
0
-20
-40
-60
-80
-100
MAX9888 toc40
MCLK = 13MHz
LRCLK = 8kHz
PLL MODE
= 32I
R
REC
AMPLITUDE (dBV)
MAX9888 toc43
AMPLITUDE (dBm)
FFT, 0dBFS (DAC TO RECEIVER)
0
-20
-40
-60
-80
-100
-120
-140
020,000
FREQUENCY (Hz)
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
R
REC
15,00010,0005000
WIDEBAND FFT, -60dBFS
(DAC TO RECEIVER)
0
-20
-40
-60
-80
-100
MCLK = 13MHz
LRCLK = 8kHz
PLL MODE
R
REC
= 32I
MAX9888 toc41
MAX9888 toc44
= 32I
-140
020,000
FREQUENCY (Hz)
36
15,00010,0005000
-120
010,000
FREQUENCY (kHz)
1000100101
-120
010,000
FREQUENCY (kHz)
1000100101
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
= V
MICBIAS
DACGAIN
SPK_
Line to Receiver
SPKRVDD
= C
PREG
= 0dB, AV
= 3.7V. Speaker loads (Z
= C
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(LINE TO RECEIVER)
0
-10
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
00.10
f = 6000Hz
f = 100Hz
OUTPUT POWER (W)
R
AV
f = 1000Hz
GAIN vs. FREQUENCY (LINE TO RECEIVER)
5
R
= 32I
REC
4
= 1µF
C
IN
3
2
1
0
-1
-2
NORMALIZED GAIN (dB)
-3
-4
-5
10100,000
FREQUENCY (Hz)
10,0001000100
REC
REC
0.080.060.020.04
= 32I
= +8dB
MAX9888 toc45
MAX9888 toc47
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO RECEIVER)
0
R
= 32I
REC
-10
= 1µF
C
IN
AV
= +8dB
REC
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
10100,000
P
= 0.05W
OUT
P
OUT
FREQUENCY (Hz)
= 0.025W
10,0001000100
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO RECEIVER)
0
V
= 200mV
RIPPLE
INPUT AC GROUNDED
-20
-40
PSRR (dB)
-60
-80
-100
RIPPLE ON SPKLVDD,
10100,000
P-P
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
10,0001000100
FREQUENCY (Hz)
MAX9888 toc46
MAX9888 toc48
37
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
MAX9888
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
REF
DACATTN
REC
SPKLVDD
= 2.2FF, C
= 0dB, AV
= 0dB, AV
MICBIAS
SPK_
DAC to Speaker
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
HPVSS
= 0dB,
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
V
= 4.2V
SPK_VDD
-10
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
= 8I + 68µH
Z
SPK
AV
= +8dB
SPK_
f = 6000Hz
f = 1000Hz
f = 100Hz
01.2
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
V
= 4.2V
SPK_VDD
-10
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
-20
Z
= 4I + 33µH
SPK
-30
AV
= +8dB
SPK_
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
f = 6000Hz
f = 1000Hz
f = 100Hz
OUTPUT POWER (W)
1.00.80.60.40.2
2.01.51.00.502.5
MAX9888 toc49
THD+N RATIO (dB)
MAX9888 toc52
THD+N RATIO (dB)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
V
= 3.7V
SPK_VDD
-10
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
-20
Z
= 8I + 68µH
SPK
AV
= +8dB
SPK_
-30
-40
-50
-60
-70
-80
f = 6000Hz
f = 1000Hz
f = 100Hz
0.80.60.40.201.0
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
V
= 3.7V
SPK_VDD
-10
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
-20
Z
= 4I + 33µH
SPK
-30
AV
= +8dB
SPK_
-40
-50
-60
-70
-80
-90
f = 6000Hz
f = 1000Hz
f = 100Hz
1.51.00.502.0
OUTPUT POWER (W)
MAX9888 toc50
THD+N RATIO (dB)
MAX9888 toc53
THD+N RATIO (dB)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
V
= 3.V
SPK_VDD
-10
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
-60
-70
-80
= 8I + 68µH
Z
SPK
AV
SPK_
f = 100Hz
= +8dB
f = 6000Hz
f = 1000Hz
0.50.40.30.20.100.6
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
V
= 3V
SPK_VDD
-10
MCLK = 12.288MHz,
LRCLK = 48kHz
-20
NI MODE
-30
Z
= 4I + 33µH
SPK
= +8dB
AV
SPK_
-40
f = 6000Hz
-50
-60
-70
-80
f = 100Hz
-90
01.4
f = 1000Hz
1.21.00.60.80.40.2
OUTPUT POWER (W)
MAX9888 toc51
MAX9888 toc54
38
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
0
V
= 4.2V
SPK_VDD
-10
MCLK = 12.288MHz,
LRCLK = 48kHz
-20
NI MODE
-30
Z
= 8I + 68µH
SPK
= +8dB
AV
SPK_
-40
-50
THD+N RATIO (dB)
-60
P
= 0.25W
OUT
-70
-80
P
= 0.55W
-90
OUT
10100,000
FREQUENCY (Hz)
10,0001000100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
0
V
= 3.7V
SPK_VDD
-10
MCLK = 12.288MHz,
LRCLK = 48kHz
-20
NI MODE
-30
Z
= 4I + 33µH
SPK
P
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
P
= 0.5W
OUT
10100,000
= 1.0W
OUT
FREQUENCY (Hz)
10,0001000100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
0
V
SPK_VDD
-10
MAX9888 toc55
MCLK = 12.288MHz,
LRCLK = 48kHz
-20
NI MODE
-30
Z
= 8I + 68µH
SPK
AV
SPK_
-40
-50
THD+N RATIO (dB)
-60
P
= 0.25W
OUT
-70
-80
P
= 0.55W
OUT
-90
10100,000
OUTPUT POWER vs. SUPPLY VOLTAGE
2200
MCLK = 12.288MHz,
2000
MAX9888 toc58
LRCLK = 48kHz
NI MODE
1800
1600
1400
1200
1000
800
OUTPUT POWER PER CHANNEL (mW)
600
400
= 8I + 68µH
Z
SPK
2.55.5
= 3.7V
= +8dB
FREQUENCY (Hz)
(DAC TO SPEAKER)
THD+N = 10%
THD+N = 10%THD+N = 10%
THD+N = 10%
SUPPLY VOLTAGE (V)
10,0001000100
THD+N = 1%
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
0
V
= 4.2V
SPK_VDD
-10
MAX9888 toc56
MCLK = 12.288MHz,
LRCLK = 48kHz
-20
NI MODE
-30
Z
= 4I + 33µH
SPK
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
P
OUT
10100,000
= 0.5W
FREQUENCY (Hz)
P
= 1.0W
OUT
10,0001000100
MAX9888 toc57
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
3500
MCLK = 12.288MHz,
3000
MAX9888 toc59
5.04.54.03.53.0
LRCLK = 48kHz
NI MODE
= 4I + 33µH
Z
2500
SPK
2000
1500
1000
OUTPUT POWER PER CHANNEL (mW)
500
0
THD+N = 10%
SUPPLY VOLTAGE (V)
MAX9888 toc60
THD+N = 1%
5.04.54.03.53.02.55.5
39
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
HPVSS
= 0dB,
GAIN vs. FREQUENCY
(DAC TO SPEAKER)
5
MCLK = 12.288MHz,
4
LRCLK = 48kHz
3
NI MODE
Z
= 8I + 68µH
SPK
2
1
0
-1
-2
NORMALIZED GAIN (dB)
-3
-4
-5
FREQUENCY (Hz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
30
MCLK = 12.288MHz,
LRCLK = 48kHz
25
Z
= 8I + 68µH
SPK
NI MODE
20
AV
= +8dB
SPK_
ALL ZEROS AT INPUT
15
10
10,000100010010100,000
MAX9888 toc61
MAX9888 toc64
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
Z
SPK
OUTPUT POWER PER CHANNEL (W)
Z
Z
SPK
SPK
= 8I + 68µH
0.51.01.52.002.5
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO SPEAKER)
0
V
= 200mV
-20
-40
PSRR (dB)
-60
RIPPLE
P-P
RIPPLE ON SPKLVDD,
SPKRVDD
= 4I + 33µH
= 4I + 33µH
V
= 4.2V
SPK_VDD
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
AV
= +8dB
SPK_
MAX9888 toc62
MAX9888 toc65
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
Z
SPK
OUTPUT POWER PER CHANNEL (W)
Z
= 8I + 68µH
= 4I + 33µH
SPK
V
SPK_VDD
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
AV
= +8dB
SPK_
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE (DAC TO SPEAKER)
0
RIPPLE ON SPKLVDD, SPKRVDD
= 200mV
V
-20
-40
PSRR (dB)
-60
RIPPLE
f = 1kHz
P-P
= 3.7V
1.20.8 1.00.4 0.60.201.6
1.4
MAX9888 toc63
MAX9888 toc66
SPK_VDD SUPPLY CURRENT (mA)
5
0
2.55.5
SPK_VDD SUPPLY VOLTAGE (V)
40
-80
5.04.54.03.53.0
-100
RIPPLE ON AVDD,
DVDD, HPVDD
10,000100010010100,000
FREQUENCY (Hz)
-80
-100
4.54.03.53.02.55.5
SUPPLY VOLTAGE (V)
5.0
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
CROSSTALK vs. FREQUENCY
(DAC TO SPEAKER)
0
MCLK = 12.288MHz,
-10
LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
CROSSTALK (dB)
-60
-70
-80
-90
= 8I + 68µH
Z
SPK
10100,000
FREQUENCY (Hz)
10,0001000100
FFT, -60dBFS (DAC TO SPEAKER)
0
MCLK = 12.288MHz,
LRCLK = 48kHz
-20
NI MODE
= 8I + 68µH
Z
SPK
-40
-60
-80
AMPLITUDE (dBV)
-100
-120
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
MAX9888 toc67
SPEAKER
OUTPUT
MAX9888 toc70
SOFTWARE TURN-ON/ OFF RESPONSE
(DAC TO SPEAKER, VSEN = 0)
SCL
2V/div
1V/div
10ms/div
FFT, -60dBFS (DAC TO SPEAKER)
0
MCLK = 13MHz,
LRCLK = 44.1kHz
-20
PLL MODE
= 8I + 68µH
Z
SPK
-40
-60
-80
AMPLITUDE (dbV)
-100
-120
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
MAX9888 toc68
SPEAKER
OUTPUT
MAX9888 toc71
SOFTWARE TURN-ON/ OFF RESPONSE
(DAC TO SPEAKER, VSEN = 1)
SCL
2V/div
1V/div
10ms/div
WIDEBAND FFT
(DAC TO SPEAKER)
20
10
0
-10
-20
-30
AMPLITUDE (dBm)
-40
-50
-60
1100
FREQUENCY (MHz)
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
Z
SPK
10
MAX9888 toc69
MAX9888 toc72
= 8I + 68µH
41
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
MAX9888
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
REF
DACATTN
REC
SPKLVDD
= 2.2FF, C
= 0dB, AV
= 0dB, AV
MICBIAS
SPK_
Line to Speaker
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
HPVSS
= 0dB,
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO SPEAKER)
0
Z
= 8I + 68µH
SPK
-10
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
AV
f = 1000Hz
0
SPK_
= +8dB
f = 6000Hz
f = 100Hz
OUTPUT POWER (W)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO SPEAKER)
0
V
= 200mV
RIPPLE
INPUT AC GROUNDED
-20
-40
PSRR (dB)
-60
-80
-100
RIPPLE ON AVDD,
MAX9888 toc73
0.80.60.20.4
RMS
DVDD, HPVDD
RIPPLE ON SPKLVDD,
SPKRVDD
10,000100010010100,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO SPEAKER)
0
Z
= 8I + 68µH
SPK
-10
= 1µF
C
IN
AV
= +8dB
SPK_
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
10100,000
MAX9888 toc76
P
= 0.55W
OUT
P
= 0.25W
OUT
FREQUENCY (Hz)
10,0001000100
-10
-20
-30
-40
-50
CROSSTALK (dB)
-60
-70
-80
-90
GAIN vs. FREQUENCY
(LINE TO SPEAKER)
5
Z
= 8I + 68µH
SPK
4
= 1µF
C
MAX9888 toc74
NORMALIZED GAIN (dB)
IN
3
2
1
0
-1
-2
-3
-4
-5
FREQUENCY (Hz)
CROSSTALK vs. FREQUENCY
(LINE TO SPEAKER)
0
Z
= 8I + 68µH
SPK
10100,000
FREQUENCY (Hz)
10,0001000100
MAX9888 toc75
10,000100010010100,000
MAX9888 toc77
42
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
= V
MICBIAS
DACGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
DAC to Headphone
SPKRVDD
= C
PREG
= 0dB, AV
= 3.7V. Speaker loads (Z
= C
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
MAX9888
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
MCLK = 13MHz
-10
LRCLK = 8kHz
FREQ MODE
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
R
HP
AV
HP_
f = 1000Hz
= 32I
= +3dB
f = 3000Hz
f = 100Hz
0.040.030.020.0100.05
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
-10
LRCLK = 96kHz
NI MODE
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
= 32I
R
HP
AV
HP_
f = 1000Hz
= +3dB
f = 6000Hz
f = 100Hz
0.040.030.020.0100.05
OUTPUT POWER (W)
MAX9888 toc78
THD+N RATIO (dB)
MAX9888 toc81
THD+N RATIO (dB)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
MCLK = 13MHz
-10
LRCLK = 44.1kHz
PLL MODE
-20
-30
-40
-50
-60
-70
-80
-90
= 32I
R
HP
AV
HP_
f = 1000Hz
= +3dB
f = 6000Hz
f = 100Hz
0.040.030.020.0100.05
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
-10
LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
-60
-70
-80
-90
= 16I
R
HP
AV
= +3dB
HP_
f = 1000Hz
f = 6000Hz
f = 100Hz
0.070.060.04 0.050.02 0.030.0100.08
OUTPUT POWER (W)
MAX9888 toc79
THD+N RATIO (dB)
MAX9888 toc82
THD+N RATIO (dB)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
-10
LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
-60
-70
-80
-90
= 32I
R
HP
AV
HP_
f = 1000Hz
= +3dB
f = 6000Hz
f = 100Hz
0.040.030.020.0100.05
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO SPEAKER)
0
MCLK = 13MHz
-10
LRCLK = 8kHz
FREQ MODE
-20
RHP = 32I
AV
-30
-40
-50
-60
-70
-80
-90
= +3dB
HP_
P
= 0.01W
OUT
P
= 0.02W
OUT
1010,000
FREQUENCY (Hz)
1000100
MAX9888 toc80
MAX9888 toc83
43
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
HPVSS
= 0dB,
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
MCLK = 13MHz
-10
LRCLK = 44.1kHz
PLL MODE
-20
= 32I
R
HP
-30
AV
= +3dB
HP_
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
P
= 0.025W
OUT
P
= 0.1W
OUT
10100,000
FREQUENCY (Hz)
10,0001000100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
-10
LRCLK = 48kHz
NI MODE
-20
RHP = 16I
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
-90
10100,000
P
= 0.01W
OUT
P
= 0.0.25W
OUT
FREQUENCY (Hz)
10,0001000100
TOTAL HARMONIC DISTORTION PLUS NOISE
0
-10
MAX9888 toc84
-20
-30
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
10
MAX9888 toc87
0
-10
-20
-30
-40
NORMALIZED GAIN (dB)
-50
-60
-70
vs. FREQUENCY (DAC TO HEADPHONE)
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 32I
AV
= +3dB
HP_
P
= 0.025W
OUT
P
= 0.01W
OUT
10100,000
FREQUENCY (Hz)
10,0001000100
GAIN vs. FREQUENCY
(DAC TO HEADPHONE)
MODE = 1
MODE = 0
MCLK = 13MHz
LRCLK = 8kHz
NI MODE
R
= 32I
HP
10,000100010010100,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
-10
MAX9888 toc85
LRCLK = 96kHz
-20
NI MODE
RHP = 32I
-30
AV
-40
-50
-60
THD+N RATIO (dB)
-70
-80
-90
-100
10100,000
HPVDD INPUT CURRENT vs. OUTPUT
120
100
MAX9888 toc88
80
60
40
HPVDD INPUT CURRENT (mA)
20
0
0.01100
= +3dB
HP_
P
= 0.025W
OUT
P
= 0.01W
OUT
10,0001000100
FREQUENCY (Hz)
POWER (DAC TO HEADPHONE)
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RHP = 16I
OUTPUT POWER PER CHANNEL (mW)
MAX9888 toc86
MAX9888 toc89
RHP = 32I
1010.1
44
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
-20
-40
PSRR (dB)
-60
-80
-100
SCL
2V/div
HEADPHONE
OUTPUT
0.5V/div
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
0
V
= 200mV
RIPPLE
INPUT ALL ZEROS
P-P
RIPPLE ON SPKLVDD,
SPKRVDD
RIPPLE ON AVDD,
DVDD, HPVDD
10,000100010010100,000
FREQUENCY (Hz)
SOFTWARE TURN-ON/ OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 1)
10ms/div
MAX9888 toc93
MAX9888 toc90
CROSSTALK vs. FREQUENCY
(DAC TO HEADPHONE)
-40
MCLK = 12.288MHz
LRCLK = 48kHz
-50
NI MODE
= 32I
R
HP
-60
-70
CROSSTALK (dB)
-80
-90
-100
FREQUENCY (Hz)
FFT, 0dBFS (DAC TO HEADPHONE)
0
MCLK = 13MHz,
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
-120
-140
LRCLK = 8kHz
FREQ MODE
= 32I
R
HP
020,000
FREQUENCY (Hz)
10,000100010010100,000
15,00010,0005000
MAX9888 toc91
HEADPHONE
MAX9888 toc94
SOFTWARE TURN-ON/ OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 0)
SCL
2V/div
OUTPUT
0.5V/div
10ms/div
FFT, -60dBFS (DAC TO HEADPHONE)
0
MCLK = 13MHz,
-20
LRCLK = 8kHz
FREQ MODE
-40
-60
-80
-100
AMPLITUDE (dBV)
-120
-140
-160
= 32I
R
HP
020,000
FREQUENCY (Hz)
MAX9888 toc92
MAX9888 toc95
15,00010,0005000
45
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
HPVSS
= 0dB,
FFT, 0dBFS (DAC TO HEADPHONE)
0
MCLK = 13MHz,
LRCLK = 44.1kHz
-20
PLL MODE
= 32I
R
-40
-60
-80
AMPLITUDE (dBV)
-100
-120
-140
HP
020,000
FREQUENCY (Hz)
15,00010,0005000
0
-20
-40
-60
-80
AMPLITUDE (dBV)
-100
FFT, -60dBFS (DAC TO HEADPHONE)
0
MAX9888 toc96
-20
-40
-60
-80
-100
AMPLITUDE (dBV)
-120
-140
-160
020,000
FFT, 0dBFS (DAC TO HEADPHONE)
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
= 32I
R
HP
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
= 32I
R
HP
FREQUENCY (Hz)
MAX9888 toc98
MAX9888 toc97
15,00010,0005000
46
-120
-140
020,000
FREQUENCY (Hz)
15,00010,0005000
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
FFT, -60dBFS (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
-20
LRCLK = 48kHz
NI MODE
-40
-60
-80
-100
AMPLITUDE (dBV)
-120
-140
-160
= 32I
R
HP
020,000
FREQUENCY (Hz)
WIDEBAND FFT, 0dBFS
(DAC TO HEADPHONE)
20
0
-20
-40
AMPLITUDE (dBm)
-60
FFT, 0dBFS (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
LRCLK = 96kHz
-20
MAX9888 toc99
AMPLITUDE (dbV)
-100
-120
-140
15,00010,0005000
NI MODE
= 32I
R
-40
-60
-80
HP
020,000
FREQUENCY (Hz)
15,00010,0005000
MAX9888 toc100
FFT, -60dBFS (DAC TO HEADPHONE)
0
MCLK = 2.288MHz
-20
LRCLK = 96kHz
NI MODE
-40
-60
-80
-100
AMPLITUDE (dBV)
-120
-140
-160
= 32I
R
HP
020,000
FREQUENCY (Hz)
MAX9888 toc101
15,00010,0005000
WIDEBAND FFT, -60dBFS
(DAC TO HEADPHONE)
20
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
= -3dB
A
VHP_
R
= 32I
HP
MAX9888 toc102
MCLK = 13MHz
LRCLK = 44.1kHz
0
PLL MODE
A
VHP_
-20
R
= 32I
HP
-40
AMPLITUDE (dBm)
-60
= -3dB
MAX9888 toc103
-80
-100
010,000
FREQUENCY (kHz)
-80
-100
1000100101
010,000
FREQUENCY (kHz)
1000100101
47
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
MAX9888
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
= 2.2FF, C
REF
= 0dB, AV
REC
= 0dB, AV
DACATTN
SPKLVDD
= V
MICBIAS
DACGAIN
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
Line to Headphone
SPKRVDD
= C
PREG
= 0dB, AV
= 3.7V. Speaker loads (Z
= C
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO HEADPHONE)
0
RHP = 32I
-10
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
-80
= +3dB
A
VHP_
f = 6000Hz
f = 1000Hz
f = 100Hz
00.05
OUTPUT POWER (W)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
0
V
= 200mV
-20
-40
PSRR (dB)
-60
-80
-100
RIPPLE
P-P
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON SPKLVDD,
SPKRVDD
10,000100010010100,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO HEADPHONE)
0
RHP = 32I
-10
= 1µF
C
MAX9888 toc104
THD+N RATIO (dB)
0.040.030.010.02
IN
-20
-30
-40
-50
P
-60
-70
-80
-90
10100,000
= 0.01W
OUT
P
= 0.025W
OUT
FREQUENCY (Hz)
10,0001000100
5
4
MAX9888 toc105
3
2
1
0
-1
-2
NORMALIZED GAIN (dB)
-3
-4
-5
CROSSTALK vs. FREQUENCY
(LINE TO HEADPHONE)
MAX9888 toc107
0
RHP = 32I
-10
-20
-30
-40
-50
CROSSTALK (dB)
-60
-70
-80
-90
10100,000
FREQUENCY (Hz)
10,0001000100
MAX9888 toc108
70
60
50
40
30
CMRR (dB)
20
10
0
GAIN vs. FREQUENCY
(LINE TO HEADPHONE)
RHP = 32I
= 1µF
C
IN
10,000100010010100,000
FREQUENCY (Hz)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
V
= -6dBV
OUT
= 1µF
C
IN
R
= 32I
HP
AV
= 0dB
PGAIN_
AV
= 20dB
PGAIN_
10,000100010010100,000
FREQUENCY (Hz)
MAX9888 toc106
MAX9888 toc109
48
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
= V
AVDD
between SPK_P and SPK_N. Receiver load (R
HPL or HPR to GND. R
= 1FF. AV
AV
1. T
MICPRE_
= 0dB, AV
PGAIN_
= +25NC, unless otherwise noted.)
A
HPVDD
= V
DVDD
= J, R
HP
= V
= +20dB, AV
PGAOUT_
= 0dB, AV
DVDDS1
= J, Z
REC
MICPGA_
= V
SPK
= 0dB, AV
= 0dB, AV
HP_
= +1.8V, V
DVDDS2
) connected between RECP and RECN. Headphone loads (RHP) connected from
REC
= J, C
= 2.2FF, C
REF
DACATTN
= 0dB, AV
REC
= 0dB, AV
Speaker Bypass Switch
SPKLVDD
MICBIAS
SPK_
= V
SPKRVDD
= C
DACGAIN
= 3.7V. Speaker loads (Z
= C
PREG
= 0dB, AV
REG
ADCLVL
= 1FF, C
= 0dB, AV
C1N-C1P
) connected
SPK
= 1FF, C
ADCGAIN
HPVSS
= 0dB,
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
MAX9888
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(SPEAKER BYPASS SWITCH)
0
RECEIVER AMPLIFIER DRIVING
-10
LOUDSPEAKER
Z
= 8I + 68µH
SPK
-20
-30
-40
-50
THD+N RATIO (dB)
-60
-70
f = 100Hz
-80
0
f = 1000Hz
OUTPUT POWER (W)
MAX9888 toc110
f = 6000Hz
0.150.200.100.05
OFF-ISOLATION vs. FREQUENCY
(SPEAKER BYPASS SWITCH)
0
SPEAKER AMP DRIVING LOUDSPEAKER
SPEAKER BYPASS SWITCH OPEN
-20
MEASURED AT RXIN_
-40
-60
50I LOAD ON RXIN_
ON RESISTANCE vs. V
(SPEAKER BYPASS SWITCH)
4.0
ISW = 20mA
3.5
3.0
2.5
(I)
2.0
V
= 3.0V
SPK_VDD
ON
R
1.5
1.0
0.5
0
V
= 3.7V
SPK_VDD
V
= 4.2V
SPK_VDD
V
SPK_VDD
06
V
(V)
COM
MAX9888 toc112
COM
MAX9888 toc111
= 5.0V
54123
-80
OFF-ISOLATION (dB)
-100
-120
RECEIVER AMP DRIVING RXIN_
10100,000
FREQUENCY (Hz)
10,0001000100
49
Stereo Audio CODEC
with FlexSound Technology
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
123456789
MAX9888
A
B
C
D
E
F
SPKRN
SPKRN
SPKRP
BCLKS1LRCLKS1
DVDDS1SDOUTS1
DGND
SPKRGND
MCLKIRQ
BCLKS2LRCLKS2
SPKLVDDSPKLP
SPKLVDDSPKLPSPKRGNDSPKLN
SPKRVDD
SPKRVDDSDINS1
N.C.
SPKLN
SPKLGNDSPKRPSPKLGNDHPSNS
MAX9888
N.C.INB1
SCLSDAREG
RECP/
RXINP
RECN/
RXINN
JACKSNS
HPVDDHPGND
C1PC1N
N.C.INB2
N.C.
N.C.N.C.
REF
MIC1P/
DIGMICDATA
MIC1N/
DIGMICCLK
HPVSS
HPL
HPR
INA2/
EXTMICN
INA1/
EXTMICP
MIC2P
50
SDOUTS2DVDDS2SDINS2MIC2N
G
AVDDDVDDPREG
AGNDMICBIAS
Stereo Audio CODEC
with FlexSound Technology
Pin Description
PINNAMEFUNCTION
A1, B1SPKRNNegative Right-Channel Class D Speaker Output
A2, B2SPKRGND Right-Speaker Ground
A3, B3SPKLVDD
A4, B4SPKLPPositive Left-Channel Class D Speaker Output
A5, B5SPKLNNegative Left-Channel Class D Speaker Output
A6RECP/RXINP
A7HPVDDHeadphone Power Supply. Bypass to HPGND with a 1FF capacitor.
A8HPGNDHeadphone Ground
A9HPVSSInverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
B6RECN/RXINN
B7C1P
B8C1N
B9HPLLeft-Channel Headphone Output
C1, C2SPKRPPositive Right-Channel Class D Speaker Output
C3, D3SPKRVDDRight-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor.
C4, C5SPKLGND Left-Speaker Ground
C6HPSNS
C7, D5, D7,
E3, E6, E7
C8INB2Single-Ended Line Input B2. Also positive differential line input B.
C9HPRRight-Channel Headphone Output
D1BCLKS1
D2LRCLKS1
D4SDINS1S1 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS1.
D6JACKSNSJack Sense. Detects the insertion of a jack. See the Headset Detection section.
D8INB1Single-Ended Line Input B1. Also negative differential line input B.
D9
N.C.No Connection
INA2/
EXTMICN
Left-Speaker, REF, Receiver Amplifier Power Supply. Bypass to SPKLGND with a 1FF and a 10FF
capacitor.
Positive Receiver Amplifier Output. Can be positive bypass switch input when receiver amp is shut
down.
Negative Receiver Amplifier Output. Can be negative bypass switch input when receiver amp is shut
down.
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or connect to
ground.
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the MAX9888 is in slave mode and
an output when in master mode. The input/output voltage is referenced to DVDDS1.
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and
determines whether S1 audio data is routed to the left or right channel. In TDM mode, LRCLKS1 is a
frame sync pulse. LRCLKS1 is an input when the MAX9888 is in slave mode and an output when in
master mode. The input/output voltage is referenced to DVDDS1.
Single-Ended Line Input A2. Also positive differential line input A or negative differential external
microphone input.
MAX9888
51
Stereo Audio CODEC
with FlexSound Technology
Pin Description (continued)
PINNAMEFUNCTION
E1DVDDS1S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
E2MCLKMaster Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
E4SDOUTS1S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1.
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00
MAX9888
E5IRQ
E8
E9
F1DGNDDigital Ground
F2BCLKS2
F3LRCLKS2
F4SDAI
F5SCLI
F6REGCommon-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
F7REFConverter Reference. Bypass to AGND with a 2.2FF capacitor.
F8
F9MIC2PPositive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
G1SDOUTS2S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2.
G2DVDDS2S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
G3SDINS2S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2.
G4DVDD
G5AVDDAnalog Power Supply. Bypass to AGND with a 1FF capacitor.
G6PREGPositive Internal Regulated Supply. Bypass to AGND with a 1FF capacitor.
G7AGNDAnalog Ground
G8MICBIAS
G9MIC2NNegative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
MIC1P/
DIGMICDATA
INA1/
EXTMICP
MIC1N/
DIGMICCLK
change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ
until it is cleared by reading the I
full output swing.
Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
be retasked as a digital microphone data input.
Single-Ended Line Input A1. Also negative differential line input A or positive differential external
microphone input.
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode and an
output when in master mode. The input/output voltage is referenced to DVDDS2.
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and
determines whether audio data on S2 is routed to the left or right channel. In TDM mode, LRCLKS2 is
a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode and an output when in master
mode. The input/output voltage is referenced to DVDDS2.
2
C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing.
2
C Serial-Clock Input
Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
be retasked as a digital microphone clock output.
Digital Power Supply. Supply for the digital core and I
capacitor.
Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external resistor in the 2.2kI to 1kI
range should be used to set the microphone current.
2
C status register 0x00. Connect a 10kI pullup resistor to DVDD for
2
C interface. Bypass to DGND with a 1FF
52
with FlexSound Technology
Detailed Description
The MAX9888 is a fully integrated stereo audio codec
with FlexSound technology and integrated amplifiers.
Two differential microphone amplifiers can accept signals from three analog inputs. One input can be retasked
to support two digital microphones. Any combination of
two microphones (analog or digital) can be recorded
simultaneously. The analog signals are amplified up
to 50dB and recorded by the stereo ADC. The digital
record path supports voice filtering with selectable
preset highpass filters and high stopband attenuation
/2. An automatic gain control (AGC) circuit moni-
at f
S
tors the digitized signal and automatically adjusts the
analog microphone gain to make best use of the ADC’s
dynamic range. A noise gate attenuates signals below
the user-defined threshold to minimize the noise output
by the ADC.
The IC includes two analog line inputs. One of the line
inputs can be optionally retasked as a third analog microphone input. Both line inputs support either stereo singleended input signals or mono differential signals. The line
inputs are preamplified and then routed either to the ADC
for recording or to the output amplifiers for playback.
Integrated analog switches allow two differential microphone signals to be routed out the third microphone
input to an external device. This eliminates the need
for an external analog switch in systems that have two
devices recording signals from the same microphone.
Through two digital audio interfaces, the device can
transmit one stereo audio signal and receive two stereo
audio signals in a wide range of formats including I
PCM, and up to four mono slots in TDM. Each interface
can be connected to either of two audio ports (S1 and
S2) for communication with external devices. Both audio
interfaces support 8kHz to 96kHz sample rates. Each
input signal is independently equalized using 5-band
parametric equalizers. A multiband automatic level
control (ALC) boosts signals by up to 12dB. One signal
path additionally supports the same voiceband filtering
as the ADC path.
The IC includes a differential receiver amplifier, stereo
Class D speaker amplifiers, and DirectDrive true ground
stereo headphone amplifiers.
2
S,
Stereo Audio CODEC
When the receiver amplifier is disabled, analog switches
allow RECP/RXINP and RECN/RXINN to be reused for
signal routing. In systems where a single transducer is
used for both the loudspeaker and receiver, an external receiver amplifier can be routed to the left speaker
through RECP/RXINP and RECN/RXINN, bypassing the
Class D amplifier, to connect to the loudspeaker. If the
internal receiver amplifier is used, then leave RECP/
RXINP and RECN/RXINN unconnected. In systems
where an external amplifier drives both the receiver and
the MAX9888’s input, one of the differential signals can
be disconnected from the receiver when not needed
by passing it through the analog switch that connects
RECP/RXINP to RECN/RXINN.
The stereo Class D amplifier provides efficient amplification for two speakers. The amplifier includes active
emissions limiting to minimize the radiated emissions
(EMI) traditionally associated with Class D. In most
systems, no output filtering is required to meet standard
EMI limits.
To optimize speaker sound quality, the IC includes an
excursion limiter, a distortion limiter, and a power limiter.
The excursion limiter is a dynamic highpass filter with
variable corner frequency that increases in response
to high signal levels. Low-frequency energy typically
causes more distortion than useful sound at high signal levels, so attenuating low frequencies allows the
speaker to play louder without distortion or damage. At
lower signal levels, the filter corner frequency reduces
to pass more low frequency energy when the speaker
can handle it. The distortion limiter reduces the volume
when the output signal exceeds a preset distortion level.
This ensures that regardless of input signal and battery
voltage, excessive distortion is never heard by the user.
The power limiter monitors the continuous power into the
loudspeaker and lowers the signal level if the speaker is
at risk of overheating.
The stereo DirectDrive headphone amplifier uses an
inverting charge pump to generate a ground-referenced
output signal. This eliminates the need for DC-blocking
capacitors or a midrail bias for the headphone jack
ground return. Ground sense reduces output noise
caused by ground return current.
The IC integrates jack detection allowing the detection
of insertion and removal of accessories as well as button
presses.
MAX9888
53
Stereo Audio CODEC
with FlexSound Technology
I2C Slave Address
Configure the MAX9888 using the I2C control bus. The
IC uses a slave address of 0x20 or 00100000 for write
operations and 0x21 or 00100001 for read operations.
2
See the I
C Serial Interface section for a complete inter-
face description.
Table 1 lists all of the registers, their addresses, and
power-on-reset states. Registers 0x00 to 0x03 and 0xFF
are read-only while all of the other registers are read/
write. Write zeros to all unused bits in the register table
when updating the register, unless otherwise noted.
The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply
current.
Table 2. Power Management Registers
REGISTERBITNAMEDESCRIPTION
Global Shutdown
Disables everything except the headset detection circuitry, which is controlled
separately.
0 = Device shutdown
1 = Device enabled
Line Input A Enable
0 = Disabled
1 = Enabled
Line Input B Enable
0 = Disabled
1 = Enabled
Microphone Bias Enable
0 = Disabled
1 = Enabled
Left ADC Enable
0 = Disabled
1 = Enabled
Right ADC Enable
0 = Disabled
1 = Enabled
Left Headphone Enable
0 = Disabled
1 = Enabled
Right Headphone Enable
0 = Disabled
1 = Enabled
Left Speaker Enable
0 = Disabled
1 = Enabled
Right Speaker Enable
0 = Disabled
1 = Enabled
Receiver Enable
0 = Disabled
1 = Enabled
Left DAC Enable
0 = Disabled
1 = Enabled
Right DAC Enable
0 = Disabled
1 = Enabled
0x4C
0x4A
0x4B
7
6VBATENSee the Battery Measurement section.
1JDWKSee the Headset Detection section.
7INAEN
6INBEN
3MBEN
1ADLEN
0ADREN
7HPLEN
6HPREN
5SPLEN
4SPREN
3RECEN
1DALEN
0DAREN
SHDN
MAX9888
59
Stereo Audio CODEC
with FlexSound Technology
Microphone Inputs
The device includes three differential microphone inputs
and a low-noise microphone bias for powering the microphones (Figure 6). One microphone input can also be configured as a digital microphone input accepting signals
from up to two digital microphones. Two microphones,
analog or digital, can be recorded simultaneously.
In the typical application, one microphone input is used
MAX9888
for the handset microphone and the other is used as an
accessory microphone. In systems using a background
noise microphone, INA can be retasked as another
microphone input.
In systems where the codec is not the only device
recording microphone signals, connect microphones to
MICBIAS
MIC1P/
DIGMICDATA
MIC1N/
DIGMICCLK
REG
MBEN
MCLK
PSCLK
CLOCK
CONTROL
MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N
then become outputs that route the microphone signals
to an external device as needed. Two devices can then
record microphone signals without needing external
analog switches.
Analog microphone signals are amplified by two stages
of gain and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable-gain amplifier (PGA) adjustable
from 0dB to 20dB in 1dB steps. To maximize the signalto-noise ratio, use the gain in the first stage whenever
possible. Zero-crossing detection is included on the PGA
to minimize zipper noise while making gain changes.
Select a frequency that is within the digital microphone’s clock frequency range.
Set OSR1 = 1 when using a digital microphone.
00 = PCLK/8
01 = PCLK/6
10 = 64 x LRCLK
11 = Reserved
Left Digital Microphone Enable
Set PAL1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
Right Digital Microphone Enable
Set PAR1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
External Microphone Connection
Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using
INA_/EXTMIC_ as a microphone input.
00 = Disabled
01 = MIC1 input
10 = MIC2 input
11 = Reserved
MAX9888
61
Stereo Audio CODEC
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Table 3. Microphone Input Registers (continued)
REGISTERBITNAMEDESCRIPTION
INA_/EXTMIC_ to MIC1_ Bypass Switch
7INABYP
4MIC2BYP
MAX9888
0x48
1RECBYP
0SPKBYP
0 = Disabled
1 = Enabled
MIC1_ to MIC2_ Bypass Switch
0 = Disabled
1 = Enabled
See the Output Bypass Switches section.
Line Inputs
The device includes two sets of line inputs (Figure 7).
Each set can be configured as a stereo single-ended
input or as a mono differential input. Each input includes
adjustable gain to match a wide range of input signal
levels. If a custom gain is needed, the external gain
mode provides a trimmed feedback resistor. Set the gain
INABYP
PGAINA:
INA1/
EXTMICP
INA2/
EXTMICN
INB1
INB2
+20dB TO -6dB
PGAINA:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
INADIFF
INBDIFF
MIX
MIXOUT1
MIX
MIXOUT2
MIX
MIXOUT3
by choosing the appropriate input resistor and using the
following formula:
AV
= 20 x log (20K/RIN)
PGAIN
The external gain mode also allows summing multiple
signals into a single input, by connecting multiple input
resistors as show in Figure 8, and inputting signals larger
than 1V
P-P
LEFT
INPUT 1
LEFT
INPUT 2
RIGHT
INPUT 1
RIGHT
INPUT 2
.
20kI
INA1/EXTMICP
VCM
20kI
INA2/EXTMICN
VCM
Figure 7. Line Input Block Diagram
62
Figure 8. Summing Multiple Input Signals into INA/INB
Stereo Audio CODEC
with FlexSound Technology
Table 4. Line Input Registers
REGISTERBITNAMEDESCRIPTION
Line Input A/B External Gain
Switches out the internal input resistor and selects a trimmed 20kI feedback resistor.
Use an external input resistor to set the gain of the line input.
0 = Disabled
1 = Enabled
The device’s stereo ADC accepts input from the microphone amplifiers and line inputs. The ADC mixer routes
any combination of the six audio inputs to the left and
right ADCs (Figure 9).
PGAM1:
+20dB TO 0dB
PA1EN:
0/20/30dB
PGAM2:
+20dB TO 0dB
PA2EN:
0/20/30dB
PGAINA:
+20dB TO -6dB
INADIFF
PGAINA:
+20dB TO -6dB
+
PGAINB:
+20dB TO -6dB
INBDIFF
PGAINB:
+20dB TO -6dB
+
Figure 9. ADC Input Mixer Block Diagram
MIX
MIXADL
MIX
MIXADR
ADLEN
ADCL
ADCR
ADREN
63
Stereo Audio CODEC
with FlexSound Technology
Table 5. ADC Input Mixer Register
REGISTERBITNAMEDESCRIPTION
7
6
5
0x22/0x23
MAX9888
4
3
2
1
0
MIXADL/MIXADR
Left/Right ADC Input Mixer
Selects which analog inputs are recorded by the left/right ADC.
1xxxxxxx = MIC1
x1xxxxxx = MIC2
xx1xxxxx = Reserved
xxx1xxxx = Reserved
xxxx1xxx = INA1
xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1)
xxxxxx1x = INB1
xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
Record Path Signal Processing
The device’s record signal path includes both automatic
gain control (AGC) for the microphone inputs and a digital noise gate at the output of the ADC (Figure 10).
Microphone AGC
The IC’s AGC monitors the signal level at the output of
the ADC and then adjusts the MIC1 and MIC2 analog
PGA settings automatically. When the signal level is
below the predefined threshold, the gain is increased up
to its maximum (20dB). If the signal exceeds the threshold, the gain is reduced to prevent the output signal level
exceeding the threshold. When AGC is enabled, the
microphone PGA is not user programmable. The AGC
provides a more constant signal level and improves the
available ADC dynamic range.
PGAM1:
+20dB TO -6dB
AUTOMATIC
PA1EN:
0/20/30dB
+20dB TO 0dB
PA2EN:
0/20/30dB
PGAM2:
MIX
MIXADL
MIX
MIXADR
ADLEN
ADREN
CONTROL
ADCL
ADCR
Figure 10. Record Path Signal Processing Block Diagram
GAIN
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
NOISE GATE
AUDIO/
VOICE
FILTERS
MODE1
AVFLT
Noise Gate
Since the AGC increases the levels of all signals below
a user-defined threshold, the noise floor is effectively
increased by 20dB. To counteract this, the noise gate
reduces the gain at low signal levels. Unlike typical noise
gates that completely silence the output below a defined
level, the noise gate in the IC applies downward expansion. The noise gate attenuates the output at a rate of
1dB for each 2dB the signal is below the threshold.
The noise gate can be used in conjunction with the AGC
or on its own. When the AGC is enabled, the noise gate
reduces the output level only when the AGC has set the
gain to the maximum setting. Figure 11 shows the gain
response resulting from using the AGC and noise gate.
AGC AND NOISE GATE
AMPLITUDE RESPONSE
0
-20
AGC AND NOISE GATE
-40
-60
-80
OUTPUT AMPLITUDE (dBFS)
-100
-120
-1200
Figure 11. AGC and Noise Gate Input vs. Output Gain
AGC ONLY
AGC AND NOISE
GATE DISABLED
NOISE GATE ONLY
-20-40-60-80-100
INPUT AMPLITUDE (dBFS)
64
Stereo Audio CODEC
with FlexSound Technology
Table 6. Record Path Signal Processing Registers
REGISTERBITNAMEDESCRIPTION
Noise Gate Attenuation
Reports the current noise gate attenuation.
000 = 0dB
001 = 1dB
010 = 2dB
011 = 3dB to 5dB
100 = 6dB to 7dB
101 = 8dB to 9dB
110 = 10dB to 11dB
111 = 12dB
Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on
both channels regardless of the AGCSRC setting.
0 = Left ADC output
1 = Maximum of either the left or right ADC output
AGC Release Time
Defined as the duration from start to finish of gain increase in the region shown in Figure
Table 6. Record Path Signal Processing Registers (continued)
REGISTERBITNAMEDESCRIPTION
AGC Attack Time
3
MAX9888
0x3D
0x3E
2
1
0
7
6
5
4
3
2
1
0
AGCATK
AGCHLD
ANTH
AGCTH
Defined as the time required to reduce gain by 63% of the total gain reduction (one time
constant of the exponential response). Attack times are longer for low AGC threshold
levels. See Figure 12 for details.
00 = 2ms
01 = 7.2ms
10 = 31ms
11 = 123ms
AGC Hold Time
The delay before the AGC release begins. The hold time counter starts whenever the
signal drops below the AGC threshold and is reset by any signal that exceeds the
threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details.
00 = AGC disabled
01 = 50ms
10 = 100ms
11 = 400ms
Noise Gate Threshold
Gain is reduced for signals below the threshold to quiet noise. The thresholds are relative
to the ADC’s full-scale output voltage.
The IC includes separate digital level control for the left
and right ADC outputs (Figure 13). To optimize dynamic
ADLEN
ADCL
range, use analog gain to adjust the signal level and set
the digital level control to 0dB whenever possible. Digital
level control is primarily used when adjusting the record
level for digital microphones.
Enable sidetone during full-duplex operation to add a
low-level copy of the recorded audio signal to the playback audio signal (Figure 14). Sidetone is commonly
DVST:
0dB TO -60dB
ADLEN
ADREN
ADCL
ADCR
SIDETONE
AUTOMATIC
GAIN
CONTROL
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
DSTS
NOISE GATE
MIX
AUDIO/
VOICE
FILTERS
MODE1
AVFLT
+
5-BAND
PARAMETRIC
EQ
used in telephony to allow the speaker to hear himself
speak, providing a more natural user experience. The
IC implements sidetone digitally. Doing so helps prevent
unwanted feedback into the playback signal path and
better matches the playback audio signal.
DV1G:
0/6/12/18dB
MULTIBAND ALC
DVEQ1:
0dB TO -15dB
EQ1ENEQ2EN
EXCURSION LIMITER
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
DCB2
MODE1
DVFLT
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
MIXDAL
MIX
MIXDAR
MIX
DACL
DALEN
DACR
DAREN
Figure 14. Sidetone Block Diagram
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Stereo Audio CODEC
with FlexSound Technology
Table 8. Sidetone Register
REGISTERBITNAMEDESCRIPTION
Sidetone Source
Selects which ADC output is fed back as sidetone. When mixing the left and right ADC
outputs, each is attenuated by 6dB to prevent full-scale signals from clipping.
00 = Sidetone disabled
01 = Left ADC
10 = Right ADC
11 = Left + Right ADC
Sidetone Level
Adjusts the sidetone signal level. All levels are referenced to the ADC’s full-scale output.
The IC includes two separate playback signal paths and
one record signal path. Digital audio interface 1 (DAI1)
is used to transmit the recorded stereo audio signal and
receive a stereo audio signal for playback. Digital audio
interface 2 (DAI2) is used to receive a second stereo
audio signal. Use DAI1 for all full-duplex operations and
for all voice signals. Use DAI2 for music and to mix two
playback audio signals. The digital audio interfaces are
separate from the audio ports to enable either interface
to communicate with any external device connected to
the audio ports.
Each audio interface can be configured in a variety of
2
formats including left justified, I
S, PCM, and time division multiplexed (TDM). TDM mode supports up to 4
mono audio slots in each frame. The IC can use up to
2 mono slots per interface, leaving the remaining two
slots available for another device. Table 9 shows how to
configure the device for common digital audio formats.
Figures 16 and 17 show examples of common audio
formats. By default, SDOUTS1 and SDOUTS2 are set
high impedance when the IC is not outputting data to
facilitate sharing the bus. Configure the interface in TDM
mode using only slot 1 to transmit and receive mono
PCM voice data.
The IC’s digital audio interfaces support both ADC to
DAC loop-through and digital loopback. Loop-through
allows the signal converted by the ADC to be routed
to the DAC for playback. The signal is routed from the
record path to the playback path in the digital audio
interface to allow the IC’s full complement of digital
signal processing to be used. Loopback allows digital
69
Stereo Audio CODEC
with FlexSound Technology
data input to either SDINS1 or SDINS2 to be routed
from one interface to the other for output on SDOUTS2
or SDOUTS1. Both interfaces must be configured for
the same sample rate, but the interface format need
not be the same. This allows the IC to route audio data
from one device to another, converting the data format
as needed. Figure 15 shows the available digital signal
routing options.
In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2
7MAS1/MAS2
6WCI1/WCI2
5BCI1/BCI2
0x14/0x1C
4DLY1/DLY2
2TDM1/TDM2
1FSW1/FSW2
0WS1/WS2
accept LRCLK and BCLK as inputs.
0 = Slave mode
1 = Master mode
DAI1/DAI2 Word Clock Invert
TDM1/TDM2 = 0:
0 = Left-channel data is transmitted while LRCLK is low.
1 = Right-channel data is transmitted while LRCLK is low.
TDM1/TDM2 = 1:
Always set WCI = 0.
DAI1/DAI2 Bit Clock Invert
BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1.
0 = SDIN is accepted on the rising edge of BCLK.
SDOUT is valid on the rising edge of BCLK.
1 = SDIN is accepted on the falling edge of BCLK.
SDOUT is valid on the falling edge of BCLK.
Master Mode:
0 = LRCLK transitions on the falling edge of BCLK.
1 = LRCLK transitions on the rising edge of BCLK.
DAI1/DAI2 Data Delay
DLY1/DLY2 has no effect when TDM1/TDM2 = 1.
0 = The most significant data bit is clocked on the first active BCLK edge after an
LRCLK transition.
1 = The most significant data bit is clocked on the second active BCLK edge after an
LRCLK transition.
DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode)
Set TDM1/TDM2 when communicating with devices that use a frame synchronization
pulse on LRCLK instead of a square wave.
0 = Disabled
1 = Enabled (BCI1/BCI2 must be set to 1)
DAI1/DAI2 Wide Frame Sync Pulse
Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 =
1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0.
0 = Disabled
1 = Enabled
DAI1/DAI2 Audio Data Bit Depth
Determines the maximum bit depth of audio being transmitted and received. Data is
always 16 bit when TDM1/TMD2 = 0.
0 = 16 bits
1 = 24 bits
Stereo Audio CODEC
MAX9888
71
Stereo Audio CODEC
with FlexSound Technology
Table 10. Digital Audio Interface Registers (continued)
REGISTERBITNAMEDESCRIPTION
ADC Oversampling Ratio
Use the higher setting for maximum performance. Use the lower setting for reduced
power consumption at the expense of performance.
00 = 96x
01 = 64x
10 = Reserved
11 = Reserved
DAI1/DAI2 BCLK Output Frequency
When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When
operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK
frequency that clocks all data input to the DAC and output by the ADC.
000 = BCLK disabled
001 = 64 x LRCLK
010 = 48 x LRCLK
011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1)
100 = PCLK/2
101 = PCLK/4
110 = PCLK/8
111 = PCLK/16
DAI1/DAI2 Audio Port Selector
Selects which port is used by DAI1/DAI2.
00 = None
01 = Port S1
10 = Port S2
11 = Reserved
DAI1 Digital Loopthrough
Connects the output of the record signal path to the input of the playback path. Data
input to DAI1 from an external device is mixed with the recorded audio signal.
0 = Disabled
1 = Enabled
DAI1/DAI2 Digital Audio Interface Loopback
LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the
digital audio input to DAI2 back out on DAI1. Selecting LBEN2 disables the ADC
output data.
0 = Disabled
1 = Enabled
DAI1/DAI2 DAC Mono Mix
Mixes the left and right digital input to mono and routes the combined signal to the left
and right playback paths. The left and right input data is attenuated by 6dB prior to the
mono mix.
0 = Disabled
1 = Enabled
MAX9888
0x15/0x1D
0x16/0x1E
7
OSR1
6
2
1
0
7
6
5LTEN1
4
3
BSEL1/
BSEL2
SEL1/SEL2
LBEN1/
LBEN2
DMONO1/
DMONO2
72
Stereo Audio CODEC
with FlexSound Technology
Table 10. Digital Audio Interface Registers (continued)
REGISTERBITNAMEDESCRIPTION
Disable DA1/DAI2 Output High-Impedance Mode
Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to
force a level on SDOUT at all times.
0 = Disabled
1 = Enabled
DAI1/DAI2 Record Path Output Enable
DAI2 outputs data only if LBEN1 = 1.
0 = Disabled
1 = Enabled
DAI1/DAI2 Playback Path Input Enable
0 = Disabled
1 = Enabled
TDM Left Time Slot
Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
11 = Slot 4
TDM Right Time Slot
Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
11 = Slot 4
TDM Slot Delay
Adds 1 BCLK cycle delay to the data in the specified TDM slot.
1xxx = Slot 4 delayed
x1xx = Slot 3 delayed
xx1x = Slot 2 delayed
xxx1 = Slot 1 delayed
The digital signal paths in the IC require a master
clock (MCLK) between 10MHz and 60MHz to function. Internally, the MAX9888 requires a clock between
10MHz and 20MHz. A prescaler divides MCLK by 1, 2,
or 4 to create the internal clock (PCLK). PCLK is used to
clock all portions of the IC.
The MAX9888 includes two digital audio signal paths,
MAX9888
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, three main clocking modes are
supported:
PLL Mode: When operating in slave mode, enable
U
the PLL to lock onto any LRCLK input. This mode
requires the least configuration, but provides the
lowest performance. Use this mode to simplify initial
setup or when normal mode and exact integer mode
cannot be used.
Normal Mode: This mode uses a 15-bit clock divider
U
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequencies and can be used in either master or slave mode.
Exact Integer Mode (DAI1 only): In both master and
U
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
Table 11. Clock Control Registers
REGISTERBITNAMEDESCRIPTION
MCLK Prescaler
0x10
0x11/0x19
5
PSCLK
4
7
6
SR1/SR2
5
4
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz P MCLK P 20MHz (PCLK = MCLK)
10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2)
11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4)
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio.
0x11
0x12/0x1A
0x13/0x1B
3
2
1
7PLL1/PLL2
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0NI1[0]/NI2[0]
FREQ1
NI1/
NI2
VALUESAMPLE RATEVALUESAMPLE RATE
0x0Disabled0x8
0x1Reserved0x9
0x2Reserved0xA
0x3Reserved0xB
0x4Reserved0xC
0x5Reserved0xD
0x6Reserved0xE
0x7Reserved0xF
PLL Mode Enable (Slave Mode Only)
PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK
frequency and automatically sets the LRCLK divider (NI1/NI2).
0 = Disabled
1 = Enabled
Normal Mode LRCLK Divider
When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12
for common NI values.
SAMPLE RATEDHF1/DHF2NI1/NI2 FORMULA
8kHz P LRCLK P 48kHz0
48kHz < LRCLK P 96kHz1
= LRCLK frequency
f
LRCLK
f
= Prescaled MCLK frequency (PCLK)
PCLK
Rapid Lock Mode
Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1
to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically
adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is
much closer to the correct value, thus speeding up lock time. Wait one LRCLK period
after programming NI1/NI2 before setting PLL1/PLL2 = 1.
Note: Values in bold are exact integers that provide maximum full-scale performance.
DHF1/2 = 0DHF1/2 = 1
3000
2C1A
2000
15551D66
343F45A9
30004000
22D42E71
2000
2AAB3ACD
6000
5833
4000
687D45A9
60004000
45A92E71
4000
2AAB3ACD
6000
5833
4000
687D
6000
45A9
4000
Passband Filtering
Each digital signal path in the IC includes options for
defining the path bandwidth (Figure 18). The playback
and record paths connected to DAI1 support both voice
and music filtering while the playback path connected to
DAI2 supports music filtering only.
The voice IIR filters provide greater than 70dB stopband
attenuation at frequencies above f
/2 to reduce aliasing.
S
Three selectable highpass filters eliminate unwanted
low-frequency signals.
DVST:
0dB TO -60d B
ADLEN
ADREN
ADCL
ADCR
SIDETONE
AUTOMATIC
GAIN
CONTROL
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
DSTS
NOISE GATE
MIX
AUDIO/
VOICE
FILTERS
MODE1
AVFLT
+
5-BAND
PARAMETRIC
EQ
Use music mode when processing high-fidelity audio
content. The music FIR filters reduce power consumption and are linear phase to maintain stereo imaging.
An optional DC-blocking filter is available to eliminate
unwanted DC offset.
In music mode, a second set of FIR filters are available
to support sample rates greater than 50kHz. The filters
can be independently selected for DAI1 and DAI2 and
support both the playback and record audio paths.
DV1G:
0/6/12/18dB
MULTIBAND ALC
DVEQ1:
0dB TO -15dB
EQ1ENEQ2EN
EXCURSION LIMITER
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
DCB2
MODE1
DVFLT
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
MIXDAL
MIX
MIXDAR
MIX
DACL
DALEN
DACR
DAREN
Figure 18. Digital Passband Filtering Block Diagram
78
Stereo Audio CODEC
with FlexSound Technology
Table 13. Passband Filtering Registers
REGISTERBITNAMEDESCRIPTION
DAI1 Passband Filtering Mode
0 = Voice filters
1 = Music filters (recommended for f
DAI1 ADC Highpass Filter Mode
MODE1AVFLT1
0See Table 14
1Select a nonzero value to enable the DC-blocking filter
DAI1 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz P LRCLK < 96kHz
> 24kHz)
S
0x18
7MODE1
6
5
4
3DHF1
AVFLT1
MAX9888
0x20
2
1
0
3DHF2
0DCB2
DVFLT1
DAI1 DAC Highpass Filter Mode
MODE1DVFLT1
0See Table 14
1Select a nonzero value to enable the DC-blocking filter
DAI2 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz < LRCLK P 96kHz
DAI2 DC Blocking Filter
Enables a DC-blocking filter on the DAI2 playback audio path.
0 = Disabled
1 = Enabled
The IC playback signal path includes automatic level
control (ALC) and a 5-band parametric equalizer (EQ)
(Figure 19). The DAI1 and DAI2 playback paths include
separate ALCs controlled by a single set of registers.
Two completely separate parametric EQs are included
for the DAI1 and DAI2 playback paths.
Automatic Level Control
The automatic level control (ALC) circuit ensures maximum signal amplitude without producing audible clipping. This is accomplished by a variable gain stage that
works on a sample by sample basis to increase the gain
up to 12dB. A look-ahead circuit determines if the next
sample exceeds full scale and reduces the gain so that
the sample is exactly full scale.
A programmable low signal threshold determines the
minimum signal amplitude that is amplified. Select a
threshold that prevents the amplification of background
noise. When the signal level drops below the low signal
threshold, the ALC reduces the gain to 0dB until the signal increases above the threshold. Figure 20 shows an
example of ALC input vs. output curves.
Stereo Audio CODEC
The ALC can optionally be configured in dual-band
mode. In this mode, the input signal is filtered into two
bands with a 5kHz center frequency. Each band is
routed through independent ALCs and then summed
together. In multiband mode, both bands use the same
parameters.
OUTPUT SIGNAL
(dBFS)
0
INPUT
SIGNAL
(dBFS)
OUTPUT SIGNAL
(dBFS)
0
LOW-LEVEL
THRESHOLD
ALC W ITH ALCTH ≠ 000
-120
MAX9888
DV1G:
0/6/12/18dB
+
MULTIBAND ALC
DVEQ1:
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
EQ1ENEQ2EN
EXCURSION LIMITER
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
FILTERS
DCB2
FILTERS
MODE1
DVFLT
AUDIO/
AUDIO/
VOICE
MIXDAL
MIX
MIXDAR
MIX
DACL
DALEN
DACR
DAREN
INPUT
SIGNAL
(dBFS)
INPUT
SIGNAL
(dBFS)
OUTPUT SIGNAL
(dBFS)
0
LOW-LEVEL
THRESHOLD
ALC W ITH ALCTH = 000
LOW-LEVEL
THRESHOLD
ALC D ISABLED
-120
-120
Figure 20. ALC Input vs. Output ExamplesFigure 19. Playback Path Signal Processing Block Diagram
81
Stereo Audio CODEC
with FlexSound Technology
Table 15. Automatic Level Control Registers
REGISTERBITNAMEDESCRIPTION
ALC Enable
7ALCEN
MAX9888
6
5
0x41
4
3ALCMB
2
1
0
ALCRLS
ALCTH
Enables ALC on both the DAI1 and DAI2 playback paths.
0 = Disabled
1 = Enabled
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Excursion
Limiter section for Excursion Limiter release times. ALC release time is defined as the
time required to adjust the gain from 12dB to 0dB.
Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be
configured properly to achieve the correct center frequency for each playback path.
0 = Single-band ALC
1 = Dual-band ALC
Low Signal Threshold
Selects the minimum signal level to be boosted by the ALC.
000 = -JdB (low-signal threshold disabled)
001 = -12dB
010 = -18dB
011 = -24dB
100 = -30dB
101 = -36dB
110 = -42dB
111 = -48dB
Parametric Equalizer
The parametric EQ contains five independent biquad
filters with programmable gain, center frequency, and
bandwidth. Each biquad filter has a gain range of Q12dB
and a center frequency range from 20Hz to 20kHz. Use a
filter Q less than that shown in Figure 21 to achieve ideal
frequency responses. Setting a higher Q results in nonideal frequency response. The biquad filters are series
connected, allowing a total gain of Q60dB.
82
1000
fs = 8kHz
100
10
1
MAXIMUM RECOMMENDED FILTER Q
0.1
100100,000
Figure 21. Maximum Recommended Filter Q vs. Frequency
CENTER FREQUENCY (Hz)
fs = 48kHz
fs = 96kHz
10,0001000
Stereo Audio CODEC
with FlexSound Technology
Use the attenuator at the EQ’s input to avoid clipping
the signal. The attenuator can be programmed for fixed
attenuation or dynamic attenuation based on signal level.
If the dynamic EQ clip detection is enabled, the signal
level from the EQ is fed back to the attenuator circuit to
determine the amount of gain reduction necessary to
avoid clipping.
Table 16. EQ Registers
REGISTERBITNAMEDESCRIPTION
DAI1/DAI2 EQ Clip Detection
Automatically controls the EQ attenuator to prevent clipping in the EQ.
0 = Enabled
1 = Disabled
DAI1/DAI2 EQ Attenuator
Provides attenuation to prevent clipping in the EQ when full-scale signals are boosted. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2
= 1.
The MAX9888 EV kit software includes a graphic interface for generating the EQ coefficients. The coefficients
are sample rate dependent and stored in registers 0x50
through 0xB3.
MAX9888
0x47
7
6
5
1EQ2EN
0EQ1EN
VS2EN
VSEN
ZDEN
See the Click-and-Pop Reduction section.
DAI2 EQ Enable
0 = Disabled
1 = Enabled
DAI1 EQ Enable
0 = Disabled
1 = Enabled
83
Stereo Audio CODEC
with FlexSound Technology
Playback Level Control
The IC includes separate digital level control for the DAI1
and DAI2 playback audio paths. The DAI1 signal path
DV1G:
0/6/12/18dB
MAX9888
+
MULTIBAND ALC
DVEQ1:
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
EQ1ENEQ2EN
EXCURSION LIMITER
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
allows boost when MODE1 = 0 and attenuation in any
mode. The DAI2 signal path allows attenuation only.
MIXDAL
DACL
DALEN
DACR
DAREN
AUDIO/
FILTERS
DCB2
AUDIO/
FILTERS
MODE1
DVFLT
VOICE
MIX
MIXDAR
MIX
Figure 22. Playback Level Control Block Diagram
Table 17. DAC Playback Level Control Register
REGISTERBITNAMEDESCRIPTION
DAI1/DAI2 Mute
0 = Disabled
1 = Enabled
DAI1 Voice Mode Gain
DV1G only applies when MODE1 = 0.
00 = 0dB
01 = 6dB
10 = 12dB
11 = 18dB
The IC’s stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and
right DACs (Figure 23).
DV1G:
0/6/12/18dB
+
MULTIBAND ALC
MAX9888
DVEQ1:
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
EQ1ENEQ2EN
EXCURSION LIMITER
PARAMETRIC
DVEQ2:
0dB TO -15dB
5-BAND
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
AUDIO/
FILTERS
DCB2
AUDIO/
VOICE
FILTERS
MODE1
DVFLT
MIXDAL
MIX
MIXDAR
MIX
Figure 23. DAC Input Mixer Block Diagram
Table 18. DAC Input Mixer Register
REGISTERBITNAMEDESCRIPTION
0x21
7
6
5
MIXDAL
4
3
2
1
MIXDAR
0
Left DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
Right DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
DACL
DALEN
DACR
DAREN
85
Stereo Audio CODEC
with FlexSound Technology
Preoutput Signal Path
The IC’s preoutput mixer stage provides mixing and level adjustment for line input signals routed to the output amplifiers. Figure 24 shows a block diagram of the preoutput signal path. 9dB is added between the line input amplifiers
and the output amplifiers to boost the 1V
maximum line input signal level to the 1V
P-P
maximum DAC signal level.
RMS
MAX9888
+
+
PGAINA:
+20dB TO -6dB
INADIFF
PGAINA:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
INBDIFF
MIX
MIXOUT1
MIX
MIXOUT2
MIX
MIXOUT3
PGAOUT1:
0dB TO -23d B
PGAOUT2:
0dB TO -23d B
PGAOUT3:
0dB TO -23d B
PREOUT1
PREOUT2
PREOUT3
+9dB
+9dB
+9dB
MIX
MIXREC
MIX
MIXSPL
MIX
MIXSPR
RECVOL:
+8dB TO -62dB
SPVOLL:
+8dB TO -62dB
SPVOLR:
+8dB TO -62dB
MIX
MIXHPL
MIX
MIXHPR
0dB
RECEN
BATTERY ADC
+6dB
SPLEN
DISTORTION LIMITER
+6dB
SPREN
HPVOLL:
+3dB TO -67dB
HPLEN
HPVOLR:
+3dB TO -67dB
HPREN
RECBYP
SPKBYP
POWER/
RECP/
RXINP
RECN/
RXINN
SPKLVDD
SPKLP
SPKLN
SPKLGND
SPKRVDD
SPKRP
SPKRN
SPKRPGND
HPL
HPSNS
HPR
Figure 24. Preoutput Signal Path Block Diagram
Preoutput Mixer
The IC’s output amplifiers each accept input from one of the three preoutput mixers. Configure each preoutput mixer to mix any combination of the four line input signals.
The IC’s preoutput PGAs allow line input signals to be attenuated to match DAC output signal levels. Use the 0dB
setting for maximum performance.
Table 20. Preoutput PGA Registers
REGISTERBITNAMEDESCRIPTION
3
2
0x35/0x36/
0x37
1
0
PGAOUT1/
PGAOUT2/
PGAOUT3
The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive 32I receivers. In
cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route the receiver
amplifier output to the left speaker outputs.
The IC’s receiver amplifier accepts input from the stereo DAC and the line inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals,
9.5dB for 3 signals, or 12dB for 4 signals.
Table 21. Receiver Output Mixer Register
REGISTERBITNAMEDESCRIPTION
MAX9888
0x28
3
2
1
0
MIXREC
Receiver Output Volume
Table 22. Receiver Output Level Register
REGISTERBITNAMEDESCRIPTION
7RECM
4
3
0x3A
2
RECVOL
1
0
Receiver Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Preoutput mixer 1
xxx1 = Preoutput mixer 2
Receiver Output Mute
0 = Disabled
1 = Enabled
Receiver Output Volume Level
VALUEVOLUME (dB)VALUEVOLUME (dB)
0x00-620x10-10
0x01-580x11-8
0x02-540x12-6
0x03-500x13-4
0x04-460x14-2
0x05-420x150
0x06-380x16+1
0x07-350x17+2
0x08-320x18+3
0x09-290x19+4
0x0A-260x1A+5
0x0B-230x1B+6
0x0C-200x1C+6.5
0x0D-170x1D+7
0x0E-140x1E+7.5
0x0F-120x1F+8
88
with FlexSound Technology
Speaker Amplifiers
The IC integrates a stereo filterless Class D amplifier that
offers much higher efficiency than Class AB without the
typical disadvantages.
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current
steering switches and consume negligible additional
power. Any power loss associated with the Class D output stage is mostly due to the I
on-resistance, and quiescent current overhead.
2
R loss of the MOSFET
Stereo Audio CODEC
MAX9888
The theoretical best efficiency of a linear amplifier is
78%, however, that efficiency is only exhibited at peak
output power. Under normal operating levels (typical
music reproduction levels), efficiency falls below 30%,
whereas the IC’s Class D amplifier still exhibits 80% efficiency under the same conditions.
Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B and FCC
electromagnetic-interference (EMI) regulation standards.
Maxim’s patented active emissions limiting edge-rate
control circuitry reduces EMI emissions (Figure 26).
The IC’s speaker amplifiers accept input from the stereo DAC and the line inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals,
9.5dB for 3 signals, or 12dB for four signals.
Table 23. Speaker Output Mixer Register
REGISTERBITNAMEDESCRIPTION
MAX9888
0x29
7
6
5
4
3
2
1
0
MIXSPL
MIXSPR
Speaker Output Volume
Table 24. Speaker Output Mixer Register
REGISTERBITNAMEDESCRIPTION
7SPLM/SPRM
4
3
0x3B/0x3C
2
SPVOLL/SPVOLR
1
0
Left Speaker Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 3
Right Speaker Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 2
The IC includes signal processing to improve the sound
quality of the speaker output and protect transducers
from damage. An excursion limiter dynamically adjusts
the highpass corner frequency, while a power limiter and
distortion limiter prevent the amplifier from outputting too
much distortion or power. The excursion limiter is located
in the DSP while the distortion limiter and power limiter
control the analog volume control (Figure 28). All three
limiters analyze the speaker amplifier’s output signal to
determine when to take action.
Excursion Limiter
The excursion limiter is a dynamic highpass filter that
monitors the speaker outputs and increases the highpass corner frequency when the speaker amplifier’s output exceeds a predefined threshold. The filter smoothly
transitions between the high and low corner frequency to
prevent unwanted artifacts. The filter can operate in four
different modes:
Fixed Frequency Preset Mode. The highpass corner
U
frequency is fixed at the upper corner frequency and
does not change with signal level.
Fixed Frequency Programmable Mode. The high-
U
pass corner frequency is fixed to that specified by the
programmable biquad filter.
Stereo Audio CODEC
Preset Dynamic Mode. The highpass filter automati-
U
cally slides between a preset upper and lower corner
frequency based on output signal level.
User Programmable Dynamic Mode. The highpass
U
filter slides between a user-programmed biquad filter
on the low side to a predefined corner frequency on
the high side.
The transfer function for the user-programmable biquad is:
bb zb z
H(z)
012
=
1 a za z
The coefficients b0, b1, b2, a1, and a2 are sample rate
dependent and stored in registers 0xB4 through 0xC7.
Store b
a
2
, b1, and b2 as positive numbers. Store a1 and
0
as negated two’s complement numbers. Separate fil-
ters can be stored for the DAI1 and DAI2 playback paths.
The MAX9888 EV kit software includes a graphic interface
for generating the user-programmable biquad coefficients.
Note: Only change the excursion limiter settings when
the signal path is disabled to prevent undesired artifacts.
-1-2
++
-1-2
++
12
MAX9888
DV1G:
0/6/12/18dB
+
MULTIBAND ALC
DVEQ1:
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
EQ1ENEQ2EN
EXCURSION LIMITER
Figure 28. Speaker Amplifier Signal Processing Block Diagram
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
DCB2
MODE1
DVFLT
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
MIX
MIXDAL
MIX
MIXDAR
DALEN
DAREN
DACL
DACR
MIX
MIXSPL
MIX
MIXSPR
SPVOLL:
+8dB TO -62dB
SPVOLR:
+8dB TO -62dB
BATTERY ADC
+6dB
SPLEN
DISTORTION LIMITER
+6dB
SPREN
POWER/
SPKLVDD
SPKLP
SPKLN
SPKLGND
SPKRVDD
SPKRP
SPKRN
SPKRPGND
91
Stereo Audio CODEC
with FlexSound Technology
Table 25. Excursion Limiter Registers
REGISTERBITNAMEDESCRIPTION
Excursion Limiter Corner Frequency
6
5
MAX9888
4
0x3F
1
0
6
0x41
0x40
92
5
4
3
2
1
0
DHPUCF
DHPLCF
ALCRLS
DHPTH
The excursion limiter has limited sliding range and minimum corner frequencies. Listed below
are all the valid filter combinations.
LOWER CORNER
FREQUENCY
Excursion limiter disabled—00000
Programmable using biquad100Hz00011
200Hz400Hz—00101
400Hz600Hz—01010
400Hz800Hz—01110
Programmable
using biquad
Programmable
using biquad
Programmable
using biquad
Programmable
using biquad
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level Control
section for ALC release times. Excursion limiter release time is defined as the time required to
slide from the high corner frequency to the low corner frequency.
Excursion Limiter Threshold
Measured at the Class D speaker amplifier outputs. Signals above the threshold use the upper
corner frequency. Signals below the threshold use the lower corner frequency. V
correctly reflect the voltage of SPKLVDD to achieve accurate thresholds.
The IC’s power limiter tracks the RMS power delivered to
the loudspeaker and briefly mutes the speaker amplifier
output if the speaker is at risk of sustaining permanent
damage.
Loudspeakers are typically damaged when the voice coil
overheats due to extended operation above the rated
power. During normal operation, heat generated in the
voice coil is transferred to the speaker’s magnet, which
transfers heat to the surrounding air. For the voice coil to
overheat, both the voice coil and the magnet must overheat. The result is that a loudspeaker can operate above
its rated power for a significant time before it heats sufficiently to cause damage.
Table 26. Power Limiter Registers
REGISTERBITNAMEDESCRIPTION
Power Limiter Threshold
If the RMS output power from the speaker amplifiers exceeds this threshold, the out-
7
6
PWRTH
5
0x42
REGISTERBITNAMEDESCRIPTION
4
2
1
0
PWRK
put is briefly muted to protect the speaker. The threshold is measured in watts assuming an 8I load. VBAT must correctly reflect the voltage of SPKLVDD/SPKRVDD to
The IC’s power limiter includes user-programmable time
constants and power thresholds to match a wide range
of loudspeakers. Program the power limiter’s threshold to
match the loudspeaker’s rated power handling. This can
be determined through measurement or the loudspeaker’s specification. Program time constant 1 to match the
voice coil’s thermal time constant. Program time constant
2 to match the magnet’s thermal time constant. The time
constants can be determined by plotting the voice coil’s
resistance vs. time as power is applied to the speaker.
THRESHOLD
(W)
Power limiter
disabled
VALUE
0x80.27
THRESHOLD
MAX9888
(W)
93
Stereo Audio CODEC
with FlexSound Technology
Table 26. Power Limiter Registers (continued)
7
6
MAX9888
5
4
0x43
3
2
1
0
PWRT2
PWRT1
Power Limiter Time Constant 2
Select a value that matches the thermal time constant of the loudspeaker’s magnet.
The IC’s distortion limiter ensures that the speaker amplifier’s output does not exceed the programmed THD+N limit.
The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is
clipped. If the distortion exceeds the programmed threshold, the output gain is reduced.
94
Stereo Audio CODEC
with FlexSound Technology
Table 27. Distortion Limiter Registers
REGISTERBITNAMEDESCRIPTION
Distortion Limit
Measured in % THD+N.
VALUETHD+N LIMIT (%)VALUETHD+N LIMIT (%)
0x0Limiter disabled0x812
0x1< 10x914
0x210xA16
0x320xB18
0x440xC20
0x560xD21
0x680xE22
0x7100xF24
Distortion Limiter Release Time Constant
Duration of time required for the speaker amplifier’s output gain to adjust back to the
nominal level after a large signal has passed.
000 = 6.2s
001 = 3.1s
010 = 1.6s
011 = 815ms
100 = 419ms
101 = 223ms
110 = 116ms
111 = 76ms
0x44
7
6
5
4
2
1
0
THDCLP
THDT1
MAX9888
Headphone Amplifier
The IC’s headphone amplifier integrates Maxim’s
DirectDrive architecture to eliminate the need for large
DC-blocking capacitors. Traditional single-supply headphone amplifiers have outputs biased at a nominal
DC voltage (typically half the supply). Large coupling
capacitors are needed to block this DC bias from the
headphone. Without these capacitors, a significant
amount of DC current flows to the headphone, resulting
in unnecessary power dissipation and possible damage
to both the headphone and headphone amplifier.
The DirectDrive architecture uses a charge pump to
create an internal negative supply voltage. This allows
the IC’s headphone outputs to be biased at GND while
operating from a single supply (Figure 29). Without a DC
component, there is no need for the large DC-blocking
capacitors. Instead of two large (220FF, typ) capacitors, the IC charge pump requires two small ceramic
capacitors, conserving board space, reducing cost, and
improving the frequency response of the headphone
amplifier. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the IC
is typically Q0.2mV, which, when combined with a 32I
load, results in less than 6FA of DC current flow to the
headphones.
In addition to the cost and size disadvantages of
the DC-blocking capacitors required by conventional
headphone amplifiers, these capacitors limit the amplifier’s low-frequency response and can distort the audio
signal. The DC-blocking capacitor not only blocks DC,
but also low-frequency audio. Improving the low-frequency response of a conventional headphone amplifier
requires increasing the capacitor size, further adding
to the cost and size of the solution. Due to the voltage
coefficient of the capacitors used for DC blocking, they
introduce significant distortion near the corner frequency
of the highpass filter they create. This distortion further
degrades the low-frequency audio quality.
95
Stereo Audio CODEC
with FlexSound Technology
Alternative approaches to eliminating the output-coupling capacitors involve biasing the headphone return
(sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues:
U The sleeve is typically grounded to the chassis. Using
the midrail biasing approach, the sleeve must be
isolated from system ground, complicating product
design.
MAX9888
U During an ESD strike, the amplifier’s ESD structures
are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an
ESD strike.
U When using the headphone jack as a line out to other
equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment,
resulting in possible damage to the amplifiers.
The IC features a low-noise charge pump to generate
a negative supply for the headphone amplifier. The
nominal switching frequency is well beyond the audio
range, and thus does not interfere with audio signals.
The switch drivers feature a controlled switching speed
that minimizes noise generated by turn-on and turn-off
transients. By limiting the switching speed of the charge
pump, the di/dt noise caused by the parasitic trace
inductance is minimized. The charge pump is active only
in headphone modes.
To reduce audible noise at the outputs, the IC’s headphone amplifier includes headphone ground sensing.
Connect the sense line (HPSNS) to the ground terminal
of the device’s headphone jack. Any noise present at
the headphone ground is then added to the headphone
output. The result is elimination of this noise from the
audible output. If ground sensing is not required, connect HPSNS directly to ground. Figure 30 shows a block
diagram of the headphone output section including the
headphone sense function.
Headphone Output Mixers
The IC’s headphone amplifier accepts input from the
stereo DAC and the line inputs. The output of the left and
right DAC cannot be mixed at the headphone mixer. Use
MIXDAL/MIXDAR to mix the left and right audio channels
before conversion.
V
DD
VDD/2
GND
CONVENTIONAL AMPLIFIER BIASING SCHEME
+V
DD
GND
-V
DD
DirectDrive AMPLIFIER BIASING SCHEME
Figure 29. Traditional Amplifier Output vs. DirectDrive Output
96
(VSS)
DACL
DALEN
DACR
DAREN
PGAOUT1:
0dB TO -23dB
PREOUT1
+9dB
PREOUT2
+9dB
PGAOUT2:
0dB TO -23dB
Figure 30. Headphone Amplifier Block Diagram
MIX
MIXHPL
MIX
MIXHPR
HPVOLL:
+3dB TO -67dB
HPL
HPLEN
HPSNS
HPVOLR:
+3dB TO -67dB
HPR
HPREN
Stereo Audio CODEC
with FlexSound Technology
Table 28. Headphone Output Mixer Register
REGISTERBITNAMEDESCRIPTION
7
6
5
4
0x27
3
2
1
0
MIXHPL
MIXHPR
Headphone Output Volume
Table 29. Headphone Output Level Register
REGISTERBITNAMEDESCRIPTION
7HPLM/HPRM
4
0x38/0x39
3
HPVOLL/HPVOLR
2
1
0
Left Headphone Output Mixer
10xx = Left DAC
01xx = Right DAC (requires DALEN = 0 for proper operation)
11xx = Left DAC
xx1x = Reserved
xxx1 = Preoutput mixer 1
Right Headphone Output Mixer
10xx = Left DAC (requires DAREN = 0 for proper operation)
01xx = Right DAC
11xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 2
The IC includes two output bypass switches that solve
common applications problems. When a single transducer is used for the loudspeaker and receiver, the need
exists for two amplifiers to power the same transducer.
Bypass switches connect the IC’s receiver amplifier
output to the speaker amplifier’s output, allowing either
amplifier to power the same transducer. In systems where
MAX9888
SPKLP
SPKLN
10I*
10I*
EXTERNAL
RECEIVER
AMP
0dB
RECEN
+6dB
SPLEN
POWER/DISTORTION
SPEAKER AMPLIFIER BYPASS USING THE
RECP/RXINP
0dB
RECEN
RECBYP
SPKBYP
+6dB
SPLEN
POWER/DISTORTION
LIMITER
*OPTIONAL 10I RESISTORS IMPROVE DISTORTION
THROUGH THE ANALOG SWITCH.
SPEAKER AMPLIFIER BYPASS USING AN
RECN/RXINN
SPKLVDD
SPKLGND
EXTERNAL RECEIVER AMPLIFIER
an external receiver amplifier is used, route its output to
the left speaker through RECP/RXINP and RECN/RXINN,
bypassing the Class D amplifier. In systems where an
external amplifier drives both the receiver and the IC’s
line input, one of the differential signals can be disconnected from the receiver when not needed by passing it
through the analog switch that connects RECP/RXINP to
RECN/RXINN.
RECP/RXINP
RECN/RXINN
RECBYP
SPKBYP
SPKLVDD
SPKLP
SPKLN
SPKLGND
LIMITER
INTERNAL RECEIVER AMPLIFIER
0dB
RECEN
RECBYP
SPKBYP
+6dB
SPLEN
POWER/DISTORTION
LIMITER
CONTROLLING AN EXTERNAL RECEIVE
AMPLIFIER AND SPEAKER
EXTERNAL
RECEIVER AMP
RECN/RXINN
RECN/RXINN
SPKLVDD
SPKLP
SPKLN
SPKLGND
Figure 31. Output Bypass Switch Block Diagrams
Table 30. Output Bypass Switches Register
REGISTERBITNAMEDESCRIPTION
7INABYP
4MIC2BYP
1RECBYP
0x48
0SPKBYP
98
See the Microphone Inputs section.
RXINP to RXINN Bypass Switch
Shorts RXINP to RXINN allowing a signal to pass through the MAX9888. Disable the
receiver amplifier when RECBYP = 1.
0 = Disabled
1 = Enabled
RXIN to SPKL Bypass Switch
Shorts RXINP/RXINN to SPKLP/SPKLN allowing either the internal or an external
receiver amplifier to power the left speaker. Disable the left speaker amplifier when
SPKBYP = 1.
0 = Disabled
1 = Enabled
Stereo Audio CODEC
with FlexSound Technology
Click-and-Pop Reduction
The IC includes extensive click-and-pop reduction circuitry. The circuitry minimizes clicks and pops at turn-on,
turn-off, and during volume changes.
Zero-crossing detection is implemented on all analog
PGAs and volume controls to prevent large glitches
when volume changes are made. Instead of making a
volume change immediately, the change is made when
the audio signal crosses the midpoint. If no zero-crossing
occurs within the timeout window, the change is forced.
Volume slewing breaks up large volume changes into the
smallest available step size and the steps through each
step between the initial and final volume setting. When
Table 31. Click-and-Pop Reduction Register
REGISTERBITNAMEDESCRIPTION
Enhanced Volume Smoothing
During volume slewing, the controller waits for each step in the ramp to be applied
before sending the next step. When zero-crossing detection is enabled this prevents
7VS2EN
6VSEN
0x49
5ZDEN
1EQ2EN
0EQ1EN
large steps in the output volume when no zero crossings are detected.
0 = Enabled
1 = Disabled
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
Volume Adjustment Smoothing
Volume changes are smoothed by stepping through intermediate steps. Also ramps
the volume from minimum to the programmed value at turn-on and back to minimum at
turn-off.
0 = Enabled
1 = Disabled
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
Zero-Crossing Detection
Holds volume changes until there is a zero crossing in the audio signal. This reduces
click and pop during volume changes (zipper noise). If no zero crossing is detected
within 100ms, the volume change is forced.
0 = Enabled
1 = Disabled
Applies to volume changes in PGAM1, PGAM2, PGAOUTA, PGAOUTB, PGAOUTC,
HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
See the 5-Band Parametric EQ section.
enabled, volume slewing also occurs at device turn-on
and turn-off. During turn-on the volume is set to mute
before the output is enabled. Once the output is on, the
volume ramps to the desired level. At turn-off the volume
is ramped to mute before the outputs are disabled.
When there is no audio signal zero-crossing detection
can prevent volume slewing from occurring. Enable
enhanced volume slewing to prevent the volume controller from requesting another volume level until the previous one has been set. Each step in the volume ramp
then occurs after a zero crossing has occurred in the
audio signal or the timeout window has expired. During
turn-off, enhance volume slewing is always disabled.
MAX9888
99
Stereo Audio CODEC
with FlexSound Technology
Jack Detection
The IC features jack detection that can detect the insertion and removal of a jack as well as the load type. When
a jack is detected, an interrupt on IRQ can be triggered
to alert the microcontroller of the event. Figure 32 shows
the typical configuration for jack detection.
Jack Insertion
To detect a jack insertion, the IC must have a power
MAX9888
supply and MICBIAS should be disabled. Set JDETEN
to enable jack detection circuitry and apply a pullup current to JACKSNS. Set JDWK to minimize supply current.
Clear JDWK to differentiate between headsets with a
microphone and headphones without a microphone. The
voltage on JACKSNS is equal to SPKLVDD as long as no
Figure 32. Typical Configuration for Jack Detection
load is applied to JACKSNS. Table 32 shows the change
in JKSNS that occurs when a jack is inserted.
Accessory Button Detection
After jack insertion, the MAX9888 can detect button
presses on accessories that include a microphone and
a switch that shorts the microphone signal to ground.
Set JDETEN to enable jack detection circuitry. A pullup
current is automatically applied to JACKSNS if MICBIAS
is disabled. Clear JDWK to allow differentiation between
the microphone load and a short to ground. Button
presses can be detected both when MICBIAS is enabled
and disabled. Table 33 shows the change in JKSNS that
occurs when the accessory button is pressed.
HPL
HPR
MICBIAS
JACKSNS
MIC1P
Table 32. Change in JKSNS Upon Jack Insertion
JACK TYPEJDWK = 1JDWK = 0
GNDGNDRL
MICGNDRL
JKSNS: 11 è 00JKSNS: 11 è 00
JKSNS: 11 è 00JKSNS: 11 è 01
Table 33. Change in JKSNS Upon Button Press
JACK TYPEMICBIAS ENABLED OR DISABLED
MICGNDRL
JKSNS: 01 è 00
100
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