The MAX9875 combines a high-efficiency Class D
audio power amplifier with a stereo Class AB capacitorless DirectDrive
®
headphone amplifier. Maxim’s 3rd
generation, filterless Class D amplifier with active emissions limiting technology provides Class AB performance with Class D efficiency.
The MAX9875 delivers up to 725mW from a 3.7V supply
into an 8Ω load with 87% efficiency to extend battery life.
The filterless modulation scheme combined with active
emissions limiting circuitry and spread-spectrum modulation greatly reduces EMI while eliminating the need for
output filtering used in traditional Class D devices.
The stereo Class AB headphone amplifier in the
MAX9875 uses Maxim’s DirectDrive architecture, that
produces a ground-referenced output from a single supply, eliminating the need for large DC-blocking capacitors, saving cost, space, and component height.
The device utilizes a user-defined input architecture,
three preamplifier gain settings, an input mixer, volume
control, comprehensive click-and-pop suppression, and
I
2
C control.
The MAX9875 is available in a thermally efficient,
space-saving 20-bump WLP package.
Applications
Cell Phones
Portable Multimedia Players
Features
♦ Low Emissions, Filterless Class D Amplifier
Achieves Better than 10dB Margin Under EN55022
Class B Limits
♦ High Speaker Amplifier PSRR (72dB at 217Hz)
♦ High Headphone Amplifier PSRR (84dB at 217Hz)
♦ I
2
C Control
♦ Hardware and Software Shutdown Mode
♦ Click-and-Pop Suppression
♦ Current-Limit and Thermal Protection
♦ Available in a Space-Saving, 2.5mm x 2.0mm WLP
) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 3.3V. Z
SPK
= ∞, RHP= ∞. C1 = C2 = C
BIAS
= 1µF. TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: HPR and HPL should be limited to no more than 9V above VSS, or above PVDD + 0.3V, whichever limits first.
Note 2: HPR and HPL should be limited to no more than 9V below PVDD, or below V
SS
- 0.3V, whichever limits first.
V
DD
, PVDD to PGND .............................................-0.3V to +5.5V
V
DD
to PVDD .........................................................-0.3V to +0.3V
V
SS
to PGND .........................................................-5.5V to +0.3V
C1N to PGND..............................................(V
SS
- 0.3V) to +0.3V
C1P to PGND...........................................-0.3V to (PVDD + 0.3V)
HPL, HPR to V
SS
(Note 1)......-0.3V to the lower of (PVDD - (VSS+ 0.3V)) or +9V
HPL, HPR to PVDD
(Note 2) .....+0.3V to the higher of (V
SS
- (PVDD - 0.3V)) or -9V
GND to PGND.....................................................................±0.3V
INA1, INA2, INB1, INB2, BIAS..................................-0.3V to +4V
SDA, SCL...............................................................-0.3V to +5.5V
All Other Pins to GND..............................-0.3V to (PVDD + 0.3V)
Continuous Current In/Out of PVDD, PGND, OUT_........±800mA
Continuous Current In/Out of HPR and HPL .....................140mA
Continuous Input Current V
SS
...........................................100mA
Continuous Input Current (all other pins) .........................±20mA
Duration of OUT_ Short Circuit to GND or PVDD .......Continuous
Duration of Short Circuit Between OUT+ and OUT- ..Continuous
Duration of HP_ Short Circuit to GND or PVDD..........Continuous
) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 3.3V. Z
SPK
= ∞, RHP= ∞. C1 = C2 = C
BIAS
= 1µF. TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C.) (Note 3)
Note 3: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design.
Note 4: Amplifier inputs are AC-coupled to GND.
Note 5: Output levels higher than 825mW are not recommended for extended durations. Production tested with Z
The MAX9875 signal path consists of flexible inputs,
signal mixing, volume control, and output amplifiers
(Figure 1).
The inputs can be configured for single-ended or differential signals (Figure 2). The internal preamplifiers feature three programmable gain settings of 0dB, +9dB,
and +20dB. Following preamplification, the input signals are mixed, volume adjusted, and routed to the
headphone and speaker amplifiers based on the output mode configuration (see Table 7). The volume control stages provide up to 75dB attenuation. The
headphone amplifier is configured as a unity-gain
buffer while the speaker amplifier provides +12dB of
additional gain.
When an input is configured as mono differential it can
be routed to the speaker or to both headphones. When
an input is stereo, it is mixed to mono without attenuation
for the speaker and kept stereo for the headphones.
When the application does not require the use of both
INA_ and INB_, the SNR of the MAX9875 is improved
by deselecting the unused input through the I2C output
mode register and AC-coupling the unused inputs to
ground with a 330pF capacitor. The 330pF capacitor
and the input resistance to the MAX9875 form a highpass filter preventing audible noise from coupling into
the outputs.
PINNAMEFUNCTION
A1HPRRight Headphone Output
A2HPLLeft Headphone Output
A3V
A4C1NCharge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor between C1P and C1N.
A5C1PCharge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor between C1P and C1N.
B1V
B2BIAS
B3SDASerial-Data Input. Connect a pullup resistor from SDA to a 1.7V to 3.6V supply.
B4N.C.No Connection
B5OUT+Positive Speaker Output
C1INB2Input B2. Right input or positive input (see the Differential Input Configuration (∆IN_) section).
C2INB1Input B1. Left input or negative input (see the Differential Input Configuration (∆IN_) section).
C3SCLSerial-Clock Input. Connect a pullup resistor from SCL to a 1.7V to 3.6V supply.
C4PGNDPower Ground
C5PVDDClass D and Charge-Pump Power Supply. Bypass with a 1µF capacitor to PGND.
D1INA2Input A2. Right input or positive input (see the Differential Input Configuration (∆IN_) section).
D2INA1Input A1. Left input or negative input (see the Differential Input Configuration (∆IN_) section).
D3GNDAnalog Ground
D4N.C.No Connection
D5OUT-Negative Speaker Output
SS
DD
Headphone Amplifier Negative Power Supply. Bypass with a 1µF capacitor to PGND.
Analog Supply. Connect to PVDD. Bypass with a 1µF capacitor to GND.
Common-Mode Bias. Bypass to GND with a 1µF capacitor. Pulse low to reset the part and place in
shutdown (see the Typical Application Circuit).
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
The MAX9875 features three volume control registers
(see Table 4) allowing independent volume control of
mono speaker and stereo headphone amplifier outputs.
Each volume control register has 31 steps providing 0 to
75dB (typ) of attenuation and a mute function.
Class D Speaker Amplifier
The MAX9875 integrates a filterless Class D amplifier
that offers much higher efficiency than Class AB without the typical disadvantages.
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as currentsteering switches and consume negligible additional
power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET
on-resistance, and quiescent current overhead.
The theoretical best efficiency of a linear amplifier is
78%, however, that efficiency is only exhibited at peak
output power. Under normal operating levels (typical
music reproduction levels), efficiency falls below 30%,
whereas the MAX9875 still exhibits 70% efficiency
under the same conditions (Figure 3).
Ultra-Low EMI Filterless Output Stage
In traditional Class D amplifiers, the high dV/dt of the
rising and falling edge transitions results in increased
EMI emissions, which requires the use of external LC
filters or shielding to meet EN55022 electromagneticinterference (EMI) regulation standards. Limiting the
dV/dt normally results in decreased efficiency. Maxim’s
active emissions limiting circuitry actively limits the
dV/dt of the rising and falling edge transitions, providing reduced EMI emissions, while maintaining up to
87% efficiency.
In addition to active emission limiting, the MAX9875
features a spread-spectrum modulation mode that flattens the wideband spectral components. Proprietary
techniques ensure that the cycle-to-cycle variation of
the switching period does not degrade audio reproduction or efficiency (see the
Typical Operating
Characteristics
). Select spread-spectrum modulation
mode through the I
2
C interface (Table 6). In spreadspectrum modulation mode, the switching frequency
varies randomly by ±60kHz around the center frequency (1.176MHz). The effect is to reduce the peak energy
at harmonics of the switching frequency. Above
10MHz, the wideband spectrum looks like white noise
for EMI purposes (see Figure 4).
Speaker Current Limit
Most applications will not enter current limit unless the
output is short circuited or connected incorrectly.
When the output current of the speaker amplifier
exceeds the current limit (1.5A, typ) the MAX9875 disables the outputs for approximately 250µs. At the end of
250µs, the outputs are re-enabled, if the fault condition
still exists, the MAX9875 will continue to disable and reenable the outputs until the fault condition is removed.
MAX9875 EFFICIENCY
vs. IDEAL CLASS EFFICIENCY
MAX9875 fig03
OUTPUT POWER (W)
EFFICIENCY (%)
0.750.500.25
10
20
30
40
50
60
70
80
90
100
0
01.00
MAX9875
IDEAL CLASS AB
VDD = V
PVDD
= 3.7V (MAX9875)
V
SUPPLY
= 3.7V (IDEAL CLASS AB)
Figure 3. MAX9875 Efficiency vs. Class AB Efficiency
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply). Large coupling capacitors are needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to
the headphone, resulting in unnecessary power dissipation and possible damage to both the headphone
and headphone amplifier.
Maxim’s DirectDrive architecture uses a charge pump to
create an internal negative supply voltage. This allows
the headphone outputs of the MAX9875 to be biased at
GND while operating from a single supply (Figure 5).
Without a DC component, there is no need for the large
DC-blocking capacitors. Instead of two large (220µF,
typ) capacitors, the MAX9875 charge pump requires
two small ceramic capacitors, conserving board space,
reducing cost, and improving the frequency response of
the headphone amplifier. See the Output Power vs.
Load Resistance graph in the
Typical Operating
Characteristics
for details of the possible capacitor
sizes. There is a low DC voltage on the amplifier outputs
due to amplifier offset. However, the offset of the
MAX9875 is typically ±0.15mV, which, when combined
with a 32Ω load, results in less than 10µA of DC current
flow to the headphones.
In addition to the cost and size disadvantages of the
DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier’s
low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return
(sleeve) to the DC bias voltage of the headphone
amplifiers. This method raises some issues:
1) The sleeve is typically grounded to the chassis.
Using the midrail biasing approach, the sleeve must
be isolated from system ground, complicating product design.
2) During an ESD strike, the amplifier’s ESD structures
are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an
ESD strike.
3) When using the headphone jack as a line out to
other equipment, the bias voltage on the sleeve may
conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers.
The MAX9875 features a low-noise charge pump. The
switching frequency of the charge pump is 1/2of the
Class D switching frequency, regardless of the operating
mode. When the Class D amplifiers are operated in
spread-spectrum mode, the charge pump also switches
with a spread-spectrum pattern. The nominal switching
frequency is well beyond the audio range, and thus does
not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise
generated by turn-on and turn-off transients. By limiting
the switching speed of the charge pump, the di/dt noise
caused by the parasitic trace inductance is minimized.
Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the
size of C2 (see the
Typical Application Circuit
). The
charge pump is active only in headphone modes.
Headphone Current Limit
The headphone amplifier current is limited to 140mA (typ).
The current limit clamps the output current, which appears
as clipping when the maximum current is exceeded.
Shutdown Mode
The MAX9875 features two ways of entering low-power
shutdown. The hardware shutdown function is controlled
by pulsing BIAS low for 1ms. While BIAS is low the amplifiers are shut down. Following an 80ms reset period, the
MAX9875 reverts to its power-on-reset condition. Pull
BIAS low using an open-drain output that is not pulled up
with a resistor (see the
Typical Application Circuit).
The
open-drain output leakage must not exceed 100nA and
must be able to sink at least 1mA.
The device can also be placed in shutdown mode by
writing to the SHDN bit in the Output Mode Control
Register.
Click-and-Pop Suppression
The MAX9875 features click-and-pop suppression that
eliminates audible transients from occurring at startup
and shutdown.
Use the following procedure to start up the MAX9875:
1) Configure the desired output mode and preamplifier gain.
2) Set the SHDN bit to 1 to start up the amplifier.
3) Wait 10ms for the startup time to pass.
4) Increase the output volume to the desired level.
To disable the device simply set SHDN to 0.
During the startup period, the MAX9875 precharges the
input capacitors to prevent clicks and pops. If the output
amplifiers have been programmed to be active they are
held in shutdown until the precharge period is complete.
When power is initially applied to the MAX9875, the
power-on-reset state of all three volume control registers
is mute. For most applications, the volume can be set to
the desired level once the device is active. If the clickand-pop is too high, step through intermediate volume
settings with zero-crossing detection disabled. Stepping
through higher volume settings has a greater impact on
click-and-pop than lower volume settings.
For the lowest possible click-and-pop, start up the device
at minimum volume and then step through each volume
setting until the desired setting is reached. Disable zerocrossing detection if no input signal is expected.
V
DD
VDD/2
GND
CONVENTIONAL AMPLIFIER BIASING SCHEME
DirectDrive AMPLIFIER BIASING SCHEME
+V
DD
GND
-V
DD
(VSS)
Figure 5. Traditional Amplifier Output vs. MAX9875 DirectDrive
Output
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
Zero-crossing detection limits distortion in the output
signal during volume transitions by delaying the transition until the mixer output crosses the internal bias voltage. A timeout period (typically 60ms) forces the
volume transition if the mixer output signal does not
cross the bias voltage.
1 = Zero-crossing detection is enabled.
0 = Zero-crossing detection is disabled.
Differential Input Configuration (∆IN_)
The inputs INA_ and INB_ can be configured for mono
differential or stereo single-ended operation.
1 = IN__ is configured as a mono differential input with
IN_2 as the positive and IN_1 as the negative input.
0 = IN__ is configured as a stereo single-ended input
with IN_2 as the right and IN_1 as the left input.
Preamplifier Gain (PGAIN_)
The preamplifier gain of INA_ and INB_ can be programmed by writing to PGAIN_.
00 = 0dB
01 = +9dB
10 = +20dB
11 = Reserved
The MAX9875 is controlled through five I
2
C programmable registers. Table 1 shows the MAX9875’s complete register map. Tables 2, 3, and 5 show the
individual registers.
SHDN is an active-low shutdown bit that overrides all
settings and places the entire device in low-power shutdown mode. The I
2
C interface is fully active in this shutdown mode. All register settings are preserved while in
shutdown.
Volume Control
The device has a separate volume control for left headphone, right headphone, and speaker amplifiers. The
total system gain is a combination of the input gain, the
volume control, and the output amplifier gain. Table 4
shows the volume settings for each volume control.
Table 4. Volume Control Settings
Table 5. Output Mode Control
Table 3. Speaker/Left Headphone/Right Headphone Volume Control
REGISTERB7B6B5B4B3B2B1B0
0x01000SVOL (Table 4)
0x02000HPLVOL (Table 4)
0x03000HPRVOL (Table 4)
CODE
000000MUTE
100001-75
200010-71
300011-67
400100-63
500101-59
600110-55
700111-51
801000-47
901001-44
1001010-41
1101011-38
1201100-35
1301101-32
1401110-29
1501111-26
B4B3B2B1B0
_VOL
GAIN (dB)
CODE
1610000-23
1710001-21
1810010-19
1910011-17
2010100-15
2110101-13
2210110-11
2310111-9
2411000-7
2511001-6
2611010-5
2711011-4
2811100-3
2911101-2
3011110-1
31111110
B4B3B2B1B0
_VOL
GAIN (dB)
REGISTERB7B6B5B4B3B2B1B0
0x04SHDN0OSC (Table 6 )OUTMODE (Table 7)
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
The MAX9875 has a stereo DirectDrive headphone amplifier and a mono Class D amplifier. Table 7 shows how
each of the output amplifiers can be configured and connected to the input signals. For simplicity, not all possible
combinations of ∆INA and ∆INB are shown.
OSC
B5B4
001176, spread spectrum588, spread spectrum
011100, fixed frequency550, fixed frequency
10700, fixed frequency350, fixed frequency
11Reserved
CLASS D OSCILLATOR MODE (kHz)CHARGE-PUMP OSCILLATOR MODE (kHz)
Figure 7. START, STOP, and REPEATED START Conditions
SMBus is a trademark of Intel Corp.
I2C Interface Specification
The MAX9875 features an I2C/SMBus™-compatible, 2wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9875 and the
master at clock rates up to 400kHz. Figure 6 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9875 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted
to the MAX9875 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9875 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9875
transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of
each byte of data. Each read sequence is framed by a
START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an
input and an open-drain output. A pullup resistor, typically greater than 500Ω, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater
than 500Ω, is required on SCL if there are multiple masters on the bus, or if the single master has an opendrain SCL output. Series resistors in line with SDA and
SCL are optional. Series resistors protect the digital
inputs of the MAX9875 from high voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions
section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 7). A START
condition from the master signals the beginning of a
transmission to the MAX9875. The master terminates
transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
SDA
t
t
LOW
SCL
t
HD:STA
START
CONDITION
SU:DAT
t
HIGH
t
R
t
HD:DAT
t
F
t
SU:STA
REPEATED
START CONDITION
t
SU:STA
t
SU:STO
STOP
CONDITION
t
BUF
START
CONDITION
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
The MAX9875 recognizes a STOP condition at any
point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The MAX9875 is preprogrammed with a slave address
of 1001101R/(W). The address is defined as the seven
most significant bits (MSBs) followed by the Read/Write
bit. Setting the Read/Write bit to 1 configures the
MAX9875 for read mode. Setting the Read/Write bit to 0
configures the MAX9875 for write mode. The address is
the first byte of information sent to the MAX9875 after
the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9875 uses to handshake receipt each byte of data
when in write mode (see Figure 8). The MAX9875 pulls
down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication.
The master pulls down SDA during the ninth clock
cycle to acknowledge receipt of data when the
MAX9875 is in read mode. An acknowledge is sent by
the master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the MAX9875, followed
by a STOP condition.
Write Data Format
A write to the MAX9875 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the MAX9875.
Figure 10 illustrates the frame format for writing n-bytes
of data to the MAX9875.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9875.
The MAX9875 acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
Figure 11. Reading One Indexed Byte of Data from the MAX9875
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9875
ACKNOWLEDGE FROM MAX9875
B1 B0B3 B2B5 B4B7 B6
A
A0
ACKNOWLEDGE FROM MAX9875
R/W
S
A
1 BYTE
ACKNOWLEDGE FROM MAX9875
B1 B0B3 B2B5 B4B7 B6
P
A
SLAVE ADDRESS
REGISTER ADDRESS
DATA BYTE 1
DATA BYTE n
Figure 10. Writing n-Bytes of Data to the MAX9875
The second byte transmitted from the master configures the MAX9875’s internal register address pointer.
The pointer tells the MAX9875 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9875 upon receipt of the address pointer data.
The third byte sent to the MAX9875 contains the data
that will be written to the chosen register. An acknowledge pulse from the MAX9875 signals receipt of the
data byte. The address pointer autoincrements to the
next register address after each received data byte.
This autoincrement feature allows a master to write to
sequential registers within one continuous frame. Figure
10 illustrates how to write to multiple registers with one
frame. The master signals the end of transmission by
issuing a STOP condition.
Register addresses greater than 0x04 are reserved. Do
not write to these addresses.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The MAX9875 acknowledges receipt of
its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read
command resets the address pointer to register 0x00.
The first byte transmitted from the MAX9875 will be the
contents of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincrements
after each read data byte. This autoincrement feature
allows all registers to be read sequentially within one
continuous frame. A STOP condition can be issued after
any number of read data bytes. If a STOP condition is
issued followed by another read operation, the first data
byte to be read will be from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9875‘s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX9875 then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all
correctly received bytes except the last byte. The final
byte must be followed by a not acknowledge from the
master and then a STOP condition. Figure 11 illustrates
the frame format for reading one byte from the
MAX9875. Figure 12 illustrates the frame format for
reading multiple bytes from the MAX9875.
ACKNOWLEDGE FROM MAX9875
SA
ACKNOWLEDGE FROM MAX9875
0
R/W
ACKNOWLEDGE FROM MAX9875
Sr1SLAVE ADDRESSREGISTER ADDRESSSLAVE ADDRESS DATA BYTE
NOT ACKNOWLEDGE FROM MASTER
AA
R/WREPEATED START
A
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
P
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
Traditional Class D amplifiers require an output filter to
recover the audio signal from the amplifier’s output. The
filters add cost, increase the solution size of the amplifier,
and can decrease efficiency and THD+N performance.
The traditional PWM scheme uses large differential output swings (2 x V
DD(P-P)
) and causes large ripple currents. Any parasitic resistance in the filter components
results in a loss of power, lowering the efficiency.
The MAX9875 does not require an output filter. The
device relies on the inherent inductance of the speaker
coil and the natural filtering of both the speaker and the
human ear to recover the audio component of the
square-wave output. Eliminating the output filter results
in a smaller, less costly, more efficient solution.
Because the frequency of the MAX9875 output is well
beyond the bandwidth of most speakers, voice coil
movement due to the square-wave frequency is very
small. Although this movement is small, a speaker not
designed to handle the additional power can be damaged. For optimum results, use a speaker with a series
inductance > 10µH. Typical 8Ω speakers exhibit series
inductances in the 20µH to 100µH range.
Component Selection
Optional Ferrite Bead Filter
In applications where speaker leads exceed 20mm,
additional EMI suppression can be achieved by using a
filter constructed from a ferrite bead and a capacitor to
ground. A ferrite bead with low DC resistance, highfrequency (> 1.176MHz) impedance of 100Ω to 600Ω,
and rated for at least 1A should be used. The capacitor
value varies based on the ferrite bead chosen and the
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
Input Capacitor
An input capacitor, CIN, in conjunction with the input
impedance of the MAX9875 forms a highpass filter that
removes the DC bias from an incoming signal. The AC-
coupling capacitor allows the amplifier to automatically
bias the signal to an optimum DC level. Assuming zero
source impedance, the -3dB point of the highpass filter
is given by:
Choose C
IN
so that f
-3dB
is well below the lowest frequency of interest. Use capacitors whose dielectrics
have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased
distortion at low frequencies.
BIAS Capacitor
BIAS is the output of the internally generated DC bias voltage. The BIAS bypass capacitor, C
BIAS
, reduces power
supply and other noise sources at the common-mode
bias node. Bypass BIAS with a 1µF capacitor to GND.
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mΩ for optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
Flying Capacitor (C1)
The value of the flying capacitor (C1) affects the output
resistance of the charge pump. A C1 value that is too
small degrades the device’s ability to provide sufficient
current drive, which leads to a loss of output voltage.
Figure 13. Optional Ferrite Bead Filter
ACKNOWLEDGE FROM MAX9875
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9875
AA
AP
0
ACKNOWLEDGE FROM MAX9875
R/W
SA
R/W
REPEATED START
Sr1SLAVE ADDRESSREGISTER ADDRESSSLAVE ADDRESS DATA BYTE
Figure 12. Reading n-Bytes of Indexed Data from the MAX9875
Increasing the value of C1 reduces the charge-pump output resistance to an extent. Above 1µF, the on-resistance
of the switches and the ESR of C1 and C2 dominate.
Output Holding Capacitor (C2)
The output capacitor value and ESR directly affect the
ripple at VSS. Increasing the value of C2 reduces output
ripple. Likewise, decreasing the ESR of C2 reduces both
ripple and output resistance. Lower capacitance values
can be used in systems with low maximum output power
levels. See the Output Power vs. Load Resistance graph
in the
Typical Operating Characteristics
.
PVDD Bulk Capacitor (C3)
In addition to the recommended PVDD bypass capacitance, bulk capacitance equal to C3 should be used.
Place the bulk capacitor as close to the device as possible.
Supply Bypassing,
Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use wide traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Wide traces also aid in moving heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
Connect PVDD to a 2.7V to 5.25V source. Bypass
PVDD to the PGND pin with a 1µF ceramic capacitor.
Additional bulk capacitance should be used to prevent
power-supply pumping. Place the bypass capacitors
as close to the MAX9875 as possible.
Connect VDDto PVDD. Bypass VDDto GND with a 1µF
capacitor. Place the bypass capacitors as close to the
MAX9875 as possible.
RF Susceptibility
GSM radios transmit using time-division multiple
access (TDMA) with 217Hz intervals. The result is an
RF signal with strong amplitude modulation at 217Hz
that is easily demodulated by audio amplifiers. Figure
14 shows the susceptibility of the MAX9875 to a transmitting GSM radio placed in close proximity. Although
there is measurable noise at 217Hz and its harmonics,
the noise is well below the threshold of hearing using
typical headphones.
In RF applications, improvements to both layout and
component selection decreases the MAX9875’s sus-
ceptibility to RF noise and prevent RF signals from
being demodulated into audible noise. Trace lengths
should be kept below
1
/4the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling
RF signals into the MAX9875. The wavelength λ in
meters is given by:
λ = c/f
where c = 3 x 108m/s, and f = the RF frequency of interest.
Route audio signals on middle layers of the PCB to
allow ground planes above and below shield them from
RF interference. Ideally the top and bottom layers of the
PCB should primarily be ground planes to create effective shielding.
Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it
exhibits the frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at RF frequencies.
These capacitors, when placed at the input pins, can
effectively shunt the RF noise at the inputs of the
MAX9875. For these capacitors to be effective, they
must have a low-impedance, low-inductance path to
the ground plane. Do not use microvias to connect to
the ground plane as these vias do not conduct well at
RF frequencies.
RF SUSCEPTIBILITY
MAX9875 fig14
FREQUENCY (Hz)
EFFICIENCY (dBµ)
10k1k100
-130
-110
-90
-70
-50
-30
-10
-150
10100k
THRESHOLD OF HEARING
MAX9875
NOISE FLOOR
Figure 14. MAX9875 Susceptibility to a GSM Cell Phone Radio
MAX9875
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability
testing results, refer to the
Application Note: UCSP—A
Wafer-Level Chip-Scale Package
on Maxim’s website
at www.maxim-ic.com/ucsp. See Figure 15 for the
recommended PCB footprint for the MAX9875.
Low RF Susceptibility, Mono Audio
Subsystem with DirectDrive Headphone Amplifier
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 __________________
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600