MAXIM MAX9850 Technical data

General Description

The MAX9850 is a low-power, high-performance stereo audio DAC with an integrated DirectDrive headphone amplifier. The MAX9850 is designed to meet the board space and performance requirements of portable devices such as cell phones and MP3 and portable DVD players.

The MAX9850 uses Maxim’s DirectDrive headphone technology that produces a ground-biased analog audio output from a single supply, which allows for driving the headphones directly from the amplifier outputs without large DC-blocking capacitors. This feature saves board space, provides higher click/pop suppression, and improves low-frequency (bass) response. The architecture does not require the headphone jack to be biased to a DC voltage and thus allows for a conventional, grounded chassis design.

The MAX9850’s flexible clocking circuitry utilizes any available system clock up to 40MHz, eliminating the need for an external PLL and multiple crystal oscillators. The DAC supports a wide range of sample rates from 8kHz to 48kHz in both master and slave modes, making the MAX9850 the easiest to use and most versatile audio DAC available. It can also be operated like traditional synchronous DACs, at any integer-oversampling ratio.

The audio DAC receives input data over a flexible 3-wire interface that supports left-justified, right-justified audio data, or I2S-compatible audio data. Stereo audio line inputs are provided to either mix analog audio with the digital input stream, or to drive the headphone outputs directly. Mode settings, headphone amplifier volume controls, and shutdown for both the headphone and line outputs are programmed through a 2-wire, I

C-compatible interface.

The MAX9850 is fully specified over the -40°C to +85°C extended temperature range and is available in a lowprofile, 28-pin thin QFN package (5mm x 5mm x 0.8mm).

Applications

MP3/Portable Multimedia Players

Cell Phones/Smart Phones

Portable DVD Players

Features

♦ 1.8V to 3.6V Single-Supply Operation

♦ 30mW Stereo Headphone Output Power with

1.8V Supply

♦ DirectDrive Outputs Eliminate DC-Blocking

Capacitors

♦ 91dB PSRR at 1kHz

♦ Any Master Clock Up to 40MHz

♦ Flexible I

S-Compatible Digital Audio Interface

♦ I

C Headphone Volume and Mute Control

♦ Stereo Line Inputs and Outputs

♦ Clickless/Popless Operation

♦ 2-Wire (I

C)-Compatible Control Interface

♦ Available in 28-Pin Thin QFN Package

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3454; Rev 3; 4/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-PACKAGE

PKG

CODE

MAX9850ETI+

T2855-6

Pin Configuration appears at end of data sheet.

DAC

DIGITAL

AUDIO

DIGITAL

PLL

MAX9850

SDIN

BCLK

LRCLK

SDA SCL ADD

GPIO

LINE OUT

OUTR

HPR

HPL

OUTL

INL

INR

1.8V TO 3.6VMCLK

Block Diagram

**EP = Exposed pad. +Denotes lead-free package.

-40°C to +85°C 28 TQFN-EP**

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF to AGND,

LOAD_HP

= 32Ω to AGND, R

LOAD_OUT

= 10kΩ to AGND, f

LRCLK

= 48kHz, f

MCLK

= 12.288MHz, volume set to -9.5dB, TA= T

MIN

MAX

, unless otherwise noted. Typical specifications at TA= +25°C, unless otherwise noted.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(Voltages with respect to AGND.) DV

, AVDD, PVDD..................................................-0.3V to +4V

Referenced to PVDD....................................-0.3V to +0.3V

, PVSS...............................................................-4V to +0.3V

Referenced to PVSS.....................................-0.3V to +0.3V

DGND, PGND........................................................-0.3V to +0.3V

BCLK, LRCLK, HPS, SDIN.......................-0.3V to (DV

+ 0.3V)

GPIO, MCLK.............................................................-0.3V to +4V

REF, PREG...............................................-0.3V to (AV

+ 0.3V)

NREG ........................................................+0.3V to (SV

- 0.3V)

SDA, SCL, ADD ........................................................-0.3V to +4V

INL, INR .......................................................................-2V to +2V

HPR, HPL.....................................(SV

- 0.3V) to (AVDD+ 0.3V)

OUTL, OUTR .............................(NREG - 0.3V) to (PREG + 0.3V)

C1N ............................................(PV

- 0.3V) to (PGND + 0.3V)

C1P ............................................(PGND - 0.3V) to (PV

+ 0.3V)

Current Into/Out of Any Pin ...............................................100mA

Duration of HPL, HPR, OUTL,

OUTR Short Circuit to AGND .................................Continuous

Continuous Power Dissipation (T

= +70°C)

28-Pin Thin QFN (derate 35.7mW/°C above +70°C) .....2857mW

Junction Temperature......................................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

CONDITIONS

UNITS

Analog Supply Voltage

AVDD = PV

1.8 3.6 V

Digital Supply Voltage DV

1.8 3.6 V

AVDD = 1.8V 5.5 7.7

Full operation (Note 2), no headphone or line output load

= 3.0V 5.9

AVDD = 1.8V 3.5 5.3

Analog Supply Current AI

Full operation (Note 2), headphones disabled

= 3.0V

DVDD = 1.8V 2.1 2.9

Digital Supply Current DI

Full operation (Note 2), no line output load

= 3.0V 3.8

Analog Shutdown Current

AVDD

+ I

PVDD, AVDD

= P

VDD

= 1.8V 1.5 10 µA

Digital Shutdown Current

Static digital interface, D

VDD

= 1.8V 0.3 5 µA

Shutdown to Full Operation (Note 2)

1.3 ms

Power-On to Full Operation (Note 2)

PON

1.4 ms

DAC PERFORMANCE/LINE OUTPUTS (Note 3)

0dBFS Output Voltage

P-P

AVDD = 3.0V

Dynamic Range (Note 4) DR

= 1.8V 82

Unweighted 88

A-weighted 91

AVDD = 1.8V, unweighted 88

Signal-to-Noise Ratio (Note 5)

SNR

= 1.8V, A-weighted 91

SYMBOL

MIN TYP MAX

SHDN

OUT_FS

3.75

1.85 1.95 2.05

87.5

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF to AGND,

LOAD_HP

= 32Ω to AGND, R

LOAD_OUT

= 10kΩ to AGND, f

LRCLK

= 48kHz, f

MCLK

= 12.288MHz, volume set to -9.5dB, TA= T

MIN

MAX

, unless otherwise noted. Typical specifications at TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

0dBFS 87

-60dBFS

AVDD = 1.8V, 0dBFS

-81

Total Harmonic Distortion Plus Noise

fIN = 984.375Hz

= 1.8V,

-60dBFS

-22

Line Output Offset Voltage

-15 0

Channel-to-Channel Gain Matching

OUTL to OUTR, OUTR to OUTL

RIPPLE

= 100mV

P-P

, fIN = 1kHz, applied to

and PV

Power-Supply Rejection Ratio PSRR

RIPPLE

= 100mV

P-P

, fIN = 20kHz, applied

to AV

and PV

Crosstalk XTALK

OUT

= 1kHz, V

OUT

= 2V

P-P

(OUTL to OUTR) or (OUTR to OUTL)

Sampling Frequency Range f

8 48 kHz

MCLK Frequency f

MCLK

MHz

DAC 8x INTERPOLATION FILTER

Passband Frequency PB To -1dB corner 0

0.48 x f

kHz

Frequency Response FR 10Hz to 20kHz

Stopband Attenuation SBA 58 dB

Stopband Frequency SB Attenuation greater than SBA

0.58 x f

7.42 x f

kHz

LINE INPUTS (INL, INR)

Line Input Voltage

-1 +1 V

IN_ to OUT_ Gain

-1

V/V

Line Input Bias Voltage

-15 0

INL and INR Input Resistance

10 22 kΩ

INTERNAL REGULATORS (NREG, PREG)

PREG Output Voltage V

PREG

NREG Output Voltage V

NREG

REF Output Voltage V

REF

SYMBOL

THD+N

OS_LINE

ΔAV/AV

IN_LINE

V_LINE

BIAS_LINE

IN_LINE

MIN TYP MAX

27.5

-27.5

±0.04

-105

8.448

-0.1 +0.1

-1.05

1.60

-1.15

1.23

+15

-0.95

+15

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF to AGND,

LOAD_HP

= 32Ω to AGND, R

LOAD_OUT

= 10kΩ to AGND, f

LRCLK

= 48kHz, f

MCLK

= 12.288MHz, volume set to -9.5dB, TA= T

MIN

MAX

, unless otherwise noted. Typical specifications at TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

HEADPHONE OUTPUTS (HPL, HPR)

RL = 16Ω AV

= 3.0V

RL = 32Ω AV

= 3.0V

40 65

RL = 16Ω AV

= 1.8V

Output Power OUT

THD+N = 1%

volume = +6dB

= 32Ω

= 1.8V

15 25

Full-Scale Headphone Amplifier Output Voltage

Volume = +5dB, HP unloaded

RMS

Line In to HP Output Voltage Gain

V_HP

Volume = +3dB, HP unloaded

V/V

RL = 32Ω, P

OUT

= 60mW, fIN = 1kHz -94

Total Harmonic Distortion Plus Noise

RL = 16Ω, P

OUT

= 60mW, fIN = 1kHz -90

Unweighted 88

A-weighted 90

AVDD = 1.8V, unweighted 88

Signal-to-Noise Ratio (Note 6) SNR

= 1.8V, A-weighted 91

RIPPLE

= 100mV

P-P

, frequency = 1kHz,

applied to AV

and PV

Power-Supply Rejection Ratio PSRR

RIPPLE

= 100mV

P-P

, frequency = 20kHz,

applied to AV

and PV

TA = +25°C -15

Headphone Output Offset Voltage

Volume = -11.5dB

= T

MIN

to T

MAX

-25

Slew Rate SR

V/µs

Maximum Capacitive Load C

No sustained oscillations

Crosstalk XTALK

= 32Ω, P

OUT

= 3.5mW, fIN = 1kHz

(HPL to HPR) or (HPR to HPL)

-85 dB

Channel-to-Channel Gain Matching

ΔA

V/AV

Internal Charge-Pump Oscillator Frequency

kHz

Charge-Pump Operating Frequency Range

Charge-pump clock derived from MCLK

kHz

Volume Control Range

SYMBOL

fIN = 1kHz, headphone

MIN TYP MAX

OUT_FS

THD+N

OS_HP

1.16 1.23 1.30

1.34 1.41 1.48

+15

+25

0.47

150

±0.05

550 667 775

550 775

-73.5 +6.0

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF to AGND,

LOAD_HP

= 32Ω to AGND, R

LOAD_OUT

= 10kΩ to AGND, f

LRCLK

= 48kHz, f

MCLK

= 12.288MHz, volume set to -9.5dB, TA= T

MIN

MAX

, unless otherwise noted. Typical specifications at TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

Mute Attenuation

DIGITAL INPUTS (GPIO, SCL, SDA, BCLK, LRCLK, SDIN, ADD, MCLK)

Input High Voltage V

0.8 x V

Input Low Voltage V

0.2 x V

Input Leakage Current IIH, I

VIH = DVDD, VIL = DGND -10

µA

Input Hysteresis

0.09 x V

Input Capacitance C

10 pF

OPEN-DRAIN DIGITAL OUTPUTS (GPIO, SDA)

Output-High Leakage Current I

VOH = DVDD (Note 7) 1 µA

DVDD > 2V 0.4

Output Low Voltage V

IOL = 3mA

< 2V

0.2 x

CMOS DIGITAL OUTPUTS (BCLK, LRCLK)

Output High Voltage V

IOH = 1mA

0.4

Output Low Voltage V

IOL = 1mA 0.4 V

HEADPHONE SENSE INPUT (HPS)

Input High Voltage V

0.7 x V

Input Low Voltage V

0.25 x V

Full shutdown, VIH = DV

Input-High Leakage Current I

Normal operation, VIH = DV

µA

Full shutdown, VIL = DGND 1

Input-Low Leakage Current I

Normal operation, VIL = DGND

µA

Input Hysteresis

0.05 x V

SYMBOL

MIN TYP MAX

100

+10

400

100

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

6 _______________________________________________________________________________________

TIMING CHARACTERISTICS

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF to AGND,

LOAD_HP

= 32Ω to AGND, R

LOAD_LINE

= 10kΩ to AGND, f

LRCLK

= 48kHz, f

MCLK

= 12.288MHz, volume set to -9.5dB, TA= T

MIN

MAX

, unless otherwise noted. Typical specifications at TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

I2C TIMING

Serial Clock Frequency f

SCL

kHz

Bus Free Time Between STOP and START Conditions

BUF

1.3 µs

Hold Time (Repeated) START Condition

0.6 µs

SCL Pulse-Width Low t

LOW

1.3 µs

SCL Pulse-Width High t

HIGH

0.6 µs

Repeated START Condition Setup Time

0.6 µs

Data Hold Time

Data Setup Time

Bus Capacitance C

SDA and SCL Receiving Rise Time (Note 8)

20 +

SDA and SCL Receiving Fall Time (Note 8)

20 +

DVDD = 1.8V, TA = +25°C

20 +

SDA Transmitting Fall Time (Note 8)

DVDD = 3.6V, TA = +25°C

20 +

Setup Time for STOP Condition

0.6 µs

Pulse Width of Suppressed Spike

050ns

DIGITAL AUDIO TIMING

BCLK Period (Note 9) t

BCLK

Low or High BCLK Pulse Width

0.35 x ns

BCLK and LRCLK Rise Time t

Master mode, C

LOAD

= 15pF 1 ns

BCLK and LRCLK Fall Time t

Master mode, C

LOAD

= 15pF 1 ns

SDIN or LRCLK to BCLK Rising Setup Time

DBSU,

BWSU

30 ns

DVDD = 1.8V 0

SDIN or LRCLK to BCLK Rising Hold Time

DBH,

BWBH

DVDD = 3.6V 5

Note 1: The MAX9850 is 100% production tested at TA= +25°C and is guaranteed by design for TA= T

MIN

to T

MAX

Note 2: Full operation is defined as clocking all zeros into the DAC while the DAC, headphone outputs, and line outputs are all enabled. Note 3: DAC performance specifications measured using the line outputs, OUTL and OUTR. Note 4: Dynamic range is defined as the SNR of a 1kHz, -60dBFS input signal measured with an A-weighted filter, then normalized

to full scale (+60dB).

SYMBOL

HD, STA

SU, STA

HD, DAT

SU, DAT

SU, STO

BCLK_PW

MIN TYP MAX

100

0.1C

0.05C

1 / f

3 x

IC LK

BCLK

400

900

400

300

250

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

_______________________________________________________________________________________ 7

Note 5: DAC SNR measured from DAC inputs to OUTL and OUTR. Note 6: Headphone amplifier SNR measured from line inputs to headphone outputs. Note 7: GPIO is 100kΩ to ground when DV

< VOH< 3.6V.

Note 8: C

is in pF.

Note 9: f

ICLK

derived by dividing f

MCLK

by 1, 2, 3, or 4. See the Registers and Bit Descriptions section.

TYPICAL POWER DISSIPATION AT AVDD= 1.8V (No Headphone/Line Output Load)

MODE AVDD POWER DVDD POWER PVDD POWER

TOTAL POWER

Full Operation (Note 1) 4.93mW 3.76mW 5.00mW 13.70mW

DAC to Line Outputs, Headphones Disabled 3.11mW 3.76mW 3.22mW 10.10mW

Line Inputs to Line Outputs and Headphone Outputs, DAC Disabled

3.22mW 0.085mW 3.40mW 6.71mW

Line Inputs to Line Outputs, DAC and Headphones Disabled

1.39mW 0.085mW 1.61mW 3.08mW

Full Shutdown 2.7µW 0.5µW <0.1µW 3.2µW

Typical Operating Characteristics

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF, fS= 48kHz,

MCLK

= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA= +25°C, unless

otherwise noted. f

= 984.375Hz, A-weighted THD+N.)

TOTAL HARMONIC DISTORTION PLUS NOISE

0.1

THD+N (%)

0.01

0.001

(DAC TO HP) vs. POWER OUT

AVDD = 1.8V

= 16

fIN = 10kHz

fIN = 20Hz

02010 40 60

POWER OUT (mW)

fIN = 1kHz

30 50

MAX9850toc01

TOTAL HARMONIC DISTORTION PLUS NOISE

(LINE IN TO HP) vs. POWER OUT

AVDD = 1.8V

= 16

0.1

THD+N (%)

0.01

0.001

fIN = 1kHz

fIN = 10kHz

fIN = 20Hz

02010 40 60

30 50

POWER OUT (mW)

MAX9850toc02

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO HP) vs. POWER OUT

AVDD = 1.8V

= 32

0.1

THD+N (%)

0.01

fIN = 10kHz

0.001 02010 40 50

POWER OUT (mW)

fIN = 1kHz

fIN = 20Hz

MAX9850toc03

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

8 _______________________________________________________________________________________

0.001 10 100 10k 100k

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO HP) vs. FREQUENCY

0.01

0.1

MAX9850toc09

FREQUENCY (Hz)

THD+N (%)

AVDD = 1.8V R

= 16Ω

OUT

= 5mW

OUT

= 21mW

0.001 10 100 10k 100k

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO HP) vs. FREQUENCY

0.01

0.1

MAX9850toc10

FREQUENCY (Hz)

THD+N (%)

AVDD = 1.8V R

= 32Ω

OUT

= 3mW

OUT

= 15mW

0.001 10 100 10k 100k

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO LINE OUT) vs. FREQUENCY

0.01

0.1

MAX9850toc11

FREQUENCY (Hz)

THD+N (%)

AVDD = 1.8V TO 3.0V R

= 10kΩ

OUT

= 2V

P-P

0.001 10 100 10k 100k

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO HP) vs. FREQUENCY

0.01

0.1

MAX9850toc12

FREQUENCY (Hz)

THD+N (%)

AVDD = 3.0V R

= 16Ω

OUT

= 10mW

OUT

= 60mW

Typical Operating Characteristics (continued)

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF, fS= 48kHz,

MCLK

= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA= +25°C, unless

otherwise noted. fIN= 984.375Hz, A-weighted THD+N.)

TOTAL HARMONIC DISTORTION PLUS NOISE

(LINE IN TO HP) vs. POWER OUT

AVDD = 1.8V

= 32

0.1

THD+N (%)

fIN = 1kHz

MAX9850toc04

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO HP) vs. POWER OUT

AVDD = 3.0V

= 16

fIN = 1kHz

0.1

THD+N (%)

fIN = 10kHz

MAX9850toc05

TOTAL HARMONIC DISTORTION PLUS NOISE

(LINE IN TO HP) vs. POWER OUT

AVDD = 3.0V

= 16

0.1

THD+N (%)

fIN = 1kHz

fIN = 20Hz

fIN = 10kHz

MAX9850toc06

0.01

0.001 02010 40 50

POWER OUT (mW)

fIN = 10kHz

fIN = 20Hz

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO HP) vs. POWER OUT

AVDD = 3.0V

= 32

0.1

THD+N (%)

0.01

0.001 04020 100

fIN = 1kHz

fIN = 10kHz

60 80

POWER OUT (mW)

fIN = 20Hz

MAX9850toc07

0.01

fIN = 20Hz

0.001 04020 100

POWER OUT (mW)

60 80

TOTAL HARMONIC DISTORTION PLUS NOISE

(LINE IN TO HP) vs. POWER OUT

AVDD = 3.0V

= 32Ω

0.1

THD+N (%)

0.01

0.001

fIN = 1kHz

fIN = 10kHz

04020 100

POWER OUT (mW)

fIN = 20Hz

60 80

MAX9850toc08

0.01

0.001 04020 100

POWER OUT (mW)

60 80

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

_______________________________________________________________________________________ 9

0.001 10 100 10k 100k

TOTAL HARMONIC DISTORTION PLUS NOISE

(DAC TO HP) vs. FREQUENCY

0.01

0.1

MAX9850toc13

FREQUENCY (Hz)

THD+N (%)

AVDD = 3.0V R

= 32Ω

OUT

= 6mW

OUT

= 50mW

100

120

140

160

0 10203040

POWER DISSIPATION

vs. POWER OUT

MAX9850toc14

POWER OUT (mW)

POWER DISSIPATION (mW)

AVDD = PVDD = DVDD = 1.8V P

OUT

= P

HPR

+ P

HPL

LOAD

= 16Ω

LOAD

= 32Ω

100

150

200

250

300

350

0 50 100 150

POWER DISSIPATION

vs. POWER OUT

MAX9850toc15

POWER OUT (mW)

POWER DISSIPATION (mW)

AVDD = PVDD = DVDD = 3.0V P

OUT

= P

HPR

+ P

HPL

LOAD

= 16Ω

LOAD

= 32Ω

10 100 1000

POWER OUT

vs. HEADPHONE LOAD

MAX9850toc16

LOAD

(Ω)

POWER OUT (mW)

AVDD = 1.8V LINE IN TO HP OUT f

= 1kHz

THD+N = 10%

THD+N = 1%

140

10 100 1000

POWER OUT

vs. HEADPHONE LOAD

MAX9850toc17

LOAD

(Ω)

POWER OUT (mW)

100

120

AVDD = 3.0V LINE IN TO HP OUT f

= 1kHz

THD+N = 10%

THD+N = 1%

100

160

140

120

180

1.0 2.01.5 2.5 3.0 3.5 4.0

POWER OUT

vs. SUPPLY VOLTAGE

MAX9850toc18

SUPPLY VOLTAGE (V)

POWER OUT (mW)

THD+N = 10%

THD+N = 1%

RL = 16Ω LINE IN TO HP OUT f

= 1kHz

100

1.0 2.01.5 2.5 3.0 3.5 4.0

POWER OUT

vs. SUPPLY VOLTAGE

MAX9850toc19

SUPPLY VOLTAGE (V)

POWER OUT (mW)

THD+N = 1%

RL = 32Ω LINE IN TO HP OUT f

= 1kHz

THD+N = 10%

-10

-20

-30

-40

-50

-70

-80

-90

-120 10 100 10k 100k

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY (DAC TO HP)

-110

-100

-60

MAX9850toc20

FREQUENCY (Hz)

PSRR (dB)

AVDD = 1.8VDC

= 3.0VDC

LOAD

= 10kΩ

RIPPLE

APPLIED TO

AND PVDD = 100mV

P-P

CLOCKING ZEROS INTO DAC VOLUME SET AT -9.5dB

-10

-20

-30

-40

-50

-70

-80

-90

-120 10 100 10k 100k

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY (DAC TO LINE OUT)

-110

-100

-60

MAX9850toc21

FREQUENCY (Hz)

PSRR (dB)

AVDD = 1.8VDC

= 3.0VDC

LOAD

= 10kΩ

RIPPLE

APPLIED TO

AND PVDD = 100mV

P-P

CLOCKING ZEROS INTO DAC

Typical Operating Characteristics (continued)

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF, fS= 48kHz,

MCLK

= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA= +25°C, unless

otherwise noted. fIN= 984.375Hz, A-weighted THD+N.)

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

10 ______________________________________________________________________________________

-40

-50

-60

-70

-80

-90

-110

-120 10 100 10k 100k

CROSSTALK vs. FREQUENCY

(DAC IN TO HP OUT)

-100

MAX9850toc22

FREQUENCY (Hz)

CROSSTALK (dB)

L TO R

R TO L

VOLUME SET TO -9.5dB DAC IN = 0dBFS R

LOAD

= 32Ω

-40

-50

-60

-70

-80

-90

-110

-120 10 100 10k 100k

CROSSTALK vs. FREQUENCY

(LINE IN TO HP OUT)

-100

MAX9850toc23

FREQUENCY (Hz)

CROSSTALK (dB)

L TO R

R TO L

VOLUME SET TO -9.5dB LINE IN = 1V

RMS

LOAD

= 32Ω

-40

-50

-60

-70

-80

-90

-110

-120 10 100 10k 100k

CROSSTALK vs. FREQUENCY

(DAC IN TO LINE OUT)

-100

MAX9850toc24

FREQUENCY (Hz)

CROSSTALK (dB)

L TO R

R TO L

VOLUME SET TO -9.5dB DAC IN = 0dBFS

-140

-100

-120

-60

-80

-20

-40

FFT, SLAVE NONINTEGER MODE

(DAC IN = 0dBFS)

MAX9850toc25

FREQUENCY (kHz)

LINE OUT (dBFS)

0 5 10 15 20

LINE OUT f

= 1kHz

MCLK

= 12MHz

-140

-100

-120

-60

-80

-20

-40

FFT, SLAVE NONINTEGER MODE

(DAC IN = -60dBFS)

MAX9850toc26

FREQUENCY (kHz)

LINE OUT (dBFS)

0 5 10 15 20

LINE OUT f

= 1kHz

MCLK

= 12MHz

-140

-100

-120

-60

-80

-20

-40

FFT, SLAVE NONINTEGER MODE

(DAC IN = IDLE)

MAX9850toc27

FREQUENCY (Hz)

LINE OUT (dBFS)

0 5 10 15 20

LINE OUT f

MCLK

= 12MHz

-140

-100

-120

-60

-80

-20

-40

FFT, MASTER INTEGER MODE

(DAC IN = 0dBFS)

MAX9850toc28

FREQUENCY (Hz)

LINE OUT (dBFS)

0 5 10 15 20

LINE OUT f

= 1kHz

MCLK

= 12.288MHz

-140

-100

-120

-60

-80

-20

-40

FFT, MASTER INTEGER MODE

(DAC IN = -60dBFS)

MAX9850toc29

FREQUENCY (Hz)

LINE OUT (dBFS)

0 5 10 15 20

LINE OUT f

= 1kHz

MCLK

= 12.288MHz

-140

-100

-120

-60

-80

-20

-40

FFT, MASTER INTEGER MODE

(DAC IN = IDLE)

MAX9850toc30

FREQUENCY (Hz)

LINE OUT (dBFS)

0 5 10 15 20

LINE OUT f

MCLK

= 12.288MHz

Typical Operating Characteristics (continued)

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF, fS= 48kHz,

MCLK

= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA= +25°C, unless

otherwise noted. fIN= 984.375Hz, A-weighted THD+N.)

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 11

1.0

0.8

0.4

0.6

0.2

-0.2

-0.4

-0.8

-1.0 10 100 10k 100k

GAIN FLATNESS

vs. FREQUENCY

-0.6

MAX9850toc31

FREQUENCY (Hz)

GAIN (dB)

LOAD

= 32Ω

DAC IN TO HP DAC IN = 0dBFS

100

SNR vs. MCLK FREQUENCY

MAX9850toc32

MCLK FREQUENCY (MHz)

SNR (dB)

510203015 25 35 40

SLAVE NONINTEGER MODE DAC IN = -60dBFS f

LRCLK

= 32kHz, 44.1kHz, 48kHz

= 3.0V

ICLK

= f

MCLK

/ 1

ICLK

= f

MCLK

/ 2

ICLK

= f

MCLK

/ 3

ICLK

= f

MCLK

/ 4

-20

-40

-60

-80

-120

-140 10 100 10k 100k

WIDEBAND FFT

-100

MAX9850toc33

FREQUENCY (Hz)

OUT

(dBFS)

DAC IN = 0dBFS DAC IN TO LINE OUT f

= 1kHz

-20

-40

-60

-80

-120

-140 10 100 10k 100k

WIDEBAND FFT

-100

MAX9850toc34

FREQUENCY (Hz)

OUT

(dBFS)

DAC IN = -60dBFS DAC IN TO LINE OUT f

= 1kHz

-40 -15 3510 60 85

OUTPUT POWER

vs. TEMPERATURE

MAX9850toc35

TEMPERATURE (°C)

OUTPUT POWER (mW)

AVDD = 1.8V THD+N = 1%

LOAD

= 16Ω

LOAD

= 32Ω

1.8 2.2 3.02.6 3.42.0 2.82.4 3.2 3.6

AVDD AND PVDD SUPPLY CURRENT

vs. AV

AND PVDD SUPPLY VOLTAGE

MAX9850toc36

AVDD AND PVDD (V)

+ PV

SUPPLY CURRENT (mA)

TA = +85°C

TA = +25°C

TA = -40°C

1.0 2.0 3.01.5 3.52.5 4.0

DIGITAL SUPPLY CURRENT

vs. DV

MAX9850toc37

DVDD (V)

DIGITAL SUPPLY CURRENT (mA)

TA = +85°C, +25°C, -40°C

Typical Operating Characteristics (continued)

(DVDD= AVDD= PVDD= 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47µF, C2 = 2.2µF, C

NREG

= C

PREG

= C

REF

= 1µF, fS= 48kHz,

MCLK

= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA= +25°C, unless

otherwise noted. fIN= 984.375Hz, A-weighted THD+N.)

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

12 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 LRCLK

Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock and determines whether the audio data on SDIN is routed to the left or right channel. LRCLK is an input when the MAX9850 is in slave mode and an output when in master mode.

2 BCLK

Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9850 is in slave mode and an output when in master mode.

3 SDIN Digital Audio Serial Data Input

4DVDDDigital Power-Supply Input. Bypass to DGND with a 1µF ceramic capacitor.

5 MCLK Master Clock Input. All internal digital clocks are derived from MCLK.

6 DGND Digital Ground

7 ADD

C Address-Select Input. Connect to AGND, AVDD, or SDA to select one of the three possible I2C

addresses.

8 GPIO

General-Purpose Input/Output. Configure GPIO as an input or an output through the GPIO register. GPIO can perform the function of an interrupt when configured as an output. See the GPIO section.

9 INR Right-Channel Line Input. INR is mixed with the right DAC output.

10 INL Left-Channel Line Input. INL is mixed with the left DAC output.

11 OUTR Line Level Right-Channel Output. OUTR is biased at AGND.

12 OUTL Line Level Left-Channel Output. OUTL is biased at AGND.

13 REF Reference Output. Bypass to AGND with a 1µF ceramic capacitor.

14 AGND Analog Ground

15 NREG Line Output Negative Regulator Output. Bypass to AGND with a 1µF capacitor.

16 PREG Line Output Positive Regulator Output. Bypass to AGND with a 1µF capacitor.

17 AV

Analog Power Supply. Bypass to AGND with a 1µF ceramic capacitor.

18 HPR Right-Channel Headphone Output. HPR is a DirectDrive output biased at AGND.

19 HPL Left-Channel Headphone Output. HPL is a DirectDrive output biased at AGND.

20 SV

Headphone Amplifier Negative Power-Supply Input. Connect to PVSS.

21 HPS

Headphone Sense Input. Connect to the control pin of a headphone jack for automatic headphone sensing. Float HPS if unused. See the Headphone Sense Input (HPS) section.

22 PV

Inverting Charge-Pump Output. Bypass to PGND with a 2.2µF ceramic capacitor and connect to SV

to provide the headphone amplifiers with a negative supply.

23 C1N

Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47µF ceramic capacitor between C1N and C1P.

24 PGND Charge-Pump Ground

25 C1P

Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47µF ceramic capacitor between C1P and C1N.

26 PV

Charge-Pump and Headphone Amplifier Positive Power-Supply Input. Bypass to PGND with a 1µF ceramic capacitor. Connect to AV

for normal operation.

27 SCL I2C-Compatible Serial Clock Input

28 SDA I2C-Compatible Serial Data Input/Output

— EP Exposed Thermal Pad. Connect EP to AGND.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 13

Functional Diagram/Typical Operating Circuit

MONO

VOLUME/MUTE

CONTROL

LINE OUT

POSITIVE

REGULATOR

LINE OUT

NEGATIVE

REGULATOR

VOLUME/MUTE

CONTROL

LINE OUT AMP

INTERPOLATOR

RIGHT

DAC

LEFT

DAC

MAX9850

321

DIGITAL

AUDIO

INTERFACE

DSP

SDIN

BCLK

LRCLK

INTERFACE

SDA

SCL

GPIO

CLOCK CONTROL

AND DIGITAL PLL

CHARGE

PUMP

C1P C1N PV

25 23 22

PGND DGND AGND

24 620

OUTR

HPL

HPS

HPR

OUTL

LINE OUT

INL

LEFT LINE

INPUT

NREG

0.1μF1μF

2.2μF

0.47μF

ADD

10kΩ 10kΩ10kΩ

μC

1.8V TO 3.6V 54

MCLK DV

REF

1μF

INR

1.8V TO 3.6V

1μF 0.1μF1μF

1μF

PREG

RIGHT LINE

INPUT

MAX9850

Detailed Description

The MAX9850 audio digital-to-analog converter (DAC) with a stereo DirectDrive headphone amplifier is a complete digital audio playback solution. The sigma-delta DAC has 90dB of dynamic range and accepts stereo audio data at sampling frequencies ranging from 8kHz to 48kHz. Headphone output volume level, muting, and device configuration are programmed through the I

C-compatible interface. Three selectable I2C device IDs are available. Both basic modes of operation, integer and noninteger, provide full dynamic range performance and allow maximum flexibility when choosing the MAX9850’s master clock (MCLK) frequency. Integer mode operation requires that MCLK is an integer multiple of 16 times the sample rate, and provides maximum full-scale SNR performance. Noninteger mode allows maximum flexibility when choosing an MCLK frequency, as the MCLK may be any frequency in the acceptable range.

Audio data is sent to the MAX9850 through a 3-wire digital audio data bus that supports numerous input formats. LRCLK and BCLK signals are generated by the MAX9850 when configured in master mode. The MAX9850 can also be configured as a slave device, accepting LRCLK and BCLK signals from an external digital audio master. External LRCLK and BCLK signals may be either synchronous or asynchronous with MCLK when the MAX9850 is configured as a slave device.

Maxim’s DirectDrive architecture employs an internal charge pump to create a negative voltage supply to power the headphone amplifier outputs. The internal negative supply allows the analog output signals to be biased at ground, eliminating the need for an outputcoupling capacitor, reducing system cost and size.

The MAX9850’s stereo line inputs allow mixing of analog audio with digital audio. The summed audio signal is sent directly to the line and headphone outputs. The line inputs/outputs can be activated even when the DAC is disabled and MCLK is not present.

The headphone sense input (HPS) detects when a headphone is connected to the MAX9850. The HPS circuit shuts down the headphone amplifier outputs when no headphones are connected. The headphone amplifiers can be automatically enabled when HPS detects the presence of headphones.

Sigma-Delta DAC

The MAX9850 uses a sigma-delta DAC to achieve up to 91dB of SNR. The DAC receives a stereo digital input signal sampled at f

LRCLK

, interpolates the signal data

to an 8 times f

LRCLK

frequency, and digitally filters the

samples. The resulting oversampled digital signal is then converted using a multibit sigma-delta modulator followed by an analog smoothing filter that greatly attenuates high-frequency quantization noise typical with oversampling converters. Flexible clocking modes allow the MAX9850 to be used effectively in applications normally not well suited for oversampling converters all without the need for expensive sample rate converters.

Set DACEN = 0 in the enable register (register 0x5, bit B0) to disable the DAC. Set DACEN = 1 to enable the DAC.

Line Outputs/Inputs

The MAX9850 features line inputs (INR, INL) and line outputs (OUTR, OUTL). The line inputs allow a line level signal to be mixed with the DAC output, see the Functional Diagram/Typical Operating Circuit. Set LNIEN = 1 in the enable register (register 0x5, bit B1) to enable the line inputs. The line inputs are biased at AGND and can be directly coupled or AC-coupled to INR and INL, depending on the signal source.

Stereo DirectDrive line outputs (OUTR and OUTL) can be used to drive line-level loads. Line outputs internally drive the inputs of the headphone amplifier. Set LNOEN = 1 in the enable register (register 0x5, bit B2) to enable the line outputs. Disabling the line outputs will also disable the headphone outputs.

The internal charge pump must be enabled to operate the line outputs. Enable the charge pump by configuring CPEN(1:0) = 11 in the enable register (register 0x5, bit B5 and B4). See the Charge Pump section.

DirectDrive Headphone and

Line Amplifiers

Unlike the MAX9850, traditional single-supply headphone amplifiers have their outputs biased about a nominal DC voltage, typically half the supply, for maximum dynamic range. Large coupling capacitors are typically needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier.

Maxim’s DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the MAX9850 headphone and line outputs to be biased about ground, almost doubling the dynamic range while operating from a single supply. With no DC component, there is no need for the large DCblocking capacitors. Instead of two large (33µF to 330µF) capacitors, the MAX9850 charge pump

Stereo Audio DAC with DirectDrive Headphone Amplifier

14 ______________________________________________________________________________________

requires only two small ceramic capacitors (0.47µF and

2.2µF), conserving board space, reducing cost, improving the frequency response, and THD of the headphone amplifier. In addition to the cost and size disadvantages, the DC-blocking capacitors required by conventional headphone amplifiers limit low-frequency response and decrease PSRR performance. Some dielectrics can significantly distort the audio signal.

Volume Control

Program VOL(5:0) in the volume register (register 0x2, bits B5–B0) to set the volume attenuation of the headphone amplifiers. Program VOL(5:0) to 0x00 for full volume. Minimum volume occurs at VOL(5:0) greater than or equal to 0x28. VMN in the status A register (register 0x0, bit B3) sets to 1 when the MAX9850 output is programmed to and reaches volume step 0x3F. Figure 1 shows the attenuation profile for each VOL(5:0) value.

Volume Slew, Zero-Crossing Detect, and Mute

Set SLEW = 1 in the volume register (register 0x2, bit B6) to enable the volume slew circuit. When SLEW = 1 headphone amplifier volume changes will slew between programmed levels smoothly. Set the volume slew rate with SR(1:0) in the charge-pump register (register 0x7, bits B7 and B6). Table 1 lists the volume slew-rate settings for each value of SR(1:0).

Set ZDEN = 1 in the general-purpose register (register 0x3, bit B0) to force volume changes and headphone amplifier muting to occur when the audio signal is at its zero crossing. For optimal performance, set SR(1:0) to

01. This zero-crossing detection reduces audible clicks/pops caused when transitioning or slewing between volume levels.

Set MUTE = 1 in the volume register (register 0x2, bit B7) to mute the headphone amplifiers. The mute function is independent of the volume control. The programmed volume settings are not reset when mute is enabled. With the zero-crossing detection and volume slew enabled, the Mute command mutes the output after the first zero crossing or after a 200ms timeout (SR = 01).

Mono Mode

Set MONO = 1 in the general-purpose register (register 0x3, bit B2) to enable mono mode. In mono mode, HPR is disabled, the left and right audio channels are summed and output on HPL. The 6dB attenuation ensures that the summed signal amplitude does not overdrive headphone amplifiers. SMONO in the status B register (register 0x1, bit B4) sets to 1 when the MAX9850 is in mono mode.

Configuring the Headphone and Line Outputs

Set HPEN and LNOEN in the enable register (register 0x5, bits B3 and B2) equal to 1 to enable the headphone outputs (HPR and HPL). Set HPEN or LNOEN = 0 to disable the headphone outputs.

The headphone amplifier inputs are driven from the outputs of the line amplifier. Disabling the line out by setting LNOEN = 0 in the enable register (register 0x5, bit B2), deprives the headphone amplifiers of an input signal and disables the headphone outputs (HPR and HPL).

The internal charge pump must be enabled to operate the headphone and line outputs. Enable the charge pump by programming CPEN(1:0) = 11 in the enable register (register 0x5, bits B5 and B4). See the Charge Pump section for more details.

Headphone Sense Input (HPS)

The headphone sense input (HPS) monitors the headphone jack, and automatically disables the headphone amplifiers based upon the voltage applied at HPS. For automatic headphone detection, connect HPS to the

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 15

VOL(5:0) CODE

HEADPHONE ATTENUATION (dB)

564832 4016 248

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-120 064

Figure 1. Headphone Amplifier Attenuation Profile

Table 1. Slew-Rate Settings

TYPICAL VOLUME SLEW RATE

SR1

SR0

FROM FULL

FROM FULL VOLUME TO

VMN = 1 (ms)

0 0 63µs 0.1

0 1 125ms 200

1 0 63ms 100

1 1 42ms 67

VOLUME TO MUTE

MAX9850

control pin of a 3-wire headphone jack as shown in Figure 2. With no headphone present, the output impedance of the headphone amplifier pulls HPS to less than 0.3 x DVDD. When a headphone is inserted into the jack, the control pin is disconnected from the tip contact and HPS is pulled to DVDDthrough the internal 100kΩ pullup. No external resistor is required. Leave HPS floating if automatic headphone sensing is not used. HPS must be high and HPEN (register 0x5, bit B3) must be set to 1 for the headphone amplifiers (HPR and HPL) to output an audio signal.

The MAX9850 includes an HPS debounce circuit that ignores short duration changes on HPS. The debounce circuit ensures that a headphone is properly connected before powering up and enabling the headphone amplifiers. Program DBDEL(1:0) in the general-purpose register (register 0x3, bits B4 and B3) to set the HPS debounce delay time. The delay time is based on a division of the charge-pump frequency, fCP. See the Charge Pump section for details on programming the charge-pump frequency. Table 2 lists the available delay times of the debounce circuit.

There is no delay on removal of a headphone when using automatic headphone sense. The headphone amplifiers are immediately placed into shutdown when HPS goes high.

SHPS in the status A register (register 0x0, bit B4) reports the status of HPS. SHPS = 0 when HPS is low and SHPS = 1 when HPS is high.

GPIO

Configure GPIO as an input or an output with the GPD bit in the general-purpose register (register 0x3, bit B5). GPD = 1 configures GPIO as an open-drain output while GPD = 0 makes GPIO an input. Connect an external pullup resistor from GPIO to DV

when GPIO is

configured as an output.

GPIO as an output allows the MAX9850 to drive an LED or other state indicator. It also can be used to provide an interrupt signal to alert a µC when an event has occurred. Potential events include changes in internal PLL lock state, connecting headphones to HPS, headphone outputs reaching the minimum volume, or an overcurrent on the headphone outputs. Any of these events can be programmed to pulse GPIO’s output state when GPIO is configured as an open-drain output.

Using GPIO as an input allows the MAX9850 to receive a signal from a µC’s digital I/O or other device. The status of GPIO is read through SGPIO in the status A register (register 0x0, bit B6).

GPIO as an Output

Set GPD = 1 (register 0x3, bit B5) to configure GPIO as an output. Program the output operating mode of GPIO with GM(1:0) in the general-purpose register (register 0x3, bits B7 and B6). GPIO can be programmed to output logic-high, a logic-low, or it can be programmed to output an interrupt signal by changing state when the ALERT bit in the status A register (register 0x0, bit B7) sets. Table 3 lists GPIO’s modes of operation.

Stereo Audio DAC with DirectDrive Headphone Amplifier

16 ______________________________________________________________________________________

100k

SHDN*

HPS

MAX9850

*SHDN = 1 FOR THIS DIAGRAM

Figure 2. Headphone Sense (HPS) Input

Table 2. HPS Debounce Times

DBDEL(0)

DEBOUNCE

TIME

(ms)

DEBOUNCE TIME

BASED ON

fCP = 667kHz (ms)

0 0 0 0 (Disabled)

Approx 200

Approx 400

Approx 800

Table 3. GPIO Output Operating Modes (GPD = 1)

GM(1)

MODE DESCRIPTION

0 0 GPIO = 0

0 1 GPIO = High impedance

1 0 GPIO = 0, ALERT output pulse enabled

GPIO = High impedance, ALERT output pulse enabled

DBDEL(0)

217 x 1 / f

218 x 1 / f

219 x 1 / f

GM(0)

The interrupt enable register programs the MAX9850 to set ALERT = 1 when an event occurs. GPIO pulses when ALERT sets if GM(1:0) is programmed with 10 or

11. Table 4 contains a list of events that can set ALERT and their corresponding bit positions in the interrupt enable register. Enable the interrupt for each event by setting its bit to 1.

GPIO as an Input

The state of the GPIO input is read through SGPIO in the status A register (register 0x0, bit B6). Set ISGPIO = 1 to allow ALERT to set when SGPIO changes state.

Internal Timing

The internal clock (ICLK) and sample rate clock (LRCLK in master mode) are derived from MCLK. The MAX9850’s flexible operating modes allow any desired LRCLK sample rate to operate over a wide range of MCLK input frequencies.

Figure 3 shows a flowchart detailing how the internal clocks are derived from MCLK. The MAX9850 generates ICLK by dividing the MCLK frequency. Higher ICLK frequencies allow for greater DAC oversampling and SNR performance. Dynamic range of 90dB (typ) is possible when f

ICLK

is greater than or equal to 12MHz. Lower ICLK frequencies may require slightly less supply current but sacrifice dynamic range. See the SNR vs. MCLK Frequency graph in the Typical Operating Characteristics.

ICLK is a frequency-scaled version of MCLK that is used by the MAX9850 to clock the internal DAC circuitry and generate LRCLK and BCLK when in master mode. The charge-pump clock is derived from ICLK when the internal charge-pump oscillator is not used.

Connect an available system clock to MCLK, see the DAC Operating Modes section. MCLK can be supplied from any synchronous or available asynchronous system clock whose frequency falls within the 8.448MHz to 13MHz, or 16.896MHz to 40MHz range. Any MCLK within these ranges allow the MAX9850 to operate at any sample rate between 8kHz to 48kHz in either a master or slave mode of operation. Other MCLK frequencies can still be used, but will limit the sample rate ranges that the MAX9850 operates with as illustrated in Table 5.

Higher ICLK frequencies provide higher SNR. Always use the highest acceptable ICLK. Sample rates other than those listed in Table 5 can be used. The MAX9850 defaults to IC(1:0) = 0x0 at power-up.

DAC Operating Modes

Four DAC operating modes: master integer, slave integer, master noninteger, and slave noninteger allow flexibility for operating with various applications and virtually any available MCLK frequency within the system. The operating modes are set with MAS in the digital audio register (register 0xA, bit B7) and INT in the LRCLK MSB register (register 0x8, bit B7). Table 6 shows the four modes of operation and the equations needed to program the MAX9850 to use the DAC modes.

The master and slave integer modes are the modes in which DACs commonly operate. In these modes, LRCLK is ICLK divided by an integer value. A typical application would set MCLK equal to 256 x LRCLK. The MAX9850 requires that ICLK be an integer multiple of 16 x LRCLK where the integer multiple is at least 10 when in master or slave integer modes. Integer mode always provides the maximum full-scale signal level performance compared to other modes of operation. Choose integer mode over any other mode of operation when possible.

The master noninteger mode allows for a condition where LRCLK and ICLK may not be related by an integer value. In these modes, the MAX9850 can operate from any available MCLK in the system.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 17

Table 4. Interrupt Enable Register (0x4) Events

EVENT BIT NUMBER IN REGISTER 0x4

LCK (register 0x0, bit B5) sets when the internal PLL acquires or loses frequency lock B5

SHPS (register 0x0, bit B4) sets after the headphone is inserted and the debounce time has elapsed when the headphone amplifier is powered up and ready

VMN (register 0x0, bit B3) sets when the headphone amplifier minimum volume is reached B3

IOHL or IOHR (register 0x0, bits B1 or B0) sets after an overcurrent at either HPL or HPR B0

Figure 3. Internally Generated Clock Signals Derived from MCLK

IC(1:0)

MASTER CLOCK

(MCLK)

*LRCLK IS GENERATED WHEN IN MASTER MODE ONLY. THE DIVIDER IS SET WITH THE LRCLK MSB AND LRCLK LSB REGISTERS.

0x0 = 1/1 0x1 = 1/2 0x2 = 1/3 0x3 = 1/4

INTERNAL CLOCK

(ICLK)

CP(4:0)

LRCLK DIVIDER

CHARGE-PUMP CLOCK

LRCLK*

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

18 ______________________________________________________________________________________

*The first frequency listed is the minimum MCLK frequency required to operate in integer mode. The range of frequencies indicates the MCLK frequencies the MAX9850 needs to operate in any mode.

Table 5. Acceptable MCLK Frequency Ranges

MINIMUM ICLK

(MHz)

ACCEPTABLE MCLK FREQUENCIES*

(MHz)

LRCLK

(kHz)

NONINTEGER

MODE

ANY MODE

SF = 1

SF = 2

SF = 3

IC(1:0) = 0x3

SF = 4

8 1.280 1.4080 13.0

1.280 and

2.560 and

3.840 and

5.120 and

5.6320 to 40.0

11.025 1.764 1.9404 13.0

1.764 and

3.528 and

5.292 and

7.056 and

7.7616 to 40.0

12 1.920 2.1120 13.0

1.920 and

3.840 and

5.760 and

7.680 and

8.4480 to 40.0

16 2.560 2.8160 13.0

2.560 and

5.120 and

7.680 and

10.240 and

11.2640 to 40.0

22.05 3.528 3.8808 13.0

3.528 and

7.056 and

10.584 and

14.112 and

15.5232 to 40.0

24 3.840 4.2240 13.0

3.840 and

7.680 and

11.520 and

15.360 and

16.8960 to 40.0

32 5.120 5.6320 13.0

5.120 and

10.240 and

15.360 and

20.480 and

22.5280 to 40.0

44.1 7.056 7.7616 13.0

7.056 and

14.112 and

21.168 and

28.224 and

31.0464 to 40.0

48 7.680 8.4480 13.0

7.680 and

15.360 and

23.040 and

30.720 and

33.7920 to 40.0

Table 6. DAC Operating Modes

MSB LSB,

= 0

MSB LSB

LRCLK

ICLK

=×2

LSB

ICLK

LRCLK

MSB

=160

MAXIMUM ICLK

INTEGER MODE

LRCLK

)

(176 x f

LRCLK

)

(160 x f

NONINTEGER

MODE (INT = 0)

MODE

LRCLK may be any frequency within an acceptable range

LRCLK and BCLK signals supplied

IC(1:0) = 0x0

1.4080 to 13.0

1.9404 to 13.0

2.1120 to 13.0

2.8160 to 13.0

3.8808 to 13.0

4.2240 to 13.0

5.6320 to 13.0

7.7616 to 13.0

8.4480 to 13.0

SLAVE MODE

(MAS = 0)

from external source

Asynchronous

IC(1:0) = 0x1

2.8160 to 26.0

3.8808 to 26.0

4.2240 to 26.0

5.6320 to 26.0

7.7616 to 26.0

8.4480 to 26.0

11.2640 to 26.0

15.5232 to 26.0

16.8960 to 26.0

IC(1:0) = 0x2

4.2240 to 39.0

5.8212 to 39.0

6.3360 to 39.0

8.4480 to 39.0

11.6424 to 39.0

12.6720 to 39.0

16.8960 to 39.0

23.2848 to 39.0

25.3440 to 39.0

LRCLK and BCLK signals supplied

MASTER MODE

by MAX9850

Asynchronous

(MAS = 1)

INTEGER MODE

(INT = 1)

ICLK and LRCLK must be synchronous and exact integer ratio related

Synchronous

Slave modes of operation allow the MAX9850 to operate in any audio system where the LRCLK and BCLK must be supplied from an external source. When operating in slave mode, the MCLK supplied to the MAX9850 may be either synchronous or asynchronous with LRCLK. Use the slave integer mode if ICLK is synchronous and has an integer multiple of 16 x LRCLK. Integer mode ensures that the highest levels of full-scale-input signal performance can be achieved. Slave noninteger mode offers the highest degree of clock flexibility. ICLK does not need to be synchronous or an integer multiple of LRCLK when operating in slave noninteger mode.

Master modes of operation allow the MAX9850 to generate and supply an LRCLK and BCLK to other elements in the system. Use master integer mode if the provided ICLK is an integer multiple of 16 x LRCLK. Integer mode ensures that the highest levels of full-scale input signal performance can be achieved. Master noninteger mode allows the MAX9850 to supply virtually any frequency LRCLK with an accuracy better than ±0.5%.

The slave noninteger mode provides maximum flexibility for ICLK and LRCLK frequencies. The ICLK and LRCLK can be asynchronous and noninteger related. Connect any available system clock that is listed on Table 5 in the Internal Timing section. In slave noninteger mode, the acceptable MCLK frequency range is the same as master mode.

Master Integer Mode (MAS = 1, IM = 1)

The MAX9850 generates the LRCLK and BCLK in master mode. LRCLK is an integer factor of ICLK by the following equation:

where:

ICLK

= ICLK frequency. f

ICLK

must be at least 160 x

LRCLK

for proper DAC operation.

LSB

= decimal value of the data contained in LSB(7:0)

(register 0x9, bits B7–B0).

LRCLK

= LRCLK frequency.

For example:

ICLK

= 12.228MHz and N

LSB

= 16 (0x10), f

LRCLK

48kHz.

Solve the above equation for N

LSB

. Use master integer

mode if N

LSB

is an integer. Use master noninteger

mode if N

LSB

is not an integer.

Slave Integer Mode (MAS = 0, IM = 1)

The MAX9850 accepts LRCLK and BCLK from an external digital audio source when in slave integer mode. LRCLK must be an exact integer multiple of ICLK to ensure proper operation. Program LSB(7:0) (register 0x9, bits B7–B0) with the LRCLK division ratio. Use the following equation to find the value that needs to be programmed to LSB(7:0):

where:

ICLK

= ICLK frequency. f

ICLK

must be 160 x f

LRCLK

for

proper DAC operation.

LRCLK

= supplied LRCLK frequency.

LSB

= decimal value of the data contained in LSB(7:0)

(register 0x9, bits B7–B0).

For example:

ICLK

= 11.2896MHz and f

LRCLK

= 44.1kHz, N

LSB

= 16

(0x10).

Solve the above equation for N

LSB

. Use slave integer

mode if N

LSB

is an integer. Use slave noninteger mode

if N

LSB

is not an integer.

Slave Noninteger (MAS = 0, IM = 0)

In slave noninteger mode, the MAX9850 accepts an external LRCLK and converts the digital audio signal using any asynchronous ICLK within the acceptable operating range. The MAX9850 uses internal clock recovery circuitry to generate all required internal clocks. This allows the MAX9850 to operate in systems that do not have dedicated clock sources or crystal oscillators. Virtually any existing system clock will work. f

ICLK

must

be at least 176 x f

LRCLK

for proper operation.

Master Noninteger Mode (MAS = 1, IM = 0)

The ICLK frequency in some applications may not be an integer multiple of the desired LRCLK frequency. The MAX9850, operating in master noninteger mode, can generate and output any LRCLK frequency between 8kHz to 48kHz (±0.5%) with any ICLK frequen- cy within the acceptable operating range. In this mode, the MAX9850 generates LRCLK by dividing MCLK by the ratio programmed into MSB(14:8) and LSB(7:0) (register 0x8, bits B7–B0 and register 0x9, bits B6–B0). The LRCLK sample frequency can have any noninteger relationship with respect to MCLK. Calculate the values for MSB(14:8) and LSB(7:0) with the following equation:

N ROUND

MSB LSB

LRCLK

ICLK

=×

⎛

⎝

⎜

⎞

⎠

⎟

LSB

ICLK

LRCLK

×16

LRCLK

ICLK

LSB

×16

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 19

MAX9850

where:

ICLK

= ICLK frequency. f

ICLK

must be at least 176 x

LRCLK

for proper DAC operation.

LRCLK

= LRCLK frequency.

MSB,LSB

= decimal value of MSB(14:8) and LSB(7:0)

(register 0x8, bits B6–B0 and register 0x9, bits B7–B0).

Round the results of the equation to the nearest integer value.

For example:

LRCLK

= 44.1kHz, f

ICLK

= 12.288MHz.

1) Solve for N

MSB,LSB

, 15052.8.

2) Round result to nearest integer value. 15053.

3) Convert to hex, 0x3CD.

4) Program MSB(14:8) with the MSB 0x3A and program LSB(7:0) with the LSB 0xCD).

Table 7 provides examples of using master noninteger mode with various MCLK frequencies to generate useful LRCLK frequencies.

Charge Pump

The DirectDrive line and headphone outputs of the MAX9850 require a charge pump to create the internal negative power supply. Set CPEN(1:0) = 11 in the enable register (register 0x5, bits B5 and B4) to turn on the charge pump. The negative charge-pump voltage is established and the audio outputs are ready for use approximately 1.4ms after CPEN is set to 11.

The state of CP(4:0), in the charge-pump register (register 0x7, bits B4–B0), determines whether the charge-pump oscillator is derived from the internal 667kHz oscillator or from MCLK. Set CPEN(1:0) = 11 and set CP(4:0) = 0x00 to enable the internal oscillator. The charge pump runs independent from MCLK when the internal oscillator is enabled allowing the charge pump to operate when the DAC is disabled or when only the line inputs are used. No MCLK is required when only the line inputs are used.

The switching frequency of the charge pump is well beyond the audio range and does not interfere with audio signals. The switch drivers utilize techniques that minimize noise generated by turn-on and turn-off transients. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 and the PVDDbypass capacitor (see the Functional Diagram/Typical Operating Circuit).

Derive the charge-pump clock from MCLK by programming CP(4:0) to a non-zero value based on the following equation:

where:

MCLK

= MCLK frequency.

fCP= charge-pump clock frequency. Ensure fCP= 667kHz ±20% for proper operation.

SF = MCLK scale factor. SF is the decimal value of IC(1:0) + 1.

CP(4:0)

= rounded decimal value of CP(4:0) (register

0x7, bits B4–B0). N

CP(4:0)

must be greater than 1 when

deriving the charge-pump clock from I

CLK

fSF

MCLK

(:)

2=××

Stereo Audio DAC with DirectDrive Headphone Amplifier

20 ______________________________________________________________________________________

Table 7. Master Noninteger N

MSB,LSB

Examples

N (15-BIT hex VALUE)

LRCLK OUTPUT FREQUENCY (kHz)

MCLK

(MHz)

ICLK

48 44.1 32 24

16 12

18.4320

5555 4E66 38E4

2733 1C72 1555 139A 0E39

16.9344

5555

2E71

1EF6 1738 1555 0F7B

16.3840

5833 4000 3000

2000 1800 160D 1000

12.5000

39CE 29F1 1F75

14F9 0FBB 0E73

0A7C

12.2880

4000

2000 1D66 1555 1000 0EB3

0AAB

12.0000

4189 3C36

20C5 1E1B 15D8 1062 0F0E

0AEC

11.2896

45A9 4000 2E71 22D4 2000 1738 116A 1000

0B9C

9.2160

5555 4E66 38E4

2733 1C72 1555 139A 0E39

8.4672

5555

2E71

1EF6 1738 1555 0F7B

8.4480

5D17 5587 3E10 2E8C

1F08 1746 1562 0F84

Note: The N values represent the combined MSB(14:8) and LSB(7:0) values.

(MHz)

9.2160

8.4672 5CE1

8.1920

12.5000 3EEA

12.2880

12.0000

11.2896

9.2160

8.4672 5CE1

8.4480

3ACD 2AAB

3DEB

2BB1

3DEB

2AAB

22.05

2AAB

2C1A

1CE7

2AAB

2AC3

11.03

For example:

MCLK

= 12MHz, SF = 1, and fCP= 666.7kHz,

CP(4:0)

= 9.

Table 8 shows recommended CP(4:0) values for typical MCLK frequencies.

Registers and Bit Descriptions

Eleven internal registers program and report the status of the MAX9850. Table 9 lists all of the registers, their addresses, and power-on-reset state. Registers 0x0 and 0x1 are read-only while all of the other registers are read/write. Register 0xB is reserved for factory testing.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 21

Table 9. Register Map

B7 B6 B5 B4 B3 B2 B1 B0

ADDRESS

POWER-ON

RESET STATE

Status A

LCK

0x0 —

Status B X X X

SHP SLO SLI

0x1 —

Volume

VOL(5:0) 0x2 0x0C

General

Purpose

GM(1:0)

DBDEL(1:0)

0x3 0x00

Interrupt

Enable

0 0 IIOH 0x4 0x00

Enable

CPEN(1:0)

0x5 0x00

Clock 0000 IC(1:0) 0 0 0x6 0x00

Charge

Pump

SR(1:0) 0 CP(4:0) 0x7 0x00

LRCLK MSB

INT MSB(14:8) 0x8 0x00

LRCLK LSB

LSB(7:0) 0x9 0x00

Digital

Audio

INV

LSF DLY RTJ WS(1:0) 0xA 0x00

RESERVED 0xB —

X = Don’t Care.

Table 8. Recommended CP(4:0) Values for Typical MCLK Frequencies

MCLK

(MHz)

IC(1:0) SF

(kHz)

11.2896

0x08 0x0 1 705.6

12.0000

0x09 0x0 1 666.7

12.2880

0x09 0x0 1 682.7

13.0000

0x0A 0x0 1 650.0

24.0000

0x09 0x1 2 666.7

27.0000

0x07 0x2 3 642.9

ALERT SGPIO

MUTE SLEW

GPD

ISGPIO ILCK ISHPS IVMN

SHPS VMN

SMONO

CP(4:0)

IOHL IOHR

SDAC

MONO

ZDEN

SHDN MCLKEN

MAS

BCINV

HPEN LNOEN LNIEN DACEN

MAX9850

Status Registers (0x0, 0x1)

Alert Flag (ALERT)

1 = An interrupt event has occurred.

0 = No interrupt event has occurred.

ALERT is an alert flag that sets when an interrupt event has occurred. The events that can be programmed to set ALERT are as follows:

• A change in state on SGPIO indicating a change in

levels at GPIO when GPIO is configured as an input. Configure GPIO as an input and set ISGPIO = 1 in the interrupt enable register (register 0x4, bit B6).

• The internal PLL locks or unlocks with LRCLK. Set

ILCK = 1 in the interrupt enable register (register 0x4, bit B5).

• A change in state on SHPS indicating headphones

have been connected or disconnected. Set ISHPS = 1 in the interrupt enable register (register 0x4, bit B4).

• The headphone amplifier reaches its minimum vol-

ume. Set IVMN = 1 in the interrupt enable register (register 0x4, bit B3).

• An overload on either right or left headphone out-

puts (HPR, HPL). Set IIOH = 1 in the interrupt enable register (register 0x4, bit B0).

ALERT sets to 1 after an event occurs and remains set until the status A register is read. GPIO configured as an output can interrupt a µC on an ALERT event. GM(1:0) in the GPIO register (register 0x3, bits B7 and B6) control the output mode of GPIO. See the GPIO section for more information on programming GPIO as an output.

GPIO Status (SGPIO)

1 = GPIO is high.

0 = GPIO is low.

SGPIO reports the status of GPIO at the time that status A is read, regardless of whether GPIO is programmed as an input or output. A change in state on SGPIO causes ALERT to set to 1 when GPIO is configured as an input and ISGPIO = 1 in the interrupt enable register (register 0x4, bit B6).

PLL Lock Status (LCK)

1 = The internal PLL is locked with LRCLK.

0 = The internal PLL is not locked with LRCLK.

LCK reports the lock status of the internal PLL at the time that STATUS A is read. The DAC is disabled when the PLL is not locked. When the PLL is locked with LRCLK, the DAC will become operational if DACEN is equal to 1 (register 0x5, bit B0). ALERT sets to 1 when LCK changes state if ILCK = 1 in the interrupt enable register (register 0x4, bit B5).

HPS Status (SHPS)

1 = HPS is high, indicating that headphones are connected.

0 = HPS is low, indicating no headphone is connected.

SHPS reports the debounced status of HPS at the time STATUS A is read. SHPS = 0 indicates that no headphone is connected and HPS is low. SHPS sets to 1 when HPS is high, indicating headphones are connected. ALERT sets to 1 when SHPS changes state, if ISHPS = 1 in the interrupt enable register (register 0x4, bit B4).

Volume at Minimum (VMN)

1 = Headphone volume has reached its minimum volume.

0 = Headphone volume is not at its minimum.

VMN sets to 1 when the minimum headphone amplifier volume has been reached. ALERT sets to 1 when IVMN = 1 in the interrupt enable register (register 0x4, bit B3).

Headphone Overcurrent Left (IOHL)

1 = The left headphone output (HPL) has experienced an overcurrent condition.

0 = The left headphone output (HPL) is operating normally.

IOHL sets to 1, when an overcurrent occurs on the left headphone output HPL and remains set until status A is read. ALERT sets to 1 when an overcurrent on the right or left headphone output occurs if IIOH = 1 in the interrupt enable register (register 0x4, bit B0).

Headphone Overcurrent Right (IOHR)

1 = The right headphone output (HPR) has experienced an overcurrent condition.

0 = The right headphone output (HPR) is operating normally.

IOHR sets to 1 and remains set until STATUS A is read. ALERT sets to 1 when an overcurrent on the right or left headphone output occurs if IIOH = 1 in the interrupt enable register (register 0x4, bit B0).

Stereo Audio DAC with DirectDrive Headphone Amplifier

22 ______________________________________________________________________________________

Table 10. Status A (0x0) Read-Only, Bit Descriptions

B7B6B5B4B3B2B1

IOHR

ALERT SGPIO LCK SHPS VMN

IOHL

Mono Status (SMONO)

1 = The headphone amplifier outputs are in mono mode.

0 = The headphone amplifier outputs are in stereo mode.

SMONO indicates whether the headphone outputs are in mono or stereo mode. In mono mode, the left and right audio signals are mixed and output to the left headphone output. Set MONO = 1 in the general-purpose register (register 0x3, bit B2) to enter mono mode.

Headphone Amplifier Status (SHP)

0 = The headphone amplifiers are operating.

1 = The headphone amplifiers are not operating.

SHP indicates whether the headphone amplifiers are operating or not operating.

Line Output Status (SLO)

0 = The line outputs are enabled.

1 = The line outputs are disabled.

SLO indicates whether the line outputs are enabled or disabled. Set LNOEN = 1 in the enable register (register 0x5, bit B2) to enable the line outputs.

Line Input Status (SLI)

0 = The line inputs are enabled.

1 = The line inputs are disabled.

SLI indicates whether the line inputs are enabled or disabled. Set LNIEN = 1 in the enable register (register 0x5, bit B1) to enable the line inputs.

DAC Status (SDAC)

0 = The DAC is operating and has completed a softstart sequence.

1 = The DAC is not operating and has completed a soft-stop sequence.

SDAC indicates whether the DAC is operational and receiving valid clock signals, or not operating.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 23

Table 11. Status B (0x1) Read-Only, Bit Descriptions

XXX

SDAC

B6 B5

SMONO SHP SLO SLI

B3 B2 B1

MAX9850

Volume Register (0x2)

Mute Enable (MUTE)

1 = Mute headphone outputs.

0 = Unmute headphone outputs.

Set MUTE = 1 to mute the headphone outputs (HPR, HPL). The headphone output is muted on the first zero crossing of the audio signal if zero-crossing detect is enabled.

Slew-Rate Control Enable (SLEW)

1 = Enable slew-rate control.

0 = Disable slew-rate control.

The slew-rate control allows the headphone amplifiers to smoothly slew between volume settings after a volume change is made. Volume changes occur immediately when the slew-rate control is disabled.

Volume Control (VOL(5:0))

VOL(5:0) controls the headphone amplifier volume attenuation. Code 0x00 is full volume while 0x28 to 0x3F is full attenuation. VMN sets to 1 when code 0x3F is programmed and the minimum volume is reached. Table 13 lists the volume attenuation settings for each code.

Stereo Audio DAC with DirectDrive Headphone Amplifier

24 ______________________________________________________________________________________

Table 13. Volume Control Settings

Table 12. Volume (0x2) Read/Write, Bit Descriptions

MUTE

VOL(5:0)

B6 B5 B4 B3 B2 B1

SLEW

VOL(5:0) SETTING (dB)

0x00 +6.0

0x01 +5.5

0x02 +5.0

0x03 +4.5

0x04 +4.0

0x05 +3.5

0x06 +3.0

0x07 +2.5

0x08 +1.5

0x09 +0.5

0x0A -0.5

0x0B -1.5

0x0C -3.5

0x0D -5.5

VOL(5:0) SETTING (dB)

0x0E -7.5

0x0F -9.5

0x10 -11.5

0x11 -13.5

0x12 -15.5

0x13 -17.5

0x14 -19.5

0x15 -21.5

0x16 -23.5

0x17 -25.5

0x18 -27.5

0x19 -29.5

0x1A -31.5

0x1B -33.5

VOL(5:0) SETTING (dB)

0x1C -35.5

0x1D -37.5

0x1E -39.5

0x1F -41.5

0x20 -45.5

0x21 -49.5

0x22 -53.5

0x23 -57.5

0x24 -61.5

0x25 -65.5

0x26 -69.5

0x27 -73.5

0x28-0x3F Mute

——

General-Purpose Register

GPIO Output Mode Control (GM(1:0))

00 = GPIO outputs low.

01 = GPIO is high impedance.

10 = GPIO outputs low and the ALERT output pulse function is enabled.

11 = GPIO is high impedance and the ALERT output pulse function is enabled.

GM(1:0) programs the GPIO output state and enables or disables the ALERT output pulse function. The opendrain GPIO output can be programmed to output static high or a low. GPIO can also be programmed to pulse to the opposite output level than the programmed output state when an alert occurs. An alert occurs when ALERT sets to 1 in the status A register. GM(1:0) has no function when GPIO is configured as an input.

GPIO Direction (GPD)

1 = Configure GPIO as an open-drain output.

0 = Configure GPIO as an input.

The state of GPD determines whether GPIO is an input or an output.

Debounce Delay Control (DBDEL(1:0))

00 = HPS debounce delay disabled.

01 = HPS debounce delay is a nominal 200ms.

10 = HPS debounce delay is a nominal 400ms.

11 = HPS debounce delay is a nominal 800ms.

DBDEL(1:0) controls the length of HPS debounce time. The debounce time is derived from the charge-pump clock.

Mono Mode Enable (MONO)

1 = Enable mono mode.

0 = Disable mono mode, headphone outputs in stereo mode.

Set MONO = 1 to force the headphone outputs to mono mode. The stereo input signal is summed to one channel. The summed signal is output on the left headphone output (HPL).

Zero-Detect Enable (ZDEN)

1 = Enables the zero-detect function.

0 = Disables the zero-detect function.

Volume changes, headphone output muting, and entering/exiting shutdown occur only on the zero crossing of the audio signal when ZDEN = 1. For optimum performance, set SR(1:0) to 01.

Interrupt Enable Register

Note: Any of the below interrupts can be configured to trigger a hardware interrupt through GPIO. Program GPD and GM(1:0) in the general-purpose register to enable the ALERT output pulse function.

SGPIO Interrupt Enable (ISGPIO)

1 = A state change on SGPIO, when GPIO is an input, will cause ALERT to set to 1.

0 = A state change on SGPIO, when GPIO is an input, will not cause ALERT to set.

ISGPIO = 1 configures the MAX9850 to set ALERT = 1 when SGPIO changes state. The interrupt may only be enabled when GPIO is an input.

PLL Lock Interrupt Enable (ILCK)

1 = A state change on LCK will cause ALERT to set to 1.

0 = A state change on LCK will not cause ALERT to set.

ILCK = 1 configures the MAX9850 to set ALERT = 1 when the DAC’s internal PLL loses or achieves frequency lock with LRCLK. Program GM(1:0), while GPD = 1, to configure GPIO as a hardware interrupt to alert a µC when LCK changes state.

SHPS Interrupt Enable (ISHPS)

1 = A state change on SHPS will cause ALERT to set to 1.

0 = A state change on SHPS will not cause ALERT to set.

ISHPS = 1 configures the MAX9850 to set ALERT = 1 when SHPS changes state.

Volume at Minimum Interrupt Enable (IVMN)

1 = A state change on VMN will cause ALERT to set to 1.

0 = A state change on VMN will not cause ALERT to set.

IVMN = 1 configures the MAX9850 to set ALERT = 1 when the headphone amplifier is programmed to and reaches its minimum output volume. Program GM(1:0), while GPD = 1, to configure GPIO as a hardware interrupt to alert a µC when the headphone output volume is programmed to and reaches its minimum volume.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 25

Table 14. General Purpose (0x3) Read/Write, Bit Descriptions

GM(1:0)

ZDEN

Table 15. Interrupt Enable (0x4) Read/Write, Bit Descriptions

IIOH

B6 B5 B4 B3 B2 B1

GPD DBDEL(1:0) MONO

B6 B5 B4 B3 B2 B1

ISGPIO ILCK ISHPS IVMN

MAX9850

Headphone Overcurrent Interrupt Enable (IIOH)

1 = ALERT sets to 1 when either IOHL or IOHR set to 1.

0 = ALERT will not set when IOHL or IOHR set to 1.

IIOH = 1 configures the MAX9850 to set ALERT = 1 when one or both of the headphone amplifier outputs (HPL, HPR) has experienced an overcurrent condition. Program GM(1:0), while GPD = 1, to configure GPIO as a hardware interrupt to alert a µC to an overcurrent condition on the headphone outputs.

Enable Register

Shutdown (

SHDN

)

1 = The MAX9850 is powered on.

0 = The MAX9850 is in low-power shutdown mode. The I2C interface remains active.

Set SHDN = 1 to power on the MAX9850. The headphone amplifier, master clock, line inputs/outputs, DAC, charge pump, and charge-pump clock all have their own enable bits. The individual components of the MAX9850 can only be enabled after SHDN = 1.

MCLK Enable (MCLKEN)

1 = MCLK is connected to the MAX9850.

0 = MCLK is disconnected from the MAX9850.

MCLKEN must be set to 1 for the DAC to operate properly. The line inputs/outputs and headphone amplifiers will work if MCLKEN = 0, but the charge-pump clock must be derived from the internal oscillator.

Charge-Pump Enable (CPEN(1:0))

11 = Enable the internal charge pump.

00 = Disable the internal charge pump.

10 and 01 = Invalid.

Set CPEN(1:0) to 11 to enable the internal charge pump when the line outputs and headphone amplifiers are used.

Headphone Output Enable (HPEN)

1 = Enable the headphone outputs.

0 = Disable the headphone outputs.

Set HPEN = 1 to enable the headphone outputs. HPEN = 0 places the headphone outputs in high impedance. The line outputs must be enabled for the headphone amplifiers to operate properly.

Line Output Enable (LNOEN)

1 = Enable the line outputs.

0 = Disable the line outputs.

LNOEN = 0 forces the line outputs and the headphone outputs to high impedance. Set LNOEN = 1 to enable the line outputs. The line outputs must be enabled for the headphone amplifiers to operate properly.

Line Input Enable (LNIEN)

1 = Enable the line inputs.

0 = Disable the line inputs.

LNIEN = 1 enables the line inputs. LNIEN = 0 disconnects the line inputs.

DAC Enable (DACEN)

1 = Enable the audio DAC.

0 = Disable the audio DAC.

DACEN = 1 enables the DAC and all supporting circuitry including the digital audio interface and interpolating FIR filter. DACEN = 0 places the DAC and support circuitry into low-power shutdown mode.

Clock Register

Internal Clock Divide (IC(1:0))

00 = Internal clock divider is transparent (f

ICLK

MCLK

01 = (f

ICLK

= f

MCLK

/ 2).

10 = (f

ICLK

= f

MCLK

/ 3).

11 = (f

ICLK

= f

MCLK

/ 4).

IC(1:0) controls the internal clock divider that determines the internal clock frequency from the master clock.

Charge-Pump Register

Stereo Audio DAC with DirectDrive Headphone Amplifier

26 ______________________________________________________________________________________

Table 16. Enable (0x5) Read/Write, Bit Descriptions

B7B6B5B4B3B2B1

SHDN

DACEN

Table 17. Clock (0x6) Read/Write, Bit Descriptions

0000 IC(1:0) 0 0

Table 18. Charge Pump (0x7) Read/Write, Bit Descriptions

SR(1:0) 0 CP(4:0)

MCLKEN CPEN (1:0) HPEN LNOEN LNIEN

B6 B5 B4 B3 B2 B1

Slew-Rate Control (SR(1:0))

00 = Headphone volume slews from code 0x00 to 0x28 in 63µs. Not recommended when ZDEN = 1.

01 = Headphone volume slews from code 0x00 to 0x28 in 125ms.

10 = Headphone volume slews from code 0x00 to 0x28 in 63ms.

11 = Headphone volume slews from code 0x00 to 0x28 in 42ms.

Program SR(1:0) to set the rate that the MAX9850 uses to slew between two volume settings. The slew-rate control also controls the amount of time the headphone outputs take to mute or shut down after the command is given.

Charge-Pump Clock Divider (CP(4:0))

CP(4:0) controls the charge-pump clock divider. The charge-pump clock frequency (f

CPCLK

) is derived from

either ICLK or from the internal oscillator.

Program CP(4:0) = 0x00 to enable the 667kHz internal oscillator. This allows the headphone amplifiers and line outputs to operate when the DAC is disabled.

Programming CP(4:0) to any value other than 0x00 disables the internal oscillator and derives the chargepump clock from ICLK. Program CP(4:0) with a value that creates a 667kHz ±20% charge-pump clock from ICLK by the following equation:

where: f

MCLK

= MCLK frequency.

CP(4:0)

= decimal value of CP(4:0). N

CP(4:0)

must be greater than 1 when deriving the charge-pump clock from I

CLK

fCP= charge-pump clock frequency. Program fCP= 667kHz ±20% for proper operation.

SF = MCLK scale factor. SF is the decimal value of IC(1:0) + 1.

LRCLK MSB and LRCLK LSB Registers

Integer Mode (INT)

1 = Configure the MAX9850 to integer mode.

0 = Configure the MAX9850 to noninteger mode.

Integer mode operation requires that ICLK is an integer multiple of 16 times the sample rate (f

LRCLK

). See the DAC Operating Modes section. When in integer mode, f

LRCLK

= f

ICLK

/ (16 x LSB(7:0)).

LRCLK MSB Divider (MSB(14:8))

MSB(14:8) and LSB(7:0) are used to determine f

LRCLK

when in noninteger mode only (see the DAC Operating Modes section). For noninteger mode:

LRCLK LSB Divider (LSB(7:0))

LSB(7:0) combined with MSB(14:8) sets the LRCLK divider when the MAX9850 is configured in noninteger mode. Only LSB(7:0) is used to determine f

LRCLK

when the MAX9850 is configured in integer mode. See the DAC Operating Modes section.

Digital Audio Register

Master Mode (MAS)

1 = Configure the MAX9850 to master mode.

0 = Configure the MAX9850 to slave mode.

Set MAS = 1 to configure the MAX9850 to master mode. The LRCLK and BCLK are generated by the MAX9850 when in master mode. Set MAS = 0 to configure the MAX9850 as a digital audio slave that accepts LRCLK and BCLK from an external digital audio source.

LRCLK Invert (INV)

1 = Left audio data is clocked in when LRCLK is high and right data is clocked in when LRCLK is low.

0 = Left audio data is clocked in when LRCLK is low and right data is clocked in when LRCLK is high.

Set INV = 0 to conform to the I

S standard.

Bit Clock Invert (BCINV)

1 = Digital data at SDIN latches in on the falling edge of BCLK.

0 = Digital data at SDIN latches in on the rising edge of BCLK.

Set BCINV = 0 to conform to the I2S standard.

MSB LSB

LRCLK

ICLK

=×2

MCLK

NCP

××2

(:)

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 27

Table 19. LRCLK MSB (0x8) and LRCLK LSB (0x9) Read/Write, Bit Descriptions

INT

MSB(14:8)

LSB(7:0)

Table 20. Digital Audio (0xA) Read/Write, Bit Descriptions

MAS

WS(1:0)

INV BCINV LSF DLY RTJ

B4 B3 B2 B1

B6 B5 B4 B3 B2 B1

MAX9850

Least Significant Bit First (LSF)

1 = Accepts audio data LSB first. 0 = Accepts audio data MSB first. Set LSF = 0 to conform to the I

S standard.

SDIN Delay (DLY)

1 = Audio data is latched into the MAX9850 on the second rising BCLK edge after LRCLK transitions.

0 = Audio data is latched into the MAX9850 on the first rising BCLK edge after LRCLK transitions

Set DLY = 1 to conform to the I

S standard.

Right-Justified Data (RTJ)

1 = Audio data is right justified. 0 = Audio data is left justified. I

S data is left justified. Set RTJ = 0 to conform to the

I2S standard.

Word Length Select (WS(1:0))

00 = Audio data word length is 16 bits. 01 = Audio data word length is 18 bits. 10 = Audio data word length is 20 bits. 11 = Audio data word length is 24 bits. Program WS(1:0) to select the input data word length.

Programming the audio data word length ensures that the correct number of BCLK cycles are output to accommodate the incoming data word.

Digital Audio Interface

The MAX9850 receives serial digital audio data through a 3-wire interface. The data can be right or left justified, MSB or LSB first, or I2S compatible. The 3-wire serial bus carries two time-multiplexed audio data channels (SDIN), a channel-select line (LRCLK), and a bit clock line (BCLK). The configuration of the audio interface is controlled with the digital audio register, see Table 20. Typical digital audio formats, and the required digital audio register code, are listed in Table 21. Figure 4 illustrates the difference between right justified, left justified, and I2S compatible audio data.

The MAX9850 generates the BCLK and the LRCLK from ICLK when in master mode, see the Internal Timing section. In slave mode, the MAX9850 accepts an LRCLK and BCLK from an external digital audio source.

The MAX9850 can accept right- or left-justified data when operating in slave mode with extra BCLK pulses beyond what is programmed by the WS(1:0) bits. When using the I

S standard, audio data MSBit must latch into SDIN on the second BCLK rising edge following an LRCLK transition. See Figure 4 for the various relationships between clock and data that are supported by the MAX9850.

The MAX9850 can be configured to accept 16, 18, 20, or 24-bit data. The MAX9850 generates exactly the programmed number of BCLK cycles when in master mode. Program the audio data word size with WS(1:0) (register 0xA, bit B0 and B1) according to Table 22 to ensure that the MAX9850 outputs the correct number of BCLK cycles to accommodate the input word.

The internal digital processing resolution is 18 bits wide. Data words longer than 18 bits will be truncated. Zeros are internally programmed into the missing bit positions when the data word is shorter than the programmed word size.

I2C-Compatible Serial Interface

The MAX9850 features an I2C/SMBus™-compatible, 2wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the MAX9850 and the master at clock rates up to 400kHz. Figure 5 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus.

A master device writes data to the MAX9850 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9850 is 8 bits long and is followed by an acknowledge clock pulse.

Stereo Audio DAC with DirectDrive Headphone Amplifier

28 ______________________________________________________________________________________

Table 22. Audio Data Word Size

WS(1:0)

DATA WORD SIZE (BITS)

0x0 16

0x1 18

0x2 20

0x3 24

SMBus is a trademark of Intel Corp.

Table 21. Typical Digital Audio Formats

FORMAT

DIGITAL AUDIO REGISTER

CODE (0xA)

Left-Justified Audio Data X0000000

Right-Justified Audio Data X0000100

I2S-Compatible Audio Data X0001000

A master reading data from the MAX9850 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9850 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition.

SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500Ω, is required on the SDA bus. SCL operates as an input only. A pullup resistor, typically greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the

master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9850 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 29

1514131211109876543210 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RIGHTLEFT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1514131211109876543210

RIGHTLEFT

LRCLK

SDIN

BCLK

LRCLK

SDIN

BCLK

LEFT-JUSTIFIED DIGITAL AUDIO REGISTER (0xA) CONTENTS = 00000000

15X 1413121110 9 8 7 6 5 4 3 2 1 0

RIGHTLEFT

LRCLK

SDIN

BCLK

S DIGITAL AUDIO REGISTER (0xA) CONTENTS = 00001000

RIGHT-JUSTIFIED DIGITAL AUDIO REGISTER (0xA) CONTENTS = 00000100

15X 14131211109876543210

Figure 4. Right-Justified, and Left-Justified Audio Data Formats (Slave Mode, 16-Bit Data)

SCL

SDA

START

CONDITION

STOP

CONDITION

REPEATED

START

CONDITION

START

CONDITION

HD, STA

BUF

SU, STO

LOW

SU, DAT

HD, DAT

HIGH

Figure 5. 2-Wire Interface Timing Diagram

MAX9850

Start and Stop Conditions

SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 6). A START condition from the master signals the beginning of a transmission to the MAX9850. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition.

Early STOP Conditions

The MAX9850 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition.

Slave Address

The MAX9850 is programmable to one of three slave addresses (see Table 23). These slave addresses are unique device IDs. Connect ADD to GND, AV

, or SDA to set the I2C slave address. The address is defined as the seven most significant bits (MSBs) followed by the Read/Write bit. Set the Read/Write bit to 1 to configure the MAX9850 to read mode. Set the Read/Write bit to 0 to configure the MAX9850 to write mode. The address is the first byte of information sent to the MAX9850 after the START condition.

Acknowledge

The acknowledge bit (ACK) is a clocked 9th bit that the MAX9850 uses to handshake receipt of each byte of data when in write mode (see Figure 7). The MAX9850 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication.

The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX9850 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A notacknowledge is sent when the master reads the final byte of data from the MAX9850, followed by a STOP condition.

Stereo Audio DAC with DirectDrive Headphone Amplifier

30 ______________________________________________________________________________________

SCL

SDA

SSrP

Figure 6. START, STOP, and REPEATED START Conditions

Table 23. MAX9850 Address Map

MAX9850 SLAVE ADDRESS

ADD

R/W

GND

SDA

X = Don’t Care.

SCL

START

CONDITION

SDA

289

CLOCK PULSE FOR

ACKNOWLEDGMENT

ACKNOWLEDGE

NOT ACKNOWLEDGE

Figure 7. Acknowledge

A6 A5 A4 A3 A2 A1 A0

0010000

0010001

0010011

Write Data Format

A write to the MAX9850 includes transmission of a START condition, the slave address with the R/W bit set to 0 (see Table 23), one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 8 illustrates the proper frame format for writing one byte of data to the MAX9850. Figure 9 illustrates the frame format for writing n-bytes of data to the MAX9850.

The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9850. The MAX9850 acknowledges receipt of the address byte during the master-generated 9th SCL pulse.

The second byte transmitted from the master configures the MAX9850’s internal register address pointer. The pointer tells the MAX9850 where to write the next byte of data. An acknowledge pulse is sent by the MAX9850 upon receipt of the address pointer data.

The third byte sent to the MAX9850 contains the data that will be written to the chosen register. An acknowledge pulse from the MAX9850 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to

sequential registers within one continuous frame. Figure 9 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP condition.

Read Data Format

Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9850 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x0. The first byte transmitted from the MAX9850 will be the contents of register 0x0. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame.

A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read will be from register 0x0 and subsequent reads will autoincrement the address pointer until the next STOP condition.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 31

ACKNOWLEDGE FROM MAX9850

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9850

B1 B0B3 B2B5 B4B7 B6

ACKNOWLEDGE FROM MAX9850

R/W

SASLAVE ADDRESS REGISTER ADDRESS Nth DATA BYTE

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9850

B1 B0B3 B2B5 B4B7 B6

1st DATA BYTE

Figure 9. Writing n-Bytes of Data to the MAX9850

0SLAVE ADDRESS REGISTER ADDRESS DATA BYTE

ACKNOWLEDGE FROM MAX9850

R/W

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9850

B1 B0B3 B2B5 B4B7 B6

S AA

Figure 8. Writing One Byte of Data to the MAX9850

MAX9850

The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9850’s slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9850 transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. Attempting to read from register addresses higher than 0xB results in repeated reads of 0xB. Note that 0xB is a reserved register.

The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a notacknowledge from the master and then a STOP condition. Figure 10 illustrates the frame format for reading one byte from the MAX9850. Figure 11 illustrates the frame format for reading multiple bytes from the MAX9850.

Applications Information

Powering On/Off the MAX9850

The MAX9850 powers on in low-power shutdown mode with the DAC, headphones, line inputs, and outputs all disabled. For useful circuit operation to be available, the charge pump needs to be activated using CPEN(1:0) in the enable register (register 0x5, bits B5

and B4). Setting the appropriate bits in the enable register will enable the desired circuit functions on the MAX9850. Finally, the global shutdown bit, SHDN needs to be set to 1 (register 0x5, bit B7). The enable bits can all be set with a single I

C write operation.

It is good practice for an application to configure the I2C registers before taking the MAX9850 out of shutdown. This may include setting initial volume levels, DAC mode of operation, stereo or mono operation, and audio interface settings. Powering on the MAX9850 with all the registers set ensures that the audio output will not be interrupted.

The charge pump starts and establishes the internal supply voltages once the appropriate byte is written to the enable register. The MAX9850 is ready for operation approximately 10ms after the charge pump is enabled. If selected, the headphone outputs will also complete a clickless/popless power-up sequence during this time. The headphone amplifier status bit (SHP) (register 0x1, bit B3) sets to 1 once the headphones are ready to operate. The line inputs and outputs will also turn on during this 10ms startup period if enabled.

Let AC-coupling capacitors settle before enabling the line input amplifiers. The input-coupling capacitor charges to the output bias voltage of the driving device even while the MAX9850 is in shutdown. The input AC coupling capacitors are charged and ready for use immediately after power is applied to the system in most applications.

Stereo Audio DAC with DirectDrive Headphone Amplifier

32 ______________________________________________________________________________________

ACKNOWLEDGE FROM MAX9850

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9850

NOT ACKNOWLEDGE FROM MASTER

B1 B0B3 B2B5 B4B7 B6

ACKNOWLEDGE FROM MAX9850

R/W

R/WREPEATED START

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

Figure 10. Reading One Byte of Data from MAX9850

ACKNOWLEDGE FROM MAX9850

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9850

ACKNOWLEDGE FROM MASTER

B1 B0B3 B2B5 B4B7 B6

ACKNOWLEDGE FROM MAX9850

R/W

R/WREPEATED START

Sr 1

1 BYTE

AUTOINCREMENT INTERNAL

NOT ACKNOWLEDGE

FROM MASTER

B1 B0B3 B2B5 B4B7 B6

SLAVE ADDRESS

SLAVE ADDRESS FIRST DATA BYTE

Nth DATA WORD

Figure 11. Reading n-Bytes from MAX9850

The DAC begins its soft-start routine after being enabled and after receiving 32 LRCLK cycles. All internal filters are initialized and the DAC gain gradually ramps to maximum. The MAX9850’s headphone output level is determined by the headphone amplifier volume setting.

Mute the audio outputs before powering down the MAX9850 by setting MUTE to 1 (register 0x2, bit B7). Ramping the volume to its maximum attenuation is an alternative to muting the output. VMN in the status A register (register 0x0, bit B3) notifies the µC when the outputs are at maximum attenuation. Disable the headphone and line outputs once the audio is fully attenuated. Headphone and line outputs can be disabled within 50µs without any audible clicks or pops, once the audio is fully attenuated. Place the MAX9850 in shutdown after the outputs are disabled.

Stereo Speakerphone

The MAX9850 can be combined with a stereo speaker amplifier to create a complete speakerphone playback solution. The MAX9701, or another Maxim stereo speaker amplifier, can be used to drive the speakers while the MAX9850’s integrated DirectDrive headphone amplifier drives the headphones (see Figure 12).

Configure GPIO to output high when a headphone is not connected and low when the headphone is connected. Connect GPIO to the SHDN control of the MAX9701. Configure the interrupt enable register to set ALERT (register 0x0, bit B7) when HPS changes state. The µC polls the status A register and waits for ALERT to set when HPS changes state. The µC changes the state of GPIO when ALERT is set, either turning off the speaker amp because a headphone is connected or enabling the speaker amp when the headphone is disconnected.

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 33

MAX9850

MAX9701*

1.8V TO 3.6V

3.3V TO 5.5V

0.47μF

AGNDDGNDPGND

PGNDSHDN

SSSVSS

OUTR+

OUTR-

INL+

INL-

OUTL+

OUTL-

INR+

INR-

HPL

HPS

HPR

DIGITAL

AUDIO

SOURCE

SDIN

MCLK

C1N

C1P

REF

SDA

10k

SCL

BCLK

LRCLK

*FUTURE PRODUCT—CONTACT FACTORY FOR AVAILABILITY.

1μF

0.47μF

2.2μF

1μF

GPIO

OUTR

OUTL

Figure 12. Stereo Speakerphone

MAX9850

Cell Phone Audio

The MAX9850 is a complete cell-phone audio playback solution. In a typical application, ringtones are created and output through the application’s processor on the digital audio bus. Connect the baseband IC to the line inputs of the MAX9850, INR and INL. The headphone amplifier outputs a summed version of the digital audio input and the line input (see Figure 13).

Headphone Short Circuit

The headphone amplifiers can provide almost ±300mA per channel during a short-circuit event. The MAX9850 has been designed to withstand this current continuously. To avoid unnecessarily draining a battery, it is advised to enable the IOHR and IOHL hardware interrupt. The µC can service the interrupt by disabling the headphone amplifiers and waiting for a timeout period.

A headphone short-circuit event on the right channel only may also indicate that a mono headphone has been inserted into the stereo socket. The µC can then automatically disable the right channel by placing the MAX9850 in mono mode. This resolves a mono jackinduced, short-circuit condition.

PC Board Layout and Bypassing

Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect PGND, DGND, and AGND together at a single point on the PC board. Route DGND, PGND, and all traces that carry switching transients or digital signals away from AGND and traces or components in the analog audio-signal path.

Connect all components associated with the charge pump to PGND. Connect PVSSand SVSStogether at the device. Place the charge-pump capacitors as close to PVSSas possible. Ensure C2 is connected to PGND. Bypass PVDDwith 1µF to PGND. Place the bypass capacitors as close to the device as possible.

The MAX9850 thin QFN package features an exposed thermal pad on its underside. This pad lowers the package’s thermal resistance by providing a direct heat conduction path from the die to the printed circuit board. If possible, connect the exposed thermal pad to an electrically isolated, large pad of copper. If it cannot be left floating, connect it to AGND.

Stereo Audio DAC with DirectDrive Headphone Amplifier

34 ______________________________________________________________________________________

MAX9850

1μF 1μF 1μF

1.8V TO 3.6V

1μF

0.47μF

BASEBAND

APPLICATIONS

PROCESSOR

2.2μF

REF

C1P

C1N

GPIO

HPL HPS HPR

SSSVSS

PGND DGND AGND

LRCLK

BCLK

SDIN

MCLK

SDA

SCL

INR

INL

0.47μF

MAX9701*

3.3V TO 5.5V

0.47μF

PGNDSHDN

OUTR+

OUTR-

INL+

INL-

OUTL+

OUTL-

INR+

INR-

0.47μF

*FUTURE PRODUCT—CONTACT FACTORY FOR AVAILABILITY.

10kΩ

OUTR

OUTL

Figure 13. Cell Phone Audio

MAX9850

Stereo Audio DAC with DirectDrive

Headphone Amplifier

______________________________________________________________________________________ 35

21 20 19 18 17 16 15

234567

MAX9850

TQFN

TOP VIEW

C1N

PGND

C1P

SCL

SDA

HPS

HPL

HPR

PREG

NREG

AGND

REF

OUTL

OUTR

INL

INR

GPIO

ADD

DGND

MCLK

SDIN

BCLK

LRCLK

Pin Configuration

Chip Information

TRANSISTOR COUNT: 104,069

PROCESS: BiCMOS

MAX9850

Stereo Audio DAC with DirectDrive Headphone Amplifier

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

QFN THIN.EPS

MAXIM MAX9850 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual