The MAX98088 is a full-featured audio codec whose high
performance and low power consumption make it ideal
for portable applications.
Class D speaker amplifiers provide efficient amplification
for two speakers. Low radiated emissions enable completely filterless operation. Integrated bypass switches
optionally connect an external amplifier to the transducer
when the Class D amplifiers are disabled.
The IC features a stereo Class H headphone amplifier
that utilizes a dual-mode charge pump to maximize efficiency while outputting a ground referenced signal that
does not require output coupling capacitors.
The IC also features a mono differential amplifier that can
also be configured as a stereo line output.
Two differential analog microphone inputs are available as
well as support for two PDM digital microphones. Integrated
switches allow for an additional microphone input as well
as microphone signals to be routed out to external devices.
Two flexible single-ended or differential line inputs may be
connected to an FM radio or other sources.
Integrated FlexSoundK technology improves loudspeaker performance by optimizing the signal level and frequency response while limiting the maximum distortion
and power at the output to prevent speaker damage.
Automatic gain control (AGC) and a noise gate optimize
the signal level of microphone input signals to make best
use of the ADC dynamic range.
The device is fully specified over the -40NC to +85NC
extended temperature range.
FlexSound is a trademark of Maxim Integrated Products, Inc.
Features
S5.6mW Power Comsumption (DAC to HP at 97dB DR)
S101dB DR Stereo DAC (8kHz < fS < 96kHz)
S93dB DR Stereo ADC (8kHz < fS < 96kHz)
SStereo Low EMI Class D Amplifiers
950mW/Channel (8I, V
SPKVDD�
= 4.2V)
SEfficient Class H Headphone Amplifier
SDifferential Receiver Amplifier/Stereo Line Outputs
S2 Stereo Single-Ended/Mono Differential Line
5-Band Parametric EQ
Automatic Level Control (ALC)
Excursion Limiter
Speaker Power Limiter
Speaker Distortion Limiter
Microphone Automatic Gain Control
and Noise Gate
SDual I2S/PCM/TDM Digital Audio Interfaces
SAsynchronous Digital Mixing
SSupports Master Clock Frequencies from 10MHz
to 60MHz
SRF Immune Analog Inputs and Outputs
SExtensive Click-and-Pop Reduction Circuitry
SAvailable in 63-Bump WLP Package (3.80mm x
3.30mm, 0.4mm Pitch)
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX98088.related.
DVDD, AVDD, PVDD, HPVDD .............................. -0.3V to +2.2V
SPKLVDD, SPKRVDD, DVDDS1, DVDDS2 .......... -0.3V to +6.0V
DGND, HPGND, SPKLGND, SPKRGND .............. -0.1V to +0.1V
HPVSS ............................... (HPGND - 2.2V) to (HPGND + 0.3V)
C1N .................................... (HPVSS - 0.3V) to (HPGND + 0.3V)
C1P .....................................(HPGND - 0.3V) to (HPVDD + 0.3V)
REF, MICBIAS ................................. -0.3V to (SPKLVDD + 0.3V)
MCLK, SDINS1, SDINS2, JACKSNS,
SDA, SCL, IRQ .................................................-0.3V to +6.0V
LRCLKS1, BCLKS1, SDOUTS1 ......... -0.3V to (DVDDS1 + 0.3V)
LRCLKS2, BCLKS2, SDOUTS2 ......... -0.3V to (DVDDS2 + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
AVDD
SPK_P and SPK_N. Receiver load (R
to HPGND. Line out loads (R
= 2.2FF, C
= 0dB, AV
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = T
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
Supply Voltage RangeGuaranteed by PSRR
Total Supply Current
(Notes 2 and 3)
Shutdown Supply Current
(Note 2)
REF Voltage2.5V
REG Voltage0.79V
Shutdown to Full Operation
= V
PVDD
MICBIAS
DACGAIN
= V
DVDD
= C
REG
= 0dB, AV
= V
DVDDS1
) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR
REC
) connected from LOUTL or LOUTR to SPKLGND. R
LOAD
= 1FF, C
C1N-C1P
ADCLVL
= 0dB, AV
DVDDS2
= 1FF, C
= +1.8V, V
HPVDD
ADCGAIN
MIN
SPKLVDD
= C
= 0dB, AV
to T
Full-duplex 8kHz mono,
receiver output, MAS = 1
DAC playback 48kHz
I
VDD
stereo, headphone
outputs, MAS = 1
DAC playback 48kHz
stereo, speaker outputs,
MAS = 1
TA = +25NC
VSEN = 0
VSEN = 1
REG, INA1/EXTMICP, INA2/EXTMICN, INB1,
INB2, MIC1P/DIGMICDATA, MIC1N/DIGMICCLK,
MIC2P, MIC2N .................................................. -0.3V to +2.2V
HPSNS ............................... (HPGND - 0.3V) to (HPGND + 0.3V)
HPL, HPR ............................ (HPVSS - 0.3V) to (HPVDD + 0.3V)
RECP/LOUTL/RXINP, RECN/LOUTR/
RXINN .....................(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKLP, SPKLN ...........(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKRP, SPKRN .........(SPKRGND - 0.3V) to (SPKRVDD + 0.3V)
BCLK Cycle Timet
BCLK High Timet
BCLK Low Timet
BCLK or LRCLK Rise and Fall TimetR, t
SDIN to BCLK Setup Timet
LRCLK to BCLK Setup Timet
SDIN to BCLK Hold Timet
LRCLK to BCLK Hold Timet
Minimum Delay Time from LSB
BCLK Falling Edge to
High-Impedance State
Note 1: The IC is 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Note 2: Analog supply current = I
+ I
DVDDS1
+ I
DVDDS2
.
AVDD
+ I
. Speaker supply current = I
HPVDD
SPKLVDD
+ I
SPKRVDD
. Digital supply current = I
DVDD
Note 3: Clocking all zeros into the DAC.
Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 5: Gain measured relative to the 0dB setting.
Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000.
Note 7: 0dBFS for DAC input. 1V
for INA/INB inputs.
P-P
Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some full-
scale performance degradation compared to synchronous integer related MCLK/LRCLK ratios.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10: CB is in pF.
Power Consumption
(V
AVDD
= V
PVDD
= V
DVDD
= V
DVDDS1
= V
DVDDS2
= 1.8V, V
SPKLVDD
= V
SPKRVDD
= 3.7V)
MODE
PLAYBACK TO HEADPHONE ONLY
DAC Playback 48kHz Stereo HP
DAC ª HP
Low power mode, 24-bit, music filters, 256Fs
DAC Playback 48kHz Stereo HP
DAC ª HP
Low power mode, 24-bit, music filters, 256Fs, 0.1mW/channel,
RHP = 32I
A1, B1SPKRNNegative Right-Channel Class D Speaker Output
A2, B2SPKRGNDRight-Speaker Ground
A3, B3SPKLVDD
A4, B4SPKLPPositive Left-Channel Class D Speaker Output
A5, B5SPKLNNegative Left-Channel Class D Speaker Output
A6
A7PVDD
A8HPVSS
A9HPGNDHeadphone Ground
B6
B7C1P
B8C1N
B9HPVDD
C1, C2SPKRPPositive Right-Channel Class D Speaker Output
C3, D3SPKRVDD
C4, C5SPKLGNDLeft-Speaker Ground
C6, C7, D5, D6,
D7, E3
C8HPSNS
C9HPLLeft-Channel Headphone Output
D1BCLKS1
D2SDOUTS1S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1.
D4LRCLKS1
D8INB2Single-Ended Line Input B2. Also positive differential line input B.
D9HPRRight-Channel Headphone Output
E1DVDDS1
E2MCLKMaster Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
E4SDINS1S1 Digital Audio Serial-Data DAC Input. The input/output voltage is referenced to DVDDS1.
RECP/LOUTL/
RXINP
RECN/LOUTR/
RXINN
N.C. No Connection
Left-Speaker, REF, Receiver Amp Power Supply. Bypass to SPKLGND with a 1FF and a
10FF capacitor.
Positive Receiver Amplifier Output or Left Line Output. Can be positive bypass switch input
when receiver amp is shut down.
Headphone Power Supply. Bypass to HPGND with 1FF and 10FF capacitors.
Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
Negative Receiver Amplifier Output or Right Line Output. Can be negative bypass switch
input when receiver amp is shut down.
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor
between C1N and C1P.
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor
between C1N and C1P.
Noninverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor.
Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or
connect to ground.
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the IC is in slave mode
and an output when in master mode. The input/output voltage is referenced to DVDDS1.
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock
and determines whether S1 audio data is routed to the left or right channel. In TDM mode,
LRCLKS1 is a frame sync pulse. LRCLKS1 is an input when the IC is in slave mode and an
output when in master mode.
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register
E5
E6JACKSNSJack Sense. Detects the insertion of a jack. See the Jack Detection section.
E7INB1Single-Ended Line Input B1. Also negative differential line input B.
E8
E9
F1DGNDDigital Ground
F2BCLKS2
F3LRCLKS2
F4SDAI2C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing.
F5SCLI2C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing.
F6REG
F7MICBIAS
F8
F9
G1SDOUTS2S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2.
G2DVDDS2
G3SDINS2S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2.
G4DVDD
G5AVDD
G6REF
G7AGNDAnalog Ground
G8MIC2N
G9MIC2P
IRQ
MIC1P/
DIGMICDATA
INA2/
EXTMICN
MIC1N/
DIGMICCLK
INA1/
EXTMICP
0x00 change state. Read status register 0x00 to clear IRQ once set. Repeat faults have
no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10kI
pullup resistor to DVDD for full output swing.
Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can be retasked as a digital microphone data input.
Single-Ended Line Input A2. Also positive differential line input A or negative differential
external microphone input.
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode
and an output when in master mode. The input/output voltage is referenced to DVDDS2.
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock
and determines whether audio data on S2 is routed to the left or right channel. In TDM
mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode
and an output when in master mode. The input/output voltage is referenced to DVDDS2.
Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external 2.2kI resistor
should be placed between MICBIAS and the microphone output.
Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF
capacitor. Can be retasked as a digital microphone clock output.
Single-Ended Line Input A1. Also negative differential line input A or positive differential
external microphone input.
S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
Digital Power Supply. Supply for the digital core and I2C interface. Bypass to DGND with a
1FF capacitor.
Analog Power Supply. Bypass to AGND with a 1FF capacitor.
Converter Reference. Bypass to AGND with a 2.2FF capacitor.
Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF
capacitor.
Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
The MAX98088 is a fully integrated stereo audio codec
with FlexSound technology and integrated amplifiers.
Two differential microphone amplifiers can accept signals
from three analog inputs. One input can be retasked to
support two digital microphones. Any combination of two
microphones (analog or digital) can be recorded simultaneously. The analog signals are amplified up to 50dB
and recorded by the stereo ADC. The digital record path
supports voice filtering with selectable preset highpass
filters and high stopband attenuation at fS/2. An automatic gain control (AGC) circuit monitors the digitized signal
and automatically adjusts the analog microphone gain
to make best use of the ADC’s dynamic range. A noise
gate attenuates signals below the user-defined threshold
to minimize the noise output by the ADC.
The IC includes two analog line inputs. One of the line
inputs can be optionally retasked as a third analog microphone input. Both line inputs support either stereo singleended input signals or mono differential signals. The line
inputs are preamplified and then routed to the ADC for
recording and/or to the output amplifiers for playback.
The single-ended line input signals from INA1 and INA2
can bypass the PGAs, and be connected directly to the
ADC input to provide the best dynamic range.
Integrated analog switches allow two differential microphone signals to be routed out the third microphone input
to an external device. This eliminates the need for an
external analog switch in systems that have two devices
recording signals from the same microphone.
Through two digital audio interfaces, the device can
transmit one stereo audio signal and receive two stereo
audio signals in a wide range of formats including I2S,
PCM, and up to four mono slots in TDM. Each interface
can be connected to either of two audio ports (S1 and
S2) for communication with external devices. Both audio
interfaces support 8kHz to 96kHz sample rates. Each
input signal is independently equalized using 5-band
parametric equalizers. A multiband automatic level control (ALC) boosts signals by up to 12dB. One signal path
additionally supports the same voiceband filtering as the
ADC path.
The IC includes a stereo Class D speaker amplifier, a
high-efficiency Class H stereo headphone amplifier, and
a differential receiver amplifier that can be configured as
a stereo single-ended line output.
When the receiver amplifier is disabled, analog switches
allow RECP/RXINP and RECN/RXINN to be reused for
signal routing. In systems where a single transducer is
used for both the loudspeaker and receiver, an external receiver amplifier can be routed to the left speaker
through RECP/RXINP and RECN/RXINN, bypassing the
Class D amplifier, to connect to the loudspeaker. If the
internal receiver amplifier is used, then leave RECP/
RXINP and RECN/RXINN unconnected. In systems
where an external amplifier drives both the receiver and
the MAX98088’s line input, one of the differential signals
can be disconnected from the receiver when not needed
by passing it through the analog switch that connects
RECP/RXINP to RECN/RXINN.
The stereo Class D amplifier provides efficient amplification for two speakers. The amplifier includes active emissions limiting to minimize the radiated emissions (EMI)
traditionally associated with Class D. In most systems,
no output filtering is required to meet standard EMI limits.
To optimize speaker sound quality, the IC includes an
excursion limiter, a distortion limiter, and a power limiter.
The excursion limiter is a dynamic highpass filter with
variable corner frequency that increases in response
to high signal levels. Low-frequency energy typically
causes more distortion than useful sound at high signal levels, so attenuating low frequencies allows the
speaker to play louder without distortion or damage. At
lower signal levels, the filter corner frequency reduces
to pass more low frequency energy when the speaker
can handle it. The distortion limiter reduces the volume
when the output signal exceeds a preset distortion level.
This ensures that regardless of input signal and battery
voltage, excessive distortion is never heard by the user.
The power limiter monitors the continuous power into the
loudspeaker and lowers the signal level if the speaker is
at risk of overheating.
The stereo Class H headphone amplifier uses a dualmode charge pump to maximize efficiency while outputting a ground-referenced signal. This eliminates the
need for DC-blocking capacitors or a midrail bias for the
headphone jack ground return. Ground sense reduces
output noise caused by ground return current.
The IC integrates jack detection allowing the detection of
insertion and removal of accessories.
Configure the MAX98088 using the I2C control bus. The
IC uses a slave address of 0x20 or 00100000 for write
operations and 0x21 or 00100001 for read operations.
See the I2C Serial Interface section for a complete interface description.
Table 1 lists all of the registers, their addresses, and
power-on-reset states. Registers 0x00 to 0x03 and 0xFF
are read-only while all of the other registers are read/
write. Write zeros to all unused bits in the register table
when updating the register, unless otherwise noted.
Performance Mode. Selects DAC to headphone playback performance mode.
0 = High performance playback mode.
1 = Low power playback mode.
Headphone Only Playback Mode. Configures System Bias Control register bits for low
power playback when using DAC to headphone playback path only. When enabled,
this bit overrides the System Bias Control register settings. When disabled, the System
Bias Control register is used to enable system bias blocks. Set both HPPLYBCK and
PERFMODE for lowest power consumption when using DAC to headphone playback
path only.
0 = Disabled
1 = Enabled
8kHz Power Save Mode. PWRSV8K configures the ADC for reduced power consumption when fS = 8kHz. PWRSV8K can be used in conjunction with PWRSV when fS = 8kHz
for more power savings.
0 = Normal, high-performance mode.
1 = Low power mode.
Power Save Mode. PWRSV configures the ADC for reduced power consumption for all
sample rates. PWRSV can be used in conjunction with PWRSV8K for more power savings.
0 = Normal, high-performance mode.
1 = Low power mode.
Receiver/Left Line Output Enable. Use this bit to enable the differential receiver output
or left line output.
0 = Disabled
1 = Enabled
Right Line Output Enable. Use this bit to enable the right line output.
0 = Disabled
1 = Enabled
Left DAC Enable
0 = Disabled
1 = Enabled
Right DAC Enable
0 = Disabled
1 = Enabled
Bandgap Enable. Must be enabled for proper operation of 2.5V regulator and associated circuitry.
0 = Disabled
1 = Enabled
MAX98088
0x4E
2.5V Regulator Enable. SPREGEN enables a 2.5V internal regulator required for
the ADC, speaker and receiver/line out amplifier. The 2.5V regulator is powered by
Common-Mode Voltage Resistor String Enable. VCMEN enables the common mode
voltage for the input and output amplifiers in the codec.
0 = Disabled
1 = Enabled
Chip Bias Enable. BIASEN needs to be set for the codec amplifiers to be enabled.
0 = Disabled
1 = Enabled
MAX98088
Stereo Audio Codec
with FlexSound Technology
Microphone Inputs
The device includes three differential microphone inputs
and a low-noise microphone bias for powering the microphones (Figure 6). One microphone input can also be configured as a digital microphone input accepting signals
from up to two digital microphones. Any two microphones,
analog or digital, can be recorded simultaneously.
In the typical application, one microphone input is used
for the handset microphone and the other is used as an
accessory microphone. In systems using a background
noise microphone, INA can be retasked as another
microphone input.
MCLK
MICBIAS
MIC1P/
DIGMICDATA
MIC1N/
DIGMICCLK
MBEN
MIC2BYP
REG
CLOCK
CONTROL
EXTMICPA1EN:
0/20/30dB
In systems where the codec is not the only device
recording microphone signals, connect microphones to
MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N
then become outputs that route the microphone signals
to an external device as needed. Two devices can then
record microphone signals without needing external
analog switches.
Analog microphone signals are amplified by two stages
of gain and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable-gain amplifier (PGA) adjustable
from 0dB to 20dB in 1dB steps. To maximize the signalto-noise ratio, use the gain in the first stage whenever
possible. Zero-crossing detection is included on the PGA
to minimize zipper noise while making gain changes.
Select a frequency that is within the digital microphone’s clock frequency range.
Set OSR1 = 1 when using a digital microphone.
00 = PCLK/8
01 = PCLK/6
10 = 64 x LRCLK
11 = Reserved
Left Digital Microphone Enable
Set PA1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
Right Digital Microphone Enable
Set PA1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
External Microphone Connection
Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using
INA_/EXTMIC_ as a microphone input.
00 = Disabled
01 = MIC1 input
10 = MIC2 input
11 = Reserved
The device includes two sets of line inputs (Figure 7).
Each set can be configured as a stereo single-ended
input or as a mono differential input. Each input includes
adjustable gain to match a wide range of input signal
levels. If a custom gain is needed, the external gain
mode provides a trimmed feedback resistor. Set the gain
INABYP
PGAINA:
INA1/
EXTMICP
INA2/
EXTMICN
INB1
INB2
+20dB TO -6dB
PGAINA:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
PGAINB:
+20dB TO -6dB
INADIFF
INBDIFF
by choosing the appropriate input resistor and using the
following formula:
AV
= 20 x log (20kI/RIN)
PGAIN
The external gain mode also allows summing multiple
signals into a single input, by connecting multiple input
resistors as show in Figure 8, and/or inputting signals
larger than 1V
Figure 8. Summing Multiple Input Signals into INA/INB
Stereo Audio Codec
with FlexSound Technology
Table 4. Line Input Registers
REGISTERBITNAMEDESCRIPTION
Line Input A/B External Gain
Switches out the internal input resistor and selects a trimmed 20kI feedback resistor.
Use an external input resistor to set the gain of the line input.
0 = Disabled
1 = Enabled
The IC’s stereo ADC accepts input from the microphone
amplifiers, line inputs amplifiers, and directly from the
INA1 and INA2. The ADC mixer routes any combination of the eight audio inputs to the left and right ADCs
(Figure 9).
Selects which analog inputs are recorded by the left/right ADC.
1xxxxxxx = MIC1
x1xxxxxx = MIC2
xx1xxxxx = INA1 pin direct
xxx1xxxx = INA2 pin direct
xxxx1xxx = INA1
xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1)
xxxxxx1x = INB1
xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
MAX98088
Record Path Signal Processing
The device’s record signal path includes both automatic
gain control (AGC) for the microphone inputs and a digital noise gate at the output of the ADC (Figure 10).
Microphone AGC
The IC’s AGC monitors the signal level at the output of the
ADC and then adjusts the MIC1 and MIC2 analog PGA
settings automatically. When the signal level is below
the predefined threshold, the gain is increased up to its
maximum (20dB). If the signal exceeds the threshold,
the gain is reduced to prevent the output signal level
exceeding the threshold. When AGC is enabled, the
microphone PGA is not user programmable. The AGC
provides a more constant signal level and improves the
available ADC dynamic range.
PA1EN:
0/20/30dB
PA2EN:
0/20/30dB
PGAM1:
+20dB TO -6dB
PGAM2:
+20dB TO 0dB
MIX
MIXADL
MIX
ADLEN
ADREN
ADCL
ADCR
AUTOMATIC
GAIN
CONTROL
AVLG: 0/6/
12/18dB
AVL:0dB
TO -15dB
MODE1
SRMIX_
MODE
AVFLT
NOISE GATE
AUDIO/
VOICE
FILTERS
SAMPLE RATE
CONVERTER
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
Noise Gate
Since the AGC increases the levels of all signals below
a user-defined threshold, the noise floor is effectively
increased by 20dB. To counteract this, the noise gate
reduces the gain at low signal levels. Unlike typical noise
gates that completely silence the output below a defined
level, the noise gate in the IC applies downward expansion. The noise gate attenuates the output at a rate of
1dB for each 2dB the signal is below the threshold with a
maximum attenuation of 12dB.
The noise gate can be used in conjunction with the AGC
or on its own. When the AGC is enabled, the noise gate
reduces the output level only when the AGC has set the
gain to the maximum setting. Figure 11 shows the gain
response resulting from using the AGC and noise gate.
AGC AND NOISE GATE
AMPLITUDE RESPONSE
0
-20
AGC AND NOISE GATE
-40
-60
-80
OUTPUT AMPLITUDE (dBFS)
-100
AGC ONLY
AGC AND NOISE
GATE DISABLED
NOISE GATE ONLY
MIXADR
Figure 10. Record Path Signal Processing Block Diagram
Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on
both channels regardless of the AGCSRC setting.
0 = Left ADC output
1 = Maximum of either the left or right ADC output
AGC Release Time
Defined as the duration from start to finish of gain increase in the region shown in Figure
Table 6. Record Path Signal Processing Registers (continued)
REGISTERBITNAMEDESCRIPTION
AGC Attack Time
3
AGCATK
2
0x3F
1
AGCHLD
0
7
6
ANTH
5
4
0x40
3
2
AGCTH
1
0
Defined as the time required to reduce gain by 63% of the total gain reduction (one time
constant of the exponential response). Attack times are longer for low AGC threshold
levels. See Figure 12 for details.
00 = 2ms
01 = 7.2ms
10 = 31ms
11 = 123ms
AGC Hold Time
The delay before the AGC release begins. The hold time counter starts whenever the
signal drops below the AGC threshold and is reset by any signal that exceeds the
threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details.
00 = AGC disabled
01 = 50ms
10 = 100ms
11 = 400ms
Noise Gate Threshold
Gain is reduced for signals below the threshold to quiet noise. The thresholds are relative to the ADC’s full-scale output voltage.
The IC includes separate digital level control for the left
and right ADC outputs (Figure 13). To optimize dynamic
range, use analog gain to adjust the signal level and set
AUTOMATIC
GAIN
CONTROL
AVLG: 0/6/
ADCL
ADLEN
12/18dB
AVL:0dB
TO -15dB
the digital level control to 0dB whenever possible. Digital
level control is primarily used when adjusting the record
level for digital microphones.
Enable sidetone during full-duplex operation to add a
low-level copy of the recorded audio signal to the playback audio signal (Figure 14). Sidetone is commonly
used in telephony to allow the speaker to hear himself
DVST:
0dB TO -60dB
ADLEN
ADREN
ADCL
ADCR
AUTOMATIC
GAIN
CONTROL
SIDETONE
AVLG: 0/6/
12/18dB
AVL:0dB
TO -15dB
SRMIX_
MODE1
AVFLT
MODE
DSTS
NOISE GATE
AUDIO/
VOICE
FILTERS
SAMPLE RATE
CONVERTER
MIX
PARAMETRIC
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
speak, providing a more natural user experience. The
IC implements sidetone digitally. Doing so helps prevent
unwanted feedback into the playback signal path and
better matches the playback audio signal.
Selects which ADC output is fed back as sidetone. When mixing the left and right ADC
outputs, each is attenuated by 6dB to prevent full-scale signals from clipping.
00 = Sidetone disabled
01 = Left ADC
10 = Right ADC
11 = Left + Right ADC
Sidetone Level
Adjusts the sidetone signal level. All levels are referenced to the ADC’s full-scale output.
The IC includes two separate playback signal paths and
one record signal path. Digital audio interface 1 (DAI1)
is used to transmit the recorded stereo audio signal and
receive a stereo audio signal for playback. Digital audio
interface 2 (DAI2) is used to receive a second stereo
audio signal. Use DAI1 for all full-duplex operations and
for all voice signals. Use DAI2 for music and to mix two
playback audio signals. The digital audio interfaces are
separate from the audio ports to enable either interface
to communicate with any external device connected to
either audio port.
Each audio interface can be configured in a variety of formats including left justified, I2S, PCM, and time division
multiplexed (TDM). TDM mode supports up to 4 mono
audio slots in each frame. The IC can use up to 2 mono
slots per interface, leaving the remaining two slots available for another device. Table 9 shows how to configure
the device for common digital audio formats. Figures 16
and 17 show examples of common audio formats. By
default, SDOUTS1 and SDOUTS2 are set high impedance when the IC is not outputting data to facilitate sharing the bus. Configure the interface in TDM mode using
only slot 1 to transmit and receive mono PCM voice data.
The IC’s digital audio interfaces support both ADC to DAC
loop-through and digital loopback. Loop-through allows
the signal converted by the ADC to be routed to the DAC
for playback. The signal is routed from the record path to
the playback path in the digital audio interface to allow
the IC’s full complement of digital signal processing to
be used. Loopback allows digital data input to either
SDINS1 or SDINS2 to be routed from one interface to the
MAX98088
Stereo Audio Codec
with FlexSound Technology
other for output on SDOUTS2 or SDOUTS1. Both interfaces must be configured for the same sample rate, but
the interface format need not be the same. This allows
the IC to route audio data from one device to another,
converting the data format as needed. Figure 15 shows
the available digital signal routing options.
In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2
7MAS1/MAS2
6WCI1/WCI2
5BCI1/BCI2
0x14/0x1C
4DLY1/DLY2
2TDM1/TDM2
1FSW1/FSW2
0WS1/WS2
accept LRCLK and BCLK as inputs.
0 = Slave mode
1 = Master mode
DAI1/DAI2 Word Clock Invert
TDM1/TDM2 = 0:
0 = Left-channel data is transmitted while LRCLK is low.
1 = Right-channel data is transmitted while LRCLK is low.
TDM1/TDM2 = 1:
Always set WCI = 0.
DAI1/DAI2 Bit Clock Invert
BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1.
0 = SDIN is accepted on the rising edge of BCLK.
SDOUT is valid on the rising edge of BCLK.
1 = SDIN is accepted on the falling edge of BCLK.
SDOUT is valid on the falling edge of BCLK.
Master Mode:
0 = LRCLK transitions on the falling edge of BCLK.
1 = LRCLK transitions on the rising edge of BCLK.
DAI1/DAI2 Data Delay
DLY1/DLY2 has no effect when TDM1/TDM2 = 1.
0 = The most significant data bit is clocked on the first active BCLK edge after an
LRCLK transition.
1 = The most significant data bit is clocked on the second active BCLK edge after an
LRCLK transition.
DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode)
Set TDM1/TDM2 when communicating with devices that use a frame synchronization
pulse on LRCLK instead of a square wave.
0 = Disabled
1 = Enabled (BCI1/BCI2 must be set to 1)
DAI1/DAI2 Wide Frame Sync Pulse
Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 =
1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0.
0 = Disabled
1 = Enabled
DAI1/DAI2 Audio Data Bit Depth
Determines the maximum bit depth of audio being transmitted and received. Data is
always 16 bit when TDM1/TMD2 = 0.
0 = 16 bits
1 = 24 bits
Table 10. Digital Audio Interface Registers (continued)
REGISTERBITNAMEDESCRIPTION
ADC Oversampling Ratio
Use the higher setting for maximum performance. Use the lower setting for reduced
power consumption at the expense of performance.
00 = 96x
01 = 64x
10 = Reserved
11 = Reserved
When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When
operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK frequency that clocks all data input to the DAC and output by the ADC.
000 = BCLK disabled
001 = 64 x LRCLK
010 = 48 x LRCLK
011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1)
100 = PCLK/2
101 = PCLK/4
110 = PCLK/8
111 = PCLK/16
DAI1/DAI2 Audio Port Selector
Selects which port is used by DAI1/DAI2.
00 = None
01 = Port S1
10 = Port S2
11 = Reserved
DAI1 Digital Loopthrough
Connects the output of the record signal path to the input of the playback path. Data
input to DAI1 from an external device is mixed with the recorded audio signal.
0 = Disabled
1 = Enabled
DAI1/DAI2 Digital Audio Interface Loopback
LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the digital audio input to DAI2 back out on DAI1. Selecting LBEN2 disables the ADC output
data.
0 = Disabled
1 = Enabled
DAI1/DAI2 DAC Mono Mix
Mixes the left and right digital input to mono and routes the combined signal to the left
and right playback paths. The left and right input data is attenuated by 6dB prior to the
mono mix.
0 = Disabled
1 = Enabled
Table 10. Digital Audio Interface Registers (continued)
REGISTERBITNAMEDESCRIPTION
Disable DA1/DAI2 Output High-Impedance Mode
Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to
force a level on SDOUT at all times.
0 = Disabled
1 = Enabled
DAI1/DAI2 Record Path Output Enable
DAI2 outputs data only if LBEN1 = 1.
0 = Disabled
1 = Enabled
DAI1/DAI2 Playback Path Input Enable
0 = Disabled
1 = Enabled
TDM Left Time Slot
Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
11 = Slot 4
TDM Right Time Slot
Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
11 = Slot 4
TDM Slot Delay
Adds 1 BCLK cycle delay to the data in the specified TDM slot.
1xxx = Slot 4 delayed
x1xx = Slot 3 delayed
xx1x = Slot 2 delayed
xxx1 = Slot 1 delayed
The digital signal paths in the IC require a master clock
(MCLK) between 10MHz and 60MHz to function. The
MAX98088 requires an internal clock between 10MHz
and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to
create the internal clock (PCLK). PCLK is used to clock
all portions of the IC.
The MAX98088 includes two digital audio signal paths,
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, four main clocking modes are
supported:
U PLL Mode: When operating in slave mode, enable the
PLL to lock onto any LRCLK input. This mode requires
U Normal Mode: This mode uses a 15-bit clock divider
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequencies and can be used in either master or slave mode.
U Exact Integer Mode (DAI1 only): In both master and
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
U DAC Low-Power Mode: This mode bypasses the
PLL for reduce power consumptions and uses fixed
counters to generate the clocks. The DAI__DAC_LP
bits override the other clock settings.
the least configuration, but provides the lowest performance. Use this mode to simplify initial setup or
when normal mode and exact integer mode cannot
be used.
Table 11. Clock Control Registers
REGISTERBITNAMEDESCRIPTION
MCLK Prescaler
0x10
0x11/0x19
5
PSCLK
4
7
6
SR1/SR2
5
4
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz P MCLK P 20MHz (PCLK = MCLK)
10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2)
11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4)
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio.
0x11
0x12/0x1A
0x13/0x1B
3
2
1
7PLL1/PLL2
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0NI1[0]/NI2[0]
FREQ1
NI1/
NI2
VALUESAMPLE RATEVALUESAMPLE RATE
0x0Disabled0x8
0x1Reserved0x9
0x2Reserved0xA
0x3Reserved0xB
0x4Reserved0xC
0x5Reserved0xD
0x6Reserved0xE
0x7Reserved0xF
PLL Mode Enable (Slave Mode Only)
PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK
frequency and automatically sets the LRCLK divider (NI1/NI2).
0 = Disabled
1 = Enabled
Normal Mode LRCLK Divider
When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12
for common NI values.
SAMPLE RATEDHF1/DHF2NI1/NI2 FORMULA
8kHz P LRCLK P 48kHz
48kHz < LRCLK P 96kHz
f
= LRCLK frequency
LRCLK
f
= Prescaled MCLK frequency (PCLK)
PCLK
Rapid Lock Mode
Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1
to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically
adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is
much closer to the correct value, thus speeding up lock time. Wait one LRCLK period
after programming NI1/NI2 before setting PLL1/PLL2 = 1.
Sample Rate Mix Enable. If enabled, mixes data on DAI1 and DAI2. If cleared, SCR
data source is DAI2 only.
0 = SRC mix disable
1 = SRC mix enable
Sample Rate Converter Enable. Select if the SRC is enabled on per channel basis.
0 = Sample rate converter disable
1 = Sample rate converter enable
0x21
4SRMIX_MODE
3SRMIX_ENL
2SRMIX_ENR
1SRC_ENL
0SRC_ENR
MAX98088
Passband Filtering
Each digital signal path in the IC includes options for
defining the path bandwidth (Figure 19). The playback
and record paths connected to DAI1 support both voice
and music filtering while the playback path connected to
DAI2 supports music filtering only.
The voice IIR filters provide greater than 70dB stopband
attenuation at frequencies above fS/2 to reduce aliasing.
Three selectable highpass filters eliminate unwanted lowfrequency signals.
DVST:
0dB TO -60dB
ADLEN
ADREN
ADCL
ADCR
AUTOMATIC
GAIN
CONTROL
SIDETONE
AVLG: 0/6/
12/18dB
AVL:0dB
TO -15dB
SRMIX_
MODE1
AVFLT
MODE
DSTS
NOISE GATE
AUDIO/
FILTERS
SAMPLE RATE
CONVERTER
MIX
VOICE
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
PARAMETRIC
Use music mode when processing high-fidelity audio
content. The music FIR filters reduce power consumption and are linear phase to maintain stereo imaging.
An optional DC-blocking filter is available to eliminate
unwanted DC offset.
In music mode, a second set of FIR filters are available to
support sample rates greater than 50kHz. The filters can
be independently selected for DAI1 and DAI2 and support both the playback and record audio paths.
DV1G:
0/6/12/18dB
+
MULTI BAND ALC
DVEQ1:
0dB TO -15dB
5-BAND
EQ
EQ1ENEQ2EN
EXCURSION LIMITER
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
DCB2
MODE1
DVFLT
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
MIX
MIXDAL
MIX
MIXDAR
DACL
DALEN
DACR
DAREN
Figure 19. Digital Passband Filtering Block Diagram
The IC playback signal path includes automatic level
control (ALC) and a 5-band parametric equalizer (EQ)
(Figure 20). The DAI1 and DAI2 playback paths include
separate ALCs controlled by a single set of registers.
Two completely separate parametric EQs are included
for the DAI1 and DAI2 playback paths.
Automatic Level Control
The automatic level control (ALC) circuit ensures maximum signal amplitude without producing audible clipping. This is accomplished by a variable gain stage that
works on a sample by sample basis to increase the gain
up to 12dB. A look-ahead circuit determines if the next
sample exceeds full scale and reduces the gain so that
the sample is exactly full scale.
A programmable low signal threshold determines the
minimum signal amplitude that is amplified. Select a
threshold that prevents the amplification of background
noise. When the signal level drops below the low signal
threshold, the ALC reduces the gain to 0dB until the signal increases above the threshold. Figure 21 shows an
example of ALC input vs. output curves.
The ALC can optionally be configured in dual-band
mode. In this mode, the input signal is filtered into two
bands with a 5kHz center frequency. Each band is
routed through independent ALCs and then summed
together. In multiband mode, both bands use the same
parameters.
OUTPUT SIGNAL
(dBFS)
0
INPUT
SIGNAL
(dBFS)
OUTPUT SIGNAL
(dBFS)
0
LOW-LEVEL
THRESHOLD
ALC WITH ALCTH ≠ 000
-120
DV1G:
0/6/12/18dB
+
MULTI BAND ALC
DVEQ1:
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
EQ1ENEQ2EN
EXCURSION LIMITER
INPUT
SIGNAL
(dBFS)
INPUT
SIGNAL
(dBFS)
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
DCB2
MODE1
DVFLT
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
MIX
MIXDAL
MIX
MIXDAR
DACL
DALEN
DACR
DAREN
OUTPUT SIGNAL
(dBFS)
0
LOW-LEVEL
THRESHOLD
ALC WITH ALCTH = 000
LOW-LEVEL
THRESHOLD
ALC DISABLED
-120
-120
Figure 21. ALC Input vs. Output ExamplesFigure 20. Playback Path Signal Processing Block Diagram
Enables ALC on both the DAI1 and DAI2 playback paths.
0 = Disabled
1 = Enabled
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Excursion
Limiter section for Excursion Limiter release times. ALC release time is defined as the
time required to adjust the gain from 12dB to 0dB.
Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be
configured properly to achieve the correct center frequency for each playback path.
0 = Single-band ALC
1 = Dual-band ALC
Low Signal Threshold
Selects the minimum signal level to be boosted by the ALC.
000 = -JdB (low-signal threshold disabled)
001 = -12dB
010 = -18dB
011 = -24dB
100 = -30dB
101 = -36dB
110 = -42dB
111 = -48dB
0x43
7ALCEN
6
5
4
3ALCMB
2
1
0
ALCRLS
ALCTH
MAX98088
Parametric Equalizer
The parametric EQ contains five independent biquad
filters with programmable gain, center frequency, and
bandwidth. Each biquad filter has a gain range of Q12dB
and a center frequency range from 20Hz to 20kHz. Use a
filter Q less than that shown in Figure 22 to achieve ideal
frequency responses. Setting a higher Q results in nonideal frequency response. The biquad filters are series
connected, allowing a total gain of Q60dB.
Figure 22. Maximum Recommended Filter Q vs. Frequency
CENTER FREQUENCY (Hz)
fs = 48kHz
fs = 96kHz
10,0001000
MAX98088
Stereo Audio Codec
with FlexSound Technology
Use the attenuator at the EQ’s input to avoid clipping
the signal. The attenuator can be programmed for fixed
attenuation or dynamic attenuation based on signal level.
If the dynamic EQ clip detection is enabled, the signal
The MAX98088 EV kit software includes a graphical interface for generating the EQ coefficients. The coefficients
are sample rate dependent and stored in registers 0x52
through 0xB5.
level from the EQ is fed back to the attenuator circuit to
determine the amount of gain reduction necessary to
avoid clipping.
Table 17. EQ Registers
REGISTERBITNAMEDESCRIPTION
DAI1/DAI2 EQ Clip Detection
Automatically controls the EQ attenuator to prevent clipping in the EQ.
0 = Enabled
1 = Disabled
DAI1/DAI2 EQ Attenuator
Provides attenuation to prevent clipping in the EQ when full-scale signals are boosted. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2
= 1.
The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive a 32I earpiece
speaker. In cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route
the receiver amplifier output to the left speaker outputs. The receiver amplifier can also be configured as stereo singleended line outputs using the I2C interface.
The IC’s receiver amplifier accepts input from the stereo DAC, the line inputs (single-ended or differential), and the MIC
inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the
mixed signal can be configured to attenuate 6dB, 9dB, or 12dB.
The IC integrates a stereo filterless Class D amplifier that
offers much higher efficiency than Class AB without the
typical disadvantages.
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current
steering switches and consume negligible additional
power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET
on-resistance, and quiescent current overhead.
SPVOLL:
+8dB TO -62dB
MIX
DACL
DALEN
DACR
DAREN
MIXSPL
MIX
MIXSPR
SPVOLR:
+8dB TO -62dB
The theoretical best efficiency of a linear amplifier is 78%,
however, that efficiency is only exhibited at peak output
power. Under normal operating levels (typical music
reproduction levels), efficiency falls below 30%, whereas
the IC’s Class D amplifier still exhibits 80% efficiency
under the same conditions.
Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B and FCC
electromagnetic-interference (EMI) regulation standards.
Maxim’s patented active emissions limiting edge-rate
control circuitry reduces EMI emissions, allowing operation without any output filtering in typical applications.
The IC’s speaker amplifiers accept input from the stereo DAC, the line inputs (single-ended ore differential), and the MIC inputs.
Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixer can
be configured to attenuate the signal by 6dB, 9dB or 12dB.
The IC includes signal processing to improve the sound
quality of the speaker output and protect transducers
from damage. An excursion limiter dynamically adjusts
the highpass corner frequency, while a power limiter and
distortion limiter prevent the amplifier from outputting too
much distortion or power. The excursion limiter is located
in the DSP while the distortion limiter and power limiter
control the analog volume control (Figure 28). All three
limiters analyze the speaker amplifier’s output signal to
determine when to take action.
Excursion Limiter
The excursion limiter is a dynamic highpass filter that
monitors the speaker outputs and increases the highpass
corner frequency when the speaker amplifier’s output
exceeds a predefined threshold. The filter smoothly
transitions between the high and low corner frequency to
prevent unwanted artifacts. The filter can operate in four
different modes:
U Fixed-Frequency Preset Mode. The highpass corner
frequency is fixed at the upper corner frequency and
does not change with signal level.
U Fixed-Frequency Programmable Mode. The high-
pass corner frequency is fixed to that specified by the
programmable biquad filter.
U Preset Dynamic Mode. The highpass filter automati-
cally slides between a preset upper and lower corner
frequency based on output signal level.
U User-Programmable Dynamic Mode. The highpass
filter slides between a user-programmed biquad filter
on the low side to a predefined corner frequency on
the high side.
MAX98088
Stereo Audio Codec
with FlexSound Technology
The transfer function for the user-programmable biquad is:
bbzb z
H(z)
=
1 aza z
-1-2
++
012
-1-2
++
12
The coefficients b0, b1, b2, a1, and a2 are sample
rate dependent and stored in registers 0xB4 through
0xC7. Store b0, b1, and b2 as positive numbers. Store
a1 and a2 as negated two’s complement numbers.
Separate filters can be stored for the DAI1 and DAI2
playback paths.
DV1G:
0/6/12/18dB
+
MULTI BAND ALC
DVEQ1:
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
EQ1ENEQ2EN
EXCURSION LIMITER
5-BAND
PARAMETRIC
EQ
DV2:
0dB TO -15dB
DV1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
DCB2
AUDIO/
FILTERS
AUDIO/
VOICE
FILTERS
MODE1
DVFLT
MIX
MIXDAL
MIX
MIXDAR
DALEN
DAREN
The MAX98088 EV kit software includes a graphic interface
for generating the user-programmable biquad coefficients.
Note: Only change the excursion limiter settings when
the signal path is disabled to prevent undesired artifacts.
SPVOLL:
+8dB TO -62dB
+6dB
SPLEN
POWER/
DISTORTION LIMITER
+6dB
SPREN
DACL
DACR
MIX
MIXSPL
MIX
MIXSPR
SPVOLR:
+8dB TO -62dB
SPKLVDD
SPKLP
SPKLN
SPKLGND
SPKRVDD
SPKRP
SPKRN
SPKRGND
Figure 27. Speaker Amplifier Signal Processing Block Diagram
Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level
Control section for ALC release times. Excursion limiter release time is defined as the
time required to slide from the high corner frequency to the low corner frequency.
Excursion Limiter Threshold
Measured at the Class D speaker amplifier outputs. Signals above the threshold use
the upper corner frequency. Signals below the threshold use the lower corner frequency. V