MAXIM MAX97003 Technical data

19-6044; Rev 0; 9/11

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

General Description

The MAX97003 audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier. The headphone and speaker amplifiers have independent volume and on/off controls. The four inputs are configurable as two differential or four single-ended inputs.

To minimize output noise, both the headphone and speaker outputs utilize a downward expander/noise gate to attenuate noise when no desired input signal is present.

The speaker output incorporates an adjustable dynamic range compressor (DRC) and distortion limiter to protect the speaker and maximize loudness. This allows high gain for low-level signals without compromising the quality of large signals.

All controls are performed using the two-wire I2C interface. The IC operates in the extended -40NC to +85NC temperature range, and is available in the 2.0mm x

2.4mm, 20-bump WLP package (0.4mm pitch).

Applications

Cell Phones

Portable Media Players

Ordering Information appears at end of data sheet.

Features

S 2.7V to 5.5V Speaker Supply Voltage

S 1.8V Headphone Supply Voltage

S 1.0W Speaker Output (V

68µH, 1% THD+N)

S 32mW/Channel Headphone Output (RHP = 32I)

S Active Emissions Limiting for Enhanced EMI

Reduction

S Efficient Class H Headphone Amplifier

S Ground-Referenced Headphone Outputs

S Headphone Ground Sense

S 2 Stereo Single-Ended/Mono Differential Inputs

S Integrated Expander/Noise Gate for Low Output

Noise

S Integrated DRC (Speaker Outputs)

S Integrated Distortion Limiter (Speaker Outputs)

S Extensive Click-and-Pop Reduction Circuitry

S TDMA Noise Free

S 2.0mm x 2.4mm, 20-Bump WLP Package (0.4mm

Pitch)

PVDD

= 4.2V, Z

SPK

= 8I +

Simplified Block Diagram

1.8V BATTERY

POWER SUPPLY

STEREO/

MONO INPUT

STEREO/

MONO INPUT

For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX97003.related.

�� Maxim Integrated Products 1

DRC AND

EXPANDER

MAX97003

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

I2C

CONTROL

VOLUME

CLASS D

AMPLIFIER

LIMITER

CLASS H

AMPLIFIER

CHARGE

PUMP

HEADPHONE

GROUND

SENSE

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

LIST OF FIGURES

Figure 1. Signal Path .......................................................................... 22

Figure 2. Stereo Single-Ended and Differential Input Configurations ..................................... 23

Figure 3. EMI with 12in of Speaker Cable ..........................................................23

Figure 4. Low-Signal to High-Signal Transition, No Clipping, DRC Disabled ............................... 24

Figure 5. Low-Signal to High-Signal Transition, Increased Gain, DRC Disabled............................. 24

Figure 6. Low-Signal to High-Signal Transition, Increased Gain, DRC Enabled ............................. 24

Figure 7. DRC Gain Curve ...................................................................... 24

Figure 8. Expander Gain Curve .................................................................. 25

Figure 9. High-Signal to Low-Signal Transition, Expander Disabled ...................................... 25

Figure 10. High-Signal to Low-Signal Transition, Expander Enabled...................................... 25

Figure 11. High-Signal to Low-Signal Transition, Speaker Expander with Speaker Low-Power Mode ............ 26

Figure 12. Limiter Gain Curve....................................................................26

Figure 13. Traditional Amplifier Output vs. MAX97003 DirectDrive Output ................................. 27

Figure 14. Class H Operation.................................................................... 28

Figure 15. I2C Serial Interface Timing Diagram ...................................................... 40

Figure 16. START, STOP, and REPEATED START Conditions ........................................... 41

Figure 17. Acknowledge ........................................................................ 41

Figure 18. Writing 1 Byte of Data to the IC .........................................................42

Figure 19. Writing n-Bytes of Data to the IC ........................................................ 42

Figure 20. Reading One Byte of Data from the IC.................................................... 43

Figure 21. Reading n-Bytes of Data from the IC .....................................................43

Figure 22. Optional Class D Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23. WLP Ball Dimensions .................................................................46

�� Maxim Integrated Products 4

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

LIST OF TABLES

Table 1. Register Map ......................................................................... 29

Table 2. Volume Readback Registers ............................................................. 30

Table 3. Input Configuration Registers............................................................. 31

Table 4. Mixer Registers........................................................................ 32

Table 5. Headphone Volume Control Registers ...................................................... 33

Table 6. Dynamic Range Control Registers .........................................................34

Table 7. Expander Registers .................................................................... 35

Table 8. Distortion Limiter Register ............................................................... 36

Table 9. Speaker Low-Power Mode Register........................................................37

Table 10. Output Gain Register .................................................................. 38

Table 11. Advanced Configuration Control Register ..................................................39

Table 12. Power Management Register ............................................................ 40

Table 13. Startup Sequence..................................................................... 44

�� Maxim Integrated Products 5

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Functional Diagram/Typical Application Circuit

1.6V TO 2.0V 2.7V TO 5.5V

1µF

INA1

INA2

INB1 C4

INB2 C5

10µF

PGAINA

+

-3dB TO +12dB

PGAINA

-3dB TO +12dB

PGAINB

-3dB TO +12dB

PGAINB

-3dB TO +12dB

V

DD

D4

D5

0.1µF 1µF 10µF

INADIFF

INBDIFF

V

DD

C3

-63dB TO 0dB

MIX

HPLMIX

EXPANDER

MIX

HPRMIX

MIX

SPKMIX

DRC AND

EXPANDER

-63dB TO 0dB

SPKVOL:

-63dB TO 0dB

HPLVOL:

HPRVOL:

PVDD

C1

BIAS

HPVDD

0dB TO 6dB

HPLEN

HPVSS

HPVDD

0dB TO 6dB

HPREN

HPVSS

PVDD

+12dB TO 24dB

SPKEN

PGND

THD LIMITER

THDCLP

B5

BIAS

1µF

HPLA5

HPSNSB4

HPRA4

D1

SPKP

SPKN

D2

SDA C2

SCL B2

CONTROL

B1

GND

MAX97003

D3

PGND

A2

C1P

V

DD

CHARGE PUMP

A1

C1NB3CPVDD CPVSS

1µF

A3

1µF1µF

�� Maxim Integrated Products 6

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

ABSOLUTE MAXIMUM RATINGS

(Voltages with respect to GND.)

VDD, CPVDD ........................................................-0.3V to +2.2V

BIAS .......................................................... -0.3V to (VDD + 0.3V)

PVDD .................................................................... -0.3V to +6.0V

PGND ...................................................................-0.1V to +0.1V

CPVSS ................................................................. -2.2V to +0.3V

C1N ................................... (V

C1P ..................................................... -0.3V to (V

HPL, HPR .......................... (V

CPVSS

- 0.3V) to (V

CPVDD CPVDD CPVDD

+ 0.3V) + 0.3V)

+ 0.3V)

INA1, INA2, INB1, INB2 .......................................-0.3V to +6.0V

SDA, SCL .............................................................-0.3V to +6.0V

SPKP, SPKN ..........................................-0.3V to (V

PVDD

+ 0.3V)

HPSNS .................................................................. -0.3V to +0.3V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VDD = 1.8V, V configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z noted. Typical values are at TA = +25NC.) (Note 1)

= 4.2V, V

PVDD

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= V

GND

SPK

PGND

= J, RHP = J. C

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

C1P-C1N

= C

Continuous Current In/Out of PVDD, PGND, SPK_ ....... Q800mA

Continuous Current In/Out of HPR, HPL, VDD .............. Q140mA

Continuous Input Current (all other pins) ........................ Q20mA

Duration of SPK_ Short Circuit to GND or PVDD ......Continuous

Duration of Short Circuit Between SPKP and SPKN ... Continuous

Duration of HP_ Short Circuit to GND or VDD ...........Continuous

Continuous Power Dissipation (TA = +70NC)

WLP Multilayer Board

(derate 21.7mW/NC above +70NC) ................................1.74W

Junction Temperature .....................................................+150NC

Operating Temperature Range .......................... -40NC to +85NC

Storage Temperature Range ............................ -65NC to +150NC

Soldering Temperature (reflow) ......................................+260NC

CPVDD

= C

CPVSS

= C

= 1FF. TA = T

BIAS

MIN

to T

, unless otherwise

MAX

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Speaker Amplifier Supply Voltage Range

Headphone Amplifier Supply Voltage Range

Quiescent Current I

PVDD Guaranteed by PSRR test 2.7 5.5 V

V

DD

Guaranteed by PSRR test 1.6 2 V

HP mode, TA = +25NC, stereo SE input on INA routed to HP output, HP expander disabled

HP mode, TA = +25NC, stereo SE input on INA routed to HP output, HP expander enabled

SPK mode, TA = +25NC mono differential input on INA routed to SPK output; SPK expander, DRC, and limiter all disabled

SPK mode, TA = +25NC mono differential input on INA routed to SPK output; SPK expander, DRC, and limiter all enabled

SPK + HP mode, TA = +25NC stereo SE input on INA routed

I

VDD

I

PVDD

I

VDD

I

PVDD

I

VDD

I

PVDD

I

VDD

I

PVDD

I

VDD

1.21 1.6

1.07 1.3

2.46 2.95

1.34 1.6

0.1 0.15

2.25 2.6

1.35 1.65

2.6 2.95

1.21 1.6

mA

to HP and SPK output; SPK and HP expanders, DRC, and limiter all disabled

I

PVDD

2.74 3.2

�� Maxim Integrated Products 7

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 1.8V, V configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z noted. Typical values are at TA = +25NC.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Shutdown Current

Turn On-Time t

PREAMPLIFIERS

Input Resistance R

Gain

Maximum Input Signal Swing Preamp = 0dB 2.4 V

Common-Mode Rejection Ratio CMRR f = 1kHz (differential input mode), 0dB 63 dB

Input DC Voltage IN__ inputs 1.2 1.23 1.275 V

Bias Voltage V

SPEAKER AMPLIFIER

Output Offset Voltage VOS

= 4.2V, V

PVDD

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= V

GND

SPK

PGND

= J, RHP = J. C

I

SHDN

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

ON

IN

BIAS

C1P-C1N

I

VDD

I

PVDD

Time from power-on to full operation

TA = +25NC

PGAIN_ = 0x0 -3.2 -2.98 -2.79

PGAIN_ = 0x1 -1.49

PGAIN_ = 0x2 -0.22 -0.02 +0.21

PGAIN_ = 0x3 1.57

PGAIN_ = 0x4 3.04

PGAIN_ = 0x5 4.52

PGAIN_ = 0x6 6.06

PGAIN_ = 0x7 7.51

PGAIN_ = 0x8 9.01

PGAIN_ = 0x9 10.59

PGAIN_ = 0xA 11.82 12 12.36

1.2 1.23 1.275 V

TA = +25NC (volume at mute, SPKGAIN = 00)

TA = +25NC (volume at 0dB, SPKGAIN = 00)

= C

, TA = +25NC

CPVDD

= C

CPVSS

SLEW = 0 SLEW = 1

-3dB to +9dB 15 20.4 28.5

+10.5dB to +12dB 5.2 6.96 9.5

= 1FF. TA = T

BIAS

to T

MIN

0.08 2.5

0.05 1

17

10

MAX

Q0.5 Q2.5

Q1.0

, unless otherwise

FA

ms

kI

dB

P-P

mV

Click-and-Pop Level K

�� Maxim Integrated Products 8

CP

Peak voltage, TA = +25NC, A-weighted, 32 samples per second, volume at 0dB, SPKGAIN = 00 (Note 2)

Into shutdown -72

dBV

Out of shutdown -65

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 1.8V, V configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z noted. Typical values are at TA = +25NC.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power-Supply Rejection Ratio (Note 2)

Output Power (Note 3) P

Total Harmonic Distortion Plus Noise

Output Noise A-weighted

Signal-to-Noise Ratio SNR

Output Frequency f

Spread-Spectrum Bandwidth

Gain

Current Limit 2 A

Efficiency h

Volume Control

Volume Control Step Size 1 dB

Mute Attenuation f = 1kHz 118 dB

= 4.2V, V

PVDD

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= V

GND

SPK

PGND

= J, RHP = J. C

PSRR

THD+N

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

OUT

C1P-C1N

= C

TA = +25NC

THD+N = 1%

f = 1kHz, P Z

SPK

f = 1kHz, P Z

SPK

OUT

= 8I + 68FH

OUT

= 8I + 68FH

CPVDD

= C

CPVSS

V

PVDD

= C

= 2.7V to

5.5V

f = 217Hz, V

RIPPLE

= 200mV

f = 1kHz, V

RIPPLE

= 200mV

f = 10kHz, V

Z V

= 200mV

RIPPLE

= 8I + 68FH,

SPK

= 4.2V

PVDD

= 8I + 68FH,

SPK

= 3.6V

PVDD

= 4I + 33FH,

SPK

= 5.0V

PVDD

= 700mW, TA = +25NC,

= 350mW, TA = +25NC,

= 1FF. TA = T

BIAS

P-P

MIN

to T

, unless otherwise

MAX

65 90.4

80

78

72

1007

735

2585

0.06

0.029 0.048

Noise gate disabled 40

Noise gate enabled 25

Noise gate disabled 93

Noise gate enabled 98

Q10

kHz

OSC

A-weighted, P

= 700mW

OUT

Spread spectrum 298.9 kHz

SPKGAIN = 00 11.69

SPKGAIN = 01 15.4 15.65 15.92

SPKGAIN = 10 19.64

SPKGAIN = 11 23.7

P

= 1W, f = 1kHz, Z

OUT

= 8I + 68FH

SPK

92 %

SPKVOL = 0x00 -63.35 -62.87 -62.36

SPKVOL = 0x3F -0.044 0 0.13

FV

dB

mW

%

RMS

dB

�� Maxim Integrated Products 9

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 1.8V, V configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z noted. Typical values are at TA = +25NC.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CHARGE PUMP

Charge-Pump Frequency

Positive Output Voltage V

Negative Output Voltage V

Output Voltage Threshold V

Mode Transition Timeouts

HEADPHONE AMPLIFIERS

Output Offset Voltage VOS

= 4.2V, V

PVDD

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= V

GND

SPK

PGND

= J, RHP = J. C

CPVDD

CPVSS

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

HPL

OUT

= V

> V

< V

> V

< V

= C

HPR

TH

C1P-C1N

V

TH

Output voltage at which the charge pump switches modes, V

Time it takes for the charge pump to transition from invert to split mode

Time it takes for the charge pump to transition from split to invert mode

CPVDD

= C

CPVSS

= C

= 1FF. TA = T

BIAS

MIN

to T

, unless otherwise

MAX

= 0V 80 83.3 86

= 0.2V 665

= 0.5V 500

V

DD

VDD/2

-V

DD

-VDD/2

rising or falling

OUT

QV

DD

x 0.216

QV

x 0.25

DD

QV

x 0.278

30 ms

20

DD

TA = +25NC Q0.15 Q0.5

kHz

V

Fs

mV

Click-and-Pop Level K

Power-Supply Rejection Ratio (Note 2)

PSRR

�� Maxim Integrated Products 10

CP

Peak voltage, TA = +25NC, A-weighted, 32 samples per second, volume at 0dB (Note 2)

TA = +25NC

Into shutdown -73

Out of shutdown -73

VDD = 1.6V to 2.0V 65 99.9

f = 217Hz, V

RIPPLE

= 200mV

f = 1kHz, V

RIPPLE

= 200mV

f = 20kHz, V

RIPPLE

= 200mV

P-P

93

88

65

dBV

dB

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 1.8V, V configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z noted. Typical values are at TA = +25NC.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= 4.2V, V

PVDD

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= V

GND

SPK

PGND

= J, RHP = J. C

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

= 1FF. TA = T

BIAS

MIN

to T

, unless otherwise

MAX

THD+N = 1%, PGAINA = -1.5dB,

Output Power P

Channel-to-Channel Gain Tracking

Total Harmonic Distortion Plus Noise

Output Noise A-weighted

Signal-to-Noise Ratio SNR

Capacitive Drive C

Crosstalk

Gain

Volume Control

Volume Control Step Size 1 dB

Mute Attenuation f = 1kHz 100 dB

SPEAKER DRC

Release Time

Attack Time

Compression Ratio

OUT

THD+N

HPGAIN = +2dB

THD+N = 0.1%, PGAINA = -1.5dB, HPGAIN = +2dB

HPL to HPR, volume at 0dB, HPLMIX = 0x1, HPRMIX = 0x2, IN_DIFF = 0

RHP = 32I, P

RHP = 16I, P

A-weighted, P

= 10mW

OUT

1000 pF

L

HPL to HPR, HPR to HPL, RHP = 32I, P

= 10mW

OUT

HPGAIN = 00 -0.53 -0.25 +0.09

HPGAIN = 01 1.72

HPGAIN = 10 3.72

HPGAIN = 11 5.85

HP_VOL = 0x00 -63.74 -63.3 -62.9

HP_VOL = 0x3F -0.50 -0.27 +0.09

DRCRLS = 000 800

DRCRLS = 101 25

DRCATK = 000 0.5

DRCATK = 111 50

DRCEN = 001 1.34:1

DRCEN = 101

OUT

RHP = 16I

RHP = 32I

= 10mW, f = 1kHz

Noise gate disabled 10

Noise gate enabled 5.9

Noise gate disabled 94.2

Noise gate enabled 96.4

f = 20Hz to 10kHz -78

f = 1kHz -83

42

32

27

0.25 1.5 %

0.005

0.006

J:1

mW

FV

dB

ms/

step

ms

ratio

%

RMS

�� Maxim Integrated Products 11

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 1.8V, V configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z noted. Typical values are at TA = +25NC.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Compression Threshold

SPEAKER AND HEADPHONE EXPANDER

Attack Time

Release Time Low-signal to high-signal transition 0.2

Expander Threshold

SPEAKER DISTORTION LIMITER

Distortion Threshold

Attack Time 0.5 ms

Release Time

= 4.2V, V

PVDD

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= V

GND

SPK

PGND

= J, RHP = J. C

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

= 1FF. TA = T

BIAS

MIN

to T

, unless otherwise

MAX

DRCTH = 0x01 0.839

DRCTH = 0x1F 0.199

EXP_ATK = 000 500

High signal to low signal transition

EXP_ATK = 101 25

EXP_ATK = 110 15

EXP_TH = 0x1 32

EXP_TH = 0xF 1

THDCLP = 0x1 < 1

THDCLP = 0xF 24

THDRLS = 000 0.076

THDRLS = 111 6.2

V

RMS

ms/

step

ms/

step

mV

P

%

s

DIGITAL I/O CHARACTERISTICS

(VDD = 1.8V, V (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (SDA and SCL)

Input Voltage High V

Input Voltage Low V

Input Hysteresis V

Input Capacitance C

Input Leakage Current I

DIGITAL OUTPUTS (SDA Open Drain)

Output Low Voltage SDA VOL I

= 4.2V, V

PVDD

�� Maxim Integrated Products 12

GND

= V

= 0V. TA = T

PGND

iH

IL

HYS

IN

to T

MIN

, unless otherwise noted. Typical values are at TA = +25NC.)

MAX

0.7 x V

DD

0.4 x V

DD

V

200 mV

10 pF

TA = +25NC Q1.0 FA

VDD = 0V, TA = +25NC Q1.0 FA

= 3mA 0.4 V

SINK

High-Efficiency, Low-Noise Audio Subsystem

I2C TIMING CHARACTERISTICS

(VDD = 1.8V, V (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Serial-Clock Frequency f

Bus Free Time Between STOP and START Conditions

Hold Time (Repeated) START Condition

SCL Pulse-Width Low t

SCL Pulse-Width High t

Setup Time for a Repeated START Condition

PVDD

= 4.2V, V

GND

= V

PGND

SCL

t

BUF

t

HD,STA

LOW

HIGH

t

SU,STA

= 0V. TA = T

MAX97003

to T

MIN

0 400 kHz

1.3

0.6

1.3

0.6

, unless otherwise noted. Typical values are at TA = +25NC.)

MAX

Fs

Data Hold Time t

Data Setup Time t

SDA and SCL Receiving Rise Time

SDA and SCL Receiving Fall Time

SDA Transmitting Fall Time t

Setup Time for STOP Condition t

Bus Capacitance C

Pulse Width of Suppressed Spike t

Note 1: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design. Note 2: Amplifier inputs are AC-coupled to GND. Note 3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. Note 4: CB is in pF.

HD,DAT

SU,DAT

t

SU,STO

SP

0 900 ns

100 ns

(Note 4)

R

(Note 4)

F

(Note 4)

F

0.6

400 pF

B

0 50 ns

20 +

0.1C

20 +

0.1C

20 +

0.1C

ns

B

300 ns

B

250 ns

B

Fs

�� Maxim Integrated Products 13

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Typical Operating Characteristics

(VDD = 1.8V, V

PVDD

= 4.2V, V

GND

= V

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

PGND

configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= J, RHP = J. C

SPK

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

BIAS

= 1FF.)

GENERAL

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

3.0 I

SPK MODE

PVDD

EXPANDER, DRC,

2.5

AND LIMITER DISABLED

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

2.5 5.5 SUPPLY VOLTAGE (V)

0.10

0.09

MAX97003 toc01

5.04.54.03.53.0

0.08

0.07

0.06

0.05

0.04

0.03

SHUTDOWN CURRENT (µA)

0.02

0.01

0

2.5 5.5

SHUTDOWN CURRENT vs. SUPPLY VOLTAGE

I

PVDD

SUPPLY VOLTAGE (V)

MAX97003 toc02

5.04.54.03.53.0

SPEAKER AMPLIFIER

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

100

V

= 4.2V

PVDD

Z

= 8I + 68µH

SPK

10

1

P

= 800mW

0.1

THD+N RATIO (%)

0.01

0.001

OUT

P

= 200mW

OUT

10 100k

FREQUENCY (Hz)

�� Maxim Integrated Products 14

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

100

V

= 4.2V

PVDD

Z

= 4I + 33µH

MAX97003 toc03

10k1k100

SPK

10

1

P

= 1.5W

OUT

0.1

THD+N RATIO (%)

0.01

P

= 500mW

OUT

0.001 10 100k

FREQUENCY (Hz)

MAX97003 toc04

THD+N RATIO (%)

0.001

10k1k100

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

100

V

= 4.2V

PVDD

Z

= 8I + 68µH

SPK

= 600mW

P

OUT

10

1

0.1

0.01

10 100k

SSM

FFM

10k1k100

FREQUENCY (Hz)

MAX97003 toc05

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Typical Operating Characteristics (continued)

(VDD = 1.8V, V

PVDD

= 4.2V, V

GND

= V

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

PGND

configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= J, RHP = J. C

SPK

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

BIAS

= 1FF.)

SPEAKER AMPLIFIER

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

V

= 5V

PVDD

Z

= 8I + 68µH

SPK

10

1

0.1

THD+N RATIO (%)

0.01

0.001

f = 6kHz

f = 1kHz

f = 100kHz

0 2.5

OUTPUT POWER (W)

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

V

= 4.2V

PVDD

Z

= 4I + 33µH

SPK

10

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

V

= 5V

PVDD

Z

= 4I + 33µH

MAX97003 toc06

2.01.51.00.5

SPK

10

1

0.1

THD+N RATIO (%)

0.01

0.001

f = 6kHz

f = 1kHz

f = 100kHz

0 4.0

OUTPUT POWER (W)

MAX97003 toc07

THD+N RATIO (%)

0.001

3.53.02.52.01.51.00.5

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

V

= 3.6V

PVDD

Z

= 8I + 68µH

MAX97003 toc09

SPK

10

MAX97003 toc10

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

V

= 4.2V

PVDD

Z

= 8I + 68µH

SPK

10

1

0.1

0.01

f = 6kHz

f = 1kHz

f = 100kHz

0 1.6

OUTPUT POWER (W)

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

V

= 3.6V

PVDD

Z

= 4I + 33µH

SPK

10

1.41.21.00.80.60.40.2

MAX97003 toc08

MAX97003 toc11

1

0.1

THD+N RATIO (%)

0.01

0.001

f = 6kHz

f = 1kHz

f = 100kHz

0 3.0

OUTPUT POWER (W)

�� Maxim Integrated Products 15

1

0.1

THD+N RATIO (%)

0.01

2.52.01.51.00.5

0.001

f = 6kHz

f = 1kHz

f = 100kHz

0 1.2

OUTPUT POWER (W)

1.00.80.60.40.2

1

0.1

THD+N RATIO (%)

0.01

0.001

f = 6kHz

f = 1kHz

f = 100kHz

0 2.0

OUTPUT POWER (W)

1.51.00.5

MAX97003

11

High-Efficiency, Low-Noise Audio Subsystem

Typical Operating Characteristics (continued)

(VDD = 1.8V, V

PVDD

= 4.2V, V

GND

= V

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

PGND

configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= J, RHP = J. C

SPK

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

BIAS

= 1FF.)

SPEAKER AMPLIFIER

EFFICIENCY vs. OUTPUT POWER

100

Z

= 8I + 68µH

SPK

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 2.5

Z

= 4I + 33µH

SPK

OUTPUT POWER (mW)

OUTPUT POWER vs. SUPPLY VOLTAGE

4.5 Z

= 4I + 33µH

SPK

4.0

f

= 1kHz

IN

3.5

3.0

2.5

2.0

1.5

OUTPUT POWER (W)

1.0

0.5

0

2.5 5.5

10% THD+N

1% THD+N

SUPPLY VOLTAGE (V)

V

PVDD

f

IN

2.01.51.00.5

5.04.54.03.53.0

= 4.2V

= 1kHz

MAX97003 toc12

EFFICIENCY (%)

MAX97003 toc15

OUTPUT POWER (W)

EFFICIENCY vs. OUTPUT POWER

100

Z

= 8I + 68µH

SPK

90

80

70

60

50

40

30

20

10

0

0 2.5

Z

= 4I + 33µH

SPK

OUTPUT POWER (mW)

V

PVDD

1.51.00.5

OUTPUT POWER vs. LOAD RESISTANCE

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

THD+N = 10%

THD+N = 1%

LOAD RESISTANCE (I)

V

Z

= LOAD + 68µH

SPK

10010

PVDD

f

IN

f

IN

= 3.6V = 1kHz

= 4.2V

= 1kHz

MAX97003 toc13

MAX97003 toc16

k

OUTPUT POWER vs. SUPPLY VOLTAGE

2.5 Z

= 8I + 68µH

SPK

f

= 1kHz

IN

2.0

1.5

1.0

OUTPUT POWER (W)

0.5

0

2.5 5.5

10% THD+N

1% THD+N

SUPPLY VOLTAGE (V)

POWER-SUPPLY REJECTION

RATIO vs. FREQUENCY

120

100

80

60

PSRR (dB)

40

V

= 4.2V

PVDD

V

= 200mV

RIPPLE

20

Z

= 8I + 68µH

SPK

INPUTS AC-COUPLED TO GND

0

P-P

1k

FREQUENCY (Hz)

5.04.54.03.53.0

100k

10k10010

MAX97003 toc14

MAX97003 toc17

�� Maxim Integrated Products 16

MAX97003

07

High-Efficiency, Low-Noise Audio Subsystem

Typical Operating Characteristics (continued)

(VDD = 1.8V, V

PVDD

= 4.2V, V

GND

= V

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

PGND

configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= J, RHP = J. C

SPK

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

BIAS

= 1FF.)

SPEAKER AMPLIFIER

POWER-SUPPLY REJECTION

120

V

= 200mV

RIPPLE

fIN = 1kHz

100

INPUTS AC-COUPLED TO GND

80

60

PSRR (dB)

40

20

0

2.5 5.5

P-P

SUPPLY VOLTAGE (V)

WIDEBAND OUTPUT SPECTRUM

0

RBW = 100Hz FFM

-20

-40

-60

-80

OUTPUT AMPLITUDE (dBV)

-100

RATIO vs. SUPPLY VOLTAGE

-20

MAX97003 toc18

-40

-60

-80

AMPLITUDE (dBV)

-100

-120

5.04.54.03.53.0

-140

-20

MAX97003 toc21

-40

-60

-80

OUTPUT AMPLITUDE (dBV)

-100

INBAND OUTPUT SPECTRUM

0

SSM

= 1kHz

f

IN

0 20k

FREQUENCY (Hz)

15k10k5k

WIDEBAND OUTPUT SPECTRUM

0

RBW = 100Hz SSM

0

-20

MAX97003 toc19

-40

-60

-80

AMPLITUDE (dBV)

-100

-120

-140 0 20k

0

-10

MAX97003 toc22

-20

-30

-40

-50

SPEAKER VOLUME GAIN (dB)

-60

INBAND OUTPUT SPECTRUM

FFM

= 1kHz

f

IN

FREQUENCY (Hz)

SPEAKER VOLUME GAIN

vs. SPKVOL CODE

15k10k5k

MAX97003 toc20

MAX97003 toc23

-120

1010.1 100

FREQUENCY (MHz)

-120

�� Maxim Integrated Products 17

FREQUENCY (MHz)

1010.1 100

-70

SPKVOL CODE (NUMERIC)

605040302010

0

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Typical Operating Characteristics (continued)

(VDD = 1.8V, V

PVDD

= 4.2V, V

GND

= V

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

PGND

configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= J, RHP = J. C

SPK

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

BIAS

= 1FF.)

SPEAKER AMPLIFIER

SHUTDOWN RESPONSE

2ms/div

MAX97003 toc24

VS2EN = 0 SLEW = 0 ZCD = 0

SCL 2V/div

SPEAKER OUTPUT 200mA/div

TURN-ON RESPONSE

VS2EN = 0 SLEW = 0 ZCD = 0

4ms/div

MAX97003 toc25

SCL 2V/div

SPEAKER OUTPUT 200mA/div

HEADPHONE AMPLIFIER

TOTAL HARMONIC DISTORTION

100

V

PVDD

V

DD

10

R

HP

1

0.1

THD+N RATIO (%)

0.01

0.001

P

10

PLUS NOISE vs. FREQUENCY

= 4.2V

= 1.8V

= 32I

= 5mW

OUT

P

= 20mW

OUT

10k1k100 100k

FREQUENCY (Hz)

MAX97003 toc26

TOTAL HARMONIC DISTORTION

100

V

PVDD

V

DD

10

R

HP

1

0.1

THD+N RATIO (%)

P

0.01

0.001

OUT

10

PLUS NOISE vs. FREQUENCY

= 4.2V

= 1.8V

= 16I

= 10mW

P

= 25mW

OUT

10k1k100 100k

FREQUENCY (Hz)

MAX97003 toc27

THD+N RATIO (%)

0.001

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

RHP = 32I

10

1

0.1

0.01

0 0.050

0.005

f = 6kHz

f = 1kHz

f = 100Hz

0.020

0.010

0.015 OUTPUT POWER (W)

0.030

0.025

�� Maxim Integrated Products 18

0.035

MAX97003 toc28

0.040

0.045

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Typical Operating Characteristics (continued)

(VDD = 1.8V, V

PVDD

= 4.2V, V

GND

= V

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

PGND

configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= J, RHP = J. C

SPK

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

BIAS

= 1FF.)

HEADPHONE AMPLIFIER

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. OUTPUT POWER

100

RHP = 16I

10

1

0.1

THD+N RATIO (%)

0.01

0.001

f = 6kHz

f = 1kHz

f = 100Hz

OUTPUT POWER (W)

OUTPUT POWER vs. LOAD RESISTANCE

AND CHARGE-PUMP CAPACITANCE

70

C

CHARGE_PUMP

60

50

40

C

CHARGE_PUMP

= 1µF

30

OUTPUT POWER (mW)

20

C

CHARGE_PUMP

= 0.47µF

10

0

1 10k

= 2.2µF

fIN = 1kHz THD+N = 1% C

CHARGE_PUMP

C

= C

CPVDD

LOAD RESISTANCE (I)

0.050.040.030.020.010 0.07

0.06

= C

C1N-C1P

CPVSS

1k10010

100

90

MAX97003 toc29

80

70

60

50

40

30

POWER DISSIPATION (mW)

20

10

0

120

100

MAX97003 toc32

80

60

PSRR (dB)

40

20

0

POWER DISSIPATION

vs. OUTPUT POWER

R

= 16I

LOAD

R

= 32I

LOAD

fIN = 1kHz P

= P

+ P

OUT

HPL

1201008040 60200 140

OUTPUT POWER (mW)

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY

V

= 4.2V

PVDD

VDD = 1.8V V

= 200mV

RIPPLE

INPUTS AC-COUPLED TO GND R

= 32I

LOAD

on V

P-P

DD

FREQUENCY (Hz)

10k1k10010 100k

HPR

MAX97003 toc30

160

MAX97003 toc33

OUTPUT POWER vs. LOAD RESISTANCE

80

70

60

THD+N = 10%

50

40

THD+N = 1%

30

OUTPUT POWER (mW)

20

10

0

1 10k

LOAD RESISTANCE (I)

INBAND OUTPUT SPECTRUM

0

fIN = 1kHz

-20

R

= 32I

LOAD

-40

-60

-80

-100

AMPLITUDE (dBV)

-120

-140

-160 0 20k

FREQUENCY (Hz)

fIN = 1kHz

1k10010

16k 18k14k4k2k 6k 8k 10k 12k

MAX97003 toc31

MAX97003 toc34

�� Maxim Integrated Products 19

MAX97003

07

High-Efficiency, Low-Noise Audio Subsystem

Typical Operating Characteristics (continued)

(VDD = 1.8V, V

PVDD

= 4.2V, V

GND

= V

= 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal

PGND

configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential. Speaker loads (Z SCL pullup voltage = 1.8V. Z

) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and

SPK

= J, RHP = J. C

SPK

C1P-C1N

= C

CPVDD

= C

CPVSS

= C

BIAS

= 1FF.)

HEADPHONE AMPLIFIER

COMMON-MODE REJECTION RATIO

vs. FREQUENCY

100

R

= 32I

LOAD

90

80

70

60

50

CMRR (dB)

40

30

20

10

0

PGAIN = 12dB

FREQUENCY (Hz)

TURN-ON RESPONSE

PGAIN = 0dB

PGAIN = -3dB

PGAIN = 6dB

10k1k10010 100k

MAX97003 toc40

MAX97003 toc37

SCL 2V/div

0

fIN = 1kHz

-20

R

LOAD

-40

-60

-80

-100

AMPLITUDE (dBV)

-120

-140

-160

0

-10

-20

-30

INBAND OUTPUT SPECTRUM

= 16I

16k 18k14k4k2k 6k 8k 10k 12k0 20k

FREQUENCY (Hz)

HEADPHONE VOLUME GAIN

vs. HP_VOL CODE

-20

MAX97003 toc35

-40

-60

CROSSTALK (dB)

-80

-100

-120

MAX97003 toc38

CROSSTALK vs. FREQUENCY

0

R

= 32I

LOAD

FREQUENCY (Hz)

SHUTDOWN RESPONSE

HPR TO HPL

HPL TO HPR

10k1k10010 100k

VS2EN = 0 SLEW = 0 ZCD = 0

MAX97003 toc39

MAX97003 toc36

SCL 2V/div

-40

-50

HEADPHONE VOLUME GAIN (dB)

-60

-70

HP_VOL CODE (NUMERIC)

605040302010

0

�� Maxim Integrated Products 20

4ms/div

HP_ 500mV/div

VS2EN = 0 SLEW = 0 ZCD = 0

4ms/div

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Bump Configuration

TOP VIEW

(BUMP SIDE DOWN)

+

A

B

C

D

MAX97003

23 41

C1P CPVSS HPRC1N

SCL CPVDD HPSNSGND

SDA V

SPKN PGND INA1 INA2SPKP

DD

WLP

INB1

5

HPL

BIAS

INB2PVDD

Bump Description

BUMP NAME FUNCTION

A1 C1N

A2 C1P

A3 CPVSS

A4 HPR Headphone Amplifier Right Output

A5 HPL Headphone Amplifier Left Output

B1 GND Analog Ground

B2 SCL Serial Clock Input. Connect a pullup resistor from SCL to the I2C bus supply.

B3 CPVDD

B4 HPSNS Headphone Ground Sense. Connect to the headset jack’s ground terminal.

B5 BIAS

C1 PVDD

C2 SDA Serial-Data Input/Output. Connect a pullup resistor from SDA to the I2C bus supply.

C3 V

DD

C4 INB1 Input B1. Left or negative input.

C5 INB2 Input B2. Right or positive input.

D1 SPKP Positive Speaker Output

D2 SPKN Negative Speaker Output

D3 PGND Speaker Amplifier Ground and Charge-Pump Ground

D4 INA1 Input A1. Left or negative input.

D5 INA2 Input A2. Right or positive input.

Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF capacitor between C1P and C1N.

Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF capacitor between C1P and C1N.

Headphone Amplifier Negative Power Supply. Bypass with a 1FF capacitor to PGND.

Headphone Amplifier Positive Power Supply. Bypass with a 1FF capacitor to PGND.

Common-Mode Bias. Bypass to GND with a 1FF capacitor.

Speaker Amplifier Power Supply. Bypass with a 0.1FF and a 10FF capacitor to PGND.

Headphone Amplifier Supply. Bypass with a 0.1FF and a 10FF capacitor to GND.

�� Maxim Integrated Products 21

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Detailed Description

The MAX97003 audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier. The high-efficiency 1W class D speaker amplifier operates directly from a lithium-ion battery and consumes no more than 0.05FA when in shutdown mode. The headphone amplifier utilizes a dual-mode charge pump and a Class H output stage to maximize efficiency while outputting a ground-referenced signal that does not require output coupling capacitors. The headphone and speaker amplifiers have independent volume and on/off control. The four inputs are configurable as two differential inputs or four single-ended inputs. All control is performed using the two-wire I2C interface.

The speaker amplifier incorporates a distortion limiter to automatically reduce the volume level when excessive clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals. The speaker amplifier also features an adjustable DRC that provides programmable compression or limiting of the audio signal. Both the headphone and speaker

INA2

INA1

INB2

INB1

INPUT A

-3dB TO +12dB

MIXER

MUX

INPUT B

-3dB TO +12dB

amplifiers feature a downward expander/noise gate to attenuate noise when no input signal is present. The headphone amplifier features a ground-sense pin to eliminate ground loop noise when the headphone jack is in use.

Signal Path

The signal path consists of flexible inputs, signal mixing, volume control, and output amplifiers (Figure 1). The inputs can be configured for single-ended or differential signals (Figure 2). The internal preamplifiers feature programmable gain settings using internal resistors. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers based on the desired configuration.

Class D Speaker Amplifier

The Class D speaker amplifier utilizes active emissionslimiting and spread-spectrum modulation to minimize the EMI radiated by the amplifier.

HPL

-63dB TO 0dB

AND

-63dB TO 0dB0dB TO +6dB

-63dB TO 0dB+12dB TO +24dB

0dB TO +6dB

HPR

SPKP

SPKN

Figure 1. Signal Path

�� Maxim Integrated Products 22

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

STEREO SINGLE-ENDED

IN_2 (R)

R

TO MIXER

IN_1 (L)

L

DIFFERENTIAL

IN_2 (+)

IN_1 (-)

Figure 2. Stereo Single-Ended and Differential Input Configurations

90

70

50

30

EMISSION LEVEL (dBµV/m)

10

-10 0 1000

FREQUENCY (MHz)

Figure 3. EMI with 12in of Speaker Cable

900800600 700200 300 400 500100

TO MIXER

Ultra-Low EMI Filterless Output Stage

Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B electromagnetic-interference (EMI) regulation standards. Maxim’s patented active emissions limiting edge-rate control circuitry and spread-spectrum modulation reduces EMI emissions, while maintaining up to 93% efficiency. Maxim’s spread-spectrum modulation mode flattens wideband spectral components, while proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency. The IC’s spread-spectrum modulator randomly varies the switching frequency by Q10kHz around the center frequency (300kHz). Above 10MHz, the wideband spectrum looks like noise for EMI purposes. See Figure 3.

�� Maxim Integrated Products 23

High-Efficiency, Low-Noise Audio Subsystem

Figure 4. Low-Signal to High-Signal Transition, No Clipping, DRC Disabled

MAX97003

Dynamic Range Compressor (DRC)

The speaker amplifier features a dynamic range compressor (DRC) that attenuates high-amplitude signals and allows for a higher gain setting to be selected without clipping the output signal. This increases the perceived loudness of the audio signal and maintains a stable output amplitude despite changes in input amplitude. Figure 4,

Figure 5, and Figure 6 demonstrate the benefits of using

the DRC. Each of these figures uses the same input signal.

To operate the DRC, select a threshold level, compression ratio, attack time constant, and release time through registers 0x0A and 0x0B. When enabled, RMS signal levels that cross above the selected DRC threshold level are attenuated based on the selected compression ratio (Figure 7). Attenuation is achieved by automatically modifying the speaker volume to a lower gain setting. The user-selected gain setting is automatically restored when the RMS signal level falls below the DRC threshold. The attack time constant determines the time constant used when the DRC engages. The release time determines the time-per-step used when the DRC disengages.

Figure 5. Low-Signal to High-Signal Transition, Increased Gain, DRC Disabled

Figure 6. Low-Signal to High-Signal Transition, Increased Gain, DRC Enabled

OUTPUT

)

(V

RMS

0.85

Figure 7. DRC Gain Curve

THRESHOLD

0.199 TO 0.839

1:1

1.5:1 2:1

4:1

∞:1

INPUT

)

(V

RMS

0.85

�� Maxim Integrated Products 24

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

OUTPUT

(mV

)

P

1200

1:1

2:1

4:1

∞:1

THRESHOLD

1 TO 32

Figure 8. Expander Gain Curve

1200

INPUT (mV

Expander

The IC’s speaker and headphone amplifier signal paths include and expander. The expander reduces the noise floor when there is no desired input signal by attenuating peak signals that are below the selected expander threshold (Figure 8). Attenuation is achieved by automatically modifying the speaker or headphone volume to a lower gain setting. Expansion ratio and attack time settings are configured by registers 0x0C for the headphone path and 0x0D for the speaker path. The expansion ratio determines the input:output relationship used when the input signal is below the selected threshold. The expansion attack time determines the time-per-step used when the expander engages. Figure 9 and Figure 10 show the benefits of the expander by comparing the output with the expander disabled against the output with the expander enabled.

)

P

The expander acts as a noise gate when the expansion ratio is set to an input:output relationship of infinity:1. In this case, all signals below the selected threshold are muted.

Figure 9. High-Signal to Low-Signal Transition, Expander Disabled

�� Maxim Integrated Products 25

Figure 10. High-Signal to Low-Signal Transition, Expander Enabled

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Speaker Low-Power Mode

The IC’s speaker path expander includes a low-power mode that increases power efficiency when there is no desired input signal. Set the programmable threshold in register 0x0F to determine when low-power mode is activated. When low-power mode is enabled, the Class D switching output is active only if the speaker volume setting selected by the expander is above the selected low-power mode threshold. For example, if the speaker low-power mode threshold is set to -30dB and the input

SPKP

SPKN

Figure 11. High-Signal to Low-Signal Transition, Speaker Expander with Speaker Low-Power Mode

DISTORTION

(% THD+N)

DISTORTION THRESHOLD

LEVEL

< 1 TO 24

Figure 12. Limiter Gain Curve

LIMITER

ENABLED AND

GAIN INCREASED

LIMITER

DISABLED

INPUT

signal is such that the speaker expander attenuates the output volume setting to at least -30dB, the Class D amplifier is turned off (Figure 11). Low-power mode is only available when the speaker expander is enabled.

Distortion Limiter

The speaker amplifier integrates a limiter to provide speaker protection and ensures high-quality audio. When enabled, the limiter monitors the audio signal at the output of the Class D speaker amplifier and decreases the gain if the distortion exceeds the predefined threshold. Attenuation is achieved by automatically modifying the speaker volume as appropriate. The limiter automatically tracks the battery voltage to reduce the gain as the battery voltage drops.

Figure 12 shows the typical output vs. input curves with

and without the distortion limiter. The dotted line shows the maximum gain for a given distortion limit without the distortion limiter. The solid line shows how, with the distortion limiter enabled, the gain can be increased without exceeding the set distortion limit. When the limiter is enabled, selecting a high gain level results in peak signals being attenuated while low signals are left unchanged. This increases the perceived loudness without the harshness of a clipped waveform.

To operate the distortion limiter, select a distortion threshold and release time constant through the 0x0E register. ZCD must be set to 0 in register 0x11 for the distortion limiter to operate properly.

Headphone Amplifier

DirectDrive

Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier.

Maxim’s patented DirectDriveM architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the IC to be biased at GND while operating from a single supply (Figure 13). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220FF, typ) capacitors, the IC's charge pump requires

DirectDrive is a registered trademark of Maxim Integrated Products, Inc.

�� Maxim Integrated Products 26

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

two small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. See the Output Power vs. Charge-Pump Capacitance and Load Resistance graph in the Typical Operating Characteristics section for details of the possible capacitor sizes. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the IC is typically Q0.15mV, which, when combined with a 32I load, results in less than 5FA of DC current flow to the headphones.

In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier’s low-frequency response and can distort the audio signal. Previous attempts at eliminating the

V

DD

OUT

CONVENTIONAL DRIVER-BIASING SCHEME

OUT

DirectDrive BIASING SCHEME

Figure 13. Traditional Amplifier Output vs. MAX97003 DirectDrive Output

VDD/2V

GND

+V

VDD/2V

-V

DD

output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises a few issues:

• Thesleeveistypicallygroundedtothechassis.Using

the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design.

• DuringanESD strike, the amplifier’s ESD structures

are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike.

• Whenusingtheheadphonejackasalineouttoother

equipment, the bias voltage on the sleeve can conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers.

Charge Pump

The IC’s dual-mode charge pump generates both the positive and negative power supply for the headphone amplifier. To maximize efficiency, both the charge pump’s switching frequency and output voltage change based on signal level.

When the input signal level is less than 10% of VDD, the switching frequency is reduced to a low rate. This minimizes switching-losses in the charge pump. When the input signal exceeds 10% of VDD, the switching frequency increases to support the load current.

For input signals below 25% of VDD, the charge pump generates Q(VDD/2) to minimize the voltage drop across the amplifier’s power stage and thus improves efficiency. Input signals that exceed 25% of VDD cause the charge pump to output QVDD. The higher output voltage allows for full output power from the headphone amplifier.

To prevent audible glitches when transitioning from the Q(VDD/2) output mode to the QVDD output mode, the charge pump transitions very quickly. This quick change draws significant current from VDD for the duration of the transition. The bypass capacitor on VDD supplies the required current and prevent droop on VDD.

The charge pump’s dynamic switching mode can be turned off through the I2C interface. The charge pump can then be forced to output either Q(VDD/2) or QVDD regardless of input signal level.

�� Maxim Integrated Products 27

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Class H Operation

A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal. In the case of the IC, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V) are available from the charge pump. Figure 14 shows the operation of the output voltage dependent power supply.

Ground Sense

The headphone amplifier features output ground sensing that is used to reduce ground loop noise when the headphone output jack is connected to a different ground than the amplifier ground. An example of this is when the headphone jack is used as a lineout and connected to an external power amplifier. In addition, the ground sense reduces noise that can be caused by voltage drops between the amplifier ground and the headphone jack ground pin during normal headphone use. HPSNS must be connected to the ground pin on the headphone jack.

Volume-Change Features

The IC includes several features that enhance performance during volume changes. Zero-crossing detection, volume slewing, and enhanced volume smoothing are used to improve click-and-pop performance during volume changes. Volume readback is used to report the actual volume setting after the DRC, expander, or distortion limiter applies an automatic volume change.

Zero-Crossing Detection

The IC features zero-crossing detection to reduce clicks and pops during volume changes. When zero-crossing detection is enabled, all volume changes are delayed until a zero-crossing has been detected. If no zero-crossing is detected within 100ms, then the zero-crossing detector times out and volume changes are executed.

1.8V

HPVDD

0.9V V

TH

V

TH

-0.9V HPVSS

-1.8V

Figure 14. Class H Operation

32ms

OUTPUT VOLTAGE

32ms

Disabling zero-crossing detection allows volume changes to occur immediately.

Volume Slewing

The IC offers volume slewing for all volume changes to further reduce clicks and pops. When enabled, the IC ramps through intermediate volume settings when a change to the volume is made. If zero-crossing detection is disabled, slewing occurs at a rate of 0.2ms per step. If zero-crossing detection is enabled, slew time depends on the input signal. If the duration between zero-crossings is less than 0.2ms, the slew time is limited at 0.2ms per volume change. If the duration between zero-crossings is longer than 0.2ms, volume changes occur at each zero-crossing. Volume slewing also provides a soft-start at power-on and soft-stop at power-off.

Enhanced Volume Smoothing

Enhanced volume smoothing can be used when the volume slewing feature is enabled. When enhanced volume smoothing is enabled and a volume change occurs, the IC waits for each step in the ramp to be applied before executing the next step. When zero-crossing detection is enabled, enhanced volume smoothing prevents large steps in the output volume when no zero-crossings are detected.

Volume Readback

The IC features three volume readback registers that report the actual volume settings of the speaker, left headphone, and right headphone volume registers. The DRC, expander, and distortion limiter are capable of automatically adjusting these volume registers according to their respective settings.

I2C Slave Address

The IC’s audio subsystem uses a slave address of 0x9A or 1001101 R/W. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/write bit to 1 to configure the audio subsystem to read mode. Set the read/write bit to 0 to configure the IC to write mode. The address is the first byte of information sent to the IC after the START condition.

Registers Map

19 internal registers program the audio subsystem.

Table 1 lists all of the registers, their addresses, and

power-on-reset states. Register 0xFF indicates the device revision. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted.

�� Maxim Integrated Products 28

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Table 1. Register Map

REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W

STATUS

Left Headphone Volume

Readback

Right Headphone

Volume Readback

Speaker Volume

Readback

Input A Configuration 0 0 0 INADIFF PGAINA 0x03 0x00 R/W

Input B Configuration 0 0 0 INBDIFF PGAINB 0x04 0x00 R/W

Headphone Mixer HPLMIX HPRMIX 0x05 0x00 R/W

Speaker Mixer 0 0 0 0 SPKMIX 0x06 0x00 R/W

Left Headphone Volume HPLM 0 HPLVOL 0x07 0x00 R/W

0 0 HPLVOLRB 0x00 — R

0 0 HPRVOLRB 0x01 — R

0 0 SPKVOLRB 0x02 — R

Right Headphone

Volume

Speaker Volume SPKM 0 SPKVOL 0x09 0x00 R/W

Dynamic Range Control DRCEN DRCATK DRCRLS 0x0A 0x00 R/W

Dynamic Range Control 0 0 0 DRCTH 0x0B 0x00 R/W

Headphone Expander EXPHEN EXPHATK EXPHTH 0x0C 0x00 R/W

Speaker Expander EXPSEN EXPSATK EXPSTH 0x0D 0x00 R/W

Distortion Limiter THDCLP 0 THDRLS 0x0E 0x00 R/W

Speaker Low-Power

Mode

Output Gain 0 0 0 0 HPGAIN SPKGAIN 0x10 0x00 R/W

Advanced Configuration VS2EN

Power Management

REVISION ID

Rev ID REV 0xFF 0x40 R

HPRM 0 HPRVOL 0x08 0x00 R/W

SLPEN 0 SLPTH 0x0F 0x00 R/W

0 FFM 0 CPSEL FIXED 0x11 0x00 R/W

SHDN

SLEW ZCD

0 0 0 0 SPKEN HPLEN HPREN 0x12 0x00 R/W

�� Maxim Integrated Products 29

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Volume Readback

The Volume Readback registers report the actual volume setting of each output volume control when the DRC, expander, or distortion limiter is active.

Table 2. Volume Readback Registers

REGISTER BIT NAME DESCRIPTION

Output Volume

0x00/0x01/

0x02

5

4

3

2

1

0

HPLVOLRB/

HPRVOLRB/

SPKVOLRB

VALUE

0x00 -63 0x10 -47 0x20 -31 0x30 -15 0x01 -62 0x11 -46 0x21 -30 0x31 -14 0x02 -61 0x12 -45 0x22 -29 0x32 -13 0x03 -60 0x13 -44 0x23 -28 0x33 -12 0x04 -59 0x14 -43 0x24 -27 0x34 -11 0x05 -58 0x15 -42 0x25 -26 0x35 -10 0x06 -57 0x16 -41 0x26 -25 0x36 -9 0x07 -56 0x17 -40 0x27 -24 0x37 -8 0x08 -55 0x18 -39 0x28 -23 0x38 -7

0x09 -54 0x19 -38 0x29 -22 0x39 -6 0x0A -53 0x1A -37 0x2A -21 0x3A -5 0x0B -52 0x1B -36 0x2B -20 0x3B -4 0x0C -51 0x1C -35 0x2C -19 0x3C -3 0x0D -50 0x1D -34 0x2D -18 0x3D -2 0x0E -49 0x1E -33 0x2E -17 0x3E -1

0x0F -48 0x1F -32 0x2F -16 0x3F 0

GAIN

(dB)

VALUE

GAIN

(dB)

VALUE

GAIN

(dB)

VALUE

GAIN

(dB)

�� Maxim Integrated Products 30

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Input Configuration

The input configuration registers allow the selection of single-ended or differential modes as well as preamp gain settings for INA and INB.

Table 3. Input Configuration Registers

REGISTER BIT NAME DESCRIPTION

Input A/B Differential Mode. Configures the input as either a mono differential signal

0x03/0x04

4

3

2

1

0

INADIFF/

INBDIFF

PGAINA/

PGAINB

(IN_ = IN_2 - IN_1) or as a stereo signal (IN_1 = left, IN_2 = right). 0 = Stereo single-ended 1 = Differential

Input A/B Preamp Gain. Set the input gain to maximize output signal level for a given input signal range to improve the SNR of the system.

VALUE LEVEL (dB) VALUE LEVEL (dB)

0x0 -3 0x6 +6 0x1 -1.5 0x7 +7.5 0x2 -0 0x8 +9 0x3 +1.5 0x9 +10.5 0x4 +3 0xA–0xF +12 0x5 +4.5 — —

�� Maxim Integrated Products 31

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Mixers

The IC features independent mixers for the left headphone, right headphone, and speaker paths. Each output can select any combination of any inputs. This allows for mixing two audio signals together and routing independent signals to the headphone and speaker amplifiers. If one of the inputs is not selected by either mixer, it is automatically powered down to reduce current consumption.

Table 4. Mixer Registers

REGISTER BIT NAME DESCRIPTION

7

Left Headphone Mixer. Selects which of the four inputs is routed to the left headphone output.

0x05

0x06

6

5

4

3

2

1

0

3

2

1

0

HPLMIX

HPRMIX

SPKMIX

0000

xxx1 xx1x x1xx 1xxx

Right Headphone Mixer. Selects which of the four inputs is routed to the right headphone output.

0000

xxx1 xx1x x1xx 1xxx

Speaker Mixer. Selects which of the four inputs is routed to the speaker output.

0000 xxx1 xx1x x1xx 1xxx

No input INA1 (Disabled when INADIFF = 1) INA2 (Select when INADIFF = 1) INB1 (Disabled when INBDIFF = 1) INB2 (Select when INBDIFF = 1)

�� Maxim Integrated Products 32

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Volume Control

The speaker, left headphone, and right headphone have independent volume control registers that allow a gain to be selected from -63dB to 0dB.

Table 5. Headphone Volume Control Registers

REGISTER BIT NAME DESCRIPTION

0x07/0x08/

0x09

7

5

4

3

2

1

0

HPLM/

HPRM/

SPKM

HPLVOL/ HPRVOL/

SPKVOL

Output Mute

0 = Unmuted 1 = Muted

Output Volume

VALUE

0x00 -63 0x10 -47 0x20 -31 0x30 -15 0x01 -62 0x11 -46 0x21 -30 0x31 -14 0x02 -61 0x12 -45 0x22 -29 0x32 -13 0x03 -60 0x13 -44 0x23 -28 0x33 -12 0x04 -59 0x14 -43 0x24 -27 0x34 -11 0x05 -58 0x15 -42 0x25 -26 0x35 -10 0x06 -57 0x16 -41 0x26 -25 0x36 -9 0x07 -56 0x17 -40 0x27 -24 0x37 -8 0x08 -55 0x18 -39 0x28 -23 0x38 -7

0x09 -54 0x19 -38 0x29 -22 0x39 -6 0x0A -53 0x1A -37 0x2A -21 0x3A -5 0x0B -52 0x1B -36 0x2B -20 0x3B -4 0x0C -51 0x1C -35 0x2C -19 0x3C -3 0x0D -50 0x1D -34 0x2D -18 0x3D -2 0x0E -49 0x1E -33 0x2E -17 0x3E -1

0x0F -48 0x1F -32 0x2F -16 0x3F 0

GAIN

(dB)

VALUE

GAIN

(dB)

VALUE

GAIN

(dB)

VALUE

GAIN

(dB)

�� Maxim Integrated Products 33

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Dynamic Range Control

The DRC attenuates high-level signals without affecting low-level signals. Attenuation is achieved by automatically modifying the speaker volume as appropriate. When the DRC is enabled, the overall volume can be increased without clipping the high-level signals. To operate the DRC, select a compression threshold, compression ratio, attack time constant, and release time.

Table 6. Dynamic Range Control Registers

REGISTER BIT NAME DESCRIPTION

7

6

5

DRCEN

DRC Enable and Compression Ratio

000 = 1:1 (disabled) 001 = 1.34:1 010 = 2:1 011 = 4:1 100 – 111 = J:1

0x0A

0x0B

4

DRCATK

3

2

1

0

4

3

2

1

0

DRCRLS

DRCTH

DRC Attack Time Constant. Defines the time constant used during attack. 00 = 500Fs 01 = 1ms 10 = 10ms 11 = 50ms

DRC Release Time. Defines the release rate per step. 000 = 800ms 001 = 400ms 010 = 150ms 011 = 75ms 100 = 50ms 101–111 = 25ms

Compression Threshold Level. Specifies the minimum input signal level for which compression is applied.

VALUE LEVEL (V

0x00 Reserved 0x10 0.354 0x01 0.839 0x11 0.334 0x02 0.792 0x12 0.315 0x03 0.748 0x13 0.298 0x04 0.706 0x14 0.281 0x05 0.667 0x15 0.265 0x06 0.629 0x16 0.251 0x07 0.594 0x17 0.237 0x08 0.561 0x18 0.223

0x09 0.529 0x19 0.211 0x0A 0.500 0x1A–0x1F 0.199 0x0B 0.472

0x0C 0.445 0x0D 0.421

0x0E 0.397 0x0F 0.375

) VALUE LEVEL (V

RMS

)

�� Maxim Integrated Products 34

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Expander (Noise Gate)

The expander/noise gate eliminates noise when no desired signal is present by attenuating peak signals that are below the selected threshold. Attenuation is achieved by automatically modifying the headphone or speaker volume as appropriate. To operate the headphone or speaker expander, select an expansion threshold, expansion ratio, and attack time in the appropriate headphone or speaker expander registers.

Table 7. Expander Registers

REGISTER BIT NAME DESCRIPTION

7

EXPHEN/

EXPSEN

6

Headphone/Speaker Expansion Ratio

00 = 1:1 (disabled) 01 = 2:1 10 = 4:1 11 = J:1 (noise gate)

0x0C/0x0D

5

4

3

2

1

0

EXPHATK/

EXPSATK

EXPHTH/

EXPSTH

Headphone/Speaker Expander Attack Time. Decreases volume after the signal drops below the selected expander threshold.

VALUE ATTACK TIME (ms/step)

000 001 010 011 100 101 110–111

Headphone/Speaker Noise Gate Threshold. The expander attenuates or mutes the output below this threshold. Thresholds are based on the PGA input signal level.

VALUE THRESHOLD (mVP)

0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7

500 350 250 100 50 25 15

Reserved 32 20 10 8 4 2 1

�� Maxim Integrated Products 35

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Distortion Limiter

The distortion limiter monitors the audio signal at the output of the Class D speaker amplifier and decreases the gain if the distortion exceeds the selected threshold. Attenuation is achieved by automatically modifying the speaker volume as appropriate. To operate the distortion limiter, select a distortion limit (% THD+N) and a release time constant.

Table 8. Distortion Limiter Register

REGISTER BIT NAME DESCRIPTION

Distortion Limit. Measured in % THD+N. ZCD must be set to 0 for the distortion

limiter to function.

VALUE DISTORTION LIMIT (%) VALUE DISTORTION LIMIT (%)

0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7

Limiter Release Time Constant. Time constant used while increasing the gain after distortion is no longer detected at the output. 000 = 6.2s 001 = 3.1s 010 = 1.6s 011 = 815ms 100 = 419ms 101 = 223ms 110 = 116ms 111 = 76ms

Limiter disabled < 1 1 2 4 6 8 10

0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF

12 14 16 18 20 21 22 24

0x0E

7

6

THDCLP

5

4

2

1

0

THDRLS

�� Maxim Integrated Products 36

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Speaker Low-Power Mode

The speaker expander includes a low-power mode that increases power efficiency when a desired audio signal is not present. When this feature is enabled, the Class D switching output is active only if the speaker volume setting selected by the expander is above the selected low-power mode threshold. Low-power mode is only available when the speaker expander is enabled.

Table 9. Speaker Low-Power Mode Register

REGISTER BIT NAME DESCRIPTION

Speaker Low-Power Mode. Only functions if EXPSEN ≠ 0.

0 = Class D output is active continuously. 1 = Class D output is active if the speaker volume setting selected by the expander is above SLPTH.

Speaker Low-Power Mode Volume Threshold. Threshold used to determine if speaker amplifier should be enabled or disabled. If the volume selected by the expander is less than this threshold, the speaker amplifier is disabled.

VALUE

0x00 -63 0x10 -47 0x20 -31 0x30 -15 0x01 -62 0x11 -46 0x21 -30 0x31 -14 0x02 -61 0x12 -45 0x22 -29 0x32 -13 0x03 -60 0x13 -44 0x23 -28 0x33 -12 0x04 -59 0x14 -43 0x24 -27 0x34 -11 0x05 -58 0x15 -42 0x25 -26 0x35 -10 0x06 -57 0x16 -41 0x26 -25 0x36 -9 0x07 -56 0x17 -40 0x27 -24 0x37 -8 0x08 -55 0x18 -39 0x28 -23 0x38 -7 0x09 -54 0x19 -38 0x29 -22 0x39 -6 0x0A -53 0x1A -37 0x2A -21 0x3A -5 0x0B -52 0x1B -36 0x2B -20 0x3B -4 0x0C -51 0x1C -35 0x2C -19 0x3C -3 0x0D -50 0x1D -34 0x2D -18 0x3D -2 0x0E -49 0x1E -33 0x2E -17 0x3E -1 0x0F -48 0x1F -32 0x2F -16 0x3F 0

GAIN

(dB)

VALUE

GAIN

(dB)

VALUE

GAIN

(dB)

VALUE

GAIN

(dB)

0x0F

7 SLPEN

5

4

3

2

1

0

SLPTH

�� Maxim Integrated Products 37

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Output Gain

The output stage of the headphone and speaker amplifiers can be configured to provide additional gain. The headphone amplifier allows a range of 0dB to +6dB. The speaker amplifier allows range of +12dB to +24dB.

Table 10. Output Gain Register

REGISTER BIT NAME DESCRIPTION

3

HPGAIN

2

0x10

1

SPKGAIN

0

Headphone Output Gain

00 = 0dB 01 = +2dB 10 = +4dB 11 = +6dB

Speaker Output Gain

00 = +12dB 01 = +16dB 10 = +20dB 11 = +24dB

�� Maxim Integrated Products 38

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Advanced Configuration

The IC includes several advanced configurations related to automatic volume changes initiated by the DRC, expander, and distortion limiter. In addition, settings for the Class D speaker modulation scheme and headphone charge pump are configured in register 0x11.

Table 11. Advanced Configuration Register

REGISTER BIT NAME DESCRIPTION

Enhanced Volume Smoothing. During volume slewing, the controller waits for each step

in the ramp to be applied before executing the next step. When zero-crossing detection is enabled, this prevents large steps in the output volume when no zero-crossings are detected. 0 = Disabled 1 = Enabled

Volume Slewing. Determines whether volume slewing is used on all volume control changes to reduce clicks and pops. When enabled, volume changes cause the IC to ramp through intermediate volume settings whenever a change to the volume is made. If ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew time depends on the input signal frequency. This bit also activates soft-start at power-on and soft-stop at power-off. 0 = Enabled 1 = Disabled

Zero-Crossing Detection. Determines whether zero-crossing detection is used on all volume control changes to reduce clicks and pops. Disabling zero-crossing detection allows volume changes to occur immediately. Zero-crossing detection times out at 100ms. 0 = Enabled 1 = Disabled

Fixed Class D Frequency Enable

0 = Spread-spectrum modulation 1 = Fixed-frequency modulation

0x11

7 VS2EN

6

5

3 FFM

SLEW

ZCD

Charge-Pump Output Select. Works with FIXED to set QVDD or QVDD/2 outputs on

1 CPSEL

0 FIXED

�� Maxim Integrated Products 39

CPVDD and CPVSS. Ignored when FIXED = 0. 0 = QVDD on CPVDD/CPVSS 1 = QVDD/2 on CPVDD/CPVSS

Class H Mode. When enabled, this bit forces the charge pump to generate static power rails for CPVDD and CPVSS, instead of dynamically adjusting them based on output signal level. 0 = Class H mode 1 = Fixed supply mode

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Power Management

The power management register allows the speaker, left headphone, and right headphone signal paths to be enabled. It also enables the IC device.

Table 12. Power Management Register

REGISTER BIT NAME DESCRIPTION

Software Shutdown

0 = Device disabled 1 = Device enabled

Speaker Amplifier Enable

0 = Disabled 1 = Enabled

Left Headphone Amplifier Enable

0 = Disabled 1 = Enabled

Right Headphone Amplifier Enable

0 = Disabled 1 = Enabled

0x12

7

SHDN

2 SPKEN

1 HPLEN

0 HPREN

I2C Serial Interface

The IC features an I2C/SMBus-compatible, two-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz. Figure 1 shows the two-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the IC by transmitting the proper slave address followed by the register address and then the data word. Each transmit

SDA

t

SCL

t

HD,STA

START CONDITION

t

LOW

t

SU,DAT

t

HD,DAT

t

HIGH

t

R

F

sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the IC is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the IC transmits the proper slave address followed by a series of nine SCL pulses. The IC transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, a not acknowledge, and a STOP

t

STOP

CONDITION

BUF

START

CONDITION

SU,STA

REPEATED START CONDITION

t

HD,STA

t

SP

t

SU,STO

Figure 15. I2C Serial Interface Timing Diagram

�� Maxim Integrated Products 40

MAX97003

rP

High-Efficiency, Low-Noise Audio Subsystem

(P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the IC from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals. See the START and STOP Conditions section.

START and STOP Conditions

SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 16). A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission, and frees

SS

SCL

SDA

Figure 16. START, STOP, and REPEATED START Conditions

the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition.

Early STOP Conditions

The IC recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition.

Slave Address

The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the IC, the seven most significant bits are 1001101. Setting the read/write bit to 1 (slave address = 0x9B) configures the IC for read mode. Setting the read/write bit to 0 (slave address = 0x9A) configures the IC for write mode. The address is the first byte of information sent to the IC after the START condition.

Acknowledge

The acknowledge bit (ACK) is a clocked ninth bit that the IC uses to handshake receipt each byte of data when in write mode (Figure 17). The IC pulls down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the IC is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not-acknowledge is sent when the master reads the final byte of data from the IC, followed by a STOP condition.

Figure 17. Acknowledge

�� Maxim Integrated Products 41

CONDITION

SCL

SDA

START

28 9

1

NOT ACKNOWLEDGE

CLOCK PULSE FOR

ACKNOWLEDGMENT

ACKNOWLEDGE

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Write Data Format

A write to the IC includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 18 illustrates the proper frame format for writing one byte of data to the IC. Figure 19 illustrates the frame format for writing n-bytes of data to the IC.

The slave address with the R/W bit set to 0 indicates that the master intends to write data to the IC. The IC acknowledges receipt of the address byte during the master-generated ninth SCL pulse.

The second byte transmitted from the master configures the IC’s internal register address pointer. The pointer tells

ACKNOWLEDGE FROM SLAVE

S AA

0SLAVE ADDRESS REGISTER ADDRESS

R/W

ACKNOWLEDGE FROM SLAVE

the IC where to write the next byte of data. An acknowledge pulse is sent by the IC upon receipt of the address pointer data.

The third byte sent to the IC contains the data that are written to the chosen register. An acknowledge pulse from the IC signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x12 are reserved. Do not write to these addresses.

ACKNOWLEDGE FROM SLAVE

B1 B0B3 B2B5 B4B7 B6

A

DATA BYTE

1 BYTE

P

Figure 18. Writing 1 Byte of Data to the IC

ACKNOWLEDGE FROM SLAVE

S

SLAVE ADDRESS

R/W

ACKNOWLEDGE FROM SLAVE

A

Figure 19. Writing n-Bytes of Data to the IC

�� Maxim Integrated Products 42

REGISTER ADDRESS

ACKNOWLEDGE FROM SLAVE

A

DATA BYTE 1

1 BYTE

B1 B0B3 B2B5 B4B7 B6

A0

AUTOINCREMENT INTERNAL

REGISTER ADDRESS POINTER

AUTOINCREMENT INTERNAL

REGISTER ADDRESS POINTER

ACKNOWLEDGE FROM SLAVE

B1 B0B3 B2B5 B4B7 B6

DATA BYTE n

1 BYTE

P

A

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Read Data Format

Send the slave address with the R/W bit set to 1 to initiate a read operation. The IC acknowledges receipt of its slave address by pulling SDA low during the ninth SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00.

The first byte transmitted from the IC is the contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read are from register 0x00.

ACKNOWLEDGE FROM SLAVE

S

0

R/W

ACKNOWLEDGE FROM SLAVE

The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the IC’s slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The IC then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte.

The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 20 illustrates the frame format for reading one byte from the IC. Figure 21 illustrates the frame format for reading multiple bytes from the IC.

ACKNOWLEDGE FROM SLAVE

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

NOT ACKNOWLEDGE FROM MASTER

AA

R/WREPEATED START

1 BYTE

P

AA

Figure 20. Reading One Byte of Data from the IC

ACKNOWLEDGE FROM SLAVE

S

Figure 21. Reading n-Bytes of Data from the IC

�� Maxim Integrated Products 43

0

R/W

ACKNOWLEDGE FROM SALVE

REPEATED START

AUTOINCREMENT INTERNAL

REGISTER ADDRESS POINTER

ACKNOWLEDGE FROM SLAVE

R/W

AAA

1 BYTE

AUTOINCREMENT INTERNAL

REGISTER ADDRESS POINTER

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

A

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Applications Information

Filterless Class D Operation

Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x V causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency.

The IC does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution.

Because the frequency of the IC output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range.

GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers. The IC is designed specifically to reject RF signals. PCB layout, however, has a large impact on the susceptibility of the end product.

peak-to-peak) and

PVDD

RF Susceptibility

In RF applications, improvements to both layout and component selection decreases the IC’s susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the IC. The wavelength (l) in meters is given by: l = c/f where c = 3 x 108 m/s, and f = the RF frequency of interest.

Route audio signals on middle layers of the PCB to allow ground planes above and below to shield them from RF interference. Ideally, the top and bottom layers of the PCB should primarily be ground planes to create effective shielding.

Additional RF immunity can also be obtained by relying on the self-resonant frequency of capacitors as it exhibits the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at RF frequencies. These capacitors when placed at the input pins can effectively shunt the RF noise at the inputs of the IC. For these capacitors to be effective, they must have a lowimpedance, low-inductance path to the ground plane. Avoid using microvias to connect to the ground plane whenever possible as these vias do not conduct well at RF frequencies.

Startup/Shutdown Sequencing

To ensure proper device initialization and minimal clickand-pop, program the IC’s control registers in the correct order. Table 13 lists the correct startup sequence for the device. To shutdown the IC, simply set SHDN = 0.

Table 13. Startup Sequence

SEQUENCE DESCRIPTION REGISTERS

1 Ensure SHDN = 0 0x12 2 Configure inputs 0x03, 0x04 3 Configure mixers 0x05, 0x06 4 Configure volume 0x07, 0x08, 0x09 5 Configure output gain 0x10 6 Enable amplifiers 0x12 7 Configure expander and DRC 0x0A–0x0F

10 Set SHDN = 1 0x12

�� Maxim Integrated Products 44

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Component Selection

Optional Ferrite Bead Filter

For applications in which speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground (Figure 22). Use a ferrite bead with low DC resistance, high frequency (> 600MHz) impedance between 100I and 600I, and rated for at least 1A. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance.

Input Capacitor

An input capacitor, CIN, in conjunction with the input impedance of the IC line inputs forms a highpass filter that removes the DC bias from an incoming analog signal. The AC-coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero source impedance, the -3dB point of the highpass filter is given by:

=

2R C

π

1

IN IN

f

-3dB

RIN is defined in the Electrical Characteristics table under the Input Resistance section. Choose CIN so that f

is well below the lowest frequency of interest. For

-3dB

best audio quality, use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, can result in increased distortion at low frequencies.

Charge-Pump Capacitor Selection

Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric.

SPKP

MAX97000

CLASS D

Figure 22. Optional Class D Ferrite Bead Filter

SPKN

Charge-Pump Flying Capacitor

The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device’s ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. Above 1FF, the on-resistance of the internal switches and the ESR of external charge-pump capacitors dominate.

Charge-Pump Holding Capacitor

The holding capacitor (bypassing CPVSS) value and ESR directly affect the ripple at CPVSS. Increasing the capacitor’s value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating

Characteristics section for more information.

Supply Bypassing, Layout, and Grounding

Proper layout and grounding are essential for optimum performance. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect GND and PGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents digital noise from coupling into the analog signals.

Place the capacitor between C1P and C1N as close as possible to the IC to minimize trace length from C1P to C1N. Inductance and resistance added to C1P and C1N reduce the output power of the headphone amplifier. Bypass CPVDD and CPVSS with capacitors located close to the pins with a short trace length to PGND. Close decoupling of CPVDD and CPVSS minimizes supply ripple and maximizes output power from the headphone amplifier.

Bypass PVDD to PGND with as little trace length as possible. Connect SPKP and SPKN to the speaker using the shortest and widest traces possible. Reducing trace length minimizes radiated EMI. Route SPKP/SPKN as a differential pair on the PCB to minimize the loop area and thereby the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate them as close as possible to the IC to ensure maximum effectiveness. Minimize the trace length from any ground tied passive components to PGND to further minimize radiated EMI.

�� Maxim Integrated Products 45

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

An evaluation kit (EV kit) is available to provide an example layout for the IC. The EV kit allows quick setup of the IC and includes easy-to-use software allowing all internal registers to be controlled.

WLP Applications Information

For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques,

0.24mm

0.21mm

Figure 23. WLP Ball Dimensions

bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: Wafer- Level Packaging (WLP) and its Applications on Maxim’s website. Figure 23 shows the dimensions of the WLP balls used on the IC.

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX97003EWP+

+Denotes a lead(Pb)-free/RoHS-compliant package.

-40NC to +85NC

20 WLP

�� Maxim Integrated Products 46

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

20 WLP W201A2+1

21-0544

Refer to Application Note 1891

PIN 1 INDICATOR

A

E

1

AAAA

MARKING

D

TOP VIEW

E1

SE

e

D

B

C

B

A

1

53 42

SD

b

0.05

D1

M S

A

BOTTOM VIEW

NOTES:

1. Terminal pitch is defined by terminal center to center value.

2. Outer dimension is defined by center lines between scribe lines.

3. All dimensions in millimeter.

4. Marking shown is for package orientation reference only.

5. Tolerance is ± 0.02 unless specified otherwise.

6. All dimensions apply to PbFree (+) package codes only.

7. Front - side finish can be either Black or Clear.

-DRAWING NOT TO SCALE-

AB

0.05

S

A3

A1

A2

S

A

See Note 7

SIDE VIEW

E

MAX

PKG. CODE

W201A2+1

W201B2+1 2.16 2.19 1.631.60

W201C2+1

W201D2+1

MIN

2.33 2.36 1.92 1.95

2.01 2.04 1.61 1.64

2.08 1.741.712.11

TITLE

APPROVAL

PACKAGE OUTLINE 20 BUMPS, WLP PKG. 0.4mm PITCH

DOCUMENT CONTROL NO.

COMMON DIMENSIONS

A

A1

A2

0.025

A3

b

D1

E1

e

SD

SE

D

MAX

MIN

21-0544

0.64

0.19

0.45

REF

BASIC

0.27

1.20

BASIC

1.60

BASIC

0.40

BASIC

0.20 BASIC

0.00 BASIC

DEPOPULATED BUMPS

NONE

0.05

0.03

REV.

1

B

�� Maxim Integrated Products 47

MAX97003

High-Efficiency, Low-Noise Audio Subsystem

Revision History

REVISION

NUMBER

0 9/11 Initial release —

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 48

©

2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

MAXIM MAX97003 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Applications

Features

Simplified Block Diagram

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

Functional Diagram/Typical Application Circuit

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

DIGITAL I/O CHARACTERISTICS

I2C TIMING CHARACTERISTICS

Typical Operating Characteristics

Bump Configuration

Bump Description

Detailed Description

Signal Path

Class D Speaker Amplifier

Ultra-Low EMI Filterless Output Stage

Dynamic Range Compressor (DRC)

Expander

Speaker Low-Power Mode

Distortion Limiter

Headphone Amplifier

DirectDrive

Charge Pump

Class H Operation

Ground Sense

Volume-Change Features

Zero-Crossing Detection

Volume Slewing

Enhanced Volume Smoothing

Volume Readback

I2C Slave Address

Registers Map

Volume Readback

Input Configuration

Mixers

Volume Control

Dynamic Range Control

Expander (Noise Gate)

Distortion Limiter

Speaker Low-Power Mode

Output Gain

Advanced Configuration

Power Management

I2C Serial Interface

Bit Transfer

START and STOP Conditions

Early STOP Conditions

Slave Address

Acknowledge

Write Data Format

Read Data Format

Applications Information

Filterless Class D Operation

RF Susceptibility

Startup/Shutdown Sequencing

Component Selection

Optional Ferrite Bead Filter

Input Capacitor

Charge-Pump Capacitor Selection

Charge-Pump Flying Capacitor

Charge-Pump Holding Capacitor

Supply Bypassing, Layout, and Grounding

WLP Applications Information

Ordering Information

Package Information

Revision History