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MAX9675
User Manual
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MAXIM MAX9675 User Manual

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MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
________________________________________________________________
Maxim Integrated Products
1
Typical Operating Circuit
Functional Diagram
19-4230; Rev 0; 7/08
SPI and QSPI are trademarks of Motorola, Inc.
General Description
The MAX9675 is a nonblocking 16 x 16 video cross­point switch with buffered inputs and outputs. The device operates on ±5V analog supplies. Digital logic is supplied separately from an independent +2.7V to +5V supply. The MAX9675 inputs and outputs are buffered with all outputs able to drive a standard 75Ω reverse­terminated video load.
The switching matrix and programmable gain are con­trolled through an SPI™/QSPI™-compatible 3-wire seri­al interface. The serial interface is designed to operate in either of two modes to provide fast updates and ini­tialization. All outputs are held in the disabled state during power-up to avoid signal conflicts in large switching arrays.
The programmability and high level of integration make the MAX9675 an ideal choice for nonblocking video switch arrays in security, surveillance, and video­on-demand systems.
The MAX9675 is available in a 100-pin TQFP package and specified over the extended -40°C to +85°C tem­perature range.
Applications
Security Systems Video Routing Video-on-Demand Systems
Features
o 16 x16 Nonblocking Matrix with Buffered Inputs
and Outputs
o Operates at ±5V Supply
o Individually Programmable Output Buffer Gain
(A
V
= +1V/V or +2V/V)
o High-Impedance Output Disable for Wired-OR
Connections
o 0.1dB Gain Flatness to 14MHz
o -3dB Bandwidth 110MHz
o -62dB Crosstalk, -110dB Isolation at 6MHz
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
Pin Configuration appears at end of data sheet.
+Denotes a lead-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX9675ECQ+ -40°C to +85°C 100 TQFP
MAX9675
CAMERAS
IN0
IN1
IN15
MAX9675
OUT0
OUT1
MONITOR
MONITOR
MONITOR
RESET
UPDATE
SCLK
IN0
IN1
IN2
IN15
DIN
CE
POWER-ON
RESET
DISABLE ALL OUTPUTS
SERIAL
INTERFACE
A0–A3 MODE
*AV = +1V/V OR +2V/V
SWITCH MATRIX
THERMAL
SHUTDOWN
MATRIX REGISTER
UPDATE REGISTER
16 x 16
256
DECODE LOGIC
LATCHES
96 BITS
16 BITS
16
AV*
AV*
AV*
AV*
16
OUT0
OUT1
OUT2
ENABLE/DISABLE
OUT15
V V AGND
DGND
DOUT
AOUT
CC
EE
V
DD
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V
(VCC= +5V, VEE= -5V, VDD= +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ω to AGND, and TA= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.) (Note 5)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Analog Supply Voltage (VCC- VEE) .....................................+11V
Digital Supply Voltage (V
DD
- DGND) ...................................+6V
Analog Supplies to Analog Ground
(V
CC
- AGND) and (AGND - VEE) ......................................+6V
Analog Ground to Digital Ground .........................-0.3V to +0.3V
IN_ Voltage Range .......................... (V
CC
+ 0.3V) to (VEE- 0.3V)
OUT_ Short-Circuit Duration to AGND, V
CC
, or VEE......Indefinite
SCLK, CE, UPDATE, MODE, A_, DIN, DOUT,
RESET, AOUT.........................(V
DD
+ 0.3V) to (DGND - 0.3V)
Current into Any Analog Input Pin (IN_) ...........................±50mA
Current into Any Analog Output Pin (OUT_).....................±75mA
Continuous Power Dissipation (T
A
= +70°C)
100-Pin TQFP (derate 22.2mW/°C above +70°C).....1777mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage
Range
Logic-Supply Voltage Range
V
CC
V
EE
V
to
DD
DGND
-
Guaranteed by PSRR test 4.5 10.5 V
2.7 5.5 V
Gain (Note 1) A
Gain Matching (Channel to Channel)
(V
+ 2.5V) < VIN_ < (VCC - 2.5V),
EE
= +1V/V, RL = 150Ω
A
V
(V
+ 2.5V) < VIN_ < (VCC - 2.5V),
EE
= +1V/V, RL = 10kΩ
A
V
(V
+ 3.75V) < VIN_ < (VCC - 3.75V),
EE
A
= +2V/V, RL = 150Ω
V
V
(V
+ 3.75V) < VIN_ < (VCC - 3.75V),
EE
A
= +2V/V, RL = 10kΩ
V
(V
+ 1V) < VIN_ < (VCC - 1.2V),
EE
A
= +1V/V, RL = 10kΩ
V
R
= 10kΩ 0.5 1.5
L
RL = 150Ω 0.5 2
1
1
2
2
1
V/V
%
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V (continued)
(VCC= +5V, VEE= -5V, VDD= +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ω to AGND, and TA= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.) (Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Temperature Coefficient of
Gain
Input Voltage Range V
Output Voltage Range V
Input Bias Current I Input Resistance R
Output Offset Voltage V
TC
AV
_
IN
OUT
B
_ (VEE + 1V) < VIN_ < (VCC - 1.2V) 10 MΩ
IN
OFFSET
10 ppm/°C
V
A
= +1V/V
V
A
= +2V/V
V
R
= 10kΩ
L
R
= 150Ω
L
R
= 10kΩ
L
R
= 150Ω
L
R
= 10kΩ
L
R
= 150Ω
L
V
V
V
V
V
E E
+ 1
E E
2.5
E E
E E
3.75
E E
E E
2.5
4 11 µA
A
= +1V/V ±5 ±20
V
A
= +2V/V ±10 ±40
V
+
+
3
+
+
1
+
V
-
C C
1.2
V
-
C C
2.5
V
-
C C
3.1
V
-
C C
3.75
V
-
C C
1.2
V
-
C C
2.5
V
V
V
mV
Output Short-Circuit Current I
Enabled Output Impedance Z Output Leakage Current,
Disable Mode
DC Power-Supply Rejection
Ratio
Quiescent Supply Current
Sinking or sourcing, R
(V
+ 1V) < VIN_ < (VCC - 1.2V) 0.2 Ω
EE
(V
+ 1V) < V
EE
OUT
I
OD
SC
PSRR 4.5V < (V
I
CC
I
EE
I
DD
R
= ∞
L
R
= ∞
L
4 8
= 1Ω ±40 mA
L
_ < (VCC - 1.2V) 0.004 1 µA
OUT
- VEE) < 10.5V 60 70 dB
CC
Outputs enabled,
T
= +25°C
A
100 150
Outputs enabled 175 Outputs disabled 55 75
Outputs enabled,
T
= +25°C
A
95 150
Outputs enabled 175 Outputs disabled 50 75
mA
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
4 _______________________________________________________________________________________
LOGIC-LEVEL CHARACTERISTICS
(VCC= +5V, VEE= -5V, VDD= +2.7V to +5.5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ω to AGND, and TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.) (Notes 2, 5)
AC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V
(VCC= +5V, VEE= -5V, VDD= +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ω to AGND, and TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input-Voltage High Level
Input-Voltage Low Level
Input Current High Level
Input Current Low Level
Output-Voltage High Level
Output-Voltage Low Level
Output Current High Level
Output Current Low Level
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OH
I
OL
VDD = +5V 3
VDD = +3V 2
V
= +5V 0.8
DD
VDD = +3V 0.6
V
> 2V
I
VI < 1V
I
SOURCE
I
SOURCE
I
= 1mA, VDD = +5V 0.1 0.3
SINK
I
= 1mA, VDD = +3V 0.1 0.3
SINK
VDD = +5V, VO = +4.9V 1 4
VDD = +3V, VO = +2.7V 1 8
VDD = +5V, VO = +0.1V 1 4
VDD = +3V, VO = +0.3V 1 8
Excluding RESET -1 +0.01 +1 RESET -30 -20 Excluding RESET -1 +0.01 +1 RESET -300 -235
= 1mA, VDD = +5V 4.7 4.9
= 1mA, VDD = +3V 2.7 2.9
V
V
µA
µA
V
V
mA
mA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
A
= +1V/V 110
Small-Signal -3dB Bandwidth
Medium-Signal -3dB Bandwidth
Large-Signal -3dB Bandwidth
Small-Signal 0.1dB Bandwidth
Medium-Signal 0.1dB
Bandwidth
Large-Signal 0.1dB Bandwidth
Slew Rate SR
BW
BW
BW
BW
BW
SS
MS
BW
LS
0.1dB-SS
0.1dB-MS
0.1dB-LS
V
= 20mV
OUT
V
_ = 200mV
OUT
V
_ = 2V
OUT
V
= 20mV
OUT
V
_ = 200mV
OUT
V
_ = 2V
OUT
V
_ = 2V step, AV = +1V/V 150
OUT
_ = 2V step, A
V
OUT
P-P
P-P
P-P
P-P
P-P
P-P
V
V
A
= +2V/V 78
V
A
= +1V/V 80
V
A
= +2V/V 75
V
A
= +1V/V 40
V
A
= +2V/V 50
V
A
= +1V/V 14
V
A
= +2V/V 11
V
A
= +1V/V 14
V
A
= +2V/V 11
V
A
= +1V/V 14
V
A
= +2V/V 11
V
= +2V/V 150
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
_______________________________________________________________________________________ 5
AC ELECTRICAL CHARACTERISTICS—DUAL SUPPLIES ±5V (continued)
(VCC= +5V, VEE= -5V, VDD= +5V, AGND = DGND = 0, VIN_ = 0, RL= 150Ω to AGND, AV= +1V/V, and TA= +25°C, unless other­wise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Settling Time t
Switching Transient (Glitch)
(Note 3)
AC Power-Supply Rejection
Ratio
Differential Gain Error
(Note 4)
Differential Phase Error
(Note 4)
S 0.1%
V
= 0 to 2V step
OUT_
A
= +1V/V 50
V
AV = +2V/V 45
V
A
= +2V/V 60
V
f = 100kHz 70
f = 1MHz 68
R
= 1kΩ 0.002
L
RL = 150Ω 0.02
R
= 1kΩ 0.02
L
RL = 150Ω 0.12
ns
mV
dB
%
d eg r ees
A
= +1V/V 60
Crosstalk, All Hostile f = 6MHz -62 dB Off-Isolation, Input to Output f = 6MHz -110 dB Input Noise-Voltage Density e Input Capacitance C Disabled Output
Capacitance
Capacitive Load at 3dB
Output Peaking
Output Impedance Z
n
IN
Amplifier in disable mode 3 pF
30 pF
OUT
BW = 6MHz 73 µV
RMS
5 pF
f = 6MHz
Output enabled 3 Output disabled 4k
Ω
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
6 _______________________________________________________________________________________
SWITCHING CHARACTERISTICS
(VCC= +5V, VEE= -5V, VDD= +2.7V to +5.5V, DGND = AGND = 0, VIN_ = 0 for dual supplies, RL= 150Ω to AGND, CL= 100pF, A
V
= +1V/V, and TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.) (Note 5)
Note 1: Associated output voltage may be determined by multiplying the input voltage by the specified gain (AV) and adding output
offset voltage.
Note 2: Logic-level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A3–A0, MODE, and AOUT. Note 3: Switching transient settling time is guaranteed by the settling time (t
S
) specification. Switching transient is a result of updat-
ing the switch matrix.
Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V.
Note 5: All devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by design.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Delay: UPDATE to Video Out t
Delay: UPDATE to AOUT t
Delay: SCLK to DOUT Valid t
Delay: Output Disable t
Delay: Output Enable t
Setup: CE to SCLK t Setup: DIN to SCLK t Hold Time: SCLK to DIN t Minimum High Time: SCLK t Minimum Low Time: SCLK t Minimum Low Time: UPDATE t
Setup Time: UPDATE to SCLK t
Hold Time: SCLK to UPDATE t
Setup Time: MODE to SCLK t
Hold Time: MODE to SCLK t
Minimum Low Time: RESET t Delay: RESET t
PdUdVo VIN
PdUdAo
PdDo
PdHOe
PdLOe
SuCe
SuDi
HdDi
MnHCk
MnLCk
MnLUd
SuHUd
HdHUd
SuMd
HdMd
MnLRst
PdRst
= 0.5V step 200 450 ns
MODE = 0, time to AOUT = low after
UPDATE = low
Logic state change in DOUT on active
SCLK edge
V
= 0.5V, 1kΩ pulldown to AGND 300 800 ns
OUT
Output disabled, 1kΩ pulldown to AGND,
= 0.5V
V
IN
100 ns 100 ns 100 ns 100 ns 100 ns 100 ns
Rising edge of UPDATE to falling edge of
SCLK
Falling edge of SCLK to falling edge of
UPDATE
Minimum time from clock edge to MODE
with valid data clocking
Minimum time from clock edge to MODE
with valid data clocking
300 ns 10kΩ pulldown to AGND, 0.5V step 600 ns
30 200 ns
30 200 ns
200 800 ns
100 ns
100 ns
100 ns
100 ns
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
_______________________________________________________________________________________ 7
Symbol Definitions
Naming Conventions
• All parameters with time units are given a "t" desig­nation, with appropriate subscript modifiers.
• Propagation delays for clocked signals are from the active edge of clock.
• Propagation delay for level-sensitive signals is from input to output at the 50% point of a transition.
• Setup and hold times are measured from the 50% point of signal transition to the 50% point of the clocking signal transition.
• Setup time refers to any signal that must be stable before the active clock edge, even if the signal is not latched or clocked itself.
• Hold time refers to any signal that must be stable during and after active clock edge, even if the sig­nal is not latched or clocked.
• Propagation delays to unobservable internal signals are modified to setup and hold designations applied to observable I/O signals.
SYMBOL TYPE DESCRIPTION
Ao Signal
Ce Signal Clock Enable (CE)
Ck Signal Clock (SCLK)
Di Signal Serial-Data In (DIN)
Do Signal
Md Signal MODE
Oe Signal Output Enable Rst Signal Reset Input (RESET) Ud Signal UPDATE
Vo Signal Video Out (OUT)
H Property
Hd Property Hold
L Property
Mn Property Minimum
Mx Property Maximum
Pd Property Propagation Delay
Su Property Setup
Tr Property Transition
W Property Width
Address Valid Flag (AOUT)
Serial-Data Output (DOUT)
High- or Low-to-High Transition
Low- or High-to-Low Transition
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
8 _______________________________________________________________________________________
Figure 1. Timing Diagram
TIMING PARAMETER DEFINITIONS NAME DESCRIPTION
t
HdDi
t
MnHCk
t
MnLCk
t
MnLUd
t
SuHUd
Not Valid Setup Time: UPDATE to Clk with UPDATE Low t
HdHUd
Not Valid Hold Time: Clk to UPDATE with UPDATE Low t
PdDiDo
t
MnMd
t
MxTr
t
MnLRst
t
PdRstVo
TIMING PARAMETER DEFINITIONS NAME DESCRIPTION
t
PdUdVo
t
PdUdAo
t
PdDo
t
PdHOeVo
t
PdLOeVo
t
SuCe
t
SuDi
Ce: CE
Ck: SCLK
Di: DIN
Do: DOUT
Ud: UPDATE
Vo: OUT_
Ao: AOUT
Rst: RESET
t
Oe: OUTPUT ENABLE
PdHOeVo
t
PdDo
t
MnHCk
DATA AND CONTROL TIMING
t
SuCe
t
t
MnLCk
t
HdUd
Hi-Z
t
PdUdAo
t
PdLOeVo
SuDi
t
MnLUd
t
PdUdVo
t
HdDi
t
WTrVo
t
SuUd
t
t
HdCe
PdRstVo
t
MnlRst
Hi-Z
Hold Time: Clock to Data In Min High Time: Clk Min Low Time: Clk Min Low Time: Update Setup Time: UPDATE to Clk with UPDATE High
Hold Time: Clk to UPDATE with UPDATE high
Asynchronous Delay: Data In to Data Out Min Low Time: MODE Max Rise Time: Clk, Update Min Low Time: Reset Delay: Reset to Video Output
Delay: Update to Video Out Delay: UPDATE to Aout Delay: Clk to Data Out Delay: Output Enable to Video Output (High: Disable) Delay: Output Enable to Video Output (Low: Enable) Setup: Clock Enable to Clock Setup Time: Data In to Clock
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
_______________________________________________________________________________________
9
Typical Operating Characteristics
(VCC= +5V and VEE= -5V, VDD= +5V, AGND = DGND = 0, V
IN_
= 0, RL= 150Ω to AGND, and TA = +25°C, unless otherwise
noted.)
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc01
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 150Ω
AV = +2V/V
AV = +1V/V
3
-7
0.1 1 10 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc02
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 150Ω
AV = +1V/V
AV = +2V/V
3
-7
0.1 1 10 100 1000
SMALL-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc03
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 150Ω
AV = +1V/V
AV = +2V/V
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc04
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 1kΩ
AV = +1V/V
AV = +2V/V
3
-7
0.1 1 10 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc05
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 1kΩ
AV = +2V/V
AV = +1V/V
3
-7
0.1 1 10 100 1000
SMALL-SIGNAL FREQUENCY RESPONSE
-5
MAX9675 toc06
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 1kΩ
AV = +1V/V
AV = +2V/V
0.3
-0.7
0.1 1 10 100 1000
LARGE-SIGNAL GAIN FLATNESS
vs. FREQUENCY
-0.5
MAX9675 toc07
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-0.3
-0.1
0.1
0
-0.2
-0.4
-0.6
0.2
AV = +1V/V
AV = +2V/V
RL = 150Ω
0.3
-0.7
0.1 1 10 100 1000
LARGE-SIGNAL GAIN FLATNESS
vs. FREQUENCY
-0.5
MAX9675 toc08
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-0.3
-0.1
0.1
0
-0.2
-0.4
-0.6
0.2
AV = +1V/V
AV = +2V/V
RL = 1kΩ
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
(A
V
= +1V/V)
-5
MAX9675 toc09
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 150Ω
CL = 30pF
CL = 15pF
CL = 45pF
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
10 ______________________________________________________________________________________
Typical Operating Characteristics—Dual Supplies ±5V (continued)
(VCC= +5V and VEE= -5V, VDD= +5V, AGND = DGND = 0, V
IN_
= 0, RL= 150Ω to AGND, and TA = +25°C, unless otherwise
noted.)
3
-7
0.1 1 10 100 1000
LARGE-SIGNAL FREQUENCY RESPONSE
(A
V
= +2V/V)
-5
MAX9675 toc10
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-3
-1
1
0
-2
-4
-6
2
RL = 150Ω
CL = 30pF
CL = 15pF
CL = 45pF
0.1 101 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
(A
V
= +1V/V)
MAX9675 toc11
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
-10
-5
5
0
10
15
CL = 45pF
CL = 15pF
CL = 30pF
7
-3
0.1 1 10 100 1000
MEDIUM-SIGNAL FREQUENCY RESPONSE
(A
V
= +2V/V)
-1
MAX9675 toc12
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
1
3
5
4
2
0
-2
6
CL = 15pF
CL = 45pF
CL = 30pF
-40
-100
0.1 10 1001 1000
MAX9675 toc13
FREQUENCY (MHz)
CROSSTALK (dB)
-90
-80
-70
-60
-50
CROSSTALK vs. FREQUENCY
AV = +1V/V
-40
-100
0.1 10 1001 1000
MAX9675 toc14
FREQUENCY (MHz)
CROSSTALK (dB)
-90
-80
-70
-60
-50
CROSSTALK vs. FREQUENCY
AV = +2V/V
-10
-100
0.1 100101
DISTORTION vs. FREQUENCY
-70
-90
-30
-50
0
-60
-80
-20
-40
MAX9675 toc15
FREQUENCY (MHz)
DISTORTION (dBc)
AV = +1V/V
2ND HARMONIC
3RD HARMONIC
-10
-100
0.1 100101
DISTORTION vs. FREQUENCY
-70
-90
-30
-50
0
-60
-80
-20
-40
MAX9675 toc16
FREQUENCY (MHz)
DISTORTION (dBc)
AV = +2V/V
2ND HARMONIC
3RD HARMONIC
0.1 101 100 1000
ENABLED OUTPUT IMPEDANCE
vs. FREQUENCY
MAX9675 toc17
FREQUENCY (MHz)
OUTPUT IMPEDANCE (Ω)
1000
-0.1
1
10
100
1M
1
100k 10M 100M1M 1G
MAX9675 toc18
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
10
100
1k
10k
100k
DISABLED OUTPUT IMPEDANCE
vs. FREQUENCY
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________
11
Typical Operating Characteristics—Dual Supplies ±5V (continued)
(VCC= +5V and VEE= -5V, VDD= +5V, AGND = DGND = 0, V
IN_
= 0, RL= 150Ω to AGND, and TA = +25°C, unless otherwise
noted.)
-40
-50
-60
-70
-80
-90
-100
-110
-120 100k 10M 100M1M 1G
MAX9675 toc19
FREQUENCY (Hz)
OFF-ISOLATION (dB)
OFF-ISOLATION vs. FREQUENCY
10k 1M100k 10M 100M
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX9675 toc20
FREQUENCY (Hz)
PSRR (dB)
-75
-70
-60
-65
-55
-50
1000
1
10 10k 100k 1M100 1k 10M
INPUT VOLTAGE NOISE vs. FREQUENCY
100
MAX9675 toc21
FREQUENCY (Hz)
VOLTAGE NOISE (nV/√Hz)
25ns/div
LARGE-SIGNAL PULSE RESPONSE
(A
V
= +1V/V)
INPUT 1V/div
OUTPUT
0.5V/div
MAX9675 toc22
25ns/div
LARGE-SIGNAL PULSE RESPONSE
(A
V
= +2V/V)
INPUT
0.5V/div
OUTPUT
0.5V/div
MAX9675 toc23
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE
(A
V
= +1V/V)
INPUT
100mV/div
OUTPUT
50mV/div
MAX9675 toc24
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE
(A
V
= +2V/V)
INPUT
50mV/div
OUTPUT
50mV/div
MAX9675 toc25
20ns/div
SWITCHING TIME
(A
V
= +1V/V)
V
UPDATE
5V/div
V
OUT
500mV/div
MAX9675 toc26
20ns/div
SWITCHING TIME
(A
V
= +2V/V)
V
UPDATE
5V/div
V
OUT
1V/div
MAX9675 toc27
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
12 ______________________________________________________________________________________
Typical Operating Characteristics—Dual Supplies ±5V (continued)
(VCC= +5V and VEE= -5V, VDD= +5V, AGND = DGND = 0, V
IN_
= 0, RL= 150Ω to AGND, and TA = +25°C, unless otherwise
noted.)
20ns/div
SWITCHING TRANSIENT (GLITCH)
(A
V
= +1V/V)
V
UPDATE
5V/div
V
OUT
25mV/div
MAX9675 toc28
20ns/div
SWITCHING TRANSIENT (GLITCH)
(A
V
= +2V/V)
V
UPDATE
5V/div
V
OUT
25mV/div
MAX9675 toc29
0
100
50
200
150
250
300
-15
-11
-9 -7-13 -5 -3 -1
1
3
5
OFFSET VOLTAGE DISTRIBUTION
MAX9675 toc30
OFFSET VOLTAGE (mV)
-0.05
0102030405060708090100
0102030405060708090100
DIFFERENTIAL GAIN AND PHASE
(R
L
= 150Ω)
0
0
-0.02
0.05
0.02
0.04
0.10
0.06
0.08
0.15
IRE
DIFFERENTIAL
PHASE (°)
DIFFERENTIAL
GAIN (%)
MAX9675 toc31
0.01 0
0102030405060708090100
0102030405060708090100
DIFFERENTIAL GAIN AND PHASE
(R
L
= 1kΩ)
-0.004
0.02
-0.002
0
0.002
0.004
0.03
IRE
DIFFERENTIAL
GAIN (%)
MAX9675 toc32
-0.01
DIFFERENTIAL
PHASE (°)
25ns/div
LARGE-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (C
L
= 30pF, AV = +1V/V)
INPUT 1V/div
OUTPUT
0.5/Vdiv
MAX9675 toc33
25ns/div
LARGE-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (C
L
= 30pF, AV = +2V/V)
INPUT
0.5V/div
OUTPUT
0.5V/div
MAX9675 toc34
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (C
L
= 30pF, AV = +1V/V)
INPUT
100mV/div
OUTPUT
50mV/div
MAX9675 toc35
25ns/div
MEDIUM-SIGNAL PULSE RESPONSE WITH
CAPACITIVE LOAD (C
L
= 30pF, AV = +2V/V)
INPUT
50mV/div
OUTPUT
50mV/div
MAX9675 toc36
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________
13
Typical Operating Characteristics—Dual Supplies ±5V (continued)
(VCC= +5V and VEE= -5V, VDD= +5V, AGND = DGND = 0, V
IN_
= 0, RL= 150Ω to AGND, and TA = +25°C, unless otherwise
noted.)
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
-50 0-25 255075100
GAIN vs. TEMPERATURE
MAX9675 toc37
TEMPERATURE (°C)
NORMALIZED GAIN (dB)
AV = +2V/V
AV = +1V/V
1p 10n 1
µ
100p10p 1n 100n 10µ100
µ
MAX9675 toc38
10n
10
µ
1
µ
100n
100
µ
1m
10m
100m
10
1
RESET DELAY (s)
C
RESET
(F)
RESET DELAY vs. RESET CAPACITANCE
SUPPLY CURRENT vs. TEMPERATURE
70
60
50
40
30
SUPPLY CURRENT (mA)
20
MAX9675 toc39
I
CC
I
EE
10
0
-50 0 25-25 50 75 100
I
DD
TEMPERATURE (°C)
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
14 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 3, 5, 7, 9, 11, 13, 15,
17, 19, 21, 23
2, 4, 6, 8, 10, 12, 14, 16,
45, 46, 82, 83, 84, 91,
93, 95, 97
IN4–IN15 Buffered Analog Inputs
AGND Analog Ground
18, 20, 22, 24 A3–A0
25, 47, 51, 55, 59, 63,
67, 71, 75, 81
26, 27, 38–44, 76, 77,
85–89, 99, 100
V
CC
N.C. No Connection. Not internally connected. Connect to AGND.
Address Programming Inputs. Connect to DGND or V Individual Output Address Mode (see Table 3).
Positive Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND. Connect a single 10µF capacitor from one V
CC
pin to AGND.
to select the address for
DD
28 DOUT
29 DGND Digital Ground
30
31 SCLK Serial-Clock Input
32
33 MODE
34
35
36 DIN Serial-Data Input. Data is clocked in on the falling edge of SCLK.
37
48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70,
72, 74, 78, 80
49, 53, 57, 61, 65, 69,
73, 79, 98
90, 92, 94, 96 IN0–IN3 Buffered Analog Inputs
AOUT
CE
RESET
UPDATE
V
DD
OUT15–OUT0
V
EE
Serial-Data Output. In Complete Matrix Mode, data is clocked through the 96-bit Matrix Control shift register. In Individual Output Address Mode, data at DIN passes directly to DOUT.
Address Recognition Output. AOUT drives low after successful chip address recognition.
Clock Enable Input. Drive low to enable the serial data interface.
Serial Interface Mode Select Input. Drive high for Complete Matrix Mode (Mode 1) or drive low for Individual Output Address Mode (Mode 0).
Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset. All matrix settings are set to power up defaults and all analog outputs are disabled. Additional power-on-reset delay may be set by connecting a small capacitor from
RESET to DGND.
Update Input. Drive UPDATE low to transfer data from mode registers to the switch matrix.
Digital Logic Supply. Bypass VDD with a 0.1µF capacitor to DGND.
Buffered Analog Outputs. Gain is individually programmable for A = +2V/V through the serial interface. Outputs may be individually disabled (high impedance). On power-up, or assertion of RESET, all outputs are disabled.
Negative Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND. Connect a single 10µF capacitor from one V
pin to AGND.
EE
= +1V/V or A
V
V
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________ 15
Detailed Description
The MAX9675 is a highly integrated 16 16 nonblock­ing video crosspoint switch matrix. All inputs and out­puts are buffered, with all outputs able to drive standard 75Ω reverse-terminated video loads.
A 3-wire interface programs the switch matrix and ini­tializes with a single update signal. The unique serial interface operates in one of two modes: Complete Matrix Mode (Mode 1) or Individual Output Address Mode (Mode 0).
In the
Functional Diagram,
the signal path of the MAX9675 is from the inputs (IN0–IN15), through the switching matrix, buffered by the output amplifiers, and presented at the output terminals (OUT0–OUT15). The other functional blocks are the serial interface and con­trol logic. Each of the functional blocks is described in detail below.
Analog Outputs
The MAX9675 outputs are high-speed voltage feedback amplifiers capable of driving 150Ω (75Ω back-terminat­ed) loads. The gain, AV= +1V/V or +2V/V, is selectable through programming bit 4 of the serial control word.
Amplifier compensation is automatically optimized to maximize the bandwidth for each gain selection. Each output can be individually enabled and disabled through bit 5 of the serial control word. When disabled, the out­put is high impedance, presenting typically a 4kΩ load, and 3pF output capacitance, allowing multiple outputs to be connected together in building large arrays. On power-up (or asynchronous RESET), all outputs are ini­tialized in the disabled state to avoid output conflicts in large-array configurations. The programming and opera­tion of the MAX9675 is output referred. Outputs are con­figured individually to connect to any one of the 16 analog inputs, programmed to the desired gain (A
V
=
+1V/V or +2V/V), or disabled in a high-impedance state.
Analog Inputs
The MAX9675 offers 16 analog input channels. Each input is buffered before the crosspoint switch matrix, allowing one input to cross-connect to up to 16 outputs. The input buffers are voltage feedback amplifiers with high-input impedance and low-input bias current. This allows the use of very simple input clamp circuits.
Functional Diagram
RESET
SCLK
UPDATE
IN0
IN1
IN2
IN15
DIN
CE
MAX9675
POWER-ON
RESET
DISABLE ALL OUTPUTS
SERIAL
INTERFACE
A0–A3 MODE
*AV = +1V/V OR +2V/V
SWITCH MATRIX
THERMAL
SHUTDOWN
DECODE LOGIC
MATRIX REGISTER
UPDATE REGISTER
16 x 16
256
LATCHES
96 BITS
16 BITS
AV*
A
*
V
*
A
V
AV*
16
16
OUT0
OUT1
OUT2
ENABLE/DISABLE
OUT15
V V
AGND
V
DGND
DOUT
AOUT
CC
EE
DD
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
16 ______________________________________________________________________________________
Switch Matrix
The MAX9675 has 256 individual T-switches making a 16 x 16 switch matrix. The switching matrix is 100% nonblocking, which means that any input may be rout­ed to any output. The switch matrix programming is output referred. Each output may be connected to any one of the 16 analog inputs. Any one input can be rout­ed to all 16 outputs with no signal degradation.
Digital Interface
The digital interface consists of the following pins: DIN, DOUT, SCLK, AOUT, UPDATE, CE, A3–A0, MODE, and RESET. DIN is the serial-data input; DOUT is the serial­data output. SCLK is the serial-data clock that clocks data into the Data Input registers (Figure 2). Data at DIN is loaded at each falling edge of SCLK. DOUT is the data shifted out of the 96-bit Complete Matrix Mode (Mode = 1). DIN passes directly to DOUT when in Individual Output Address Mode (Mode = 0).
The falling edge of UPDATE latches the data and pro­grams the matrix. When using Individual Output Address Mode, the address recognition output AOUT drives low when control word bits D13 to D10 match the address programming inputs (A3–A0) and UPDATE is low. Table 1 is the operation truth table.
Programming the Matrix
The MAX9675 offers two programming modes: Individual Output Address Mode and Complete Matrix Mode. These two distinct programming modes are selected by toggling a single MODE pin high or low. Both modes operate with the same physical board lay­out. This flexibility allows initial programming of the IC by daisy-chaining and sending one long data word while still being able to address immediately and update individual outputs in the matrix.
Individual Output Address Mode (MODE = 0)
Drive MODE to logic-low to select mode 0. Individual outputs are programmed through the serial interface
Table 1. Operation Truth Table
CE UPDATE SCLK DIN DOUT MODE AOUT RESET OPERATION/COMMENTS
1 X X X X X X 1 No change in logic.
01↓ D
D
i
i-96
11 1
00XXX11 1
01↓ D
i
D
i
01 1
Data at DIN is clocked on the negative edge of the SCLK into the 96-bit Complete Matrix Mode register. DOUT supplies original data in 96 SCLK pulses later.
Data in the serial 96-bit Complete Matrix Mode register is transferred into parallel latches that control the switching matrix.
Data at DIN is routed to the Individual Output Address Mode shift register. DIN is also connected directly to DOUT so that all devices on the serial bus may be addressed in parallel.
00XDiD
X X XXXXX 0
i
00 1
The 4-bit chip address A compared to D remaining 10 bits in the Individual Output Address Mode register are decoded, allowing reprogramming for a single output. AOUT signals a successful individual matrix update.
Asynchronous reset. All outputs are disabled. Other logic remains unchanged.
to D10. If equal, the
13
to A0 is
3
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________ 17
with a single 16-bit control word. The control word con­sists of two don’t care MSBs, the chip address bits, out­put address bits, an output enable/disable bit, an output gain-set bit, and input address bits (Tables 2 through 6, and Figure 2).
In mode 0, data at DIN passes directly to DOUT through the data routing gate (Figure 3). In this configu­ration, the 16-bit control word is simultaneously sent to all chips in an array of up to 16 addresses.
Complete Matrix Mode (MODE = 1)
Drive MODE to logic-high to select mode 1. A single 96-bit control word consisting of sixteen 6-bit control words programs all outputs. The 96-bit control word’s
first 6-bit control word (MSBs) programs output 15, and the last 6-bit control word (LSBs) programs output 0 (Table 7 and Figures 4 and 5). Data clocked into the 96-bit Complete Matrix Mode register is latched on the falling edge of UPDATE, and the outputs are immedi­ately updated.
Initialization String
The Complete Matrix Mode (Mode = 1) is convenient to use to program the matrix at power-up. In a large matrix consisting of many MAX9675 devices, all the devices can be programmed by sending a single bit stream equal to n x 96 bits, where n is the number of MAX9675 devices on the bus. The first 96-bit data word programs the last MAX9675 in line (see the
Matrix
Programming
section)
.
Table 2. 16-Bit Serial Control Word Bit Assignments (Mode 0: Individual Output Address Mode)
Table 3. Chip Address Programming for 16-Bit Control Word (Mode 0: Individual Output Address Mode)
BIT NAME FUNCTION
0
(LSB)
10 IC Address A0
11 IC Address A1
12 IC Address A2
13 IC Address A3
14 X Don’t care
15
(MSB)
Input Address 0
1 Input Address 1
2 Input Address 2
3 Input Address 3
4 Gain Set
5 Output Enable
6 Output Address B0
7 Output Address B1
8 Output Address B2
9 Output Address B3
X Don’t care
LSB of input channel
select address
MSB of input channel
select address
Gain Select for output
buffer, 0 = gain of +1V/V,
1 = gain of +2V/V
Enable bit for output,
0 = disable, 1 = enable
LSB of output buffer
address
MSB of output buffer
address
LSB of selected chip
address
MSB of selected chip
address
IC ADDRESS BIT ADDRESS
A3
(MSB) A2 A1A0(LSB)
0 0 0 0 0h 0
0 0 0 1 1h 1
0 0 1 0 2h 2
0 0 1 1 3h 3
0 1 0 0 4h 4
0 1 0 1 5h 5
0 1 1 0 6h 6
0 1 1 1 7h 7
1 0 0 0 8h 8
1 0 0 1 9h 9
1 0 1 0 Ah 10
1 0 1 1 Bh 11
1 1 0 0 Ch 12
1 1 0 1 Dh 13
1 1 1 0 Eh 14
1 1 1 1 Fh 15
CHIP
ADDRESS
(HEX)
CHIP
ADDRESS
(DECIMAL)
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
18 ______________________________________________________________________________________
Figure 2. Mode 0: Individual Output Address Mode Timing and Programming Example
Table 4. Chip Address A3–A0 Pin Programming
Table 5. Output Selection Programming
16-BIT INDIVIDUAL OUTPUT ADDRESS MODE:
UPDATE
MODE
SCLK
FIRST 2 BITS ARE DON'T CARE BITS, LAST 14 BITS CLOCKED INTO DIN WHEN MODE = 0 CREATE ADDRESS WORD; IC ADDRESS A3–A0 IS COMPARED TO DIN EQUAL, ADDRESSED OUTPUT IS UPDATED.
t
SuMd
–DIN10 WHEN UPDATE IS LOW; IF
13
DIN
DON'T CARE X
DON'T CARE X
IC ADDRESS A3
IC ADDRESS A2
IC ADDRESS A1
IC ADDRESS A0
OUTPUT ADDRESS B3
OUTPUT ADDRESS B2
OUTPUT ADDRESS B1
OUTPUT ADDRESS B0
GAIN SET = +1V/V
OUTPUT ENABLED
t
HdMd
INPUT ADDRESS 2 = 1
INPUT ADDRESS 1 = 0
INPUT ADDRESS 3 (MSB) = 1
INPUT ADDRESS 0 (LSB) = 0
IC ADDRESS = 5 OUTPUT ADDRESS = 3 OUTPUT (i) ENABLED, AV = +1V/V,
EXAMPLE OF 16-BIT SERIAL CONTROL WORD FOR OUTPUT CONTROL IN INDIVIDUAL OUTPUT ADDRESS MODE
CONNECTED TO INPUT 12
PIN ADDRESS
C H IP
A3 A2 A1 A0
D GND D GND D GND D GND 0h 0
D GND D GND D GND V
D GND D GND V
D GND D GND V
D GND V
D GND V
D GND V
D GND V
V
V
V
V
V
V
V
V
D GND D GND D GND 8h 8
D D
D GND D GND V
D D
D GND V
D D
D GND V
D D
D D
D D
D D
D D
V
V
V
V
D GND D GND 4h 4
D D
D GND V
D D
D D
D D
D D
D D
D D
D D
V
V
D GND D GND Ch 12
D GND V
V
V
D GND 2h 2
D D
D D
D GND 6h 6
D D
D D
D GND Ah 10
D D
D D
D GND Eh 14
D D
D D
V
V
V
V
D D
D D
D D
D D
D D
D D
D D
D D
A D DR ESS
( H EX)
1h 1
3h 3
5h 5
7h 7
9h 9
Bh 11
Dh 13
Fh 15
C H IP
A D DR ESS
( D EC IM AL )
OUTPUT ADDRESS BIT
B3
(MSB)
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
B2 B1
B0
(LSB)
SELECTED
OUTPUT
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________ 19
Figure 3. Serial Interface Block Diagram
Table 6. Input Selection Programming
Table 7. 6-Bit Serial Control Word Bit Assignments (Mode 1: Complete Matrix Mode)
SCLK
CE
MODE
SCLK
CE
MODE
DIN
4
A0–A3
CHIP ADDRESS
16-BIT INDIVIDUAL OUTPUT ADDRESS
MODE REGISTER
OUTPUT ADDRESS DECODE
UPDATE
EN
4
10
96-BIT COMPLETE MATRIX MODE REGISTER
10
7
7
96-BIT PARALLEL LATCH
96
SWITCH DECODE
256
SWITCH MATRIX OUTPUT ENABLE
MODE
MODE
S
A
DATA
DOUT
ROUTING
GATE
B
96
MODE
1
AOUT
96
16
INPUT ADDRESS BIT
B3
(MSB)
B2 B1
B0
(LSB)
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
SELECTED
INPUT
BIT NAME FUNCTION
5 (MSB)
4
3
2
1
0 (LSB)
Output Enable
Gain
Set
Input
Address 3
Input
Address 2
Input
Address 1
Input
Address 0
Enable bit for output, 0 = disable, 1 = enable
Gain Select for output buffer, 0 = gain of +1V/V, 1 = gain of +2V/V
MSB of input channel select address
LSB of input channel select address
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
20 ______________________________________________________________________________________
Figure 5. Mode 1: Complete Matrix Mode Programming
Figure 4. 6-Bit Control Word and Programming Example (Mode 1: Complete Matrix Mode Programming)
SCLK
DIN
UPDATE
DOUT
EXAMPLE OF 6-BIT SERIAL CONTROL WORD FOR OUTPUT CONTROL
16 x 16 CROSSPOINT = 6-BIT CONTROL WORD
t
SuDitHdDi
t
PdDo
SCLK
DIN
t
MnLCk
t
MnHCk
OUTPUT ENABLED
GAIN SET = +1V/V
INPUT ADDRESS 3 (MSB) = 1
OUTPUT (i) ENABLED, AV = +1V/V,
CONNECTED TO INPUT 14
INPUT ADDRESS 2 = 1
INPUT ADDRESS 1 = 1
t
SuHUd
t
MnLUd
NEXT CONTROL WORD
INPUT ADDRESS 0 (LSB) = 0
UPDATE 1
MODE 1
6-BIT CONTROL WORD
DIN
OUT0OUT1OUT2
MOST-SIGNIFICANT OUTPUT BUFFER CONTROL BITS ARE SHIFTED IN FIRST, I.E., OUT15, THEN OUT14, ETC. LAST 6 BITS SHIFTED IN PRIOR TO UPDATE NEGATIVE EDGE PROGRAM OUT0.
0
0
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________ 21
RESET
The MAX9675 features an asynchronous bidirectional RESET with an internal 20kΩ pullup resistor to V
DD
.
When RESET is pulled low, either by internal circuitry, or driven externally, the analog output buffers are latched into a high-impedance state. After RESET is released, the output buffers remain disabled. The out­puts may be enabled by sending a new 96-bit data word or a 16-bit individual output address word. A reset is initiated from any of three sources. RESET can be driven low by external circuitry to initiate a reset, or RESET can be pulled low by internal circuitry during power-up (power-on reset) or thermal shutdown.
Since driving RESET low only clears the output buffer enable bit in the matrix control latches, RESET can be used to disable all outputs simultaneously. If no new data has been loaded into the 96-bit complete matrix mode register, a single UPDATE restores the previous matrix control settings.
Power-On Reset
The power-on reset ensures all output buffers are in a disabled state when power is initially applied. A V
DD
voltage comparator generates the power-on reset. When the voltage at VDDis less than 2.5V, the power­on-reset comparator pulls RESET low through internal circuitry. As the digital supply voltage ramps up cross­ing 2.5V, the MAX9675 holds RESET low for 40ns (typ). Connecting a small capacitor from RESET to DGND extends the power-on-reset delay. See the RESET Delay vs. RESET Capacitance graph in the
Typical
Operating Characteristics.
Thermal Shutdown
The MAX9675 features thermal shutdown protection with temperature hysteresis. When the die temperature exceeds +150°C, the MAX9675 pulls RESET low, dis­abling the output buffers. When the die cools by 20°C, the RESET pulldown is deasserted, and output buffers remain disabled until the device is programmed again.
Applications Information
Building Large Video-Switching Systems
The MAX9675 can be easily used to create larger switching matrices. The number of ICs required to implement the matrix is a function of the number of input channels, the number of outputs required, and whether the array needs to be nonblocking. The most straightforward technique for implementing nonblock­ing matrices is to arrange the building blocks in a grid. The inputs connect to each vertical bank of devices in parallel with the other banks. The outputs of each build­ing block in a vertical column connect together in a
wired-OR configuration. Figure 6 shows a 128-input, 32-output, nonblocking array using the MAX9675 16 x 16 crosspoint devices.
The wired-OR connection of the outputs shown in the diagram is possible because the outputs of the IC devices can be placed in a disabled or high-imped­ance output state. This disable state of the output buffers is designed for a maximum impedance vs. fre­quency while maintaining a low-output capacitance. These characteristics minimize the adverse loading effects from the disabled outputs. Larger arrays are constructed by extending this connection technique to more devices.
Driving a Capacitive Load
Figure 6 shows an implementation requiring many out­puts to be wired together. This creates a situation where each output buffer sees not only the normal load impedance, but also the disabled impedance of all the other outputs. This impedance has a resistive and a capacitive component. The resistive components reduce the total effective load for the driving output. Total capacitance is the sum of the capacitance of all the disabled outputs and is a function of the size of the matrix. Also, as the size of the matrix increases, the length of the PCB traces increases, adding more capacitance. The output buffers have been designed to drive more than 30pF of capacitance while still main­taining a good AC response. Depending on the size of the array, the capacitance seen by the output can exceed this amount. There are several ways to improve the situation. The first is to use more building-block crosspoint devices to reduce the number of outputs that need to be wired together (Figure 7).
In Figure 7, the additional devices are placed in a sec­ond bank to multiplex the signals. This reduces the number of wired-OR connections. Another solution is to put a small resistor in series with the output before the capacitive load to limit excessive ringing and oscilla­tions. Figure 8 shows the graph of the Optimal Isolation Resistor vs. Capacitive Load. A lowpass filter is created from the series resistor and parasitic capacitance to ground. A single R-C does not affect the performance at video frequencies, but in a very large system there may be many R-Cs cascaded in series. The cumulative effect is a slight rolling off of the high frequencies caus­ing a "softening" of the picture. There are two solutions to achieve higher performance. One way is to design the PCB traces associated with the outputs such that they exhibit some inductance. By routing the traces in a repeating "S" configuration, the traces that are nearest each other exhibit a mutual inductance increasing the total inductance. This series inductance causes the
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
22 ______________________________________________________________________________________
amplitude response to increase or peak at higher fre­quencies, offsetting the rolloff from the parasitic capaci­tance. Another solution is to add a small-value inductor to the output.
Crosstalk Signal and Board Routing Issues
Improper signal routing causes performance problems such as crosstalk. The MAX9675 has a typical crosstalk rejection of -62dB at 6MHz. A bad PCB layout degrades the crosstalk rejection by 20dB or more. To achieve the best crosstalk performance:
1) Place ground isolation between long critical sig-
nal PCB trace runs. These traces act as a shield to potential interfering signals. Crosstalk can be degraded by parallel traces as well as directly above and below on adjoining PCB layers.
2) Maintain controlled-impedance traces. Design as
many of the PCB traces as possible to be 75Ω trans­mission lines. This lowers the impedance of the traces, reducing a potential source of crosstalk. More power is dissipated due to the output buffer driving a lower impedance.
3) Minimize ground-current interaction by using a
good ground plane strategy.
In addition to crosstalk, another key issue of concern is isolation. Isolation is the rejection of undesirable feed­through from input to output with the output disabled. The MAX9675 achieves a -110dB isolation at 6MHz by selecting the pinout configuration such that the inputs and outputs are on opposite sides of the package.
Coupling through the power supply is a function of the quality and location of the supply bypassing. Use appropriate low-impedance components and locate them as close as possible to the IC. Avoid routing the inputs near the outputs.
Power-Supply Bypassing
The MAX9675 operates from a ±5V supply. For dual­supply operation, bypass all supply pins to ground with
0.1µF capacitors.
Figure 7. 64 x 16 Nonblocking Matrix with Reduced Capacitive Loading
Figure 6. 128 x 32 Nonblocking Matrix Using 16 x 16 Crosspoint Devices
IN (0–15)
IN (16–31)
IN (32–47)
IN (48–63)
16 IN
16 IN
16 IN
16 IN
16
MAX9675
OUT
16
MAX9675
OUT
16
MAX9675
OUT
16
MAX9675
OUT
OUTPUTS (0–15) OUTPUTS (16–32)
16 IN
16 IN
16 IN
16 IN
MAX9675
MAX9675
MAX9675
MAX9675
OUT
OUT
OUT
OUT
16
16
16
16
IN (64–79)
IN (80–95)
IN (96–111)
IN (112–127)
IN (0–15)
IN (16–31)
IN (32–47)
IN (48–63)
16 IN
16 IN
16 IN
16 IN
MAX9675
MAX9675
MAX9675
MAX9675
16 IN
16 IN
16 IN
16 IN
16
OUT
16
OUT
16
OUT
16
OUT
MAX9675
MAX9675
MAX9675
MAX9675
OUT
OUT
OUT
OUT
16 IN
16
MAX9675
IN
16
MAX9675
IN
16 IN
16
16
16
16
MAX9675
MAX9675
16
MAX9675
IN
16
MAX9675
IN
OUT
OUT
OUT
OUT
16
16
16
16
16
OUT
OUTPUTS (0–15)
16
OUT
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________ 23
Driving a PCB Interconnect or a Cable
(A
V
= +1V/V or +2V/V)
The MAX9675 output buffers can be programmed to either AV= +1V/V or +2V/V. The +1V/V configuration is typically used when driving a short-length (less than 3cm), high-impedance “local” PCB trace. To drive a cable or a 75Ω transmission line trace, program the gain of the output buffer to +2V/V and place a 75Ω resistor in series with the output. The series termination resistor and the 75Ω load impedance act as a voltage­divider that divides the video signal in half. Set the gain to +2V/V to transmit a standard 1V video signal down a cable. The series 75Ω resistor is called the back-match, reverse termination, or series termination. This 75Ω resistor reduces reflections, and provides isolation, increasing the output-capacitive-driving capability.
Matrix Programming
The MAX9675’s unique digital interface simplifies pro­gramming multiple MAX9675 devices in an array. Multiple devices are connected with DOUT of the first device connecting to DIN of the second device, and so on (Figure 9). Two distinct programming modes, indi­vidual output address mode (MODE = 0) and complete matrix mode (MODE = 1), are selected by toggling a single MODE control pin high or low. Both modes oper­ate with the same physical board layout. This allows ini­tial programming of the IC by daisy-chaining and sending one long data word while still being able to address immediately and update individual locations in the matrix.
Individual Output Address Mode (Mode 0)
In Individual Output Address Mode, the devices are connected in a serial bus configuration, with the data routing gate (Figure 3) connecting DIN to DOUT, mak­ing each device a virtual node on the serial bus. A sin­gle 16-bit control word is sent to all devices simultaneously. Only the device with the corresponding chip address responds to the programming word, and updates its output. In this mode, the chip address is set through hardware pin strapping of A3–A0. The host then communicates with the device by sending a 16-bit word consisting of 2 don’t care MSB bits, 4 chip address bits, and 10 bits of data to make the word
exactly 2 bytes in length. The 10 data bits are broken down into 4 bits to select the output to be programmed; 1 bit to set the output enable; 1 bit to set gain; and 4 bits to select the input to be connected to that output. In this method, the matrix is programmed one output at a time.
Complete Matrix Mode (Mode 1)
In Complete Matrix Mode, the devices are connected in a daisy-chain fashion where n x 96 bits are sent to pro­gram the entire matrix, and where n = the number of MAX9675 devices connected in series. This long data word is structured such that the first bit is the LSB of the last device in the chain and the last data bit is the MSB of the first device in the chain. The total length of the data word is equal to the number of crosspoint devices to be programmed in series times 96 bits per crosspoint device. This programming method is most often used at startup to initially configure the switching matrix.
Figure 8. Optimal Isolation Resistor vs. Capacitive Load
OPTIMAL ISOLATION RESISTANCE
vs. CAPACITIVE LOAD
30
25
20
15
10
ISOLATION RESISTANCE (Ω)
5
0
0 500
200100 300 400
CAPACITIVE LOAD (pF)
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
24 ______________________________________________________________________________________
Figure 9. Matrix Mode Programming
Chip Information
TRANSISTOR COUNT: 24,467
PROCESS: BiCMOS
HOST
CONTROLLER
CHIP ADDRESS = 0 CHIP ADDRESS = 1
DIN
MAX9675
SCLK
CE
MODE
UPDATE
DOUT
A3
A2
A1
A0
VIRTUAL SERIAL BUS (MODE 0: INDIVIDUAL OUTPUT ADDRESS MODE)
DIN
MAX9675
SCLK
CE
MODE
UPDATE
DOUT
A3
A2
A1
A0
CHIP ADDRESS = 2
DOUT NEXT DEVICE
DIN
MAX9675
SCLK
V
DD
CE
MODE
UPDATE
A3
V
A2
A1
A0
DD
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
______________________________________________________________________________________ 25
Pin Configuration
TOP VIEW
IN4
AGND
IN5
AGND
IN6
AGND
IN7
AGND
IN8
AGND
IN9
AGND
IN10
AGND
IN11
AGND
IN12
IN13
IN14
IN15
V
N.C.
N.C.
VEEAGND
IN3
AGND
IN2
AGND
IN1
AGND
IN0
N.C.
N.C.
N.C.
N.C.
N.C.
AGND
AGND
AGND
VCCOUT0
VEEOUT1
N.C.
N.C.
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
100
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A3
18
19
A2
20
21
A1
22
23
A0
24
25
CC
MAX9675
76
75
V
CC
74
OUT2
73
V
EE
72
OUT3
71
V
CC
70
OUT4
69
V
EE
68
OUT5
67
V
CC
66
OUT6
65
V
EE
64
OUT7
63
V
CC
62
OUT8
61
V
EE
60
OUT9
59
V
CC
58
OUT10
57
V
EE
56
OUT11
55
V
CC
54
OUT12
53
V
EE
52
OUT13
51
V
CC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
OUT15
50
EE
V
OUT14
26
N.C.
27
N.C.
28
DOUT
29
DGND
30
AOUT
SCLK
CE
MODE
RESET
UPDATE
DIN
DD
V
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AGND
AGND
CC
V
TQFP
MAX9675
Video Crosspoint Switch 110MHz, 16 x 16 Programmable Gain
26 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE OUTLINE 100L TQFP, 14x14x1.0mm
21-0085
100L,TQFP.EPS
1
B
2
MAX9675
Video Crosspoint Switch 110MHz,
16 x 16 Programmable Gain
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
27
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
100 TQFP C100-1
21-0085
PACKAGE OUTLINE, 100L TQFP, 14x14x1.0mm
21-0085
2
B
2
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