19-5199; Rev 1; 1/11
EVALUATION KIT
AVAILABLE
Dual 36V Op Amp for 18-Bit
General Description
The MAX9633 is a low-noise, low-distortion operational
amplifier that is optimized to drive ADCs for use in applications from DC to a few MHz. The MAX9633 features
low noise (3nV/√Hz at 1kHz and 3.5nV/√Hz at 100Hz)
and low distortion (130dB at 10kHz), making it suitable
for industrial, medical, and test applications.
The exceptionally fast settling-time and low input offset
voltage makes the IC an excellent solution to drive highresolution 12-bit to 18-bit SAR ADCs.
The IC operates from a wide supply voltage range up to
36V with only 3.5mA of quiescent current per amplifier.
The IC is offered in an 8-pin, 3mm x 3mm TDFN package
for operation over the -40NC to +125NC temperature range.
Applications
ADC Drivers
Data Acquisition and Instrumentation
Power Grid Systems
Motor Control
Test and Measurement Equipments
Imaging Systems
High-Performance Audio Circuitry
SAR ADC Front-End
Features
S Low-Noise (3nV/√Hz at 1kHz) and Low-Distortion
(130dB at 10kHz) ADC Driver
S Very Fast 750ns Settling Time to 16-Bit Accuracy
S Low Input Voltage Offset 200µV (max)
S Low 0.9µV/°C Input Offset Temperature Coefficient
S Gain-Bandwidth Product 27MHz
S 4.5V to 36V Wide Supply Range
S Unity Gain Stable
S ±6kV ESD Protection HBM
S 8-Pin TDFN and SOIC Packages
Ordering Information
PART TEMP RANGE
MAX9633ASA+
MAX9633ATA+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
-40NC to +125NC
-40NC to +125NC
PINPACKAGE
8 SO-EP* —
8 TDFN-EP* BMM
TOP
MARK
MAX9633
Typical Application Circuit
R1
MAX9633
R2
+15V
-15V
-3dB AT 8MHz
R
= 20I
I
C = 1nF
12 TO 18-BIT SAR ADC
EXAMPLE: MAX1320
14-BIT ADC
ANTI-ALIAS FILTER
IN
R R
C
_______________________________________________________________ Maxim Integrated Products 1
C
1MI
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC to VEE).................................-0.3V to +40V
All Other Pins ..................................(V
Short-Circuit Duration of OUTA, OUTB ................................. 10s
Continuous Input Current (any pins) ............................... ±20mA
Continuous Power Dissipation (T
SO (derate 24.4mW/NC above +70NC)
Multilayer Board .....................................................1951.2mW
- 0.3V) to (VCC + 0.3V)
EE
= +70NC)
A
TDFN (derate 24.4mW/NC above +70NC)
Multilayer Board ........................................................1905mW
Operating Temperature Range ........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
MAX9633
PACKAGE THERMAL CHARACTERISTICS (Note 1)
SO-EP
Junction-to-Ambient Thermal Resistance (q
Junction-to-Case Thermal Resistance (q
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
) ..........41°C/W
JA
) .................7°C/W
JC
ELECTRICAL CHARACTERISTICS
(VCC = +15V, VEE = -15V, VCM = 0V, RL = 10kI to V
T
= +25NC.) (Note 2)
A
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Supply Voltage Rang
Supply Current I
Power-Supply Rejection Ratio PSRR
DC SPECIFICATIONS
Input Offset Voltage V
Input Offset Voltage Drift
(Note 3)
Input Bias Current I
Input Offset Current I
Input Voltage Range V
Common-Mode Rejection Ratio CMRR
e
VCC - VEEGuaranteed by PSRR 4.5 36 V
CC
OS
DV
OS
IN+
Per amplifier
+4.5V P (V
P +36V
TA = +25NC Q70 Q200
-40NC P T
-40NC P TA P +125NC
OS
(VEE + 0.45V) P VCM P (VCC - 1.8V) Q42 Q400
B
V
EE
(VEE + 0.45V) P VCM P (VCC - 1.8V) Q30 Q300
V
EE
, V
Guaranteed by CMRR
IN-
V
EE
V
EE
+125NC
= 0V, TA = T
GND
CC
P +125NC Q290
A
P VCM P (VCC - 1.8V)
P VCM P (VCC - 1.8V) Q200 Q2000
P VCM P (VCC - 1.7V), TA = +25NC
P VCM P (VCC - 1.8V), -40NC P TA P
- VEE)
TDFN-EP
Junction-to-Ambient Thermal Resistance (q
Junction-to-Case Thermal Resistance (q
to T
MIN
= +25NC
T
A
-40NC P T
-40NC P T
T
= +25NC
A
-40NC P T
T
A
-40NC P T
+125NC
, unless otherwise noted. Typical values are at
MAX
3.5 5
P +85NC
A
P +125NC
A
112 135
P +125NC
A
= +25NC
A
P
110
0.2 0.9
4.5 22
V
EE
V
EE
106 130
105 130
) ..........42°C/W
JA
) .................8°C/W
JC
6
6.5
VCC -
1.7
VCC -
1.8
mA
dB
FV
FV/NC
nA
FA
nA
V
dB
2
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +15V, VEE = -15V, VCM = 0V, RL = 10kI to V
T
= +25NC.) (Note 2)
A
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Open-Loop Gain A
V
VOL
OH
(VEE + 0.3V) P V
(V
VCC - V
Output Voltage Swing
Short-Circuit Current I
V
OL
SC
V
OUT
TA = +25NC
AC SPECIFICATIONS
Gain Bandwidth GBWP 27 MHz
Slew Rate SR
Output Transient Recovery Time t
TR
Settling Time t
Total Harmonic Distortion THD
5V step, R
To 0.001%, DV
= 1nF, AV = +1V/V
To 0.001%, 5V step,
S
AV = -1V/V
V
OUT
20I, C
+1V/V
V
Crosstalk
Input Voltage Noise Density e
Input Voltage Noise
Input Current Noise Density i
Capacitive Loading C
n
n
L
OUT
20I, C
f = 100Hz 3.5
f = 1kHz 3
0.1Hz P f P 10Hz
f = 100Hz 12
f = 1kHz 10
No sustained oscillation, AV = +1V/V 50 pF
Note 2: All devices are 100% production tested at T
Note 3: Guaranteed by design.
GND
+ 0.45V) P V
EE
OUT
= 0V, TA = T
P (VCC - 2V), RL = 10kI
OUT
OUT
MIN
to T
, unless otherwise noted. Typical values are at
MAX
P (VCC - 2.1V), RL = 1kI
RL = 10kI
R
= 1kI
L
118 140
115 138
RL = 10kI
R
= 1kI
- V
EE
= 20I, CL = 1nF, AV = 1V/V
S
= 200mV, RS = 20I, CL
OUT
L
R
= 10kI to V
L
R
= 1kI to V
L
= 100I, CL =
R
S
EE
EE
30pF
R
= 20I, CL =
S
1nF
= 10V
P-P
= 1nF, AV =
L
, RS =
f = 1kHz 145
f = 100kHz -100
= 10V
L
= +25NC. Temperature limits are guaranteed by design.
A
P-P
= 1nF
, RS =
f = 1kHz -100
f = 10kHz -90
1.6 1.9
1.7 2.0
70 150
170 300
20 100
20 100
50 mA
18
V/Fs
500 ns
750
750
nV/√Hz
250 nV
pA/√Hz
MAX9633
dB
V
mV
ns
dBf = 10kHz 130
dB
P-P
3
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Typical Operating Characteristics
(VCC = +15V, VEE = -15V, VCM = 0V, outputs have RL = 10kI connected to V
otherwise noted.)
= 0V. Typical values are at TA = +25NC, unless
GND
50
45
MAX9633
40
35
30
25
20
OCCURRENCES (%)
15
10
5
0
-180
INPUT OFFSET VOLTAGE
vs. INPUT COMMON MODE
60
55
50
TA = +85°C
VOS HISTOGRAM
45
(µV)
40
OS
V
35
30
25
20
-15 15
TA = +25°C
TA = -40°C
INPUT COMMON MODE (V)
VOS (µV)
TA = +125°C
TA = 0°C
50
45
180100 140-100 -60 -20 20 60-140
MAX9633 toc01
40
35
30
25
20
FREQUENCY (%)
15
10
5
0
-0.5
VOS DRIFT (µV/°C)
MAX9633 toc02
0.50.40.2 0.3-0.3 -0.2 -0.1 0 0.1-0.4
INPUT OFFSET VOLTAGE
vs. SUPPLY VOLTAGE
60
VOS DRIFT HISTOGRAM
55
MAX9633 toc04
50
45
(µV)
40
OS
V
35
TA = -40°C
30
25
105-10 -5 0
20
0 40
TA = +125°C
TA = +85°C
TA = +25°C
TA = 0°C
SUPPLY VOLTAGE (V)
MAX9633 toc05
302010
SUPPLY CURRENT vs. SUPPLY VOLTAGE
6
5
4
3
2
SUPPLY CURRENT (mA)
1
0
TA = +85°C
TA = +25°C
TA = -40°C
0 40
SUPPLY VOLTAGE (V)
TA = +125°C
TA = 0°C
BIAS CURRENT
vs. INPUT COMMON MODE
50
48
46
44
42
40
38
BIAS CURRENT (nA)
36
34
32
30
-15 15
INPUT COMMON MODE (V)
TA = +125°C
TA = +85°C
TA = +25°C
TA = 0°C
TA = -40°C
MAX9633 toc03
3530252015105
MAX9633 toc06
1050-5-10
BIAS CURRENT vs. SUPPLY VOLTAGE
50
48
46
44
42
40
38
BIAS CURRENT (nA)
36
34
32
30
4
TA = +125°C
TA = +85°C
TA = -40°C
SUPPLY VOLTAGE (V)
TA = +25°C
TA = 0°C
3020 2510 1550 40
35
MAX9633 toc07
DC COMMON-MODE REJECTION RATIO
vs. TEMPERATURE
0
-20
-40
-60
-80
CMRR (dB)
-100
-120
-140
-160
TEMPERATURE (°C)
120100-40 -20 0 40 6020 80-60 140
MAX9633 toc08
DC PSRR vs. TEMPERTURE
0
-20
-40
-60
PSRR (dB)
-80
-100
-120
-140
-50 125
TEMPERATURE (°C)
MAX9633 toc09
1007525 500-25
Dual 36V Op Amp for 18-Bit
0
SAR ADC Front-End
Typical Operating Characteristics (continued)
(VCC = +15V, VEE = -15V, VCM = 0V, outputs have RL = 10kI connected to V
otherwise noted.)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
0
-20
-40
-60
CMRR (dB)
-80
-100
-120
0.1 100,000
FREQUENCY (kHz)
SMALL-SIGNAL UNITY GAIN
vs. FREQUENCY
20
15
10
5
0
GAIN (dB)
-5
-10
-15
-20
10 100,000
FREQUENCY (kHz)
10,0001000100
MAX9633 toc10
10,0001000100101
MAX9633 toc13
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
0
-20
-40
-60
PSRR (dB)
-80
-100
-120
-140
1 100,000
FREQUENCY (kHz)
LARGE-SIGNAL UNITY GAIN
vs. FREQUENCY
20
15
10
5
0
GAIN (dB)
-5
-10
-15
-20
1
10 100
1000
FREQUENCY (kHz)
= 0V. Typical values are at TA = +25NC, unless
GND
OPEN-LOOP GAIN vs. FREQUENCY
160
140
MAX9633 toc11
120
100
80
60
40
OPEN-LOOP GAIN (dB)
20
0
-20
10,000100010010
0.001 100,000
FREQUENCY (kHz)
INPUT REFERED VOLTAGE NOISE
vs. FREQUENCY
40
MAX9633 toc14
100,00010,000
1,000,00
35
30
25
20
15
10
5
INPUT REFERED VOLTAGE NOISE (nV/√Hz)
0
0.1 100k
FREQUENCY (Hz)
R
C
1000100.1
ISO
LOAD
= 20I
= 1nF
10k1k1 10 100
MAX9633
MAX9633 toc12
MAX9633 toc15
100nV/div
0.1Hz TO 10Hz NOISE vs. TIME
10s/div
MAX9633 toc16
CURRENT NOISE vs. FREQUENCY
200
180
160
140
120
100
80
60
CURRENT NOISE (pA/√Hz)
40
20
0
0.1 100k
FREQUENCY (Hz)
INPUT INFERRED
MAX9633 toc17
10k1k100101
5
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Typical Operating Characteristics (continued)
(VCC = +15V, VEE = -15V, VCM = 0V, outputs have RL = 10kI connected to V
otherwise noted.)
= 0V. Typical values are at TA = +25NC, unless
GND
SMALL-SIGNAL STEP RESPONSE vs. TIME
MAX9633
10,000
1000
(pF)
LOAD
C
100
1µs/div
CAPACITIVE LOAD
vs. ISOLATION RESISTOR
UNSTABLE
STABLE
MAX9633 toc18
IN_+
100mV/div
OUT_
100mV/div
MAX9633 toc20
LARGE-SIGNAL STEP RESPONSE
TOTAL HARMONIC DISTORTION
vs. FREQUENCY V
-100
-110
-120
-130
-140
vs. TIME
1µs/div
OUT
= 10V
MAX9633 toc19
IN_+
2V/div
OUT_
2V/div
P-P
MAX9633 toc21
-150
TOTAL HARMONIC DISTIORTION (dB)
10
1 100
10
R
(I)
ISO
-160
10 100k
FREQUENCY (Hz)
10k1k100
THD vs. OUTPUT VOLTAGE
-100
FREQUENCY = 10kHz
-105
-110
-115
-120
-125
-130
TOTAL HARMONIC DISTORTION (dB)
-135
-140
OUTPUT VOLTAGE (V
MAX9633 toc22
981 2 3 5 64 70 10
)
P-P
-20
-40
-60
-80
CROSSTALK (dB)
-100
-120
-140
CROSSTALK vs. FREQUENCY
0
0.1 100,000
FREQUENCY (kHz)
10,0001000100101
MAX9633 toc23
6
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Typical Operating Characteristics (continued)
(VCC = +15V, VEE = -15V, VCM = 0V, outputs have RL = 10kI connected to V
otherwise noted.)
OUTPUT VOLTAGE HIGH
vs. SOURCE CURRENT
15.0
(V)
V
14.5
14.0
13.5
13.0
OH
12.5
12.0
11.5
11.0
TA = +85°C
TA = -40°C
0 40
I
SOURCE
100mV STEP RESPONSE WITH C
NO C
TA = 0°C
(mA)
LOAD
TA = +125°C
TA = +25°C
35305 10 15 20 25
LOAD
MAX9633 toc26
MAX9633 toc24
(V)
V
= 0V. Typical values are at TA = +25NC, unless
GND
OUTPUT VOLTAGE LOW vs. SINK CURRENT
-14.4
-14.5
TA = 0°C
(mA)
LOAD
TA = +125°C
TA = +25°C
35305 10 15 20 25
LOAD
MAX9633 toc27
-14.6
-14.7
-14.8
OL
-14.9
-15.0
-15.1
-15.2
0 40
TA = +85°C
TA = -40°C
I
SINK
2V STEP RESPONSE WITH C
NO C
MAX9633 toc25
MAX9633
C
LOAD
C
LOAD
C
LOAD
200ns/div
= 50pF
= 100pF
= 150pF
100mV/div
OUTPUT IMPEDANCE vs. FREQUENCY
100
10
1
OUTPUT IMPEDANCE (I)
0.1
0.01
0.1 100k
FREQUENCY (Hz)
C
= 50pF
LOAD
1V/div
C
= 100pF
LOAD
C
= 150pF
LOAD
200ns/div
MAX9633 toc28
10k1k100101
7
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Pin Configuration
MAX9633
TOP VIEW
OUTA
INA+
V
EE
TOP VIEW
+
1
2INA-
MAX9633
3
4
EP*
V
8
CC
OUTB
7
6
INB-
5
INB+
+
SO-EP
MAX9633
CC
V
OUTB
8 7
1 2 3
INA-
OUTA
INB-
6 5
EP*
INA+
INB+
4
EE
V
TQFN-EP
*EP = EXPOSED PAD. CONNECT TO VEE EXTERNALLY OR LEAVE UNCONNECTED.
Pin Description
PIN NAME FUNCTION
1 OUTA Output A
2 INA- Negative Input A
3 INA+ Positive Input A
4 V
EE
Negative Supply Voltage. Bypass with a 0.1FF capacitor to ground.
5 INB+ Positive Input B
6 INB- Negative Input B
7 OUTB Output B
8 V
CC
— EP Exposed Pad. Connect to V
Positive Supply Voltage. Bypass with a 0.1FF capacitor to ground.
externally or leave unconnected.
EE
8
Dual 36V Op Amp for 18-Bit
Detailed Description
The MAX9633 is designed in a new 36V, high-speed
complementary BiCMOS process that is optimized for
excellent AC dynamic performance combined with highvoltage operation.
The exceptionally fast settling time, low noise, low distortion, high bandwidth, and low input offset voltage make
the IC an excellent solution to drive (up to 18-bit)highresolution and fast SAR ADCs.
The MAX9633 is unity gain stable and operates either
with a single supply voltage up to 36V or with dual supplies up to Q18V.
Applications Information
Driving High-Resolution SAR ADCs
High-resolution SAR ADCs typically switch an input
capacitor in the order of tens of pF during the track and
hold phases. Such capacitor switching can cause a
voltage glitch at the input of the ADC that behaves as a
load-transient condition for the driving amplifier. In many
applications, this glitch is avoided by placing an external
capacitor at the ADC input that is in the order of 20 to 50
times the ADC input capacitor. If the ADC input capacitor ranges from 15pF to 30pF, then the external capacitor
is anything between 300pF to 1.5nF, depending on the
application. An isolation resistor can be placed in series
between the amplifier’s output and the external capacitor, as shown in the Typical Application Circuit.
During the load-transient condition described, the driving amplifier must be able to settle to 0.5 x LSB within
the ADC acquisition time (t
approximation, the number of time constants required to
settle to 0.5 x LSB is a logarithm function of the number
N of bits:
=
The external RC time constant must be such that:
2) k x R
As an example, consider a 16-bit SAR ADC with 500ns
acquisition time and 20pF input capacitor.
From 1): k = 12
Assuming a factor of 50 for the external capacitor:
Finally, formula 2) gives: R
The IC is optimized for very fast load-transient recovery
with big capacitive loads and small isolation resistors.
L
C = 1nF
). Assuming a first order
ACQ
N 1
+
( )
x C < t
P 40I
L
ACQ
SAR ADC Front-End
This makes it ideal to drive high-resolution and fast SAR
ADCs.
Recommended SAR ADCs
The MAX9633’s wide supply range and fast settling
make it ideal for driving high-resolution SAR ADCs, such
as the MAX1320. The MAX1320 is a 14-bit, 8-channel, simultaneous-sampling ADC that measures analog
inputs up to Q5V. Sampling up to 250ksps per channel
for eight channels, the MAX1320 achieves 77dB SNR,
90dBc SFDR, and -86dB THD. The MAX1320’s fast
sample rate and typical input resistance of 8.6kI often
make it necessary to have a low-noise op amp, such as
the MAX9633, driving its inputs. The MAX9633 is also
a good fit for an anti-aliasing active filter prior to the
MAX1320 as shown in the Typical Application Circuit.
The MAX1320 is part of a family of simultaneous sampling
ADCs (MAX1316–MAX1326). Other options include ADCs
that measure 0V to 5V inputs, or Q10V inputs, and two 4
or 8 simultaneous input channels. The MAX1320’s high
speed and resolution make it a fit for multiphase motor
control and power-grid monitoring.
The MAX9633 is also well-suited to drive the 16-bit
MAX11046 8-channel, simultaneous-sampling, SAR
ADC. The MAX11046 is rated for up to 250ksps. An input
driver is typically not necessary at sampling rates below
100ksps. For applications that require > 100ksps sample
rates, the MAX9633 offers small size, high bandwidth,
and ultra-low -100dB THD at 100kHz.
Low Noise and Low Distortion
The MAX9633 is designed for applications that require
very low voltage noise, making it ideal for low source
impedance. When driving 16-bit SAR ADCs with a Q5V
full-scale input, such as the MAX11046, the MAX9633
very low input voltage noise density specification guarantees 16-bit resolution up to 10MHz of signal bandwidth.
The MAX9633 is also designed for ultra-low distortion performance. THD specifications in the Electrical
Characteristics and Typical Operating Characteristics
is calculated up to the 5th harmonic. Even when driving
high voltage swing up to 10V
excellent low distortion operation up and beyond 100kHz
of bandwidth.
Besides driving high-resolution and high-bandwidth SAR
ADCs, applications that benefit for low-noise and lowdistortion applications can be found in industrial powergrid and smart-grid, industrial motor-control, medical
imaging, automated test equipment, instrumentation,
and professional audio equipment.
, the MAX9633 maintains
P-P
MAX9633
9
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Input Common Mode and Output Swing
The IC’s input common-mode range as well as the output range can swing to the negative rail V
features are very important for applications where the
MAX9633 is used with a single supply (V
to ground). In such a case, being able to swing the input
common-mode to the negative rail offers ground-sensing
capability.
. These two
EE
connected
EE
MAX9633
Input Differential Voltage Protection
During normal op-amp operation, the inverting and noninverting inputs of the IC are at essentially the same voltage. However, either due to fast input voltage transients
or due to other fault conditions, these pins can be forced
to be at two different voltages.
Internal back-to-back diodes protect the inputs from an
excessive differential voltage (Figure 1). Therefore, IN+
and IN- can be any voltage within the range shown in the
Absolute Maximum Ratings. Note the protection time is
still dependent on the package thermal limits.
If the input signal is fast enough to create the internal
diode’s forward bias condition (0.7), the input signal current must be limited to 20mA or less. If the input signal
current is not inherently limited, an external input series
resistor can be used to limit the signal input current.
Care should be taken in choosing the input series resistor value, since it degrades the low-noise performance
of the device.
Figure 1. Input Protection Circuit
The IC has built-in circuits to protect from electrostatic
discharge (ESD) events. An ESD event produces a short,
high-voltage pulse that is transformed into a short current
pulse once it discharges through the device. The built-in
protection circuit provides a current path around the op
amp that prevents it from being damaged. The energy
absorbed by the protection circuit is dissipated as heat.
ESD protection is guaranteed up to 6kV with the Human
Body Model (HBM).
The Human Body Model simulates the ESD phenomenon
wherein a charged body directly transfers its accumulated electrostatic charge to the ESD-sensitive device. A
common example of this phenomenon is when a person
accumulates static charge by walking across a carpet
and then transfers all of the charge to an ESD-sensitive
device by touching it.
The IC can operate with dual supplies from Q2.25V
to Q18V or with a single supply from +4.5V to +36V
with respect to ground. When used with dual supplies,
bypass both V
tor to ground. When used with a single supply, bypass
V
technique helps optimize performance by decreasing
the amount of stray capacitance at the op amp’s inputs
and outputs. To decrease stray capacitance, minimize
trace lengths by placing external components close to
the op amp’s pins.
For high-frequency designs, ground vias are critical to
provide a ground return path for high-frequency signals
and should be placed around the signal traces and
near the decoupling capacitors. Signal routing should
be short and direct to avoid parasitic effects. Avoid
using right angle connectors since they may introduce
a capacitive discontinuity and ultimately limit the frequency response.
Electrostatic Discharge (ESD)
Power Supplies and Layout
and VEE with their own 0.1FF capaci-
CC
with a 0.1FF capacitor to ground. Careful layout
CC
10
Chip Information
PROCESS: BiCMOS
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
8 SO-EP S8E+14
8 TDFN-EP T833+3
21-0111 90-0151
21-0137 90-0058
8L, SOIC EXP. PAD.EPS
MAX9633
11
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX9633
12
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
COMMON DIMENSIONS
SYMBOL
MIN. MAX.
A 0.70 0.80
D 2.90 3.10
E 2.90 3.10
A1
0.00 0.05
L 0.20 0.40
0.25 MIN.k
A2 0.20 REF.
PACKAGE VARIATIONS
PKG. CODE
T633-2
T833-2
T833-3
T1033-1
T1033MK-1
T1033-2
T1433-1
N D2
6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF
8 1.50±0.10 2.30±0.10
8 1.50±0.10 2.30±0.10
1.50±0.10
1.70±0.10 2.30±0.1014
E2 e
2.30±0.1010
2.30±0.101.50±0.10
2.30±0.10 MO229 / WEED-3 2.00 REF0.25±0.050.50 BSC1.50±0.1010
JEDEC SPEC
0.65 BSC MO229 / WEEC
0.65 BSC MO229 / WEEC
0.50 BSC
0.50 BSC MO229 / WEED-3
0.40 BSC
0.40 BSC
0.40 BSC
MO229 / WEED-3
- - - -
- - - - 0.20±0.05 2.40 REFT1433-3F 14 2.30±0.101.70±0.10
b
[(N/2)-1] x e
0.30±0.05 1.95 REF
0.30±0.05 1.95 REF
2.00 REF0.25±0.05
0.25±0.05 2.00 REF10
2.40 REF0.20±0.05- - - -
0.20±0.05 2.40 REFT1433-2 14 2.30±0.101.70±0.10
MAX9633
13
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
Revision History
REVISION
NUMBER
0 9/10 Initial release —
1 1/11 Added SO-EP package 1, 2, 8, 11
REVISION
DATE
MAX9633
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
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©
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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