The MAX9526 is a low-power video decoder that converts NTSC or PAL composite video signals to 8-bit or
10-bit YCbCr component video compliant with the ITUR BT.656 standard. The device powers up in fully operational mode and automatically configures itself to
decode the detected input standard. The MAX9526
typically consumes 200mW of power in normal operation and typically less than 100µW in shutdown mode.
An internal 10-bit, 54MHz analog-to-digital converter
(ADC) samples the input with four times oversampling.
The MAX9526 features a DC restoration circuit with offset correction and automatic gain control to accurately
optimize the full-scale range of the ADC.
An integrated analog anti-aliasing filter eliminates the
need for external filtering. The MAX9526 includes a 2:1
input multiplexer with automatic signal selection based
on activity at the inputs.
An internal line-locked phase-locked loop (PLL) generates the sample clock and the line-locked clock (LLC)
output to provide an ITU-compliant output. Alternatively,
the PLL can be configured to provide a sample clock
and output clock at 2x and 1x the frequency of the
crystal oscillator, respectively.
The MAX9526 provides a multiline adaptive comb filter to
reduce cross-chrominance and cross-luminance artifacts.
A single 1.8V supply is used for both the digital and
analog supplies. The digital outputs operate from a
separate +1.7V to +3.45V supply to allow direct connection to a wide range of digital processors. The
MAX9526 operates over the -40°C to +125°C automotive temperature range and is available in both a
28-pin QSOP and a 32-pin TQFN (5mm x 6mm).
Applications
Automotive Entertainment Systems
Collision Avoidance Systems
Security Surveillance/CCTV Systems
Televisions
Features
o Supports All NTSC and PAL Standards
NTSC M, NTSC J, NTSC 4.43,
PAL B/G/H/I/D, PAL M, PAL N, PAL 60
o Easy to Configure and Operate with Only
16 User-Programmable Registers
o Automatic Configuration and Standard Select
o 10-Bit 4x Oversampling (54Msps) ADC with True
10-Bit Digital Processing
o Flexible Output Formatting
10-Bit Parallel ITU-R BT.656 Output with
Embedded TRS
8-Bit Parallel ITU-R BT.656 Output with Separate
HS and VS
o +1.8V Digital and Analog Supply Voltage
o +1.7V to +3.45V Digital I/O Supply Voltage
o Full Automotive Temperature Range (-40°C to
+125°C)
o Low-Power Modes
Shutdown (< 100µW typ)
Sleep Mode with Continuous Activity Detection
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND .......................................................-0.3V to +2V
DVDD to DGND ........................................................-0.3V to +2V
DVDDIO to DGND .................................................-0.3V to +3.6V
AGND to DGND.....................................................-0.1V to +0.1V
D9–D0, LLC to DGND .........................-0.3V to (DVDDIO + 0.3V)
V
IN1
, V
IN2
, V
REF
to AGND .......................-0.3V to (AVDD + 0.3V)
XTAL/OSC, XTAL2 to AGND ....................................-0.3V to +2V
IRQ, SDA, SCL, DEVADR to DGND ......................-0.3V to +3.6V
Continuous Current In/Out All Pins ...................................±50mA
Sync Slice Comparator LevelActivity detect slicer, referenced to V
DC Restore Current DAC FullScale Range (Source and Sink)
(Note 3)
D C Restor e S ync- Ti p Level at
/V
V
IN1
IN2AGCGAIN = 0xF, ADAGC = 10.72
ANALOG INPUT FILTER AND ADC (Note 4)
C utoff Fr eq uency ( 3d B) f
P assb and Fl atness
S top b and C utofff
S top b and Attenuati on
Ful l - S cal e C onver si on Rang e
AGC Gai n S tep si ze0.167V/V
D i ffer enti al N onl i near i tyD N LAGCGAIN = 0x0, ADAGC = 1±0.5LSB
Integ r al N onl i near i tyIN LAGCGAIN = 0x0, ADAGC = 1±1LSB
S i g nal - to- N oi se Rati oS N R
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
3dB
S B
Slow3
Medium6
Medium-fast (default)12
Fast24
AGCGAIN = 0x0, ADAGC = 10.51
f < 5MHz, V
measured at 1MHz
f > f
SB
measured at 1MHz
AGC disabled,
gain programmed
using I
referenced to V
Incl ud es fi l ter + AD C + d i g i tal anti - al i asi ng
fi l ter , i np ut i s - 1d BFS ; AD AG C = 1,
AGC GAIN [ 3:0] = 0x0, d efi ned as r ati o of
RM S si g nal to RM S noi se i n d B
= 0.65V
VIN
, V
= 0.65V
VIN
2
C (ADAGC = 1),
IN1/VIN2
, reference level
P-P
, reference level
P-P
AGC GAIN = 0x0670830
AGC GAIN = 0xF270330
CLMP
50mV
13MHz
0.25dB
53MHz
36dB
mV
58.8dB
µA
V
P-P
P ow er - S up p l y Rej ecti onP S R
D i ffer enti al P haseDP
AD AGC = 1
AGC GAIN [ 3:0] = 0x0
i np ut l evel = 1M H z si ne
w ave at - 2d BFS
5-step modulated staircase,
f = 3.58MHz or 4.43MHz
1.7V < V
AV D D
1.9V , 1.7V <
V
< 1.9V
D V D D
V
= 1.8V +
AV D D
100m V
500kH z
V
AV D D
100m V
3.58M H z
V
AV D D
100m V
4.43M H z
at
P - P
= 1.8V +
at
P - P
= 1.8V +
at
P - P
<
-40
-67
dBFS
-58
-57
1.0degrees
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
Note 1: All devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design.
Note 2: NTSC 75% color bar signal applied to video input. C
L
= 10pF on D9–D0 and LLC. External XTAL.
Note 3: Internal test only. Digital core controls sync level adjustment current to adjust offset in analog signal path. Adjust level is
based on value of sync level as converted by ADC. Digital core switches sourcing or sinking current into V
IN1
or V
IN2
nodes. Speed of correction (value of current) is controlled through I2C.
Note 4: Filter and ADC performance measured using ADC outputs prior to composite digital demodulation (decoding).
Note 5: Decoded luminance and chrominance specifications measured using entire signal path from video input to digital compo-
11, 238, 22DGNDDigital Ground. Connect both DGND terminals together.
1210SDA
1311SCL
NAMEFUNCTION
IN1
REF
IN2
Single-Ended Composite Video Input 1. AC-couple the input video signal with a 0.1µF
capacitor.
Video Reference Bypass. Bypass V
possible to the device.
Single-Ended Composite Video Input 2. AC-couple the input video signal with a 0.1µF
capacitor.
Analog Power-Supply Input. Connect to a +1.8V supply. Bypass AVDD to AGND with a
0.1µF capacitor.
External Crystal. Connect XTAL2 to one terminal of the crystal oscillator. Ground XTAL2
when applying an external clock to XTAL/OSC.
External Crystal/Oscillator. Connect XTAL/OSC to one terminal of a crystal or an
external clock source. Connect XTAL2 to the other terminal of the crystal oscillator.
2
I
C Device Address Select Input. Connect to DVDD, DGND, or SDA to select 1 of 3
available I
Digital Power-Supply Input. Connect to a +1.8V supply. Bypass DVDD to DGND with a
0.1µF capacitor in parallel with a 10µF capacitor.
2
C-Compatible Serial-Data Input/Output. Connect a 10kΩ pullup resistor from SDA to
I
DVDDIO for full output swing.
2
I
C-Compatible Serial-Clock Input. Connect a 10kΩ pullup resistor from SCL to
DVDDIO for full output swing.
2
C slave addresses (see Table 5).
to AGND with a 0.1µF capacitor as close as
REF
Hardware Interrupt Open-Drain Output. If not masked, IRQ is pulled low when the bits
1412IRQ
13–16, 18,
15–20, 25–28
2120LLC
2423DVDDIO
—9, 17, 25, 29N.C.No Connection. Not internally connected.
——EPExposed Pad (TQFN Only). EP is internally connected to GND. Connect EP to GND.
19, 24, 26,
27, 28
D0–D9
in the status register change state. Repeated faults have no effect on IRQ until IRQ is
cleared by reading the corresponding status register. Connect a 10kΩ pullup resistor
from IRQ to DVDDIO for full output swing.
Digital Video Outputs Bit 0–Bit 9, 10-Bit Component Digital Video Outputs. The output
format is 10-bit ITU-R BT.656, 4:2:2 with embedded sync. D1 and D0 can be
configured as horizontal and vertical sync outputs using the Clock and Output register
0x0D. D0 is LSB.
Line-Locked 27MHz Clock Output. With line-locked mode, the LLC clock varies in
response to horizontal line rate of the incoming video. In async mode, the LLC clock is
synchronous to the crystal (see Table 1).
Digital I/O Power-Supply Input. Accepts a +1.7V to +3.45V voltage input. Bypass to
DGND with a 0.1µF capacitor.
MAX9526
Detailed Description
The MAX9526 is a simple, low-power video decoder
that converts all modes of NTSC and PAL composite
video signals to 10-bit YCbCr component video compatible with the ITU-R BT.656 standard. The device
powers up in fully operational mode and automatically
configures itself to standard NTSC or standard PAL.
An internal 10-bit, 54MHz ADC samples at four times
the sampling rate specified in ITU-R BT.601. The analog front-end of the MAX9526 features a DC restoration
circuit, automatic gain control, and automatic offset correction. These blocks are controlled with digital processing to accurately optimize the full-scale range of
the ADC. An integrated analog anti-aliasing filter eliminates the need for off-chip filtering. The device includes
a 2:1 input multiplexer that can be configured to automatically select the input based on activity.
The system clock is generated with an external 27MHz
crystal and an internal oscillator. Optionally, a 27MHz or
54MHz external clock can be connected to the
XTAL/OSC input. An internal line-locked digital PLL is
used to generate the 54MHz ADC sample clock that is
synchronous to the incoming video signal with up to
±5% variation in horizontal line length. The digital output data and LLC clock are line locked to the video
input and provide a standard ITU output. The PLL can
also be configured to asynchronously sample the input
using the crystal oscillator or external clock.
The MAX9526 provides a 5-line adaptive comb filter to
separate the luminance (Y) and chrominance (C) video
components and reduce cross-chrominance and crossluminance artifacts. The MAX9526 operates with any
type of standard composite video signal source including DVD players, video cameras, navigation systems,
and VCRs.
The device powers up in fully operational video
decoder mode. An I
2
C register interface monitors status
and enables programming of many decoder functions
including brightness, contrast, saturation, and hue. The
10-bit output can be reconfigured to provide 8-bit data
with separate horizontal and vertical syncs.
Analog Front-End (AFE)
The MAX9526 AFE implements DC restoration, automatic gain control (AGC), analog anti-aliasing filter
(LPF), activity detection, channel selection, and analogto-digital conversion. A block diagram of the AFE is
shown in Figure 1.
Activity Detect and Automatic Channel Selection
The MAX9526 continuously monitors activity at both
video inputs, V
IN1
and V
IN2
. Activity on the selected
channel is detected using the ADC output. On the
unselected channel an analog sync-tip clamp and sync
slicer are used to detect sync amplitudes greater than
50mV. In sleep mode, the analog sync-tip clamps and
sync slicers are used to detect activity on both inputs,
while the rest of the AFE is in a shutdown state.
The output of the activity detect circuit is reported
through the Status register 0x00. The user must manually select which video input to process by setting
INSEL in register 0x09 appropriately.
The MAX9526 can optionally be configured to automatically select the video input that indicates the presence
of activity by setting AUTOSEL = 1 in register 0x09.
When activity is present on both V
IN1
and V
IN2
at
power-up or when there is no activity on either input
channel, V
IN1
is selected. When there is activity on V
IN2
and there is no activity on V
IN1
, then V
IN2
is selected.
When V
IN2
is automatically selected with the presence
of activity, the input only switches to V
IN1
when activity
goes away on V
IN2
.
Low-Power, High-Performance
NTSC/PAL Video Decoder
A differential signal path is used to process the analog
video signal to minimize the effect of noise coupling. A
DC reference (V
REF
) of 850mV is internally generated
and decoupled externally with a 0.1µF capacitor.
Identical signal paths and video buffers are used for
both the selected video input and the video reference
voltage. The signals are converted to a fully differential
signal by the analog AGC circuit.
DC Restoration DAC
The video inputs, V
IN1
and V
IN2
, are AC-coupled to the
MAX9526 with 0.1µF capacitors. The DC restoration circuit sets the sync level at the output of the ADC by sinking or sourcing current at the selected video input. A
digital control at the ADC output is used to monitor the
average sync level. An error signal is generated in the
digital control block that is used by a current DAC to
source or sink current to the AC-coupled input to
restore the DC level. The DC restoration circuit also corrects the offset in the analog signal chain and sets the
sync level at the ADC output to code 32 (decimal).
Analog Automatic Gain Control (Analog AGC)
The MAX9526 includes an analog variable-gain amplifier with a digitally controlled gain for automatic gain
control (AGC). The AGC uses the sync amplitude at the
output of the ADC to control the gain. For signals without copy protection, the AGC adjusts the gain until the
sync amplitude is 208 (decimal) codes at the ADC output. For inputs with copy protection, the AGC automatically compensates for the reduced sync amplitude on
active lines.
The analog AGC loop can be disabled and the gain is
set manually to 1 of 16 values using the Gain Control
register 0x0A. The range of analog gain is 3.5dB to
12dB.
Analog Lowpass Filter (LPF)
The MAX9526 includes a high-performance anti-aliasing
analog lowpass filter with a 3dB bandwidth of 13MHz
(typ) and better than 0.25dB (typ) passband flatness to
5MHz. This eliminates the need for external filtering on
the video inputs. The filter typically provides 36dB attenuation at 53MHz (1MHz below ADC sample rate).
54Msps Video ADC
A 10-bit, 54Msps ADC converts the filtered analog
composite video signal for digital signal processing
(composite video demodulation).
Digital Filtering
Digital filtering at the ADC output removes any out-ofband interference and improves the signal-to-noise
ratio before decoding. The signal path includes a digital anti-aliasing lowpass filter that has 1dB of passband
flatness to 5.5MHz and a minimum of 45dB of stopband
attenuation for frequencies greater than 9MHz.
Sync Processing, Clock Generation,
and PLL
The sync processing, clock generation, and PLL extract
the timing information from incoming video and generate the clock for the rest of the chip. Figure 2 shows the
block diagram for this block.
Crystal Oscillator/Clock Input
The MAX9526 includes a low-jitter crystal oscillator circuit optimized for use with an external 27MHz crystal.
The device also accepts an external CMOS logic-level
clock at either 27MHz or 54MHz. To use an external
clock (27MHz or 54MHz) instead of a crystal, set
XTAL_DIS = 1 in register 0x0D. To use a 54MHz external clock instead of a 27MHz clock, SEL_54MHz must
also be set to 1 in register 0x0D.
Figure 2. Sync Processing, Clock Generation, and PLL
FROM AFE
10
SYNC
PROCESSING
XTAL/OSC
OSCILLATOR
XTAL2
NONSTD
VIDEO
CLOCK
GENERATOR
AND PLL
CLOCK
MUX
MUX
MAX9526
Sync Processing
The sync processing block extracts the sync information
and automatically detects 525 line or 625 line inputs.
Clock Generator and PLL
The PLL operates in either line-locked clock (LLC)
mode or async mode. Selection of the mode is controlled automatically by the MAX9526 or can optionally
be overwritten with the LLC_MODE bits in PLL Control
register 0x0E.
In LLC mode, a hybrid analog/digital PLL generates a
low-jitter line-locked clock. The 54MHz sample clock is
synchronous to the input video. The LLC clock output is
also synchronous to the input video. The ITU output has
the correct number of samples per line and lines per
field. The PLL is designed to lock to signals with up to
160ns peak jitter. When the jitter exceeds the 160ns
peak, the PLL coasts until the jitter improves. If the jitter
continuously exceeds the 160ns peak, the PLL relocks
and the HLOCK status bit in register 0x00 is set to 0.
In LLC mode, the bandwidth of the PLL can be optionally programmed to one of eight values between 180Hz
and 2000Hz using the PLLBW bits in PLL Control register 0x0E. The default value for the PLL bandwidth is
500Hz.
In async mode, the sample clock frequency is generated by multiplying the crystal frequency by a factor of
two and the video signal is sampled asynchronously
with the 2x crystal clock. To eliminate artifacts, the
MAX9526 uses an adaptive poly-phase filter to correct
timing and phase errors introduced by the asynchronous sampling. The LLC output is generated by dividing the 54MHz sampling clock by two.
The ITU output in async mode has the correct number of
lines per frame and the correct number of pixels per line
except on the first line of each field. The timing correction block uses this line to compensate for timing errors
between the incoming video signal and the crystal. As a
result, the first line of each field is longer or shorter for
several pixels depending on the magnitude of the frequency difference between the incoming video signal
and the local crystal. For example, a 100ppm frequency
difference between the incoming video signal and the
crystal results in approximately 23 extra or fewer pixels
on the first line of each field. Line length errors on line
one are of no consequence for most applications since it
is in the vertical blanking interval and does not contain
active video or any other type of data.
The types of inputs that cause the PLL to automatically
switch to async mode are video inputs with a nonstandard carrier frequency. For standard video, the carrier
frequency is always a precise multiple of the horizontal
frequency. A typical nonstandard input is video cassette
recorders in which the carrier is not a precise multiple of
the horizontal frequency. The nonstandard detect
(NONSTD) status from the decoder is used to automatically switch the PLL to async mode when nonstandard
carrier frequencies are detected. The NONSTD status is
monitored in the Status register 0x00.
Clocking Modes
In addition to automatic configuration, the MAX9526
can also be manually configured to provide maximum
flexibility in setting the clock inputs and outputs of the
chip. Table 1 summarizes the clocking modes that are
supported.
Digital Composite Decoding
Figure 3 shows a block diagram of the digital composite decoder. This block converts the digitized composite video signal to digital component video.
Sync Level Correction and Sync Extraction
The sync extraction function extracts the raw sync signals from the video and the extracted sync information
is sent to the sync processor. The sync level from the
AFE is code 32 (decimal) on a 10-bit scale and the
blanking level is approximately 208 (decimal) codes
above the sync level. The sync slicer default threshold
is set to approximately the middle of the sync pulse at
decimal code 128. The sync slice level can optionally
be manually adjusted using the slice bits in register
0x0F.
The sync level correction block features an optional
digital clamp that can be enabled in register 0x09.
Enabling the digital clamp sets the sync level to code 0
(decimal) and gives higher frequency tracking of the
input signals. When the digital clamp is enabled, the
sync slice level in register 0x0F should be adjusted
accordingly to provide equivalent noise rejection.
Sync Processor and Analog Copy
Protection Detection
The sync processor extracts the horizontal sync and
vertical sync signals. Field pulses and burst gate pulses are generated based on VSYNC and HSYNC,
respectively. The sync processing block provides sync
timing to measure the sync level and amplitude for the
black level control and composite AGC. The sync
processor also detects incoming video signal standards (525 line NTSC and 625 line PAL). Video standard information is available in Status register 0x01.
The detected video standard is used to automatically
configure the decoder. The MAX9526 detects NTSC-M
(standard NTSC) and PAL B/G/H/I/D (standard PAL)
Low-Power, High-Performance
NTSC/PAL Video Decoder
The sync processor block also detects analog copy
protection. Extracted copy protection information is
available in Status register 0x01.
Composite Automatic Gain Control (AGC)
In addition to the analog AGC that optimizes the ADC
full-scale range, a digital AGC is used to more accurately set the video amplitude. The Composite AGC
uses the amplitude of the sync signal to set the gain.
Adaptive Comb Filter
The MAX9526 uses a 5-line adaptive comb filter to separate luminance and chrominance components from a
single composite channel. The adaptation algorithm
does not require configuration. The adaptive comb filter
adjusts based on the relationship and content of video
data between neighboring lines. The filter automatically
adapts the comb filter structure between a 5-line filter
and a notch filter.
Chrominance Signal Demodulator
After luminance (Y) and chrominance (C) components
are separated, the Y component passes through a
delay line to compensate for the C component delay
through the demodulator. The chrominance signal path
contains an AGC before the signal demodulator. The
chrominance AGC uses the color burst amplitude to set
the gain. The chrominance is demodulated using a
subcarrier signal locked to the burst. The demodulated
chrominance signals, Cb and Cr, are lowpass filtered to
eliminate unwanted products of demodulation.
Output Formatting
Figure 4 shows the output formatting section of the
MAX9526.
Image Enhancement and Color Correction
The MAX9526 provides contrast, brightness, hue, and
saturation manual control in registers 0x05 to 0x08.
Time Base Correction
The MAX9526 provides time base correction (TBC) to
allow the decoder to properly process unstable and
nonstandard video from sources such as a VCR. The
time base correction minimizes the effect of sampling
jitter to ensure that there are a correct number of pixels
per active line.
Test Pattern Insertion
The MAX9526 automatically outputs a black screen
when there is no video at the inputs. The test pattern
can also be configured to provide a blue screen, 75%
color bars, or 100% color bars through register 0x0C.
Timing Reference Signal Insertion
and ITU-R BT.656 Encoding
The MAX9526 multiplexes the Y, Cr, and Cb signals
with an embedded timing reference signal conforming
to the ITU-R BT.656 standard.
SAV and EAV sequences are inserted into the data
stream to indicate the active video time in ITU-R BT.656
format. The output timing insertion is illustrated in
Figure 5. The SAV and EAV sequences are shown in
Table 2.
Output Timing
The output setup and hold diagram is shown in Figure 6.
Sample clock = input clock divided by 2, then
multiplied by 2x through the PLL. This mode uses the
PLL to filter high-frequency jitter on the input source.
Invalid mode. The PLL can only be bypassed when
the output is not a line-locked clock.
Input clock = 54MHz external clock.
Sample clock = input clock. Use this mode when a
low-jitter, 54MHz input clock is used.
Multiple asynchronous video input signals can be
decoded synchronously using multiple MAX9526s in
asynchronous (async) sampling mode. Figure 7 shows
an example of decoding four video input signals.
The MAX9526 is configured for async sampling mode
by writing the following registers:
Register 0x0D, B3 (XTAL_DIS) = 1 (disables the
crystal oscillator)
When the MAX9526 is in async sampling mode, the
data outputs, D9–D0, of all decoders are synchronous
with the input clock (XTAL/OSC). The video content in
the data outputs is not frame aligned because the video
sources into each MAX9526 is asynchronous. A small
FPGA can be implemented to multiplex all four channels into a single 8- or 10-bit bus. This FPGA can also
format the outputs to be compatible for input into a
compression processor, which is commonly used in
digital video recorders (DVRs).
The crystal oscillator (external or internal) must have
better than ±50ppm accuracy for acceptable decoding
in this mode. An accuracy of ±10ppm is recommended
for optimal performance.
Recommended Crystal Parameters
Recommended crystal parameters are shown in Table 3.
Power-Supply Decoupling
For systems where additional power-supply isolation is
required, the circuit shown in Figure 8 can be used.
Additional supply decoupling is added and analog
power (AVDD) isolation is increased with the use of a ferrite bead (FB). The analog ground connection (AGND)
should be connected to a separate ground plane that
has a small bridge to the main ground plane of the system. The video input termination (V
IN1/VIN2
), video refer-
ence (V
REF
) decoupling, and AVDD supply decoupling
should also be connected to the AGND ground plane.
I2C Serial Interface
The MAX9526 features an I2C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9526 and the
master at clock rates up to 400kHz. Figure 10 shows
the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The
master device writes data to the MAX9526 by transmitting the proper slave address followed by the register
address and then the data word. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9526 is 8 bits long and is
followed by an acknowledge clock pulse. A master
reading data from the MAX9526 transmits the proper
slave address followed by a series of nine SCL pulses.
The MAX9526 transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read
sequence is framed by a START or REPEATED START
condition, a not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500Ω, is
required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500Ω, is required
on SCL if there are multiple masters on the bus, or if the
single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the MAX9526 from
high-voltage spikes on the bus lines, as well as minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions
section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 11). A START
condition from the master signals the beginning of a
transmission to the MAX9526. The master terminates
transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9526 recognizes a STOP condition at any
point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For
DEVADR connected to DGND, setting the read/write bit to
1 (slave address = 0x43) configures the MAX9526 for
read mode. Setting the read/write bit to 0 (slave address
= 0x42) configures the MAX9526 for write mode. The
address is the first byte of information sent to the
MAX9526 after the START condition. The MAX9526 slave
address is configurable with DEVADR. Table 5 shows the
addresses of the MAX9526.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9526 uses to handshake receipt each byte of data
when in write mode (see Figure 12). The MAX9526 pulls
down SDA during the entire master-generated 9th clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX9526 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not acknowledge is
sent when the master reads the final byte of data from
the MAX9526, followed by a STOP condition.
Write Data Format
A write to the MAX9526 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a
STOP condition. Figure 13 illustrates the proper frame
format for writing one byte of data to the MAX9526.
Figure 14 illustrates the frame format for writing n bytes
of data to the MAX9526.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9526.
The MAX9526 acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
The second byte transmitted from the master configures the MAX9526’s internal register address pointer.
The pointer tells the MAX9526 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9526 upon receipt of the address pointer data.
The third byte sent to the MAX9526 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9526 signals receipt of the data
byte. The address pointer autoincrements to the next
register address after each received data byte. This
autoincrement feature allows a master to write to
sequential registers within one continuous frame. Figure
14 illustrates how to write to multiple registers with one
frame. The master signals the end of transmission by
issuing a STOP condition.
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9526 acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START command followed
by a read command resets the address pointer to register 0x00.
The first byte transmitted from the MAX9526 is the contents of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement
feature allows all registers to be read sequentially within
one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condition is issued followed by another read operation, the
first data byte to be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9526’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX9526 then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condition. Figure 15 illustrates the frame format for reading
one byte from the MAX9526. Figure 16 illustrates the
frame format for reading multiple bytes from the
MAX9526.
Figure 10. I2C Serial Interface Timing Diagram
Figure 12. Acknowledge
Figure 11. START, STOP, and REPEATED START Conditions
1 = Color carrier has fallen below color kill threshold
since last register 0 read.
0 = Color carrier has not fallen below color kill thresh-
old since last register 0 read.
CTHR reports when the chroma carrier is below color
kill threshold. See register 0x0B for color kill threshold
and color kill enable settings.
ADC Out-of-Range (ADCOVR)
1 = ADC has gone outside the full-scale range since
last register 0 read.
0 = ADC has not gone outside the full-scale range
since last register 0 read.
ADCOVR triggers when the ADC input is above or
below the ADC input range. This bit is cleared after
reading status register 0. ADCOVR is not triggered on
lines during the vertical blanking interval, on lines at the
start or end of the field that may have pulses from copy
protection, or on lines that may have ancillary data.
Horizontal Lock (HLOCK)
1 = Line-locked PLL is locked to horizontal line rate and
has not lost lock since last status register 0 read.
0 = Line-locked PLL has lost lock since last status reg-
ister 0 read.
Nonstandard Video (NONSTD)
1 = Nonstandard video detected.
0 = Standard video format detected.
For standard video, the carrier frequency is always a
precise multiple of the horizontal frequency. An example of nonstandard inputs are video cassette recorders
in which the carrier is not a precise multiple of the horizontal frequency.
Demodulator Lost Lock (LSTLCK)
1 = Demodulator has lost lock since last status register
0 read.
0 = Demodulator has maintained lock since last status
register 0 read.
I2C Bit Descriptions
Status Register 1
Status Register 0
525 Line Mode (L525)
1 = 525 line video detected.
0 = 625 line video detected.
This output is only valid when the decoder is locked
and operating normally.
Analog Copy Protection (ACP)
1 = Analog copy protection detected.
0 = No analog copy protection detected.
REGB7B6B5B4B3B2B1B0
0x00VID1VID20CTHRADCOVRHLOCKNONSTDLSTLCK
REGB7B6B5B4B3B2B1B0
0x010L52500000ACP
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
This interrupt is masked by the HLOCK and LSTLCK
status. Changes in the L525 status triggers a hardware
interrupt only when HLOCK = 1 and LSTLCK = 0. See
register 0x01, B6.
Analog Copy Protection Interrupt Enable (IACP)
1 = Any change in ACP status bit (register 0x01, B0)
triggers a hardware interrupt.
0 = No interrupt on analog copy protection changes
(default).
See register 0x01, B0.
Interrupt Mask Register 0
Interrupt Mask Register 1
Active Video 1 Interrupt (IVID1)
1 = Change in VID1 bit status triggers a hardware
interrupt.
0 = No interrupt on VID1 changes (default).
See register 0x00, B7.
Active Video 2 Interrupt (IVID2)
1 = Change in VID2 bit status triggers a hardware
interrupt.
0 = No interrupt on VID2 changes (default).
See register 0x00, B6.
Color Kill Threshold Interrupt (ICTHR)
1 = Transition in CTHR bit from 0 to 1 triggers a hard-
Bit B6 sets the video line rate when AUTOD = 0. When
AUTOD = 1 (default), B6 is ignored.
Bit B5 (Unconventional Video)
1 = PAL Combination N, PAL M, NTSC 4.43, PAL 60.
0 = PAL B/G/H/I/D (standard PAL), NTSC M (standard
NSTC), or NTSC J (default).
The 3 bits in the STDSEL register can be used to program the expected input video format. Bit B6 (525 vs.
625 line video) can be automatically set by using the
autodetect function (see AUTOD bit description, register 0x04, B4).
B[7:5]
000:PAL B/G/H/I/D (standard PAL)
001:PAL Combination N
010:NTSC M (standard NTSC)
011:PAL M
100:N/A
101:NTSC 4.43
110:NTSC J
111:PAL60
Standard Autodetect (AUTOD)
1 = Automatically detects 525 vs. 625 line video
(default).
0 = Manually programs 525 vs. 625 line video.
Autodetect function can only be used to distinguish
between standard PAL and standard NTSC. The
autodetect function requires register 0x04, B7 = B5 = 0.
Low-Power Shutdown (SHDN)
1 = Low-power shutdown mode.
0 = Normal operation (default).
In shutdown, all logic outputs are low (unless programmed to high impedance using register 0x0D, B1).
I2C register contents are retained during shutdown.
System Reset (RESET)
1 = All registers and system state returned to power-on
default conditions.
0 = Normal operation (default).
Because all registers’ contents are set to power-on
default state, this bit clears itself after being written.
Sleep Mode (SLEEP)
1 = Low-power sleep mode.
0 = Normal operation (default).
In sleep mode, all logic outputs are low (unless programmed to high impedance using register 0x0D, B1).
I2C register contents are retained. Video activity detect
is still active. Activity status is available in register 0x00.
Soft Reset (RESET_S)
This bit resets everything on the device except the register values. This bit is self-clearing.
1 = Soft reset.
0 = Normal operation (default).
Standard Select, Shutdown, and Control Register
REGB7B6B5B4B3B2B1B0
0x04STDSELAUTODSHDNRESETSLEEPRESET_S
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
1 = Automatically selects video input with activity
detect.
When activity is present on both or neither V
IN1
and
V
IN2
after a reset (POR, register reset, sleep mode,
shutdown), V
IN1
is selected. If there is activity on V
IN2
and no activity on V
IN1
, then V
IN2
is selected. When
V
IN2
is automatically selected with the presence of
activity, the input switches to V
IN1
only when activity
goes away on V
IN2
.
0 = Video input is selected manually (default).
See INSEL (register 0x09, B6) for manual input selection.
Manual Video Input Select (INSEL)
1 = Select V
IN2
.
0 = Select V
IN1
(default).
Video autoselect bit (AUTOSEL) must be 0 for this register to take effect.
Analog DC Restoration Current Range
(DCRESTORE_RANGE)
This bit sets the full-scale range of the DC restoration
DAC. Increasing the full-scale current range increases
the bandwidth and range of the DC restoration loop.
10 = Slow (±3µA into video input coupling capacitor)
11 = Medium (±6µA into video input coupling capacitor)
00 = Medium-fast (±12µA into video input coupling
capacitor) (default)
01 = Fast (±24µA into video input coupling capacitor)
Digital Clamp Disable (D_CLMP_DIS)
This bit disables the digital clamp.
1 = Disables digital sync-tip clamp (default).
0 = Enables digital sync-tip clamp.
Enabling the digital clamp sets the sync level to code 0
(decimal) and gives higher frequency tracking of input
signals. If the digital clamp is enabled, the sync slice
level in register 0x0F should be adjusted accordingly to
provide equivalent noise rejection. Typically,
SSLICE[3:0] should be reduced by 2 LSBs when
D_CLMP_DIS is set to 1.
Video Input Select and Clamp Control Register
Gain-Control Register
Chrominance AGC Disable (CRAGC)
1 = Chroma gain is frozen.
0 = Automatic chroma gain is based on color burst
level (default).
To freeze the chroma gain at the default value of 17
(hex), set CRAGC = 1 and apply a soft reset.
Composite AGC Disable (CMPAGC)
1 =Digital composite gain frozen at default value
(80 (hex)).
0 = Automatic digital composite gain based on sync
level (default).
Disable Analog Automatic Gain Control (ADAGC)
1 = Analog automatic gain control is disabled.
0 = Analog automatic gain control is enabled (default).
The analog automatic gain-control (AGC) loop adjusts
the AGC gain to optimally use the available ADC fullscale range.
REGB7B6B5B4B3B2B1B0
0x09AUTOSELINSELDCRESTORE_RANGE00D_CLMP_DIS0
REGB7B6B5B4B3B2B1B0
0x0ACRAGCCMPAGC0ADAGCAGCGAIN
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
1 = D9–D0 are the ADC outputs directly without being
processed by video demodulator.
0 = D9–D0 are 10-bit YCbCr component video
(default).
With RAWADC = 1, the D9–D0 output data rate is
54Msps and the LLC clock output is 54MHz. Figure 17
shows the typical setup and hold timings of the output
signals with RAWADC = 1.
LLC can optionally be inverted by setting LLC_INV = 1
in register 0x0D, B5.
With RAWADC = 1 the ADC outputs are filtered with the
digital lowpass filter before being routed to D9–D0. The
ADC outputs can be directly connected to D9–D0 without filtering by setting RAWADC = 1 and DISAAFLT = 1
in register 0x0F, B5.
Color Test Signal Register
Figure 17. Typical Setup and Hold Timings in RAWADC Mode
REGB7B6B5B4B3B2B1B0
0x0CRAWADC0TGEnabTGTIMTGSRC0CBAR
D9–D0
LLC
(54MHz)
~8ns
~18.5ns
~8ns
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
In default mode, the MAX9526 outputs a test pattern
when video is removed. The timing standard for the test
pattern is the last timing standard that is at the output of
the decoder. If the MAX9526 is reset and has no video
inputs, the default output timing standard is 525 lines
(60Hz). See register 0x04 for manually configuring the
video standard decoding. Table 7 gives some common
examples of setting up video standards and test pattern generation.
Test Pattern Enable (TGEnab)
1 = Force a test pattern at video output.
0 = Output a test pattern if no video is present at the
video inputs (default).
Test Signal Output Timing Standard (TGTIM)
1 = 525 line, 60Hz frame rate.
0 = 625 line, 50Hz frame rate (default).
This bit is ignored if TGSRC = 1.
Test Signal Timing Source (TGSRC)
1 = Test generator uses timing from incoming video
signal (if signal is valid).
0 = Test generator uses internally generated timing
(default).
Color Bar Select (CBAR)
00 = Black screen (default)
01 = Blue screen
10 = 75% color bars
11 = 100% color bars
DESCRIPTION
Default mode, test pattern
has last timing standard
used at output
Force test pattern with last
timing standard used at
output
1 = Clip ITU output to Y range is between 64–940 and
CbCr range is between 64–960.
0 = Clip ITU output to Y range and CbCr range is
between 5–1019 (default).
Inverted Line-Locked Clock (LLC_INV)
This signal inverts the polarity of the line-locked clock
that is output from the MAX9526. This can be used to
solve board level timing problems for other devices.
1 = Invert LLC clock.
0 = Do not invert LLC clock (default).
Input Clock Frequency Select (SEL_54MHz)
1 = 54MHz clock at XTAL/OSC input.
0 = 27MHz clock at XTAL/OSC input (default).
This bit is only applicable when the crystal oscillator is
disabled (XTAL_DIS = 1).
Crystal Oscillator Disable (XTAL_DIS)
1 = XTAL/OSC is either a 27MHz or a 54MHz CMOS
clock input.
0 = Enables the 27MHz crystal oscillator (default).
Horizontal/Vertical Sync Output (HSVS)
1 = D1 and D0 output horizontal and vertical sync
pulses, respectively.
0 = D1 and D0 are LSBs of digital component video
output (default).
The rising edge of horizontal sync (HS) coincides with
the end of active video (rises after 3FFh 000h of EAV
code). The falling edge coincides with the start of
active video (SAV) code (falls after completing 3FFh
000h of SAV code). Figure 18 shows the horizontal and
vertical sync timing.
The vertical sync pulse (VS) line transitions are detailed
in Table 8. Note that the VS line transitions on pin D0
are shifted by 1 to 2 lines relative to the V flag transitions embedded in the ITU data stream. The V flag transitions embedded in the ITU data stream follow the
ITU-R BT.656-4 standard.
Data Output Disable (DATAZ)
1 = Logic data outputs (D9–D0) are disabled and
placed in high-impedance state.
0 = Logic data outputs (D9–D0) are enabled (default).
The DATAZ bit forces data outputs high impedance
regardless of whether the device is in shutdown.
Clock Output Disable (LLCZ)
1 = Logic clock output (LLC) is disabled and placed
in a high-impedance state.
0 = Logic clock output (LLC) is enabled (default).
The LLCZ bit forces LLC high impedance regardless of
whether the device is in shutdown.
Clock and Output Control Register
Table 8. VS (Pin D0) Line Transitions
REGB7B6B5B4B3B2B1B0
0x0D0CLIPLLC_INVSEL_54MHZXTAL_DISHSVSDATAZLLCZ
VERTICAL SYNC PULSES
(VS on Pin D0)
Field 1
Field 2
Start (VS = 1)Line 623Line 2
Finish (VS = 0)Line 21Line 21
Start (VS = 1)Line 309Line 265
Finish (VS = 0)Line 335Line 284
625525
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPEPACKAGE CODEOUTLINE NO.
LAND
PATTERN NO.
28 QSOPE28-1
21-0055
90-0173
32 TQFN-EPT3256-1
21-0183
90-0134
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
MAX9526
Low-Power, High-Performance
NTSC/PAL Video Decoder
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600