MAXIM MAX9526 Technical data

General Description

The MAX9526 is a low-power video decoder that con­verts NTSC or PAL composite video signals to 8-bit or
10-bit YCbCr component video compliant with the ITU­R BT.656 standard. The device powers up in fully oper­ational mode and automatically configures itself to
decode the detected input standard. The MAX9526
typically consumes 200mW of power in normal opera­tion and typically less than 100µW in shutdown mode.

An internal 10-bit, 54MHz analog-to-digital converter
(ADC) samples the input with four times oversampling.
The MAX9526 features a DC restoration circuit with off­set correction and automatic gain control to accurately
optimize the full-scale range of the ADC.

An integrated analog anti-aliasing filter eliminates the
need for external filtering. The MAX9526 includes a 2:1
input multiplexer with automatic signal selection based
on activity at the inputs.

An internal line-locked phase-locked loop (PLL) gener­ates the sample clock and the line-locked clock (LLC)
output to provide an ITU-compliant output. Alternatively,
the PLL can be configured to provide a sample clock
and output clock at 2x and 1x the frequency of the
crystal oscillator, respectively.

The MAX9526 provides a multiline adaptive comb filter to
reduce cross-chrominance and cross-luminance artifacts.

A single 1.8V supply is used for both the digital and
analog supplies. The digital outputs operate from a
separate +1.7V to +3.45V supply to allow direct con­nection to a wide range of digital processors. The
MAX9526 operates over the -40°C to +125°C automo­tive temperature range and is available in both a
28-pin QSOP and a 32-pin TQFN (5mm x 6mm).

Applications

Automotive Entertainment Systems

Collision Avoidance Systems

Security Surveillance/CCTV Systems

Televisions

Features

o Supports All NTSC and PAL Standards

NTSC M, NTSC J, NTSC 4.43,
PAL B/G/H/I/D, PAL M, PAL N, PAL 60

o Easy to Configure and Operate with Only

16 User-Programmable Registers

o Automatic Configuration and Standard Select
o 10-Bit 4x Oversampling (54Msps) ADC with True

10-Bit Digital Processing

o Flexible Output Formatting

10-Bit Parallel ITU-R BT.656 Output with

Embedded TRS

8-Bit Parallel ITU-R BT.656 Output with Separate

HS and VS

o +1.8V Digital and Analog Supply Voltage
o +1.7V to +3.45V Digital I/O Supply Voltage
o Full Automotive Temperature Range (-40°C to

+125°C)

o Low-Power Modes

Shutdown (< 100µW typ)
Sleep Mode with Continuous Activity Detection

(< 5mW typ)

o 2-to-1 Video Input Mux with AGC

MAX9526

Low-Power, High-Performance

NTSC/PAL Video Decoder

________________________________________________________________

Maxim Integrated Products

1

19-4535; Rev 3; 2/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

ANALOG

FRONT-END

DIGITAL

DECODER

OUTPUT

PROCESSING

SYNC

PROCESSING,

CLOCK

GENERATION,

AND PLL

I

2

C INTERFACE

AND REGISTERS

V

IN1

V

IN2

XTAL/OSC

XTAL2

SDA
SCL

DEVADDR

IRQ

D9–D0

LLC

CLOCK

10

1010

NONSTD

VIDEO

MAX9526

Functional Diagram

Ordering Information

+

Denotes lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

*

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

MAX9526AEI+ -40°C to +125°C 28 QSOP

MAX9526AEI/V+ -40°C to +125°C 28 QSOP

MAX9526ATJ+ -40°C to +125°C 32 TQFN-EP*

MAX9526ATJ/V+ -40°C to +125°C 32 TQFN-EP*

MAX9526

Low-Power, High-Performance
NTSC/PAL Video Decoder

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(V

AVDD

= V

DVDD

= +1.8V, V

DVDDIO

= +3.3V, V

AGND

= V

DGND

= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDD to AGND .......................................................-0.3V to +2V

DVDD to DGND ........................................................-0.3V to +2V

DVDDIO to DGND .................................................-0.3V to +3.6V

AGND to DGND.....................................................-0.1V to +0.1V

D9–D0, LLC to DGND .........................-0.3V to (DVDDIO + 0.3V)

V

IN1

, V

IN2

, V

REF

to AGND .......................-0.3V to (AVDD + 0.3V)

XTAL/OSC, XTAL2 to AGND ....................................-0.3V to +2V

IRQ, SDA, SCL, DEVADR to DGND ......................-0.3V to +3.6V

Continuous Current In/Out All Pins ...................................±50mA

Continuous Power Dissipation (T

A

= +70°C)

28-Pin QSOP Single-Layer Board

(derate 10.8mW/°C above +70°C).............................860mW

28-Pin QSOP Multilayer Board

(derate 12.6mW°C above +70°C)............................1009mW

32-Pin TQFN Multilayer Board

(derate 20.8mW/°C above +70°C)...........................1663mW

Operating Temperature Range .........................-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

SUPPLIES

Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V

Digital Supply Voltage Range DVDD 1.7 1.8 1.9 V

Digital I/O Supply Voltage Range DVDDIO 1.7 3.3 3.45 V

Analog Supply Current
(Note 2)

Digital Supply Current
(Note 2)

Digital I/O Supply Current
(Note 2)

VIDEO INPUTS, V

Input Voltage Range Guaranteed by full-scale conversion range 0.27 0.5 0.83 V

Input Resistance R

Input Capacitance C

Video Input Reference Voltage

)

(V

REF

Sync-Tip Clamp Level V

Input Clamping Current

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

, AND CLAMP

REF

I

AVDD

I

DVDD

I

DVDDIO

IN

IN

V

REF

CLMP2

Normal operation 42 55

Sleep mode 2.2 3

Shutdown 0.5 100 µA

Normal operation 70 110 mA

Sleep mode 5 1000

Shutdown 5 1000

Normal operation, V

Normal operation, V

Sleep mode, V

Shutdown, V

Activity detect clamp 550 mV

Activity detect clamp,
V

= V

VIN

CLMP2

DVDDIO

= 1.8V 3.5

DVDDIO

= 3.3V 6.4

DVDDIO

= 3.3V 0.8 10

DVDDIO

= 3.3V 0.8 10

+ 150mV

2MΩ

8pF

850 mV

2.0 µA

mA

µA

mA

µA

P-P

MAX9526

Low-Power, High-Performance

NTSC/PAL Video Decoder

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

DVDD

= +1.8V, V

DVDDIO

= +3.3V, V

AGND

= V

DGND

= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.) (Note 1)

Sync Slice Comparator Level Activity detect slicer, referenced to V

DC Restore Current DAC Full­Scale Range (Source and Sink)
(Note 3)

D C Restor e S ync- Ti p Level at

/V

V

IN1

IN2 AGCGAIN = 0xF, ADAGC = 1 0.72

ANALOG INPUT FILTER AND ADC (Note 4)

C utoff Fr eq uency ( 3d B) f

P assb and Fl atness

S top b and C utoff f

S top b and Attenuati on

Ful l - S cal e C onver si on Rang e

AGC Gai n S tep si ze 0.167 V/V

D i ffer enti al N onl i near i ty D N L AGCGAIN = 0x0, ADAGC = 1 ±0.5 LSB

Integ r al N onl i near i ty IN L AGCGAIN = 0x0, ADAGC = 1 ±1 LSB

S i g nal - to- N oi se Rati oS N R

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

3dB

S B

Slow 3

Medium 6

Medium-fast (default) 12

Fast 24

AGCGAIN = 0x0, ADAGC = 1 0.51

f < 5MHz, V
measured at 1MHz

f > f

SB

measured at 1MHz

AGC disabled,
gain programmed
using I
referenced to V

Incl ud es fi l ter + AD C + d i g i tal anti - al i asi ng
fi l ter , i np ut i s - 1d BFS ; AD AG C = 1,
AGC GAIN [ 3:0] = 0x0, d efi ned as r ati o of
RM S si g nal to RM S noi se i n d B

= 0.65V

VIN

, V

= 0.65V

VIN

2

C (ADAGC = 1),

IN1/VIN2

, reference level

P-P

, reference level

P-P

AGC GAIN = 0x0 670 830

AGC GAIN = 0xF 270 330

CLMP

50 mV

13 MHz

0.25 dB

53 MHz

36 dB

mV

58.8 dB

µA

V

P-P

P ow er - S up p l y Rej ecti on P S R

D i ffer enti al P hase DP

AD AGC = 1
AGC GAIN [ 3:0] = 0x0
i np ut l evel = 1M H z si ne
w ave at - 2d BFS

5-step modulated staircase,
f = 3.58MHz or 4.43MHz

1.7V < V

AV D D

1.9V , 1.7V <
V

< 1.9V

D V D D

V

= 1.8V +

AV D D

100m V
500kH z

V

AV D D

100m V

3.58M H z

V

AV D D

100m V

4.43M H z

at

P - P

= 1.8V +

at

P - P

= 1.8V +

at

P - P

<

-40

-67

dBFS

-58

-57

1.0 degrees

MAX9526

Low-Power, High-Performance
NTSC/PAL Video Decoder

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

DVDD

= +1.8V, V

DVDDIO

= +3.3V, V

AGND

= V

DGND

= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.) (Note 1)

D i ffer enti al Gai nDG

2T P ul se Resp onse 2T = 200ns or 250ns 0.4 %

2T Bar Resp onse

2T P ul se to Bar Rati ng

Gr oup D el ay D i stor ti on 100kH z < f < 5M H z±1ns

D EC O D ED L U M IN A N C E A N D C H R O M IN A N C E C H A N N EL S ( N o t e 5 )

C hr om a Band w i d th BW

Lum a Band w i d th BW

Lum a N onl i near i ty 5- step stai r case 1 %

Lum a Li ne Ti m e D i stor ti on ( H - Ti l t) LD M easur ed at the outp ut r eg ar d i ng acti ve vi d eo 0.5 %

Lum a Fi el d Ti m e D i stor ti on ( V - Ti l t) FD M easur ed at the outp ut r eg ar d i ng acti ve vi d eo 0.1 %

D IG IT A L C O M PO SI T E D EC O D ER

Lock Ti m e 3 frames

H or i zontal Li ne Ti m e S tati c V ar i ati on -5 +5 %

M axi m um H or i zontal Li ne Ti m e
Ji tter ( Async M od e)

M axi m um H or i zontal Li ne Ti m e
Ji tter ( LLC m od e)

Li ne- Locked C l ock Fr eq uency f

M i ni m um P eak S i g nal to RM S N oi se P r op er com p osi te d ecod er op er ati on 23 dB

PL L

Async M od e Ji tter Id eal i np ut cl ock 20 ps

Li ne- Locked P LL Loop Band w i d th
S et b y Reg i ster 0x0E [ 2:0]

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

C

L

LLC

5- step m od ul ated stai r case,
f = 3.58M H z or 4.43M H z

Bar ti m e i s 18µs, the beginning 2.5% and
ending 2.5% of the bar time are ignored,
2T = 200ns or 250ns

Bar ti m e i s 18µs, the beginning 2.5% and
ending 2.5% of the bar time are ignored,
2T = 200ns or 250ns

V ar i es w i th i np ut l i ne r ate 27 MHz

000 180

001 250

010 375

011 ( d efaul t) 500

100 750

101 1000

110 1500

111 2000

1%

0.2 %

0.2 %

1 MHz

5.5 MHz

5µs

160 ns

RMS

Hz

MAX9526

Low-Power, High-Performance

NTSC/PAL Video Decoder

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

DVDD

= +1.8V, V

DVDDIO

= +3.3V, V

AGND

= V

DGND

= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.) (Note 1)

CRYSTAL OSCILLATOR

Fr eq uency Fund am ental m od e onl y 27.000 MHz

X TAL/OS C , X TAL2 Inp ut
C ap aci tance

M axi m um Load C ap aci tor C

Fr eq uency Accur acy ±50 ppm

X TAL/OS C Log i c- Low Thr eshol d V

X TAL/OS C Log i c- H i g h Thr eshol d V

X TAL/OS C Inp ut Leakag e C ur r ent I

M axi m um Inp ut C l ock Ji tter 500 ps

I2C SERIAL INTERFACE (Note 6)

Serial-Clock Frequency f

Bus Free Time Between STOP
and START Conditions

Hold Time (REPEATED) START
Condition

SCL Pulse-Width Low t

SCL Pulse-Width High t

Setup Time for a REPEATED
START Condition

Data Hold Time t

Data Setup Time t

SDA and SCL Receiving Rise
Time (Note 7)

SDA and SCL Receiving Fall
Time (Note 7)

SDA Transmitting Fall Time
(Note 7)

Setup Time for STOP Condition t

Bus Capacitance C

Pulse Width of Suppressed Spike t

HIGH-SPEED LOGIC OUTPUTS (D9–D0, LLC)

Output Low Voltage V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

C

,

X TA L

C

X TA L2

, C

L1

IL

IH

IH, IIL

SCL

t

BUF

t

HD, STA

LOW

HIGH

t

SU, STA

HD, DAT

SU, DAT

t

R

t

F

t

F

SU, STO

B

SP

OL

L2

X TAL osci l l ator d i sab l ed , cl ock i np ut m od e
( X TAL_D IS = 1)

X TAL osci l l ator d i sab l ed , cl ock i np ut m od e
( X TAL_D IS = 1)

X TAL osci l l ator d i sab l ed , cl ock i np ut m od e
( X TAL_D IS = 1)

V

V

IOL = 5mA, V

IOL = 2mA, V

= 3.3V

DVDDIO

= 1.8V 150

DVDDIO

= 3.3V 0.4

DVDDIO

= 1.7V 0.4

DVDDIO

0.7 x

V

DVDD

-10 ±0.01 +10 µA

0 400 kHz

1.3 µs

0.6 µs

1.3 µs

0.6 µs

0.6 µs

0 900 ns

100 ns

20 +

0.1C

20 +

0.1C

20 +

0.1C

0.6 µs

050ns

4pF

45 pF

0.3 x

V

DVDD

B

B

B

300 ns

300 ns

250

400 pF

V

V

P-P

ns

V

MAX9526

Low-Power, High-Performance
NTSC/PAL Video Decoder

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

DVDD

= +1.8V, V

DVDDIO

= +3.3V, V

AGND

= V

DGND

= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.) (Note 1)

Note 1: All devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design.
Note 2: NTSC 75% color bar signal applied to video input. C

L

= 10pF on D9–D0 and LLC. External XTAL.

Note 3: Internal test only. Digital core controls sync level adjustment current to adjust offset in analog signal path. Adjust level is

based on value of sync level as converted by ADC. Digital core switches sourcing or sinking current into V

IN1

or V

IN2

nodes. Speed of correction (value of current) is controlled through I2C.

Note 4: Filter and ADC performance measured using ADC outputs prior to composite digital demodulation (decoding).
Note 5: Decoded luminance and chrominance specifications measured using entire signal path from video input to digital compo-

nent outputs.

Note 6: V

DVDDIO

= 1.8V and 3.3V.

Note 7: C

B

is in pF.

Output High Voltage V

Data to LLC Rising Edge Hold
Time

Data to LLC Rising Edge Setup
Time

Rise and Fall Time tR, t

Output Leakage I

OPEN-DRAIN OUTPUTS (SDA and IRQ)

Output High Current I

LOGIC INPUTS (SDA, SCL, DEVADR)

Logic-Low Threshold V

Logic-High Threshold V

Input Leakage Current I

SDA/SCL Off Leakage Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OH

t

HD

t

SU

F

OH, IOL

OL

OH

IL

IH

IH, IIL

IH

IOH = 5mA, V

IOH = 2mA, V

CL = 10pF, V

CL = 25pF, V

= 3.3V

DVDDIO

= 1.7V

DVDDIO

= 1.8V 3

DVDDIO

= 3.3V 3

DVDDIO

V

V

Outputs in high-impedance mode -10 ±0.01 +10 µA

IOL = 3mA, 1.7V < V

IOL = 3mA, 2V < V

V

= 3.3V ±0.01 10 µA

OUT

DVDDIO

< 2V

DVDDIO

< 3.3V 0.4

V

V

AVDD

= V

= V

DVDD

= 0V -10 ±0.01 +10 µA

DVDDIO

x

DVDDIO

0.8V

-

DVDDIO

0.4V

13.5 18.5 23.5 ns

13.5 18.5 23.5 ns

0.2 x

V

DVDDIOOutput Low Voltage V

0.3 x

V

DVDDIO

0.7 x

DVDDIO

-10 ±0.01 +10 µA

V

ns

V

V

V

MAX9526

Low-Power, High-Performance

NTSC/PAL Video Decoder

_______________________________________________________________________________________

7

Typical Operating Characteristics

(V

AVDD

= V

DVDD

= +1.8V, V

DVDDIO

= 3.3V, V

AGND

= V

DGND

= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.)

FULL-SCALE

CONVERSION RANGE

800

)

P-P

600

400

FULL-SCALE INPUT RANGE (mV

200

015

5 10

GAIN CODE (Reg0x0A[3:0]) (DECIMAL)

MAX9526 toc01

0

-10

-20

AMPLITUDE (dB)

-30

-40

0.1 100

ADC SNR

vs. GAIN CODE

60

59

58

57

56

55

SNR (dB)

54

53

52

51

50

015

AGC GAIN CODE (REG0x0A[3:0]) (DECIMAL)

105

MAX9526 toc04

10

0

-10

-20

-30

-40

AMPLITUDE (dB)

-50

-60

-70

-80
030

ANALOG INPUT

FILTER RESPONSE

FREQUENCY (MHz)

DIGITAL COMPOSITE

ANTI-ALIASING FILTER

FREQUENCY (MHz)

101

2010

ADC EFFECTIVE NUMBER OF BITS

vs. INPUT FREQUENCY

10.0

AGCGAIN = 0000
DIGITAL ANTI-ALIASING FILTER DISABLED

9.5

MAX9526 toc02

9.0

8.5

ENOB (LSB)

8.0

7.5

7.0
06

FREQUENCY (MHz)

DIGITAL Y FILTER

10

0

MAX9526 toc05

-10

-20

-30

-40

AMPLITUDE (dB)

-50

-60

-70

-80
030

FREQUENCY (MHz)

MAX9526 toc03

42

MAX9526 toc06

2010

10

0

-10

-20

-30

-40

AMPLITUDE (dB)

-50

-60

NTSC

-70

-80
010

FREQUENCY (MHz)

PAL

6824

MAX9526 toc07

10

0

-10

-20

-30

-40

AMPLITUDE (dB)

-50

-60

-70

-80

DIGITAL Cb/Cr FILTER

DIGITAL NOTCH FILTER

NTSC

0

FREQUENCY (MHz)

PAL

DECODED VIDEO OUTPUT

100% COLOR BARS (Y WAVEFORM)

1000

MAX9526 toc08

800

600

400

AMPLITUDE (LSB)

200

6824

0

060

4020

TIME (µs)

MAX9526 toc09

MAX9526

Low-Power, High-Performance
NTSC/PAL Video Decoder

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(V

AVDD

= V

DVDD

= +1.8V, V

DVDDIO

= 3.3V, V

AGND

= V

DGND

= 0V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.)

VIDEO INPUT AND ADC OUTPUT

100% COLOR BARS

MAX9526 toc16

TIME (µs)

VIDEO INPUT (V)

ADC OUTPUT (LSB)

605010 20 30 40

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0.5

200

400

600

800

1000

0

070

100% COLOR BARS (Cb WAVEFORM)

1000

800

600

400

AMPLITUDE (LSB)

200

0

060

DECODED VIDEO OUTPUT

4020

TIME (µs)

MAX9526 toc10

DECODED VIDEO OUTPUT

100% COLOR BARS (Cr WAVEFORM)

1000

800

600

400

AMPLITUDE (LSB)

200

0

060

4020

TIME (µs)

OUTPUT CLOCK JITTER

vs. PLL BANDWIDTH

4.0

3.5

MAX9526 toc11

3.0

2.5

2.0

1.5

OUTPUT CLOCK JITTER (ns)

1.0

0.5

0

0 2000

PLL BANDWIDTH (Hz)

MAX9526 toc12

15001000500

OUTPUT CLOCK JITTER
vs. VIDEO INPUT LEVEL

1.4

PLLBW = 180Hz

1.3

1.2

1.1

1.0

0.9

OUTPUT CLOCK JITTER (ns)

0.8

0.7

0.6

0.2 0.7
VIDEO INPUT LEVEL (V)

3.0

2.5

MAX9526 toc13

2.0

1.5

1.0

OUTPUT CLOCK JITTER (ns)

0.5

0.60.50.3 0.4

0

OUTPUT CLOCK JITTER

vs. VIDEO INPUT SNR

PLLBW = 180Hz

ASYNC
MODE

LLC
MODE

10 60

TEMPERATURE (°C)

50403020

MAX9526 toc14

SUPPLY CURRENT (µA)

1000

100

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

10

1

0.1

-40
TEMPERATURE (°C)

POWER-SUPPLY REJECTION

vs. FREQUENCY

-40

V

= 1.8V + 100mV

AVDD

-45

-50

-55

-60

-65

AGCGAIN = 1111

-70

AMPLITUDE (dBFS)

-75

-80

-85

-90

0.01 10

P-P

AGCGAIN = 0000

10.1

FREQUENCY (MHz)

DVDD

MAX9526 toc17

MAX9526 toc15

AVDD

DVDDIO

12080400

MAX9526

Low-Power, High-Performance

NTSC/PAL Video Decoder

_______________________________________________________________________________________ 9

Pin Description

PIN

QSOP TQFN-EP

130V

231V

332V

4 1 AGND Analog Ground

5 2 AVDD

6 3 XTAL2

7 4 XTAL/OSC

8 5 I.C. Internal connection. Connect to DGND.

9 6 DEVADR

10, 22 7, 21 DVDD

11, 23 8, 22 DGND Digital Ground. Connect both DGND terminals together.

12 10 SDA

13 11 SCL

NAME FUNCTION

IN1

REF

IN2

Single-Ended Composite Video Input 1. AC-couple the input video signal with a 0.1µF
capacitor.

Video Reference Bypass. Bypass V
possible to the device.

Single-Ended Composite Video Input 2. AC-couple the input video signal with a 0.1µF
capacitor.

Analog Power-Supply Input. Connect to a +1.8V supply. Bypass AVDD to AGND with a

0.1µF capacitor.

External Crystal. Connect XTAL2 to one terminal of the crystal oscillator. Ground XTAL2
when applying an external clock to XTAL/OSC.

External Crystal/Oscillator. Connect XTAL/OSC to one terminal of a crystal or an
external clock source. Connect XTAL2 to the other terminal of the crystal oscillator.

2

I

C Device Address Select Input. Connect to DVDD, DGND, or SDA to select 1 of 3

available I

Digital Power-Supply Input. Connect to a +1.8V supply. Bypass DVDD to DGND with a

0.1µF capacitor in parallel with a 10µF capacitor.

2

C-Compatible Serial-Data Input/Output. Connect a 10kΩ pullup resistor from SDA to

I
DVDDIO for full output swing.

2

I

C-Compatible Serial-Clock Input. Connect a 10kΩ pullup resistor from SCL to

DVDDIO for full output swing.

2

C slave addresses (see Table 5).

to AGND with a 0.1µF capacitor as close as

REF

Hardware Interrupt Open-Drain Output. If not masked, IRQ is pulled low when the bits

14 12 IRQ

13–16, 18,

15–20, 25–28

21 20 LLC

24 23 DVDDIO

— 9, 17, 25, 29 N.C. No Connection. Not internally connected.

— — EP Exposed Pad (TQFN Only). EP is internally connected to GND. Connect EP to GND.

19, 24, 26,

27, 28

D0–D9

in the status register change state. Repeated faults have no effect on IRQ until IRQ is
cleared by reading the corresponding status register. Connect a 10kΩ pullup resistor
from IRQ to DVDDIO for full output swing.

Digital Video Outputs Bit 0–Bit 9, 10-Bit Component Digital Video Outputs. The output
format is 10-bit ITU-R BT.656, 4:2:2 with embedded sync. D1 and D0 can be
configured as horizontal and vertical sync outputs using the Clock and Output register
0x0D. D0 is LSB.

Line-Locked 27MHz Clock Output. With line-locked mode, the LLC clock varies in
response to horizontal line rate of the incoming video. In async mode, the LLC clock is
synchronous to the crystal (see Table 1).

Digital I/O Power-Supply Input. Accepts a +1.7V to +3.45V voltage input. Bypass to
DGND with a 0.1µF capacitor.

MAX9526

Detailed Description

The MAX9526 is a simple, low-power video decoder
that converts all modes of NTSC and PAL composite
video signals to 10-bit YCbCr component video com­patible with the ITU-R BT.656 standard. The device
powers up in fully operational mode and automatically
configures itself to standard NTSC or standard PAL.

An internal 10-bit, 54MHz ADC samples at four times
the sampling rate specified in ITU-R BT.601. The ana­log front-end of the MAX9526 features a DC restoration
circuit, automatic gain control, and automatic offset cor­rection. These blocks are controlled with digital pro­cessing to accurately optimize the full-scale range of
the ADC. An integrated analog anti-aliasing filter elimi­nates the need for off-chip filtering. The device includes
a 2:1 input multiplexer that can be configured to auto­matically select the input based on activity.

The system clock is generated with an external 27MHz
crystal and an internal oscillator. Optionally, a 27MHz or
54MHz external clock can be connected to the
XTAL/OSC input. An internal line-locked digital PLL is
used to generate the 54MHz ADC sample clock that is
synchronous to the incoming video signal with up to
±5% variation in horizontal line length. The digital out­put data and LLC clock are line locked to the video
input and provide a standard ITU output. The PLL can
also be configured to asynchronously sample the input
using the crystal oscillator or external clock.

The MAX9526 provides a 5-line adaptive comb filter to
separate the luminance (Y) and chrominance (C) video
components and reduce cross-chrominance and cross­luminance artifacts. The MAX9526 operates with any
type of standard composite video signal source includ­ing DVD players, video cameras, navigation systems,
and VCRs.

The device powers up in fully operational video
decoder mode. An I

2

C register interface monitors status
and enables programming of many decoder functions
including brightness, contrast, saturation, and hue. The
10-bit output can be reconfigured to provide 8-bit data
with separate horizontal and vertical syncs.

Analog Front-End (AFE)

The MAX9526 AFE implements DC restoration, auto­matic gain control (AGC), analog anti-aliasing filter
(LPF), activity detection, channel selection, and analog­to-digital conversion. A block diagram of the AFE is
shown in Figure 1.

Activity Detect and Automatic Channel Selection

The MAX9526 continuously monitors activity at both
video inputs, V

IN1

and V

IN2

. Activity on the selected
channel is detected using the ADC output. On the
unselected channel an analog sync-tip clamp and sync
slicer are used to detect sync amplitudes greater than
50mV. In sleep mode, the analog sync-tip clamps and
sync slicers are used to detect activity on both inputs,
while the rest of the AFE is in a shutdown state.

The output of the activity detect circuit is reported
through the Status register 0x00. The user must manu­ally select which video input to process by setting
INSEL in register 0x09 appropriately.

The MAX9526 can optionally be configured to automati­cally select the video input that indicates the presence
of activity by setting AUTOSEL = 1 in register 0x09.
When activity is present on both V

IN1

and V

IN2

at
power-up or when there is no activity on either input
channel, V

IN1

is selected. When there is activity on V

IN2

and there is no activity on V

IN1

, then V

IN2

is selected.

When V

IN2

is automatically selected with the presence

of activity, the input only switches to V

IN1

when activity

goes away on V

IN2

.

Low-Power, High-Performance
NTSC/PAL Video Decoder

10 ______________________________________________________________________________________

Figure 1. Analog Front-End

ACTIVITY

DETECT

DC RESTORATION

DAC

V

IN1

V

IN2

V

REF

INTERNAL

BIAS

ANALOG

AGC

ANALOG

LPF

10-BIT

ADC

DIGITAL

CONTROL

DIGITAL

FILTERING

1010

TO DECODER

V

REF

Generation

A differential signal path is used to process the analog
video signal to minimize the effect of noise coupling. A
DC reference (V

REF

) of 850mV is internally generated
and decoupled externally with a 0.1µF capacitor.
Identical signal paths and video buffers are used for
both the selected video input and the video reference
voltage. The signals are converted to a fully differential
signal by the analog AGC circuit.

DC Restoration DAC

The video inputs, V

IN1

and V

IN2

, are AC-coupled to the
MAX9526 with 0.1µF capacitors. The DC restoration cir­cuit sets the sync level at the output of the ADC by sink­ing or sourcing current at the selected video input. A
digital control at the ADC output is used to monitor the
average sync level. An error signal is generated in the
digital control block that is used by a current DAC to
source or sink current to the AC-coupled input to
restore the DC level. The DC restoration circuit also cor­rects the offset in the analog signal chain and sets the
sync level at the ADC output to code 32 (decimal).

Analog Automatic Gain Control (Analog AGC)

The MAX9526 includes an analog variable-gain amplifi­er with a digitally controlled gain for automatic gain
control (AGC). The AGC uses the sync amplitude at the
output of the ADC to control the gain. For signals with­out copy protection, the AGC adjusts the gain until the
sync amplitude is 208 (decimal) codes at the ADC out­put. For inputs with copy protection, the AGC automati­cally compensates for the reduced sync amplitude on
active lines.

The analog AGC loop can be disabled and the gain is
set manually to 1 of 16 values using the Gain Control
register 0x0A. The range of analog gain is 3.5dB to
12dB.

Analog Lowpass Filter (LPF)

The MAX9526 includes a high-performance anti-aliasing
analog lowpass filter with a 3dB bandwidth of 13MHz
(typ) and better than 0.25dB (typ) passband flatness to
5MHz. This eliminates the need for external filtering on
the video inputs. The filter typically provides 36dB atten­uation at 53MHz (1MHz below ADC sample rate).

54Msps Video ADC

A 10-bit, 54Msps ADC converts the filtered analog
composite video signal for digital signal processing
(composite video demodulation).

Digital Filtering

Digital filtering at the ADC output removes any out-of­band interference and improves the signal-to-noise
ratio before decoding. The signal path includes a digi­tal anti-aliasing lowpass filter that has 1dB of passband
flatness to 5.5MHz and a minimum of 45dB of stopband
attenuation for frequencies greater than 9MHz.

Sync Processing, Clock Generation,

and PLL

The sync processing, clock generation, and PLL extract
the timing information from incoming video and gener­ate the clock for the rest of the chip. Figure 2 shows the
block diagram for this block.

Crystal Oscillator/Clock Input

The MAX9526 includes a low-jitter crystal oscillator cir­cuit optimized for use with an external 27MHz crystal.
The device also accepts an external CMOS logic-level
clock at either 27MHz or 54MHz. To use an external
clock (27MHz or 54MHz) instead of a crystal, set
XTAL_DIS = 1 in register 0x0D. To use a 54MHz exter­nal clock instead of a 27MHz clock, SEL_54MHz must
also be set to 1 in register 0x0D.

MAX9526

Low-Power, High-Performance

NTSC/PAL Video Decoder

______________________________________________________________________________________ 11

Figure 2. Sync Processing, Clock Generation, and PLL

FROM AFE

10

SYNC

PROCESSING

XTAL/OSC

OSCILLATOR

XTAL2

NONSTD
VIDEO

CLOCK

GENERATOR

AND PLL

CLOCK

MUX

MUX

MAX9526

Sync Processing

The sync processing block extracts the sync information
and automatically detects 525 line or 625 line inputs.

Clock Generator and PLL

The PLL operates in either line-locked clock (LLC)
mode or async mode. Selection of the mode is con­trolled automatically by the MAX9526 or can optionally
be overwritten with the LLC_MODE bits in PLL Control
register 0x0E.

In LLC mode, a hybrid analog/digital PLL generates a
low-jitter line-locked clock. The 54MHz sample clock is
synchronous to the input video. The LLC clock output is
also synchronous to the input video. The ITU output has
the correct number of samples per line and lines per
field. The PLL is designed to lock to signals with up to
160ns peak jitter. When the jitter exceeds the 160ns
peak, the PLL coasts until the jitter improves. If the jitter
continuously exceeds the 160ns peak, the PLL relocks
and the HLOCK status bit in register 0x00 is set to 0.

In LLC mode, the bandwidth of the PLL can be option­ally programmed to one of eight values between 180Hz
and 2000Hz using the PLLBW bits in PLL Control regis­ter 0x0E. The default value for the PLL bandwidth is
500Hz.

In async mode, the sample clock frequency is generat­ed by multiplying the crystal frequency by a factor of
two and the video signal is sampled asynchronously
with the 2x crystal clock. To eliminate artifacts, the
MAX9526 uses an adaptive poly-phase filter to correct
timing and phase errors introduced by the asynchro­nous sampling. The LLC output is generated by divid­ing the 54MHz sampling clock by two.

The ITU output in async mode has the correct number of
lines per frame and the correct number of pixels per line
except on the first line of each field. The timing correc­tion block uses this line to compensate for timing errors
between the incoming video signal and the crystal. As a
result, the first line of each field is longer or shorter for
several pixels depending on the magnitude of the fre­quency difference between the incoming video signal
and the local crystal. For example, a 100ppm frequency
difference between the incoming video signal and the
crystal results in approximately 23 extra or fewer pixels
on the first line of each field. Line length errors on line
one are of no consequence for most applications since it
is in the vertical blanking interval and does not contain
active video or any other type of data.

The types of inputs that cause the PLL to automatically
switch to async mode are video inputs with a nonstan­dard carrier frequency. For standard video, the carrier

frequency is always a precise multiple of the horizontal
frequency. A typical nonstandard input is video cassette
recorders in which the carrier is not a precise multiple of
the horizontal frequency. The nonstandard detect
(NONSTD) status from the decoder is used to automati­cally switch the PLL to async mode when nonstandard
carrier frequencies are detected. The NONSTD status is
monitored in the Status register 0x00.

Clocking Modes

In addition to automatic configuration, the MAX9526
can also be manually configured to provide maximum
flexibility in setting the clock inputs and outputs of the
chip. Table 1 summarizes the clocking modes that are
supported.

Digital Composite Decoding

Figure 3 shows a block diagram of the digital compos­ite decoder. This block converts the digitized compos­ite video signal to digital component video.

Sync Level Correction and Sync Extraction

The sync extraction function extracts the raw sync sig­nals from the video and the extracted sync information
is sent to the sync processor. The sync level from the
AFE is code 32 (decimal) on a 10-bit scale and the
blanking level is approximately 208 (decimal) codes
above the sync level. The sync slicer default threshold
is set to approximately the middle of the sync pulse at
decimal code 128. The sync slice level can optionally
be manually adjusted using the slice bits in register
0x0F.

The sync level correction block features an optional
digital clamp that can be enabled in register 0x09.
Enabling the digital clamp sets the sync level to code 0
(decimal) and gives higher frequency tracking of the
input signals. When the digital clamp is enabled, the
sync slice level in register 0x0F should be adjusted
accordingly to provide equivalent noise rejection.

Sync Processor and Analog Copy

Protection Detection

The sync processor extracts the horizontal sync and
vertical sync signals. Field pulses and burst gate puls­es are generated based on VSYNC and HSYNC,
respectively. The sync processing block provides sync
timing to measure the sync level and amplitude for the
black level control and composite AGC. The sync
processor also detects incoming video signal stan­dards (525 line NTSC and 625 line PAL). Video stan­dard information is available in Status register 0x01.
The detected video standard is used to automatically
configure the decoder. The MAX9526 detects NTSC-M
(standard NTSC) and PAL B/G/H/I/D (standard PAL)

Low-Power, High-Performance
NTSC/PAL Video Decoder

12 ______________________________________________________________________________________