MAXIM MAX9401, MX9404 User Manual

General Description

The MAX9401/MAX9404 are extremely fast and lowskew quad ECL/PECL differential buffers/receivers for data and clock signals. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state.

The MAX9401 has high-impedance (open) input and the MAX9404 has an integrated 100Ω differential input termination, which reduces external component count. Both devices have double amplitude swing open emitter outputs suitable for driving long cables. The MAX9401/MAX9404 operate over a VCC- VEE= +3.0V to +5.5V supply range, and are specified for operation from -40°C to +85°C. These devices are offered in space-saving 32-pin 5mm x 5mm QFN exposed-paddle (EP) and TQFP packages.

Applications

Data and Clock Driver and Buffer

Central Office Backplane Clock Distribution

DSLAM Backplane

Base Station

ATE

Features

♦ Differential Double-Swing ECL/PECL Outputs

♦ Input Compatible with LVECL/LVPECL

♦ Guaranteed 900mV Differential Output at 3.0GHz

Clock Rate

♦ 365ps Propagation Delay in Asynchronous Mode

♦ 10ps Channel-to-Channel Skew in Synchronous

Mode

♦ Integrated 100Ω Input Terminations (MAX9404)

♦ Compatible +3.3V/+5.0V Nominal Supplies

♦ Selectable Synchronous/Asynchronous

Operation

MAX9401/MAX9404

Quad ECL/PECL Differential

Buffers/Receivers

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

19-2245; Rev 0; 10/01

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

*Future product—contact factory for availability. **EP = Exposed paddle

Ordering Information

PART

TEMP.

PINPACKAGE

INPUT

IMPEDANCE

MAX9401EGJ*

-40°C to

32 QFN-EP**

Open

MAX9401EHJ

-40°C to

32 TQFP

Open

MAX9404EGJ*

-40°C to

32 QFN-EP**

100Ω

MAX9404EHJ

-40°C to

32 TQFP

100Ω

Functional Diagram appears at end of data sheet.

RANGE

+85°C

(5mm x 5mm)

TOP VIEW

SEL

CLK

*EXPOSED PAD AND CORNER PINS ARE CONNECTED TO V

OUT0

OUT3

VEEIN1

IN0

32313029282726

MAX9401/

MAX9404

1011121314

IN3

QFN-EP*

25 IN1

24 V

OUT1

OUT2

IN2

VEEIN1

IN1

24 V

OUT1

OUT2

1611 12

IN2

SEL

CLK

IN0

VCCOUT0

IN0

32 28

IN3

293031

MAX9401 MAX9404

IN3

OUT3

TQFP

OUT0

OUT3

MAX9401/MAX9404

Quad ECL/PECL Differential Buffers/Receivers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VCCto VEE.............................................................-0.3V to +6.0V

All Other Pins to V

...................................-0.3V to (VCC+ 0.3V)

Differential Input Voltage….................................................±3.0V

Continuous Output Current .................................................70mA

Surge Output Current….. ..................................................100mA

Continuous Power Dissipation (T

= +70°C) 32-Pin 5mm x 5mm TQFP (derate 9.5mW/°C

above +70°C)..............................................................761mW

32-Pin 5mm x 5mm QFN-EP (derate 21.3mW/°C

above +70°C)..................................................................1.7W

Junction-to-Ambient Thermal Resistance in Still Air

32-Pin TQFP............................................................+105°C/W

32-Pin QFN-EP…. .....................................................+47°C/W

Junction-to-Ambient Thermal Resistance with

500LFPM Airflow

32-Pin TQFP..............................................................+73°C/W

Junction-to-Case Thermal Resistance

32-Pin TQFP..............................................................+25°C/W

32-Pin QFN-EP… ........................................................+2°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection

Human Body Model (Inputs and Outputs).................>1.25kV

Soldering Temperature (10s) ...........................................+300°C

DC ELECTRICAL CHARACTERISTICS

(VCC- VEE= +3.0V to +5.5V, outputs terminated with 50Ω ±1% to VCC- 3.3V, inputs are driven, unless otherwise noted. Typical values are at V

- VEE= +3.3V, V

IHD

= VCC- 0.9V, V

ILD

= VCC- 1.7V, TA= +25°C, unless otherwise noted.) (Notes 1, 2, 3)

INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL)

Differential Input High Voltage V

Differential Input Low Voltage V

Differential Input Voltage V

Input Current IIH, I

IN to IN Differential Input Resistance

OUTPUTS (OUT_, OUT_)

Differential Output Voltage V

Output Common-Mode Voltage V

POWER SUPPLY

Supply Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IHD

ILD

OCM

Figure 3

Figure 3 V

Figure 3 0.2 3.0 V

MAX9401

MAX9404

EN, EN, SEL, SEL, IN_, IN_, CLK, or CLK = V

IHD

or V

ILD

EN, EN , SEL, SEL, CLK, or CLK = V

IHD

or V

ILD

MAX9404 86 114 Ω

2.0

-10 25

0.2

- V OLFigure 3 1.2 1.4 V

Figure 3

1.8

1.4

(Note 4) 84 118 mA

µA

MAX9401/MAX9404

Quad ECL/PECL Differential

Buffers/Receivers

_______________________________________________________________________________________ 3

Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to V

except VIDand VOD.

Note 3: DC parameters are production tested at T

= +25°C. DC limits are guaranteed by design and characterization over the full

operating range.

Note 4: Outputs are open. Inputs driven high or low. Note 5: Guaranteed by design and characterization. Limits are set to ±6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Device jitter added to the input signal.

AC ELECTRICAL CHARACTERISTICS

(VCC- VEE= +3.0V to +5.5V, outputs terminated with 50Ω ±1% to VCC- 3.3V, outputs are enabled, input transition time = 125ps (20% to 80%), f

CLK

= 3.0GHz, fIN= 1.5GHz, V

IHD

= VEE+2.0V to VCC, V

ILD

= VEEto VCC- 0.2V, V

IHD

- V

ILD

= 0.2 to 3.0V, unless oth-

erwise noted. Typical values are at V

- VEE= +3.3V, V

IHD

= VCC- 0.9V, V

ILD

= VCC- 1.7V, TA= +25°C, unless otherwise noted.)

(Notes 1, 5)

)

(

)

p-p

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IN to OUT Differential Propagation Delay

CLK to OUT Differential Propagation Delay

IN to OUT Channel-to-Channel Skew

CLK to OUT Channel-toChannel Skew

Maximum Clock Frequency f

Maximum Data Frequency f

Added Random Jitter (Note 7) t

Added Deterministic Jitter (Note 7)

IN to CLK Setup Time t

CLK to IN Hold Time t

Output Rise Time t

Output Fall Time t

Propagation Delay Temperature Coefficient

, t

P LH 1

P H L 1

, t

P LH 2

P H L 2

SKD1

SKD2

CLK(MAX

IN(MAX)

SEL = high, Figure 4 300 365 550 ps

SEL = low, Figure 5 580 620 758 ps

SEL = high (Note 6) 15 55 ps

SEL = low (Note 6) 10 40 ps

VOH - VOL ≥ 900mV, SEL = low 3.0 GHz

SEL = high, VOH - VOL ≥ 900mV 1.5 GHz

SEL = low, fIN = 1.5GHz, f clock

= 3.0GHz,

CLK

1.4 2.5

SEL = high, fIN = 1.5GHz 0.9 2.7

SEL = low, f

-1 PRBS pattern

SEL = high, IN_ = 1.5Gbps, 223-1 PRBS pattern

/∆T 1 ps/°C

∆t

Figure 5 80 ps

Figure 4 116 145 ps

Figure 4 115 145 ps

= 3.0GHz, IN_ = 1.5Gbps,

CLK

20 30

36 55

RMS

MAX9401/MAX9404

Quad ECL/PECL Differential Buffers/Receivers

4 _______________________________________________________________________________________

Typical Operating Characteristics

(Outputs terminated with 50Ω to VCC- 3.3V, VCC- VEE= +3.3V, V

IHD

= VCC- 0.9V, V

ILD

= VCC- 1.7V, output is enabled, SEL = high,

SEL = low, input transition time = 125ps (20% to 80%), f

CLK

= 3.0GHz, fIN= 1.5GHz, TA= +25°C, unless otherwise noted.)

100

-40 10-15 35 60 85

SUPPLY CURRENT vs. TEMPERATURE

MAX9401/04 toc01

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

OUTPUTS ARE OPEN; INPUTS ARE HIGH OR LOW

1.6

1.2

0.8

0.4

0 1.50.5 1.0 2.0 2.5 3.0

DIFFERENTIAL OUTPUT VOLTAGE

- VOL) vs. IN_ FREQUENCY

MAX9401/04 toc02

IN_ FREQUENCY (GHz)

DIFFERENTIAL OUTPUT VOLTAGE (mV)

100

106

118

112

124

130

-40 10-15 35 60 85

TRANSITION TIME vs. TEMPERATURE

MAX9401/04 toc03

TEMPERATURE (°C)

TRANSITION TIME (ps)

300

380

540

460

620

700

-40 10-15 35 60 85

PROPAGATION DELAY

vs. TEMPERATURE

MAX9401/04 toc04

TEMPERATURE (°C)

PROPAGATION DEALY (ps)

IN-TO-OUT DELAY

CLK-TO-OUT DELAY

Pin Description

PIN NAME FUNCTION

1, 8, 11, 17,

24, 30

2 SEL

3 SEL Inverting Differential Select Input

4 CLK

5 CLK Noninverting Differential Clock Input

Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.

Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronized mode.

Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = low.

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