General Description
The MAX9400/MAX9402/MAX9403/MAX9405 are
extremely fast, low-skew quad LVECL/ECL or LVPECL/
PECL buffer/receivers designed for high-speed data
and clock driver applications. These devices feature an
ultra-low propagation delay of 335ps and channel-tochannel skew of 16ps in asynchronous mode with
86mA supply current.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low
state.
A variety of input and output terminations are offered for
maximum design flexibility. The MAX9400 has open
inputs and open emitter outputs. The MAX9402 has
open inputs and 50Ω series outputs. The MAX9403 has
100Ω differential input impedance and open emitter
outputs. The MAX9405 has 100Ω differential input
impedance and 50Ω series outputs.
These devices operate with a supply voltage of (VCCVEE) = 2.375V to 5.5V, and are specified for operation
from -40°C to +85°C. These devices are offered in
space-saving 32-pin 5mm ✕ 5mm TQFP and 32-lead
5mm ✕ 5mm QFN packages.
Applications
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
Features
♦ 400mV Differential Output at 3.0GHz Data Rate
♦ 335ps Propagation Delay in Asynchronous Mode
♦ 8ps Channel-to-Channel Skew in Synchronous
Mode
♦ Integrated 50Ω Outputs (MAX9402/MAX9405)
♦ Integrated 100Ω Inputs (MAX9403/MAX9405)
♦ Synchronous/Asynchronous Operation
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
MAX9400
MAX9402
MAX9403
MAX9405
TQFP (5mm x 5mm)
TOP VIEW
32 28
293031
25
26
27
IN0
VCCOUT0
OUT0
IN0
VEEIN1
IN1
10
13
15
14
1611 12
9
IN3
V
CC
OUT3
IN2
V
EE
17
18
19
20
21
22
23
OUT1
24 V
CC
OUT1
V
EE
V
EE
OUT2
OUT2
V
CC
2
3
4
5
6
7
8V
CC
EN
CLK
SEL
1V
CC
SEL
CLK
EN
IN3
OUT3
IN2
Pin Configurations
19-2223; Rev 2; 1/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
PART
TEMP
RANGE
PIN-
DATA
OUTPUT
MAX9400EHJ
Open
MAX9400EGJ*
Open
MAX9402EHJ
50Ω
MAX9402EGJ*
32 QFN
50Ω
MAX9403EHJ
Open
MAX9403EGJ*
32 QFN
Open
MAX9405EHJ
50Ω
MAX9405EGJ*
32 QFN
50Ω
Pin Configurations continued at end of data sheet.
*Future product—contact factory for availability.
PACKAGE
-40°C to +85°C 32 TQFP Open
-40°C to +85°C 32 QFN Open
-40°C to +85°C 32 TQFP Open
-40°C to +85°C
-40°C to +85°C 32 TQFP 100Ω
-40°C to +85°C
-40°C to +85°C 32 TQFP 100Ω
-40°C to +85°C
INPUT
Open
100Ω
100Ω
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC- VEE= 2.375V to 5.5V, MAX9400/MAX9403 outputs terminated with 50Ω ±1% to VCC- 2.0V. Typical values are at VCC- V
EE
=
3.3V, V
IHD
= VCC- 0.9V, V
ILD
= VCC- 1.7V, TA= +25°C, unless otherwise noted.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto VEE................................................................-0.3V to +6V
Inputs to V
EE
...............................................-0.3V to (VCC+ 0.3V)
Differential Input Voltage .......................................................±3V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
Continuous Power Dissipation (T
A
= +70°C)
32-Pin 5mm x 5mm TQFP
(derate 9.5mW/°C above +70°C).................................761mW
32-Lead 5mm x 5mm QFN
(derate 21.3mW/°C above +70°C)...................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin 5mm x 5mm TQFP ........................................+105°C/W
32-Lead 5mm x 5mm QFN ........................................+47°C/W
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
32-Pin 5mm x 5mm TQFP .........................................+73°C/W
Junction-to-Case Thermal Resistance
32-Pin 5mm x 5mm TQFP .........................................+25°C/W
32-Lead 5mm x 5mm QFN .........................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (Inputs and Outputs) ........................2kV
Soldering Temperature (10s) ...........................................+300°C
PARAMETER
CONDITIONS
UNITS
INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL)
Differential Input High Voltage V
IHD
Figure 1
V
EE
+
1.4
V
Differential Input Low Voltage V
ILD
Figure 1
0.2
V
V
CC
- VEE < +3.0V 0.2
Differential Input Voltage V
ID
Figure 1
V
CC
- VEE ≥ +3.0V 0.2 3.0
V
MAX9400/
MAX9402
EN, EN, SEL, SEL , IN_, IN_,
-10 25
Input Current
MAX9403/
MAX9405
EN, EN, SEL, SEL, CLK, or
CLK = V
IHD
or V
ILD
-10 25
µA
Differential Input Resistance
R
IN
MAX9403/MAX9405 86 114 Ω
OUTPUTS (OUT_, OUT_)
Differential Output Voltage
V
OH
-
V
OL
Figure 1
mV
Output Common-Mode Voltage V
OCM
Figure 1
1.5
1.1
V
Internal Current Source I
SINK
MAX9402/MAX9405, Figure 2 6.5 8.3 10 mA
Output Impedance R
OUT
MAX9402/MAX9405, Figure 2 40 50 60 Ω
POWER SUPPLY
MAX9402/MAX9405
180
Supply Current I
EE
MAX9400/MAX9403 86 118
mA
SYMBOL
MIN TYP MAX
IHD
or V
IIH, I
IL
CLK, or CLK = V
ILD
V
EE
600 660
VCC -
VCC -
1.25
150
V
CC
VCC -
VCC -
V
EE
VCC -
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VCC- VEE= 2.375V to 5.5V, outputs terminated with 50Ω ±1% to VCC- 2.0V, enabled, CLK = 3.2GHz, fIN= 1.6GHz, input transition
time = 125ps (20% to 80%), V
IHD
= VEE+ 1.2V to VCC, V
ILD
= VEEto VCC- 0.2V, V
IHD
- V
ILD
= 0.2V to smaller of |VCC- VEE| or 3V,
unless otherwise noted. Typical values are at V
CC
- VEE= 3.3V, V
IHD
= VCC- 0.9V, V
ILD
= VCC1.7V, TA= +25°C, unless otherwise
noted.) (Notes 1, 4)
PARAMETER
CONDITIONS
UNITS
437
IN-to-OUT Differential
Propagation Delay
t
PLH1
t
PHL1
437
ps
597
CLK-to-OUT Differential
Propagation Delay
t
PLH2
t
PHL2
SEL = low, Figure 4
597
ps
IN-to-OUT Channel-to-Channel
Skew (Note 5)
t
SKD1
SEL = high 16 80 ps
CLK-to-OUT Channel-toChannel Skew (Note 5)
t
SKD2
SEL = low 8 55 ps
Maximum Clock Frequency
)
V
OH
-
VOL ≥ 500mV, SEL = low 3.0
GHz
Maximum Data Frequency
)
V
OH
-
VOL ≥ 400mV, SEL = high 2
GHZ
1.3
Added Random Jitter (Note 6) t
RJ
SEL = high, fIN = 2GHz
1.5
ps
(RMS)
SEL = low, f
CLK
= 3.0GHz, IN_ = 3.0Gbps
2
23
- 1 PRBS pattern
17 30
Added Deterministic Jitter
(Note 6)
t
DJ
SEL = high, IN = 2.0Gbps 223 - 1 PRBS
pattern
40 55
ps
(P-P)
IN-to-CLK Setup Time t
S
Figure 4 80 ps
CLK-to-IN Hold Time t
H
Figure 4 80 ps
Output Rise Time t
R
Figure 3 80 120 ps
Output Fall Time t
F
Figure 3 80 120 ps
Propagation Delay Temperature
Coefficient
∆tPD/
∆T
0.2 1
ps/°C
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 6: Device jitter added to the input signal.
SYMBOL
f
CLK(MAX
f
IN(MAX
MIN TYP MAX
MAX9400/MAX9403 237 335
MAX9402/MAX9405
SEL = high, Figure 3
237 335
MAX9400/MAX9403 397 475
MAX9402/MAX9405
SEL = low, f
= 3.0GHz clock, fIN = 1.5GHz 0.64
CLK
397 475
0.74
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VCC- VEE= 3.3V, MAX9400, outputs terminated with 50Ω ±1% to VCC- 2.0V, enabled, SEL = high, CLK = 2.0GHz, fIN= 1.0GHz,
input transition time = 125ps (20% to 80%), V
IHD
= VCC- 1.0V, V
ILD
= VCC- 1.5V, TA= +25°C, unless otherwise noted.)
70
75
85
80
90
95
-40 10-15 35 60 85
SUPPLY CURRENT (IEE)
vs. TEMPERATURE
MAX9400 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
0
200
600
400
800
1000
0 1000500 1500 2000 2500 3000 3500
OUTPUT AMPLITUDE (VOH - VOL)
vs. IN_ FREQUENCY
MAX9400 toc02
IN_ FREQUENCY (MHz)
OUTPUT AMPLITUDE (mV)
100
90
80
70
60
-40 10-15 356085
OUTPUT RISE/FALL
vs. TEMPERATURE
MAX9400 toc03
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)
t
R
t
F
325
335
330
345
340
350
355
-40 85
IN-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
MAX9400 toc04
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
10-15 35 60
t
PLH
t
PHL
520
500
480
460
440
-40 10-15 356085
CLK-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
MAX9400 toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
t
PLH2
t
PHL2
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1, 8,11,
17, 24, 30
V
CC
Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
2 SEL
Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four
channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four
channels to operate in synchronous mode.
3 SEL Inverting Differential Select Input
4 CLK Noninverting Differential Clock Input
5 CLK
Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs
to the outputs when SEL = low.
6EN
Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables
the outputs. Setting EN = low and EN = high (differential low) drives outputs low.
7 EN Inverting Differential Output Enable Input
9 IN3 Noninverting Differential Input 3
10 IN3 Inverting Differential Input 3
12 OUT3 Inverting Differential Output 3
13 OUT3 Noninverting Differential Output 3
14, 20,
21, 27
V
EE
Negative Supply Voltage
15 IN2 Noninverting Differential Input 2
16 IN2 Inverting Differential Input 2
18 OUT2 Inverting Differential Output 2
19 OUT2 Noninverting Differential Output 2
22 OUT1 Noninverting Differential Output 1
23 OUT1 Inverting Differential Output 1
25 IN1 Inverting Differential Input 1
26 IN1 Noninverting Differential Input 1
28 OUT0 Noninverting Differential Output 0
29 OUT0 Inverting Differential Output 0
31 IN0 Inverting Differential Input 0
32 IN0 Noninverting Differential Input 0
— EP Exposed Paddle (MAX940_EGJ only). Connected to VEE internally. See package dimensions.
MAX9400/MAX9402/MAX9403/MAX9405
Detailed Description
The MAX9400/MAX9402/MAX9403/MAX9405 are
extremely fast, low-skew quad LVECL/ECL or LVPECL/
PECL buffer/receivers designed for high-speed data
and clock driver applications. The devices feature an
ultra-low propagation delay of 335ps and channel-tochannel skew of 16ps in asynchronous mode with an
86mA supply current.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low state.
A variety of input and output terminations are offered
for maximum design flexibility. The MAX9400 has open
inputs and open-emitter outputs. The MAX9402 has
open inputs and 50Ω series outputs. The MAX9403 has
100Ω differential input impedance and open-emitter
outputs. The MAX9405 has 100Ω differential input
impedance and 50Ω series outputs.
Supply Voltage
The MAX9400/MAX9402/MAX9403/MAX9405 are designed for operation with a single supply. Using a single
negative supply of VEE= -2.375V to -5.5V (VCC= ground)
yields LVECL/ECL-compatible input and output levels.
Using a single positive supply of VCC= 2.375V to 5.5V
(VEE= ground) yields LVPECL/PECL input and output
levels.
Data Inputs
The MAX9400/MAX9402 have open inputs and require
external termination. The MAX9403/MAX9405 have integrated 100Ω differential input termination resistors from
IN_ to IN_, reducing external component count.
Outputs
The MAX9402/MAX9405 have internal 50Ω series output termination resistors and 8mA internal pulldown
current sources. Using integrated resistors reduces
external component count.
The MAX9400/MAX9403 have open-emitter outputs. An
external termination is required. See the Output
Termination section.
Enable
Setting EN = high and EN = low enables the device.
Setting EN = low and EN = high forces the outputs to a
differential low, and all changes on CLK, SEL, and IN_
are ignored.
Asynchronous Operation
Setting SEL = high and SEL = low enables the four
channels to operate independently as buffer/receivers.
The CLK signal is ignored in this mode. In asynchronous mode, the CLK signal should be set to either a
logic low or high state to minimize noise coupling.
Synchronous Operation
Setting SEL = low and SEL = high enables all four
channels to operate in synchronous mode. In this
mode, buffered inputs are clocked into flip-flops simultaneously on the rising edge of the differential clock
input (CLK and CLK).
Differential Signal Input Limit
The maximum signal magnitude of the differential
inputs is VCC- VEEor 3V, whichever is less.
Applications Information
Input Bias
Unused inputs should be biased or driven as shown in
Figure 5. This avoids noise coupling that might cause
toggling at the unused outputs.
Output Termination
Terminate open-emitter outputs (MAX9400/MAX9403)
through 50Ω to VCC- 2V or use an equivalent Thevenin
termination. Terminate both outputs and use identical
termination on each for the lowest output-to-output
skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if
OUT_ is used as a single-ended output, terminate both
OUT_ and OUT_.
Ensure that the output currents do not exceed the current limits as specified in the Absolute Maximum
Ratings table. Under all operating conditions, the
device’s total thermal limits should be observed.
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity. Bypass
VCCto VEEwith high-frequency surface-mount ceramic
0.1µF and 0.01µF capacitors as close to the device as
possible with the 0.01µF capacitor closest to the device
pins. Use multiple bypass vias for connection to minimize inductance.
Circuit Board Traces
Input and output trace characteristics affect the performance of the MAX9400/MAX9402/MAX9403/MAX9405.
Connect each of the inputs and outputs to a 50Ω char-
acteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode
noise immunity by maintaining the distance between
differential traces and avoid sharp corners. Minimize
the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω char-
Quad Differential LVECL/LVPECL
Buffer/Receivers
6 _______________________________________________________________________________________
acteristic impedance through connectors and across
cables. Minimize skew by matching the electrical
length of the traces.
Chip Information
TRANSISTOR COUNT: 713
PROCESS: Bipolar
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
_______________________________________________________________________________________ 7
V
CC
V
ID
V
ID
= 0V
V
IHD
(MAX) V
CC
V
EE
V
ILD
(MAX)
V
OH
- V
OL
V
OCM
V
OH
V
OL
V
EE
V
ID
V
ID
= 0V
V
IHD
(MIN)
V
ILD
(MIN)
INPUT VOLTAGE DEFINITION OUTPUT VOLTAGE DEFINITION
Figure 1. Input and Output Voltage Definitions
IN_
IN_
IN_
IN_
V
CC
OUT_
OUT_
V
CC
V
EE
OUT_
OUT_
50Ω
50Ω
8mA8mA
MAX9400/MAX9402 MAX9403/MAX9405
MAX9402/MAX9405
MAX9400/MAX9403
100Ω
Figure 2. Input and Output Configurations
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
8 _______________________________________________________________________________________
t
PLH1
t
PHL1
VOH - V
OL
V
IHD
- V
ILD
VOH - V
OL
VOH - V
OL
t
R
t
F
80%
20% 20%
80%
DIFFERENTIAL OUTPUT
WAVEFORM
IN_
IN_
OUT_
OUT_
OUT_ - OUT_
SEL = HIGH
EN = HIGH
Figure 3. IN-to-OUT Propagation Delay and Transition Timing Diagram
V
IHD
- V
ILD
V
IHD
- V
ILD
V
IHD
- V
ILD
CLK
CLK
IN_
IN_
OUT_
OUT_
t
H
t
S
t
H
t
PLH2
t
PHL2
SEL = LOW
EN = HIGH
Figure 4. CLK-to-OUT Propagation Delay Timing Diagram
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
_______________________________________________________________________________________ 9
IN_
IN_
100Ω
1kΩ
V
CC
V
EE
1/4 MAX9400/MAX9402
OUT_
OUT_
IN_
IN_
1kΩ
V
CC
V
EE
1/4 MAX9403/MAX9405
OUT_
OUT_
100Ω
Figure 5. Input Bias Circuits for Unused Inputs
32
31
30
29
28
27
26
IN0
IN0
V
CC
OUT0
OUT0
VEEIN1
25 IN1
9
10
11
12
13
14
15
IN3
IN3
V
CC
OUT3
OUT3
V
EE
IN2
16
IN2
17
18
19
20
21
22
23
V
CC
*EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE.
OUT2
OUT2
V
EE
V
EE
OUT1
OUT1
8
7
6
5
4
3
2
V
CC
EN
EN
CLK
CLK
SEL
SEL
MAX9400
MAX9402
MAX9403
MAX9405
QFN-EP*
1V
CC
24 V
CC
TOP VIEW
*EXPOSED PADDLE
*
*
*
*
Pin Configurations (continued)
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
10 ______________________________________________________________________________________
Functional Diagram
DQ
CK
D Q
CK
1
0
IN0
IN0
OUT0
OUT0
DQ
CK
D Q
CK
1
0
IN1
IN1
OUT1
OUT1
DQ
CK
D Q
CK
1
0
IN2
IN2
OUT2
OUT2
DQ
CK
D Q
CK
1
0
IN3
IN3
CLK
CLK
SEL
SEL
EN
EN
OUT3
OUT3
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
______________________________________________________________________________________ 11
32L TQFP, 5x5x01.0.EPS
B
1
2
21-0110
PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm
B
2
2
21-0110
PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
12 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.
32L QFN.EPS
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2005 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.
Loading...