MAXIM MAX9390, MAX9391 Technical data

General Description

The MAX9390/MAX9391 dual 2 x 2 crosspoint switches
perform high-speed, low-power, and low-noise signal
distribution. The MAX9390/MAX9391 multiplex one of two
differential input pairs to either or both low-voltage differ­ential signaling (LVDS) outputs for each channel.
Independent enable inputs turn on or turn off each differ­ential output pair.

Four LVCMOS/LVTTL logic inputs (two per channel) con­trol the internal connections between inputs and outputs.
This flexibility allows for the following configurations: 2 x 2
crosspoint switch, 2:1 mux, 1:2 splitter, or dual repeater.
This makes the MAX9390/MAX9391 ideal for protection
switching in fault-tolerant systems, loopback switching for
diagnostics, fanout buffering for clock/data distribution,
and signal regeneration.

Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the common­mode voltage exceeds the specified range. The
MAX9390 provides high-level input fail-safe detection
for LVDS, HSTL, and other GND-referenced differential
inputs. The MAX9391 provides low-level input fail-safe
detection for LVPECL, CML, and other VCC-referenced
differential inputs.

Ultra-low 82ps

(P-P)

(max) pseudorandom bit sequence
(PRBS) jitter ensures reliable communications in high­speed links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switch­ing performance guarantees 1.5GHz operation and less
than 65ps (max) skew between channels.

LVDS inputs and outputs are compatible with the
TIA/EIA-644 LVDS standard. The LVDS outputs drive
100Ω loads. The MAX9390/MAX9391 are offered in a
32-pin TQFP and 5mm x 5mm thin QFN package with
exposed paddle and operate over the extended tem­perature range (-40°C to +85°C).

Also refer to the MAX9392/MAX9393 with flow-through
pinout.

Applications

High-Speed Telecom/Datacom Equipment

Central-Office Backplane Clock Distribution

DSLAM

Protection Switching

Fault-Tolerant Systems

Features

♦ 1.5GHz Operation with 250mV Differential Output

Swing

♦ 2ps

(RMS)

(max) Random Jitter

♦ AC Specifications Guaranteed for 150mV

Differential Input

♦ Signal Inputs Accept Any Differential Signaling

Standard

♦ LVDS Outputs for Clock or High-Speed Data

♦ High-Level Input Fail-Safe Detection (MAX9390)

♦ Low-Level Input Fail-Safe Detection (MAX9391)

♦ +3.0V to +3.6V Supply Voltage Range

♦ LVCMOS/LVTTL Logic Inputs Control Signal

Routing

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2

Crosspoint Switches

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

Ordering Information

19-2829; Rev 1; 7/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*Future product—contact factory for availability.

Pin Configurations continued at end of data sheet.

Functional Diagram and Typical Operating Circuit appear at
end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX9390EHJ -40°C to +85°C 32 TQFP

MAX9390ETJ* -40°C to +85°C 32 Thin QFN

MAX9391EHJ -40°C to +85°C 32 TQFP

MAX9391ETJ* -40°C to +85°C 32 Thin QFN

TOP VIEW

INA1

INA1

INB0

VCCASEL0

293031

MAX9390
MAX9391

INB0

BSEL0

TQFP

INA0

INA0

GND

26

25

27

24 V

CC

OUTA0

23

OUTA0

22

ENA0

21

GND

20

OUTA1

19

OUTA1

18

ENA1

17

14

15

13

CC

V

INB1

INB1

1611 12

BSEL1

OUTB1

OUTB1

GND

ENB0

OUTB0

OUTB0

ASEL1

32 28

1ENB1

2

3

4

5

6

7

8V

CC

10

9

GND

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2
Crosspoint Switches

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, EN_ _ = VCC, VCM= 0.05V to (VCC- 0.6V) (MAX9390), VCM= 0.6V to (VCC- 0.05V)
(MAX9391) T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, |VID| = 0.2V, VCM= +1.2V, TA= +25°C.)

(Notes 1, 2, and 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCto GND...........................................................-0.3V to +4.1V

IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _,

_SEL_ to GND.........................................-0.3V to (V

CC

+ 0.3V)

IN_ _ to IN_ _ ..........................................................................±3V

Short-Circuit Duration (OUT_ _, OUT_ _) ...................Continuous

Continuous Power Dissipation (T

A

= +70°C)
32-Pin QFP (derate 13.1mW/°C

above +70°C).............................................................1047mW

32-Pin 5mm x 5mm Thin QFN (derate 21.3mW/°C

above +70°C).............................................................1702mW

Junction-to-Ambient Thermal Resistance in Still Air

32-Pin QFP..............................................................+76.4°C/W

32-Pin 5mm x 5mm Thin QFN....................................+47°C/W

Junction-to-Case Thermal Resistance

32-Pin 5mm x 5mm Thin QFN......................................+2°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection (Human Body Model)

(IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, SEL_ _) ................±2kV

Soldering Temperature (10s) ...........................................+300°C

LVCMOS/LVTTL INPUTS (EN_ _, _SEL_)

Input High Voltage V

Input Low Voltage V

Input High Current I

Input Low Current I

DIFFERENTIAL INPUTS (IN_ _, IIIINNNN____ ____)

Differential Input Voltage V

Input Common-Mode Range V

Input Current

LVDS OUTPUTS (OUT_ _, OOOOUUUUTTTT____ ____)

Differential Output Voltage V

Change in Magnitude of V
Between Complementary Output
States

Offset Common-Mode Voltage V

Change in Magnitude of V
Between Complementary Output
States

PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS

OD

OS

IH

IL

IH

IL

ID

CM

I

IN_ _

I

IN_ _ MAX9391 |V

OD

∆V

OD

OS

∆V

OS

VIN = +2.0V to V

VIN = 0 to +0.8V 0 10 µA

V

> 0 and V

ILD

MAX9390 0.05 VCC - 0.6

MAX9391 0.6 VCC - 0.05

MAX9390 |VID| < 3.0V -75 +10

,

RL = 100Ω, Figure 2 250 350 450 mV

Figure 2 1.0 50 mV

Figure 2 1.125 1.25 1.375 V

Figure 2 1.0 50 mV

2.0 V

0 0.8 V

CC

< VCC, Figure 1 0.1 3.0 V

IHD

| < 3.0V -10 +100

ID

020µA

CC

V

V

µA

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2

Crosspoint Switches

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, fIN< 1.34GHz, t

R_IN

= t

F_IN

= 125ps, RL= 100Ω±1%, |VID| > 150mV, VCM= +0.075V to (VCC- 0.6V)

(MAX9390 only), V

CM

= +0.6V to (VCC- 0.075V) (MAX9391 only), EN_ _ = VCC, TA= -40°C to +85°C, unless otherwise noted. Typical

values are at V

CC

= +3.3V, |VID| = 0.2V, VCM= +1.2V, fIN= 1.34GHz, TA= +25°C.) (Note 5)

Note 1: Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except V

ID

, VOD, and ∆VOD.

Note 2: Current into the device defined as positive. Current out of the device defined as negative.
Note 3: DC parameters tested at T

A

= +25°C and guaranteed by design and characterization for TA= -40°C to +85°C.

Note 4: Current through either output.
Note 5: Guaranteed by design and characterization. Limits set at ±6 sigma.
Note 6: t

SKEW

is the magnitude difference of differential propagation delays for the same output over same conditions. t

SKEW

=

|t

PHL

- t

PLH

|.

Note 7: Measured between outputs of the same device at the signal crossing points for a same-edge transition, under the same

conditions.

Note 8: Device jitter added to the differential input signal.

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, EN_ _ = VCC, VCM= 0.05V to (VCC- 0.6V) (MAX9390), VCM= 0.6V to (VCC- 0.05V)
(MAX9391) T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, |VID| = 0.2V, VCM= +1.2V, TA= +25°C.)

(Notes 1, 2, and 3)

(

)

(

)

Output Short-Circuit Current
(Either Output Shorted to GND)

Output Short-Circuit Current
(Outputs Shorted Together)

SUPPLY CURRENT

Supply Current I

PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS

V

|I

|I

OS

OSB

CC

V

= ±100m V

ID

|

( N ote 4)

V

= ±100mV, V

ID

|

(Note 4)

RL = 100Ω, EN_ _ = V

OUT_ _

V

OUT_ _

OUT_ _

= V

CC

RL = 100Ω, EN_ _ = VCC, switching at
670MHz (1.34Gbps)

or V

= V

OUT_ _

= 0 30 40

OUT_ _

= 0 18 24

OUT_ _

mA

5.0 12 mA

68 98

68 98

mA

PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS

_SEL_ to Switched Output t

SWITCH

Disable, Time to Differential
Output Low

Enable, Time to Differential
Output High

Switching Frequency f

Low-to-High Propagation Delay t

High-to-Low Propagation Delay t

t

PHD

t

PDH

MAX

PLH

PHL

Figure 3 1.1 ns

Figure 4 1.7 ns

Figure 4 1.7 ns

VOD > 250mV 1.50 2.20 GHz

Figures 1, 5 294 409 565 ps

Figures 1, 5 286 402 530 ps

Pulse Skew |t

Output-to-Output Skew t

Output Low-to-High Transition
Time (20% to 80%)

Output High-to-Low Transition
Time (80% to 20%)

Added Random Jitter t

Added Deterministic Jitter t

PLH

- t

|t

PHL

SKEW

CCS

t

R

t

F

RJ

DJ

Figures 1, 5 (Note 6) 7 97 ps

Figures 5, 6 (Note 7) 10 65 ps

Figures 1, 5; fIN = 100MHz 112 153 185 ps

Figures 1, 5; fIN = 100MHz 112 153 185 ps

f

= 1.34GHz, clock pattern (Note 8) 2 ps

IN_ _

1.34Gbps, 223 - 1 PRBS (Note 8) 55 82 ps

RMS

P-P

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2
Crosspoint Switches

4 _______________________________________________________________________________________

Typical Operating Characteristics

(VCC= +3.3V, |VID| = 0.2V, VCM= +1.2V, fIN= 1.34GHz, TA= +25°C.)

SUPPLY CURRENT

vs. TEMPERATURE

MAX9390 toc01

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

603510-15

58

62

66

70

74

78

82

54

-40 85

VCC = +3.6V

VCC = +3.3V

VCC = +3V

OUTPUT AMPLITUDE

vs. FREQUENCY

MAX9390 toc02

FREQUENCY (GHz)

OUTPUT AMPLITUDE (mV)

2.22.00.2 0.4 0.6 1.0 1.2 1.4 1.60.8 1.8

50

100

150

200

250

300

350

400

0

02.4

OUTPUT RISE AND FALL TIMES

vs. TEMPERATURE

MAX9390 toc03

TEMPERATURE (°C)

RISE/FALL TIME (ps)

603510-15

130

140

150

160

170

180

120

-40 85

t

F

fIN = 100MHz

t

R

PROPAGATION DELAY

vs. TEMPERATURE

MAX9390 toc04

TEMPERATURE (°C)

PROPAGATION DELAY (ps)

603510-15

360

370

380

390

400

410

420

430

440

450

350

-40 85

MAX9390

DIFFERENTIAL INPUT CURRENT

vs. TEMPERATURE

MAx9390 toc05

TEMPERATURE (°C)

INPUT CURRENT (µA)

603510-15

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

5

10

-50

-40 85

VIN = -0.1V

VIN = 3V

MAX9391

DIFFERENTIAL INPUT CURRENT

vs. TEMPERATURE

MAX9390 toc06

TEMPERATURE (°C)

INPUT CURRENT (µA)

603510-15

0

10

20

30

40

50

60

70

80

-10

-40 85

VIN = 3.2V

VIN = 0.3V

MAX9390 INPUT CURRENT vs. V

IHD

MAX9390 toc07

V

IHD

(V)

INPUT CURRENT (µA)

3.33.02.4 2.70.6 0.9 1.2 1.5 1.8 2.10.3

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

5

10

-50

03.6

IN_ _ OR
IN_ _ = GND

VCC = +3V

VCC = +3.6V

MAX9391

DIFFERENTIAL INPUT CURRENT vs. V

ILD

MAX9390 toc08

V

ILD

(V)

INPUT CURRENT (µA)

3.33.02.4 2.70.6 0.9 1.2 1.5 1.8 2.10.303.6

-10

10

0

40

30

20

50

60

70

80

VCC = +3.6V

VCC = +3V

IN_ _ OR
IN_ _ = V

CC

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2

Crosspoint Switches

_______________________________________________________________________________________ 5

Pin Description

PIN NAME FUNCTION

1 ENB1

2 OUTB1

3 OUTB1

4, 9,

20, 25

5 ENB0

6 OUTB0

7 OUTB0

8, 13,

24, 29

10 INB0

11 INB0

GND Ground

V

B1 Output Enable. Drive ENB1 high to enable the B1 LVDS outputs. An internal 435kΩ resistor pulls ENB1
low when unconnected.

B1 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTB1 and OUTB1 at the
receiver inputs to ensure proper operation.

B1 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTB1 and OUTB1 at the
receiver inputs to ensure proper operation.

B0 Output Enable. Drive ENB0 high to enable the B0 LVDS outputs. An internal 435kΩ resistor pulls ENB0
low when unconnected.

B0 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTB0 and OUTB0 at the
receiver inputs to ensure proper operation.

B0 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTB0 and OUTB0 at the
receiver inputs to ensure proper operation.

Power-Supply Input. Bypass each VCC to GND with 0. 1µF and 0.01µF ceramic capacitors. Install both

CC

bypass capacitors as close to the device as possible, with the 0.01µF capacitor closest to the device.

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
unconnected (MAX9391).

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V
pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).

pulls

CC

CC

12 BSEL0

14 INB1

15 INB1

16 BSEL1

Input Select for B0 Output. Selects the differential input to reproduce at the B0 differential outputs. Connect
BSEL0 to GND or leave open to select the INB0 (INB0) set of inputs. Connect BSEL0 to V
INB1 (INB1) set of inputs. An internal 435kΩ resistor pulls BSEL0 low when unconnected.

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
unconnected (MAX9391).

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V
pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).

Input Select for B1 Output. Selects the differential input to reproduce at the B1 differential outputs. Connect
BSEL1 to GND or leave open to select the INB0 (INB0) set of inputs. Connect BSEL1 to VCC to select the
INB1 (INB1) set of inputs. An internal 435kΩ resistor pulls BSEL1 low when unconnected.

to select the

CC

CC

pulls

CC

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2
Crosspoint Switches

6 _______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

17 ENA1

18 OUTA1

19 OUTA1

21 ENA0

22 OUTA0

23 OUTA0

26 INA0

27 INA0

28 ASEL0

A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An internal 435kΩ resistor pulls ENA1
low when unconnected.

A1 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTA1 and OUTA1 at the
receiver inputs to ensure proper operation.

A1 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTA1 and OUTA1 at the
receiver inputs to ensure proper operation.

A0 Output Enable. Drive ENA0 high to enable the A0 LVDS outputs. An internal 435kΩ resistor pulls ENA0
low when unconnected.

A0 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTA0 and OUTA0 at the
receiver inputs to ensure proper operation.

A0 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTA0 and OUTA0 at the
receiver inputs to ensure proper operation.

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V
pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
unconnected (MAX9391).

Input Select for A0 Output. Selects the differential input to reproduce at the A0 differential outputs. Connect
ASEL0 to GND or leave open to select the INA0 (INA0) set of inputs. Connect ASEL0 to V
INA1 (INA1) set of inputs. An internal 435kΩ resistor pulls ASEL0 low when unconnected.

CC

pulls

CC

to select the

CC

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V

30 INA1

31 INA1

32 ASEL1

— EP Exposed Paddle (QFN Package Only). Connect to GND for optimal thermal and EMI characteristics.

pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).

LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
unconnected (MAX9391).

Input Select for A1 Output. Selects the differential input to reproduce at the A1 differential outputs. Connect
ASEL1 to GND or leave open to select the INA0 (INA0) set of inputs. Connect ASEL1 to VCC to select the
INA1 (INA1) set of inputs. An internal 435kΩ resistor pulls ASEL1 low when unconnected.

CC

CC

pulls

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2

Crosspoint Switches

_______________________________________________________________________________________ 7

Figure 1. Output Transition Time and Propagation Delay Timing
Diagram

Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram

Figure 2. Test Circuit for VODand V

OS

V

OUT_ _

V

OUT_ _

V

V

IN_ _

IN_ _

= 0

V

ID

t

PLH

= 0

V

OD

80%

t

R

V

= V

ID

VOD = V

OD

IN_ _

OUT_ _

= 0

- V

- V

IN_ _

OUT_ _

50% V

20%

t

AND t

PLH

MEASURED FOR ANY COMBINATION OF _SEL0 AND _SEL1.

PHL

80%

50%

= 0

V

ID

t

PHL

V

OD

V

OD

t

F

= 0

= 0

20%

V

IHD

V

ILD

IN_0

IN_0

= 0

V

ID

1/4 MAX9390/MAX9391

IN_ _

IN_ _

EN_ _ = HIGH
VID = V

IN_ _

- V

IN_ _

∆VOD = VOD - VOD*

= VOS - VOS*

∆V

OS

AND V

V

OD

V

OD

ARE MEASURED WITH VID = +100mV

OS

* AND VOS* ARE MEASURED WITH VID = -100mV

V

IHD

V

OUT_ _

V

OD

RL/2

V

OS

/2

R

L

OUT_ _

ILD

IN_1

= 0

V

ID

IN_1

1.5V

_SEL_

OUT_ _

V

IN_0 IN_0

= 0

OD

OUT_ _

t

SWITCH

EN_0 = EN_1 = HIGH
V

= V

- V

ID

IN_ _

IN_ _

IN_1

1.5V

V

OD

V

IHD

V

ILD

V

IH

V

IL

= 0

t

SWITCH

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2
Crosspoint Switches

8 _______________________________________________________________________________________

Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram

Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit

IN_ _

IN_ _

1/4 MAX9390/MAX9391

PULSE

GENERATOR

50Ω

RL = 100Ω ±1%

= 1.0pF

C

L

OUT_ _

C

L

RL/2

L

/2

+1.25V

OUT_ _

R

C

L

V

V

WHEN VID = +100mV

OUT_ _

V

WHEN VID = -100mV

OUT_ _

V

WHEN VID = -100mV

OUT_ _

V

WHEN VID = +100mV

OUT_ _

EN_ _

_SEL0

IN_0

0

1

PULSE

GENERATOR

IN_0

MAX9390
MAX9391

1.5V

t

t

PHD

PHD

50%

50%

VID = V

C

1.5V

t

PDH

t

PDH

- V

IN_ _

IN_ _

C

L

L

R

L

OUT_0

OUT_0

3V

0

50%

50%

50Ω

50Ω

IN_1

IN_1

EN_0 = EN_1 = HIGH
1 CHANNEL SHOWN

0

1

_SEL1

RL = 100Ω ±1%
C

= 1.0pF

L

C

L

C

L

R

L

OUT_1

OUT_1

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2

Crosspoint Switches

_______________________________________________________________________________________ 9

Detailed Description

The LVDS interface standard provides a signaling
method for point-to-point communication over a con­trolled-impedance medium as defined by the ANSI
TIA/EIA-644 standard. LVDS utilizes a lower voltage
swing than other communication standards, achieving
higher data rates with reduced power consumption,
while reducing EMI emissions and system susceptibility
to noise.

The MAX9390/MAX9391 1.5GHz dual 2 x 2 crosspoint
switches optimize high-speed, low-power, point-to­point interfaces. The MAX9390 accepts LVDS and
HSTL signals, while the MAX9391 accepts LVPECL and
CML signals. Both devices route the input signals to
either or both LVDS outputs.

When configured as a 1:2 splitter, the outputs repeat
the selected inputs. This configuration creates copies
of signals for protection switching. When configured as
a repeater, the device operates as a two-channel
buffer. Repeating restores signal amplitude, allowing
isolation of media segments or longer media drive.
When configured as a 2:1 mux, select primary or back­up signals to provide a protection-switched, fault-toler­ant application.

Input Fail-Safe

The differential inputs of the MAX9390/MAX9391 pos­sess internal fail-safe protection. Fail-safe circuitry
forces the outputs to a differential low condition for
undriven inputs or when the common-mode voltage
exceeds the specified range. The MAX9390 provides
high-level input fail-safe detection for LVDS, HSTL, and
other GND-referenced differential inputs. The MAX9391
provides low-level input fail-safe detection for LVPECL,
CML, and other VCC-referenced differential inputs.

Select Function

The _SEL_ logic inputs control the input and output sig­nal connections. Two logic inputs control the signal rout­ing for each channel. _SEL0 and _SEL1 allow the
devices to be configured as a differential crosspoint
switch, 2:1 mux, dual repeater, or 1:2 splitter (Figure 7).
See Table 1 for mode-selection settings (insert A or B for
the _). Channels A and B possess separate select
inputs, allowing different configurations for each channel.

Enable Function

The EN_ _ logic inputs enable and disable each set of
differential outputs. Connect EN_ 0 to V

CC

to enable

the OUT_0/OUT_0 differential output pair. Connect
EN_0 to GND to disable the OUT_0/OUT_0 differential
output pair. The differential output pairs assert to a dif­ferential low condition when disabled.

Figure 6. Output Channel-to-Channel Skew

Figure 7. Programmable Configurations

V

OUT_0

VOD = 0

V

OUT_0

t

CCS

V

OUT_1

V

= 0 VOD = 0

OD

V

OUT_1

VOD = V

t

MEASURED WITH _SEL0 = _SEL1 = HIGH OR LOW

CCS

(1:2 SPLITTER CONFIGURATION).

OUT_ _

- V

OUT_ _

VOD = 0

t

CCS

IN_0

IN_1

2 x 2 CROSSPOINT

IN_0

IN_1

2:1 MUX

IN_0 OR IN_1

1:2 SPLITTER

IN_0

IN_1

DUAL REPEATER

OUT_0

OUT_1

OUT_0 OR OUT_1

OUT_0

OUT_1

OUT_0

OUT_1

MAX9390/MAX9391

Applications Information

Differential Inputs

The MAX9390/MAX9391 inputs accept any differential
signaling standard within the specified common-mode
voltage range. The fail-safe feature detects common­mode input signal levels and generates a differential
output low condition for undriven inputs or when the
common-mode voltage exceeds the specified range.
Leave unused inputs unconnected or connect to V

CC

for the MAX9390 or to GND for the MAX9391.

Expanding the Number of LVDS Output

Ports

Cascade devices to make larger switches. Consider
the total propagation delay and total jitter when deter­mining the maximum allowable switch size.

Power-Supply Bypassing

Bypass each VCCto GND with high-frequency surface­mount ceramic 0.1µF and 0.01µF capacitors in parallel
as close to the device as possible. Install the 0.01µF
capacitor closest to the device.

Differential Traces

Input and output trace characteristics affect the perfor­mance of the MAX9390/MAX9391. Connect each input
and output to a 50Ω characteristic impedance trace.
Maintain the distance between differential traces and
eliminate sharp corners to avoid discontinuities in dif­ferential impedance and maximize common-mode
noise immunity. Minimize the number of vias on the dif­ferential input and output traces to prevent impedance
discontinuities. Reduce reflections by maintaining the
50Ω characteristic impedance through connectors and
across cables. Minimize skew by matching the electri­cal length of the traces.

Output Termination

Terminate LVDS outputs with a 100Ω resistor between
the differential outputs at the receiver inputs. LVDS out­puts require 100Ω termination for proper operation.

Ensure that the output currents do not exceed the cur­rent limits specified in the Absolute Maximum Ratings.
Observe the total thermal limits of the MAX9390/
MAX9391 under all operating conditions.

Cables and Connectors

Use matched differential impedance for transmission
media. Use cables and connectors with matched differ­ential impedance to minimize impedance discontinu­ities. Avoid the use of unbalanced cables. Balanced
cables such as twisted pair offer superior signal quality
and tend to generate less EMI due to canceling effects.

Board Layout

Use a four-layer printed circuit (PC) board providing
separate signal, power, and ground planes for high­speed signaling applications. Bypass VCCto GND as
close to the device as possible. Install termination
resistors as close to receiver inputs as possible. Match
the electrical length of the differential traces to minimize
signal skew.

Anything-to-LVDS Dual 2 x 2
Crosspoint Switches

10 ______________________________________________________________________________________

Table 1. Input/Output Function Table

_SEL0 _SEL1 OUT_0 / OUT_0 OUT_1 / OUT_1 MODE

0 0 IN_0 / IN_0 IN_0 / IN_0 1:2 splitter
0 1 IN_0 / IN_0 IN_1 / IN_1 Repeater
1 0 IN_1 / IN_1 IN_0 / IN_0 Switch
1 1 IN_1 / IN_1 IN_1 / IN_1 1:2 splitter

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2

Crosspoint Switches

______________________________________________________________________________________ 11

Typical Operating Circuit

+3.0V TO
+3.6V

0.1µF 0.01µF

Z0 = 50Ω

= 50Ω

Z

0

LVCMOS/LVTTL
LOGIC INPUTS

100Ω

INA0

INA0

INA1

INA1

INB0

INB0

INB1

INB1

ENA0

ENA1

ENB0

ENB1

ASEL0

ASEL1

BSEL0

BSEL1

V

CC

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

= 50Ω

Z

0

100Ω

LVDS

RECEIVER

MAX9173

MAX9390
MAX9391

OUTA0

OUTA0

OUTA1

OUTA1

OUTB0

OUTB0

OUTB1

OUTB1

GNDGND GNDGND

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2
Crosspoint Switches

12 ______________________________________________________________________________________

Chip Information

TRANSISTOR COUNT: 1565

PROCESS: Bipolar

Functional Diagram

Pin Configurations (continued)

INA0

INA0

INA1

INA1

OUTB0

OUTB0

ENB0

BSEL0

OUTB1

OUTB1

ENB1

BSEL1

0

1

1

0

0

1

1

0

MAX9390
MAX9391

OUTA0

OUTA0

ENA0

ASEL0

OUTA1

OUTA1
ENA1

ASEL1

INB0

INB0

INB1

INB1

TOP VIEW

INA1

INA1

VCCASEL0

293031

MAX9390
MAX9391

*EXPOSED PADDLE

INB0

INB0

BSEL0

INA0

INA0

GND

26

25

27

14

15

13

CC

V

INB1

1611 12

INB1

OUTB1

OUTB1

GND

ENB0

OUTB0

OUTB0

ASEL1

32 28

1ENB1

2

3

4

5

6

7

8V

CC

9

GND

10

THIN QFN

*CONNECT EXPOSED PADDLE TO GND.

24 V

23

22

21

20

19

18

17

BSEL1

CC

OUTA0

OUTA0

ENA0

GND

OUTA1

OUTA1

ENA1

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2

Crosspoint Switches

______________________________________________________________________________________ 13

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

PIN # 1
I.D.

D

C

0.15 C A

D/2

0.15

C B

E/2

E

0.10

C

A

0.08 C

A3

A1

(NE-1) X e

DETAIL A

L

D2

C

k

e

(ND-1) X e

L

e e

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm

APPROVAL

L

D2/2

b

0.10 M

E2/2

L

DOCUMENT CONTROL NO.

21-0140

C A B

PIN # 1 I.D.

0.35x45

C

E2

L

k

CC

QFN THIN.EPS

L

L

REV.

1

C

2

COMMON DIMENSIONS

NOTES:

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

EXPOSED PAD VARIATIONS

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE

16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm

21-0140

REV.DOCUMENT CONTROL NO.APPROVAL

2

C

2

MAX9390/MAX9391

Anything-to-LVDS Dual 2 x 2
Crosspoint Switches

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

32L TQFP, 5x5x01.0.EPS