MAXIM MAX9386, MAX9387, MAX9388 User Manual

General Description

The MAX9386/MAX9387/MAX9388 are fully differential, high-speed, low-jitter ECL/PECL multiplexers (muxes) with output buffer(s). The devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a single output buffer. The MAX9387 is a 5:1 mux with dual output buffers, and is intended for use in redundant systems. The MAX9388 is a 4:1 mux with a single output buffer, and is pin compatible with the MC100EP57.

Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function on the MAX9386/ MAX9387. The MAX9388 has two select inputs, SEL0 and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip output VBB, nominally VCC- 1.425V. The select inputs accept signals between VCCand VEE. Internal pulldowns to VEEensure a low-default condition if the select inputs are left open.

The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output VBB. All the differential inputs have internal bias and clamping circuits that ensure low-default output states when the inputs are left open.

The MAX9386/MAX9387/MAX9388 operate with a wide supply range

VCC- V

EE|

of 2.375V to 5.5V. The MAX9386/MAX9388 are offered in 20-pin TSSOP and QSOP packages. The MAX9387 is offered in 24-pin TSSOP and QSOP packages.

Applications

High-Speed Telecom and Datacom Applications

Central Office Backplane Clock Distribution

DSLAM/DLC

Features

♦ 318ps (typ) Propagation Delay

♦ >2.7GHz Toggle Frequency

♦ 0.3ps(RMS) Random Jitter

♦ <14ps (max) at +25°C Output-to-Output Skew

(MAX9387)

♦ -2.375V to -5.5V Supplies for Differential

LVECL/ECL

♦ +2.375V to +5.5V Supplies for Differential

LVPECL/PECL

♦ Outputs Low for Open Inputs

♦ Dual Output Buffers (MAX9387)

♦ Pin Compatible with MC100EP57 (MAX9388EUP)

♦ >2kV ESD Protection (Human Body Model)

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers

with Single/Dual Output Buffers

________________________________________________________________ Maxim Integrated Products 1

19-2617; Rev 1; 12/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART

TEMP

RANGE

PIN-

SELECTION

MAX9386EUP

5:1 mux with 1 output buffer

MAX9386EEP*

5:1 mux with 1 output buffer

Pin Configurations

Pin Configurations continued at end of data sheet.

Ordering Information continued at end of data sheet.

*Future product—contact factory for availability.

PACKAGE

-40°C to +85°C 20 TSSOP

-40°C to +85°C 20 QSOP

TOP VIEW

MAX9386

SEL2

SEL1

SEL0D1

BB1

BB2

TSSOP/QSOP

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VCC- VEE...............................................................-0.3V to +6.0V

Inputs (D_, D_, SEL_) to V

......................-0.3V to (VCC+ 0.3V)

D_ to D_ ..............................................................................±3.0V

Continuous Output Current .................................................50mA

Surge Output Current........................................................100mA

BB_

Sink/Source Current ...............................................±600µA

Continuous Power Dissipation (T

= +70°C)

20-Lead TSSOP (derate 11.0mW/°C above +70°C) ....880mW

θJAin Still Air ...........................................................+91°C/W

...........................................................................+20°C/W

24-Lead TSSOP (derate 12.2mW/°C above +70°C) ....976mW

in Still Air ...........................................................+82°C/W

...........................................................................+15°C/W

20-Lead QSOP (derate 9.1mW/°C above +70°C) .......727mW

in Still Air .........................................................+110°C/W

...........................................................................+34°C/W

24-Lead QSOP (derate 9.5mW/°C above +70°C) .......762mW

in Still Air .........................................................+105°C/W

...........................................................................+34°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection Human Body Model (D_, D_, Q_, Q_, SEL_, V

BB_

) .............≥2kV

Lead Temperature (soldering, 10s) .................................+300°C

DC ELECTRICAL CHARACTERISTICS

(VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to V

- 2V. Typical values are at VCC- VEE= 3.3V, V

IHD

= VCC- 1V,

ILD

= VCC- 1.5V, unless otherwise noted.) (Notes 1–4)

-40°C +25°C +85°C

PARAMETER

CONDITIONS

UNITS

INPUT (D_, D_, SEL_)

Single-Ended Input High Voltage

VBB connected to the unused input (Figure 1)

VCC -

Single-Ended Input Low Voltage

VBB connected to the unused input (Figure 1)

VCC -

Differential Input High Voltage

IHD

Figure 1

Differential Input Low Voltage

ILD

Figure 1

- V

< 3.0V

Differential Input Voltage

Figure 1

- V

≥ 3.0V

Input Current I

, VIL, V

IHD

, V

ILD

µA

SYMBOL

MIN TYP MAX MIN TYP MAX MIN TYP MAX

1.225

1.945

1.2

0.095

0.095 3.000 0.095 3.000 0.095 3.000

-100 +100 -100 +100 -100 +100

I H D - V I LD

1.225

0.880

1.625

0.095

1.945

1.2

0.095

0.880

1.625

0.095

1.225

1.945

1.2

0.095

0.880

1.625

0.095

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers

with Single/Dual Output Buffers

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to V

- 2V, V

IHD

- V

ILD

= 0.15V to 1V, fIN≤ 2.5GHz input duty cycle

= 50%, input transition time = 125ps (20% to 80%). Typical values are at V

- VEE= 3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V, fIN=

622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)

-40°C +25°C +85°C

CONDITIONS

UNITS

Differential Input-to-Output Delay

PLHD

PHLD

Figure 2

SEL_-to-Output Delay

PLH2

PHL2

Figure 4, input transition time = 500ps

Output-toOutput Skew

MAX9387 only, Figure 5 (Note 9)

Input-to-Output Skew

SKIO

Figure 6 (Note 10)

SKPP

(Note 11)

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to V

- 2V. Typical values are at VCC- VEE= 3.3V, V

IHD

= VCC- 1V,

ILD

= VCC- 1.5V, unless otherwise noted.) (Notes 1–4)

-40°C +25°C +85°C

PARAMETER

SYMBOL

CONDITIONS

UNITS

OUTPUT (Q_, Q_)

Single-Ended Output High Voltage

Figure 2

Single-Ended Output Low Voltage

Figure 2

Differential Output Voltage

Figure 2

REFERENCE OUTPUT (VBB_ )

Reference Voltage Output

BB1

BB2

(Note 5)

POWER SUPPLY

MAX9386

MAX9387

(Note 6)

MAX9388

1.145

1.945

OH - V OL

+ I

BB1

= ±0.5mA

BB2

1.525

Supply Current

MIN TYP MAX MIN TYP MAX MIN TYP MAX

650 830 650 840 650 840

VCC -

1.425

34 50 36 50 38 50

40 60 42 60 45 60

31 47 33 47 35 47

0.895

1.695

1.325

1.145

1.945

1.525

1.425

1.145

1.945

1.525

0.895

1.695

1.325

VCC -

1.425

0.895

1.695

1.325

PARAMETER SYMBOL

P ar t- to- P ar t S kew

(20% to 80%) (Note 8)

SKOO

MIN TYP MAX MIN TYP MAX MIN TYP MAX

222 309 377 238 318 395 254 333 431

1.64 1.4 1.6

3.9 26 3.9 14 8.0 26

7.3 53 7.7 50 8.3 50

111 130 133

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers

4 _______________________________________________________________________________________

Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into an I/O pin is defined as positive. Current out of an I/O pin is defined as negative. Note 3: DC parameters production tested at T

= +25°C and guaranteed by design over the full operating temperature range.

Note 4: Single-ended data input operation using V

BB_

is limited to (VCC- VEE) ≥ 3.0V.

Note 5: Use V

BB_

only for inputs that are on the same device as the V

BB_

reference.

Note 6: All pins open except V

and VEE.

Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 8: Measured from the 50% point of the input signal with the 50% point equal to V

, to the 50% point of the output signal.

Note 9: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 10: Measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the

differential input signal.

Note 11: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge

transition.

Note 12: Device jitter added to the differential input signal.

AC ELECTRICAL CHARACTERISTICS (continued)

VCC- VEE= 2.375V to 5.5V, outputs loaded with 50Ω±1% to V

- 2V, V

IHD

- V

ILD

= 0.15V to 1V, fIN≤ 2.5GHz input duty cycle

= 50%, input transition time = 125ps (20% to 80%). Typical values are at V

- VEE= 3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V, fIN=

622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)

-40°C +25°C +85°C

PARAMETER

SYMBOL

CONDITIONS

UNITS

Added Random Jitter (Note 12)

Clock

fIN = 2.5GH z

ps(RMS)

Added Deterministic Jitter (Note 12)

PRBS 2

- 1

P-P

Switching Frequency

MAX

VOH - VOL ≥ 300mV, Figure 2

GHz

Select Toggle Frequency

SEL

MHz

Output Rise and Fall Time (20% to 80%)

, tFFigure 2

fIN = 156M H z 0.3 1.15 0.3 1.15 0.3 1.15

pattern

fIN = 622M H z 0.3 1.15 0.3 1.15 0.3 1.15

fIN = 156M b p s 3395 3395 3395

fIN = 622M b p s 2161 2161 2161

MIN TYP MAX MIN TYP MAX MIN TYP MAX

0.3 1.15 0.3 1.15 0.3 1.15

2.7 2.7 2.7

100 100 100

67 105 138 74 117 155 81 128 165

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers

with Single/Dual Output Buffers

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(VCC- VEE= 3.3V, V

IHD

= VCC- 1V, V

ILD

= VCC- 1.5V, outputs loaded with 50Ω±1% to V

- 2V, f

= 1.5GHz, input duty cycle =

50%, input transition time = 125ps (20% to 80%), unless otherwise noted.)

SUPPLY CURRENT (IEE)

vs. TEMPERATURE

MAX9386 toc01

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

6035-15 10

-40 85

OUTPUT AMPLITUDE (VOH - VOL)

vs. FREQUENCY

MAX9386 toc02

FREQUENCY (MHz)

OUTPUT VOLTAGE (mV)

2400200016001200800400

200

400

600

800

1000

0 2800

OUTPUT RISE/FALL vs. TEMPERATURE

MAX9386 toc03

TEMPERATURE (°C)

RISE/FALL TIME (ps)

603510-15

100

110

120

130

140

150

-40 85

FALL

RISE

DIFFERENTIAL PROPAGATION DELAY

vs. INPUT HIGH VOLTAGE

MAX9386 toc04

INPUT HIGH VOLTAGE (V)

PROPAGATION DELAY (ps)

2.72.42.11.81.5

280

290

300

310

320

330

340

350

360

370

270

1.2 3.0

PLHD

PHLD

DIFFERENTIAL PROPAGATION DELAY

vs. TEMPERATURE

MAX9386 toc05

TEMPERATURE (°C)

TRANSITION TIME (ps)

603510-15

290

300

310

320

330

340

350

280

-40 85

PLHD

PHLD

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers

6 _______________________________________________________________________________________

MAX9386

NAME FUNCTION

1 2 D0 Noninverting Differential Input 0. Internal 250kΩ to VCC and 150kΩ to VEE.

23D0 Inverting Differential Input 0. Internal 150kΩ to VCC and 150kΩ to VEE.

3 4 D1 Noninverting Differential Input 1. Internal 250kΩ to VCC and 150kΩ to VEE.

45D1 Inverting Differential Input 1. Internal 150kΩ to VCC and 150kΩ to VEE.

5 6 D2 Noninverting Differential Input 2. Internal 250kΩ to VCC and 150kΩ to VEE.

67D2 Inverting Differential Input 2. Internal 150kΩ to VCC and 150kΩ to VEE.

7 8 D3 Noninverting Differential Input 3. Internal 250kΩ to VCC and 150kΩ to VEE.

89D3 Inverting Differential Input 3. Internal 150kΩ to VCC and 150kΩ to VEE.

9 — D4 Noninverting Differential Input 4. Internal 250kΩ to VCC and 150kΩ to VEE.

10 — D4 Inverting Differential Input 4. Internal 150kΩ to VCC and 150kΩ to VEE.

11 10, 11 V

Negative Supply

12 12 V

BB2

Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass V

BB2

to VCC with a 0.01µF ceramic

capacitor. Otherwise leave open.

13 13 V

BB1

Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass V

BB1

to VCC with a 0.01µF ceramic

capacitor. Otherwise leave open.

14, 20

1, 14

17, 20

Positive Supply. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.

15 15 Q Inverting Output. Typically terminate with 50Ω resistor to VCC - 2V.

16 16 Q Noninverting Output. Typically terminate with 50Ω resistor to VCC - 2V.

17 18 SEL0 Select Logic Input 0. Internal 120kΩ pulldown to VEE.

18 19 SEL1 Select Logic Input 1. Internal 120kΩ pulldown to VEE.

19 — SEL2 Select Logic Input 2. Internal 120kΩ pulldown to VEE.

MAX9386/MAX9388 Pin Description

MAX9388

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers

with Single/Dual Output Buffers

_______________________________________________________________________________________ 7

MAX9387

NAME FUNCTION

1, 18, 24

Positive Supply. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.

2 D0 Noninverting Differential Input 0. Internal 250kΩ to VCC and 150kΩ to VEE.

3 D0 Inverting Differential Input 0. Internal 150kΩ to VCC and 150kΩ to VEE.

4 D1 Noninverting Differential Input 1. Internal 250kΩ to VCC and 150kΩ to VEE.

5 D1 Inverting Differential Input 1. Internal 150kΩ to VCC and 150kΩ to VEE.

6 D2 Noninverting Differential Input 2. Internal 250kΩ to VCC and 150kΩ to VEE.

7 D2 Inverting Differential Input 2. Internal 150kΩ to VCC and 150kΩ to VEE.

8 D3 Noninverting Differential Input 3. Internal 250kΩ to VCC and 150kΩ to VEE.

9 D3 Inverting Differential Input 3. Internal 150kΩ to VCC and 150kΩ to VEE.

10 D4 Noninverting Differential Input 4. Internal 250kΩ to VCC and 150kΩ to VEE.

11 D4 Inverting Differential Input 4. Internal 150kΩ to VCC and 150kΩ to VEE.

12, 13 V

Negative Supply

14 V

BB2

Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass V

BB2

to VCC with a 0.01µF ceramic capacitor. Otherwise

leave open.

15 V

BB1

Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass V

BB1

to VCC with a 0.01µF ceramic capacitor. Otherwise

leave open.

16 Q1 Inverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.

17 Q1 Noninverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.

19 Q0 Inverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.

20 Q0 Noninverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.

21 SEL0 Select Logic Input 0. Internal 120kΩ pulldown to VEE.

22 SEL1 Select Logic Input 1. Internal 120kΩ pulldown to VEE.

23 SEL2 Select Logic Input 2. Internal 120kΩ pulldown to VEE.

MAX9387 Pin Description

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers

8 _______________________________________________________________________________________

Figure 1. Input Definitions

DIFFERENTIAL INPUT VOLTAGE DEFINITION

IHD

- V

ILD

IHD

(MAX)

ILD

(MAX)

IHD

(MIN)

ILD

(MIN)

IHD

- V

ILD

SINGLE-ENDED INPUT VOLTAGE DEFINITION

Figure 2. Differential Input-to-Output Propagation Delay Timing Diagram

IHD

- V

ILD

VOH - V

IHD

PLHD

PHLD

ILD

20%

80%

DIFFERENTIAL OUTPUT

WAVEFORM

0V (DIFFERENTIAL)

20%

80%

Q_ - Q_

Figure 3. Single-Ended Input-to-Output Propagation Delay Timing Diagram

VOH - V

PLH1

PHL1

D_ WHEN D_ = V

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers

with Single/Dual Output Buffers

_______________________________________________________________________________________ 9

Figure 4. Select Input (SEL0)-to-Output (Q_, Q_) Delay Timing Diagram

VOH - V

PLH2

PHL2

IHD

ILD

IHD

- V

ILD

D_, D1

SEL_ = VIL OR OPEN SELO

Figure 5. Output-to-Output Skew (t

SKOO

) Definition (MAX9387 Only)

SKOO

Figure 6. Input-to-Output Skew (t

SKIO)

Definition

D1 OR D2 OR D3

SKIO

= | t

PLHD

* - t

PLHD

** | OR | t

PHLD

* - t

PHLD

** |

PLHD

PHLD

PLHD

** t

PHLD

PLHD

*: MEASURED BETWEEN D0, D0 INPUT, AND OUTPUT.

PLHD

**: MEASURED BETWEEN ANY OTHER INPUT AND OUTPUT.

MAX9386/MAX9387/MAX9388

Detailed Description

The MAX9386/MAX9387/MAX9388 are fully differential, high-speed, and low-jitter ECL/PECL muxes with output buffer(s). The devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a single output buffer. The MAX9387 is a 5:1 mux with dual output buffers, and is intended for use in redundant systems. The MAX9388 is a 4:1 mux with a single output buffer, and is pin compatible with the MC100EP57.

Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function on the MAX9386/ MAX9387. The MAX9388 has two select inputs, SEL0 and SEL1 (see Tables 1 and 2). The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip output V

BB,

nominally VCC-

1.425V. The select inputs accept signals between V

and VEE. Internal 120kΩ pulldowns to VEEensure a low default condition if the select inputs are left open, selecting the D0, D0 input.

The differential inputs D, D can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference voltage

BB.

The reference output voltages, V

BB1

and V

BB2,

provide the reference voltage for single-ended operation for each mux. A single-ended input of at least VBB_ ±100mV or a differential input of at least 100mV switches the outputs to the VOHand VOLlevels specified in the DC Electrical Characteristics. The maximum magnitude of the differential input from D to D is ±3.0V. This limit also applies to the difference between a single-ended input and any reference voltage input.

Specifications for the high and low voltages of a differential input (V

IHD

and V

ILD

) and the differential input

voltage (V

IHD

- V

ILD

) apply simultaneously.

Single-Ended Operation

The recommended supply voltage for single-ended operation is 3.0V to 5.5V. The differential inputs (D, D) can be configured to accept single-ended inputs when operating at supply voltages greater than 2.725V. In single-ended mode operation, the unused complementary input needs to be connected to the on-chip reference voltage, VBB, as a reference. For example, the differential D, D input is converted to a noninverting, single-ended input by connecting VBBto D and connecting the single-ended input to D. Similarly, an inverting input is obtained by connecting VBBto D and connecting the single-ended input to D. With a differential input configured as single ended (using V

), the

single-ended input can be driven to V

or VEEor with

a single-ended LVPECL/LVECL signal.

In single-ended mode operation, a user must ensure that the supply voltage (VCC- VEE) is greater than

2.725V. This is because the input high minimum level must be at (V

+ 1.2V) or higher for proper operation.

The reference voltage, VBB, must be at least (VEE+

1.2V) for the same reason because it becomes the highlevel input when a single-ended input swings below it. The minimum VBBoutput for the MAX9386/MAX9387/ MAX9388 is (VCC- 1.38V). Substituting the minimum VBBoutput for (VBB= VEE+ 1.2V) results in a minimum supply (V

- VEE) of 2.725V. Rounding up to standard supplies gives the recommended single-ended operating supply ranges (VCC- VEE) of 3.0V to 5.5V.

When using the VBBreference output, bypass it with a

0.01µF ceramic capacitor to VCC. If not used, leave it open. The VBBreference can source or sink a total of

0.5mA (shared between V

BB1

and V

BB2

), which is suffi-

cient to drive five inputs.

Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers

10 ______________________________________________________________________________________

Table 1. Mux Select Input Truth Table for MAX9386/MAX9387

SEL2 SEL1 SEL0

DATA OUTPUT

L or open

D0*

L or open

HD1

L or open

HH D3

HXX D4

*Default output when SEL0, SEL1, and SEL2 are left open.

SEL1 SEL0

DATA OUTPUT

L or open L or open D0*

L or open H D1

H L or open D2

HHD3

*Default output when SEL0 and SEL1 are left open.

Table 2. Mux Select Input Truth Table for MAX9388

L or open L or open

L or open

Applications Information

Output Termination

Terminate the outputs through 50Ω to VCC- 2V or use equivalent Thevenin terminations. Terminate each Q and Q output with identical termination on each for minimal distortion. When a single-ended signal is taken from the differential output, terminate both Q and Q.

Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device’s total thermal limits should be observed.

Supply Bypassing

Bypass VCCto VEEwith high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors. For PECL, bypass each VCCto VEE. For ECL, bypass each VEEto VCC. Place the capacitors as close to the device as possible with the 0.01µF capacitor closest to the device pins.

Use multiple vias when connecting the bypass capacitors to ground. When using the V

BB1

or V

BB2

reference outputs, bypass each one with a 0.01µF ceramic capacitor to VCC. If the V

BB1

or V

BB2

reference outputs

are not used, they can be left open.

Traces

Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity.

Signal reflections are caused by discontinuities in the 50Ω characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.

Chip Information

TRANSISTOR COUNT: 583

PROCESS: Bipolar

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers

with Single/Dual Output Buffers

______________________________________________________________________________________ 11

BB1

BB2

MUX

150kΩ

150kΩ120kΩ 150kΩ

250kΩ

D4**

SEL0

SEL1

SEL2**

D4**

Q0 (Q*)

MAX9386 (*) DOES NOT HAVE Q1 AND Q1 OUTPUTS, AND MAX9388 (**) DOES NOT HAVE D4, D4, AND SEL2 INPUTS.

Q1*

MAX9386 MAX9387 MAX9388

Functional Block Diagram

Ordering Information (continued)

PART

TEMP

RANGE

PIN-

SELECTION

MAX9387EUG

5:1 mux with 2

output buffers

M AX 9387E E G *

5:1 mux with 2

output buffers

MAX9388EUP

4:1 mux with 1 output buffer

MAX9388EEP*

4:1 mux with 1 output buffer

*Future product—contact factory for availability.

PACKAGE

-40°C to +85°C 24 TSSOP

-40°C to +85°C 24 QSOP

-40°C to +85°C 20 TSSOP

-40°C to +85°C 20 QSOP

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers

12 ______________________________________________________________________________________

TOP VIEW

SEL1

SEL0

BB1

BB2

MAX9388

SEL2

SEL1

SEL0

BB1

BB2

MAX9387

TSSOP/QSOP

12V

Pin Configurations (continued)

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers

with Single/Dual Output Buffers

______________________________________________________________________________________ 13

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

TSSOP4.40mm.EPS

MAX9386/MAX9387/MAX9388

Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

QSOP.EPS

MAXIM MAX9386, MAX9387, MAX9388 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual