General Description
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make
the device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs and repeats
them at eight differential outputs. Outputs are compatible with LVECL and LVPECL, and can directly drive
50Ω terminated transmission lines.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output voltage V
BB.
All inputs have internal pulldown resistors to
V
EE.
The internal pulldowns and a fail-safe circuit
ensure differential low default outputs when the inputs
are left open or at VEE.
The MAX9325 operates over a 2.375V to 3.8V supply
range for interfacing to differential HSTL and LVPECL
signals. This allows high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For LVECL operation, the device operates with a
-2.375V to -3.8V supply.
The MAX9325 is offered in 28-lead PLCC and spacesaving 28-lead QFN packages. The MAX9325 is specified for operation from -40°C to +85°C.
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Features
♦ 50ps (max) Output-to-Output Skew
♦ 1.5ps
RMS
(max) Random Jitter
♦ Guaranteed 300mV Differential Output at 700MHz
♦ +2.375V to +3.8V Supplies for Differential
HSTL/LVPECL
♦ -2.375V to -3.8V Supplies for Differential LVECL
♦ Two Selectable Differential Inputs
♦ On-Chip Reference for Single-Ended Inputs
♦ Outputs Low for Inputs Open or at V
EE
♦ Pin Compatible with MC100LVE310
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
________________________________________________________________ Maxim Integrated Products 1
28
27
26
25
24
23
22
Q0
Q0
Q1
VCCQ1
Q2
Q2
8
9
10
11
12
13
14
N.C.
Q7
V
CC
Q7
Q6
Q6
15
16
17
18
19
20
21
Q5
*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V
EE
.
Q5
Q4
V
CC
Q4
Q3
Q3
7
6
5
4
3
2
1
CLK1
V
BB
V
CC
CLKO
CLK_SEL
V
EE
MAX9325
QFN
Q0
Q1
V
CC
Q2
N.C.
V
CC
Q7
Q6
Q5
V
CC
Q4
Q3
CLK1
V
BB
V
CC
CLKO
CLK_SEL
V
EE
Q5
Q4
Q3
CLKO
CLKO
CLK1
CLK1
Q7
Q6
Q2
Q1
Q0
PLCC
TOP VIEW
567891011
22
232425 192021
12
13
14
15
16
17
18
26
27
28
1
2
3
4
MAX9325
*
*
*
*
CLK_SEL INPUT CLOCK
INPUT SELECT TRUTH TABLE
L
H
CLK0, CLK0 SELECTED
CLK1, CLK1 SELECTED
Pin Configurations
Ordering Information
19-2511; Rev 3; 11/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX9325EQI -40°C to +85°C 28 PLCC
MAX9325EGI -40°C to +85°C
28 QFN 5mm x 5mm
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
((VCC- VEE) = 2.375V to 3.8V, RL= 50Ω ±1% to V
CC
- 2V. Typical values are at (VCC- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V).)
(Notes 1–4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE...............................................................-0.3V to +4.1V
Inputs (CLK_,
CLK_, CLK_SEL) to VEE......-0.3V to (V
CC
+ 0.3V)
CLK_ to CLK_ .....................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
V
BB
Sink/Source Current................................................±0.65mA
Continuous Power Dissipation (T
A
= +70°C)
28-Lead PLCC (derate 10.5mW/°C above +70°C) .....842mW
θ
JA
in Still Air .............................................................+95°C/W
θ
JC
.............................................................................+25°C/W
28-Lead QFN (derate 20.8mW/°C above +70°C) ....1667mW
θ
JA
in Still Air ............................................................+48°C/W
θ
JC
..............................................................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (CLK_, CLK_, Q_, Q_)....................≥2kV
Soldering Temperature (10s) ...........................................+300°C
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
SINGLE-ENDED INPUT (CLK_SEL)
Single-Ended
Input High
Voltage
V
IH
Figure 1
V
CC
V
CC
V
CC
V
CC
V
CC
V
Single-Ended
Input Low
Voltage
V
IL
Figure 1
V
CC
V
CC
V
CC
V
Input Current I
IN
VIH, V
IL
µA
DIFFERENTIAL INPUT (CLK_, CLK_)
Single-Ended
Input High
Voltage
V
IH
Figure 1
V
CC
V
CC
V
CC
V
Single-Ended
Input Low
Voltage
V
IL
Figure 1
V
CC
V
CC
VCC
V
Differential Input
High Voltage
V
IHD
Figure 1
V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
V
- 1.165
V
EE
CC
- 1.475
- 1.165
V
EE
- 1.475
- 1.165
V
EE
- 1.475
-10.0 +150 -10.0 +150 -10.0 +150
V
CC
- 1.475
V
CC
- 1.165
V
EE
V
EE
+ 1.2
- 1.165
V
EE
V
EE
+ 1.2
V
CC
- 1.165
V
- 1.475
V
CC
EE
V
EE
+ 1.2
V
CC
- 1.475
V
CC
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
((VCC- VEE) = 2.375V to 3.8V, RL= 50Ω ±1% to V
CC
- 2V. Typical values are at (VCC- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V).)
(Notes 1–4)
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
Differential Input
Low Voltage
V
ILD
Figure 1
V
CC
V
CC
V
CC
V
(V
CC
- V
EE
) <
V
CC
V
CC
V
CC
Differential Input
Voltage
V
IHD
-
V
ILD
(VCC - VEE) ≥
3.0V, Figure 1
V
Input Current I
IN
V
IH, VIL
, V
IHD
,
V
ILD
µA
OUTPUT (Q_, Q_)
Single-Ended
Output High
Voltage
V
OH
Figure 2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
Single-Ended
Output Low
Voltage
V
OL
Figure 2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
Differential
Output Voltage
Figure 2
mV
REFERENCE VOLTAGE OUTPUT (VBB)
Reference
Voltage Output
V
BB
IBB = ±0.5mA
(Note 5)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
SUPPLY
Supply Current
I
EE
(Note 6) 35 50 39 55 42 65
mA
3.0V, Figure 1
VOH - V
OL
MIN TYP MAX MIN TYP MAX MIN TYP MAX
V
EE
0.095
- 0.095
- V
EE
0.095 3.0 0.095 3.0 0.095 3.0
-10.0 +150.0 -10.0 +150.0 -10.0 +150.0
- 1.085
- 1.810
- 0.977
- 1.695
- 0.880
- 1.620
535 718 595 749 595 769
V
EE
0.095
- 1.025
- 1.810
- 0.949
- 1.697
- 0.095
- V
EE
- 0.88
V
CC
- 1.62
V
EE
0.095
- 1.025
V
CC
- 1.810
- 0.929
- 1.698
- 0.095
- VEE
- 0.88
V
CC
- 1.62
V
CC
- 1.38
- 1.318
- 1.26
- 1.38
- 1.325
- 1.26
- 1.38
- 1.328
- 1.26
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS—PLCC Package
((VCC- VEE) = 2.375V to 3.8V, RL= 50Ω ±1% to V
CC
- 2V, fIN≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
are at (V
CC
- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V).) (Note 7)
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
Differential
Input-to-Output
Delay
t
PLHD
t
PHLD
Figure 2
ps
Single-Ended
Input-to-Output
Delay
t
PLH
t
PHL
ps
Output-toOutput Skew
(Note 9)
50 ps
Part-to-Part
Skew
t
SKPP
(Note 10)
ps
Added Random
Jitter
t
RJ
fIN = 0.5GHz
clock pattern
(Note 11)
ps
RMS
Added
Deterministic
Jitter
t
DJ
fIN = 1.0Gbps,
2E
23
- 1 PRBS
ps
P-P
Switching
Frequency
f
MAX
VOH - V
OL
≥
300mV clock
pattern
GHz
Output Rise/Fall
Time (20% to
80%)
t
R
, t
F
Figure 2
ps
MIN TYP MAX MIN TYP MAX MIN TYP MAX
525 725 550 750 575 775
Figure 3 (Note 8) 500 750 550 800 600 850
t
SKOO
Differential input
pattern (Note 11)
50 50
160 190 225
1.5 1.5 1.5
100 100 100
1.5 1.5 1.5
140 440 140 440 140 440
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________ 5
AC ELECTRICAL CHARACTERISTICS—QFN Package
((VCC- VEE) = 2.375V to 3.8V, RL= 50Ω ±1% to V
CC
- 2V, fIN≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
are at (V
CC
- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V).) (Note 7)
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
Differential
Input-to-Output
Delay
t
PLHD
t
PHLD
Figure 2
ps
Single-Ended
Input-to-Output
Delay
t
PLH
t
PHL
ps
Output-toOutput Skew
(Note 9)
50 ps
Part-to-Part
Skew
t
SKPP
(Note 10)
ps
Added Random
Jitter
t
RJ
fIN = 0.5GHz
clock pattern
(Note 11)
ps
RMS
Added
Deterministic
Jitter
t
DJ
fIN = 1.0Gbps,
2E
23
- 1 PRBS
95
ps
P-P
Switching
Frequency
f
MAX
VOH - VOL ≥
300mV clock
pattern
GHz
Output Rise/Fall
Time (20% to
80%)
t
R
, t
F
Figure 2
ps
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Note 4: Single-ended input operation using V
BB
is limited to (VCC- VEE) = 3.0V to 3.8V.
Note 5: Use V
BB
only for inputs that are on the same device as the V
BB
reference.
Note 6: All pins open except V
CC
and VEE.
Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8: Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal.
Note 9: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal.
Note 10: Measured between outputs of different parts under identical condition for same-edge transition.
Note 11: Device jitter added to the input signal. Differential input signal.
Figure 3 (Note 8) 253 581 310 586 324 606
t
SKOO
Differential input
pattern (Note 11)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
250 575 298 553 309 576
50 50
192 215 218
1.5 1.5 1.5
95 95
1.5 1.5 1.5
97 411 104 210 111 232
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
6 _______________________________________________________________________________________
SUPPLY CURRENT (IEE)
vs. TEMPERATURE
MAX9325 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
25
30
35
40
45
50
20
-40 85
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
MAX9325 toc02
FREQUENCY (MHz)
OUTPUT VOLTAGE (V)
1000 1500500
300
500
400
600
700
800
0
TRANSITION TIME vs. TEMPERATURE
TRANSITION TIME (ps)
160
240
200
280
320
360
400
MAX9325 toc03
TEMPERATURE (°C)
603510-15-40 85
t
F
t
R
PROPAGATION DELAY
vs. TEMPERATURE
MAX9325 toc05
TEMPERATURE (°C)
603510-15
550
650
750
450
-40 85
PROPAGATION DELAY (ps)
t
PLHD
t
PHLD
Typical Operating Characteristics
(PLCC package, typical values are at (VCC- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V), RL= 50Ω ±1% to V
CC
- 2V, fIN=
500MHz, input transition time = 125ps (20% to 80%).)
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________ 7
Pin Description
PIN
PLCC QFN
NAME FUNCTION
1, 8, 15, 22
V
CC
Positive Supply Voltage. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible, with the smaller
value capacitor closest to the device.
25CLK0 Inverting Differential Clock Input 0. Internal 105kΩ pulldown to VEE.
36V
BB
Reference Output Voltage. Connect to the inverting or noninverting clock input to
provide a reference for single-ended operation. When used, bypass V
BB
to VCC with a
0.01µF ceramic capacitor. Otherwise leave open.
47CLK1 Noninverting Differential Clock Input 1. Internal 105kΩ pulldown to VEE.
58CLK1 Inverting Differential Clock Input 1. Internal 105kΩ pulldown to VEE.
69N.C. Not Connected
710Q7 Inverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V.
912Q7Noninverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V.
10 13 Q6 Inverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V.
11 14 Q6 Noninverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V.
12 15 Q5 Inverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V.
13 16 Q5 Noninverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V.
14 17 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.
16 19 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.
17 20 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.
18 21 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.
19 22 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.
20 23 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.
21 24 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
23 26 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
24 27 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
25 28 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
26 1 V
EE
Negative Supply Voltage
27 2
Clock Select Input. When driven low, the CLK0 input is selected. Drive high to select
the CLK1 Input. The CLK_SEL threshold is equal to VBB. Internal 75kΩ pulldown to VEE.
28 3 CLK0 Noninverting Differential Clock Input 0. Internal 105kΩ pulldown to VEE.
Exposed
Exposed
Pad
—Internally Connected to V
EE
4, 11, 18, 25
CLK_SEL
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
8 _______________________________________________________________________________________
DIFFERENTIAL INPUT VOLTAGE DEFINITION
V
CC
V
CC
V
ILD
(MAX)
V
IHD
(MAX)
V
ILD
(MIN)
V
IHD
(MIN)
V
EE
V
EE
V
BB
V
IH
V
IL
V
IHD
- V
ILD
SINGLE-ENDED INPUT VOLTAGE DEFINITION
V
IHD
- V
ILD
Figure 1. Input Voltage Definitions
CLK
CLK
Q_
Q_
Q_ - Q_
20%
20%
80%
80%
V
IHD
- V
ILD
V
OH
- V
OL
V
OH
- V
OL
V
OH
- V
OL
DIFFERENTIAL OUTPUT WAVEFORM
0V (DIFFERENTIAL)
V
IHD
V
ILD
V
OH
V
OL
t
PLHD
t
R
t
F
t
PHLD
Figure 2. Differential Input (CLK_,
CLK
_) to Output (Q_, Q_) Delay Timing Diagram
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________ 9
Detailed Description
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make the
device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs, and repeats
them at eight differential outputs. Outputs are compatible with LVECL and LVPECL, and can directly drive 50Ω
terminated transmission lines.
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLK_SEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLK_SEL is set by
an internal V
BB
voltage reference. The selected input is
reproduced at eight differential outputs at speeds up to
700MHz.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output voltage (V
BB
). A single-ended input of at least VBB±95mV
or a differential input of at least 95mV switches the outputs to the VOHand VOLlevels specified in the DC
Electrical Characteristics. The maximum magnitude of
the differential input from CLK_ to CLK_ is ±3.0V or
±(VCC- VEE), whichever is less. This limit also applies
to the difference between a single-ended input and any
reference voltage input.
The single-ended CLK_SEL input has a 75kΩ pulldown
to VEEthat selects the default input, CLK0, CLK0, when
CLK_SEL is left open or at VEE. All the differential inputs
have 105kΩ pulldowns to VEE. Internal pulldowns and a
fail-safe circuit ensure differential low default outputs
when the inputs are left open or at VEE.
Specifications for the high and low voltages of a differential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.375V to +3.8V supply
range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.375V to -3.8V supply.
Single-Ended Operation
CLK_SEL is a single-ended input with the input threshold
internally set to VBB, and can be driven to VCCor VEEor
by a single-ended LVPECL/LVECL signal. The CLK_,
CLK_ are differential inputs but can be configured to
accept single-ended inputs when operating at supply
voltages greater than 2.58V. The recommended supply
voltage for single-ended operation is 3.0V to 3.8V. A dif-
OR
V
BB
V
BB
V
BB
V
BB
t
PLH
t
PHL
VOH - V
OL
Q_
Q_
CLK_ WHEN CLK_ = V
BB
V
OH
V
IL
V
IL
V
IH
V
IH
V
OL
CLK_ WHEN CLK_ = V
BB
Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
10 ______________________________________________________________________________________
ferential input is configured for single-ended operation
by connecting the on-chip reference voltage, VBB, to an
unused complementary input as a reference. For example, the differential CLK0, CLK0 input is converted to a
noninverting, single-ended input by connecting VBBto
CLK0 and connecting the single-ended input to CLK0.
Similarly, an inverting input is obtained by connecting
VBBto CLK0 and connecting the single-ended input to
CLK0. With a differential input configured as singleended (using VBB), the single-ended input can be driven
to VCCor VEEor with a single-ended LVPECL/LVECL
signal.
When configuring a differential input as a single-ended
input, a user must ensure that the supply voltage (VCCVEE) is greater than 2.58V. This is because the input
high minimum level must be at (VEE+ 1.2V) or higher
for proper operation. The reference voltage VBBmust
be at least (VEE+ 1.2V) or higher for the same reason
because it becomes the high-level input when the other
single-ended input swings below it. The minimum V
BB
output for the MAX9325 is (VCC- 1.38V). Substituting
the minimum VBBoutput for (VBB= VEE+ 1.2V) results
in a minimum supply (V
CC
- VEE) of 2.58V. Rounding up
to standard supplies gives the single-ended operating
supply ranges (VCC- VEE) of 3.0V to 3.8V for the
MAX9325.
When using the V
BB
reference output, bypass it with a
0.01µF ceramic capacitor to V
CC
. If not used, leave it
open. The VBBreference can source or sink 0.5mA,
which is sufficient to drive two inputs.
Applications Information
Output Termination
Terminate the outputs through 50Ω to (VCC- 2V) or use
equivalent Thevenin terminations. Terminate each Q and
Q output with identical termination on each for low output
distortion. When a single-ended signal is taken from the
differential output, terminate both Q_ and Q_.
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings
table. Under all operating conditions, the device’s total
thermal limits should be observed.
Supply Bypassing
Bypass each VCCto VEEwith high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors. Place the
capacitors as close to the device as possible with the
0.01µF capacitor closest to the device pins.
Use multiple vias when connecting the bypass capacitors to ground. When using the VBBreference output,
bypass it with a 0.01µF ceramic capacitor to VCC. If the
VBBreference is not used, it can be left open.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity.
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Exposed-Pad Package
The 28-lead QFN package (MAX9325EGI) has the
exposed paddle on the bottom of the package that provides the primary heat removal path from the IC to the
PC board, as well as excellent electrical grounding to
the PC board. The MAX9325EGI’s exposed pad is
internally connected to VEE. Do not connect the
exposed pad to a separate circuit ground plane
unless VEEand the circuit ground are the same.
Chip Information
TRANSISTOR COUNT: 1030
PROCESS: Bipolar
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
0
1
Q5
Q6
Q6
Q7
Q7
V
EE
V
EE
CLK1
CLK_SEL
CLK1
105kΩ
75kΩ
V
EE
CLK0
CLK0
105kΩ
MAX9325
Functional Diagram
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
______________________________________________________________________________________ 11
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PLCC.EPS
FAMILY PACKAGE OUTLINE:
20L, 28L, 44L, 52L, 68L PLCC
1
1
21-0049
D
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
D1
D
C
A2
B1
B
A1
A
A3
D2
e
D3D1D
D3
N
22.61
20.320.800D3
D2 0.890 0.930
REF REF
23.62
4.20
2.29
3.69
0.51
0.33
0.66
0.23
9.78
8.89
7.37
5.08
12.32
11.43
9.91
7.62
17.40
16.51
14.99
12.70
MIN
MIN
24.13
25.02
0.1200.090A1
REFD3 0.200
0.485
0.300
0.685
0.500
0.985
D
D1
D2
D3
D1
D
0.650
0.590
0.950
D
D1
D2
D3
0.450
0.390
0.695
0.656
0.630
0.958
0.995
REF
0.495
0.456
0.430
REF
0.050
0.385
INCHES
D
D1D20.350
0.290
MIN
A2
A3
B
B1
C
e
0.145
0.020
0.013
0.026
0.009
0.395
0.356
0.330
MAX
0.156
0.021
0.032
---
0.011
INCHES
A 0.165
MIN
0.180
MAX
3.04
REF
28
44
68
17.65
16.66
16.00
REF
24.33
25.27
12.57
11.58
10.92
REF
AC
AE
AB
10.03
9.04
8.38
MAX
N
20
3.96
---
0.53
0.81
0.28
1.27
AA
4.57
MAX
NOTES:
1. D1 DOES NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED
.20mm (.008") PER SIDE.
3. LEADS TO BE COPLANAR WITHIN .10mm.
4. CONTROLLING DIMENSION: MILLIMETER
5. MEETS JEDEC MO047-XX AS SHOWN IN TABLE.
6. N = NUMBER OF PINS.
REFREFD3 0.600 15.24
17.53
19.05
19.94
D1
D2
D
0.750
0.690
0.785
0.756
0.795
0.730
52
19.20
20.19
18.54
AD
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32L QFN.EPS
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