MAXIM MAX9325 User Manual

General Description

The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPECL inputs and repeats them at eight differential outputs. Outputs are compatible with LVECL and LVPECL, and can directly drive 50Ω terminated transmission lines.

The differential inputs can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output voltage V

BB.

All inputs have internal pulldown resistors to

EE.

The internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at VEE.

The MAX9325 operates over a 2.375V to 3.8V supply range for interfacing to differential HSTL and LVPECL signals. This allows high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For LVECL operation, the device operates with a

-2.375V to -3.8V supply.

The MAX9325 is offered in 28-lead PLCC and spacesaving 28-lead QFN packages. The MAX9325 is specified for operation from -40°C to +85°C.

Applications

Precision Clock Distribution

Low-Jitter Data Repeaters

Features

♦ 50ps (max) Output-to-Output Skew

♦ 1.5ps

RMS

(max) Random Jitter

♦ Guaranteed 300mV Differential Output at 700MHz

♦ +2.375V to +3.8V Supplies for Differential

HSTL/LVPECL

♦ -2.375V to -3.8V Supplies for Differential LVECL

♦ Two Selectable Differential Inputs

♦ On-Chip Reference for Single-Ended Inputs

♦ Outputs Low for Inputs Open or at V

♦ Pin Compatible with MC100LVE310

MAX9325

2:8 Differential LVPECL/LVECL/HSTL Clock and

Data Driver

________________________________________________________________ Maxim Integrated Products 1

VCCQ1

N.C.

*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V

CLK1

CLKO

CLK_SEL

MAX9325

QFN

N.C.

CLK1

CLKO

CLK_SEL

CLKO

CLK1

PLCC

TOP VIEW

567891011

232425 192021

MAX9325

CLK_SEL INPUT CLOCK

INPUT SELECT TRUTH TABLE

CLK0, CLK0 SELECTED

CLK1, CLK1 SELECTED

Pin Configurations

Ordering Information

19-2511; Rev 3; 11/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Functional Diagram appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX9325EQI -40°C to +85°C 28 PLCC

MAX9325EGI -40°C to +85°C 28 QFN 5mm x 5mm

MAX9325

2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

((VCC- VEE) = 2.375V to 3.8V, RL= 50Ω ±1% to V

- 2V. Typical values are at (VCC- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V).)

(Notes 1–4)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VCC- VEE...............................................................-0.3V to +4.1V

Inputs (CLK_,

CLK_, CLK_SEL) to VEE......-0.3V to (V

+ 0.3V)

CLK_ to CLK_ .....................................................................±3.0V

Continuous Output Current .................................................50mA

Surge Output Current........................................................100mA

Sink/Source Current................................................±0.65mA

Continuous Power Dissipation (T

= +70°C)

28-Lead PLCC (derate 10.5mW/°C above +70°C) .....842mW

in Still Air .............................................................+95°C/W

.............................................................................+25°C/W

28-Lead QFN (derate 20.8mW/°C above +70°C) ....1667mW

in Still Air ............................................................+48°C/W

..............................................................................+2°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection

Human Body Model (CLK_, CLK_, Q_, Q_)....................≥2kV

Soldering Temperature (10s) ...........................................+300°C

-40°C +25°C +85°C

PARAMETER

SYMBOL

CONDITIONS

UNITS

SINGLE-ENDED INPUT (CLK_SEL)

Single-Ended Input High Voltage

Figure 1

Single-Ended Input Low Voltage

Figure 1

Input Current I

VIH, V

µA

DIFFERENTIAL INPUT (CLK_, CLK_)

Single-Ended Input High Voltage

Figure 1

Single-Ended Input Low Voltage

Figure 1

VCC

Differential Input High Voltage

IHD

Figure 1

MIN TYP MAX MIN TYP MAX MIN TYP MAX

- 1.165

- 1.475

- 1.165

- 1.475

- 1.165

- 1.475

-10.0 +150 -10.0 +150 -10.0 +150

- 1.475

- 1.165

+ 1.2

- 1.165

+ 1.2

- 1.165

- 1.475

+ 1.2

- 1.475

MAX9325

2:8 Differential LVPECL/LVECL/HSTL Clock and

Data Driver

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

((VCC- VEE) = 2.375V to 3.8V, RL= 50Ω ±1% to V

- 2V. Typical values are at (VCC- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V).)

(Notes 1–4)

-40°C +25°C +85°C

PARAMETER

SYMBOL

CONDITIONS

UNITS

Differential Input Low Voltage

ILD

Figure 1

- V

) <

Differential Input Voltage

IHD

ILD

(VCC - VEE) ≥

3.0V, Figure 1

Input Current I

IH, VIL

, V

IHD

ILD

µA

OUTPUT (Q_, Q_)

Single-Ended Output High Voltage

Figure 2

Single-Ended Output Low Voltage

Figure 2

Differential

Output Voltage

Figure 2

REFERENCE VOLTAGE OUTPUT (VBB)

Reference

Voltage Output

IBB = ±0.5mA (Note 5)

SUPPLY

Supply Current

(Note 6) 35 50 39 55 42 65

3.0V, Figure 1

VOH - V

MIN TYP MAX MIN TYP MAX MIN TYP MAX

0.095

- 0.095

- V

0.095 3.0 0.095 3.0 0.095 3.0

-10.0 +150.0 -10.0 +150.0 -10.0 +150.0

- 1.085

- 1.810

- 0.977

- 1.695

- 0.880

- 1.620

535 718 595 749 595 769

0.095

- 1.025

- 1.810

- 0.949

- 1.697

- 0.095

- V

- 0.88

- 1.62

0.095

- 1.025

- 1.810

- 0.929

- 1.698

- 0.095

- VEE

- 0.88

- 1.62

- 1.38

- 1.318

- 1.26

- 1.38

- 1.325

- 1.26

- 1.38

- 1.328

- 1.26

MAX9325

2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS—PLCC Package

((VCC- VEE) = 2.375V to 3.8V, RL= 50Ω ±1% to V

- 2V, fIN≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values

are at (V

- VEE) = 3.3V, VIH= (VCC- 1V), VIL= (VCC- 1.5V).) (Note 7)

-40°C +25°C +85°C

PARAMETER

SYMBOL

CONDITIONS

UNITS

Differential Input-to-Output Delay

PLHD

PHLD

Figure 2

Single-Ended Input-to-Output Delay

PLH

PHL

Output-toOutput Skew

(Note 9)

50 ps

Part-to-Part Skew

SKPP

(Note 10)

Added Random Jitter

fIN = 0.5GHz clock pattern (Note 11)

RMS

Added Deterministic Jitter

fIN = 1.0Gbps, 2E

- 1 PRBS

P-P

Switching Frequency

MAX

VOH - V

≥ 300mV clock pattern

GHz

Output Rise/Fall Time (20% to 80%)

, t

Figure 2

MIN TYP MAX MIN TYP MAX MIN TYP MAX

525 725 550 750 575 775

Figure 3 (Note 8) 500 750 550 800 600 850

SKOO

Differential input

pattern (Note 11)

50 50

160 190 225

1.5 1.5 1.5

100 100 100

1.5 1.5 1.5

140 440 140 440 140 440

+ 8 hidden pages